| 1 | /* |
| 2 | * (C) GraÅžvydas "notaz" Ignotas, 2011 |
| 3 | * |
| 4 | * This work is licensed under the terms of any of these licenses |
| 5 | * (at your option): |
| 6 | * - GNU GPL, version 2 or later. |
| 7 | * - GNU LGPL, version 2.1 or later. |
| 8 | * See the COPYING file in the top-level directory. |
| 9 | */ |
| 10 | |
| 11 | |
| 12 | .text |
| 13 | .align 2 |
| 14 | |
| 15 | .macro load_varadr reg var |
| 16 | #if defined(__ARM_ARCH_7A__) && !defined(__PIC__) |
| 17 | movw \reg, #:lower16:\var |
| 18 | movt \reg, #:upper16:\var |
| 19 | #else |
| 20 | ldr \reg, =\var |
| 21 | #endif |
| 22 | .endm |
| 23 | |
| 24 | #ifdef __ARM_NEON__ |
| 25 | |
| 26 | .global mix_chan @ (int start, int count, int lv, int rv) |
| 27 | mix_chan: |
| 28 | vmov.32 d14[0], r2 |
| 29 | vmov.32 d14[1], r3 @ multipliers |
| 30 | mov r12, r0 |
| 31 | load_varadr r0, ChanBuf |
| 32 | load_varadr r2, SSumLR |
| 33 | add r0, r12, lsl #2 |
| 34 | add r2, r12, lsl #3 |
| 35 | 0: |
| 36 | vldmia r0!, {d0-d1} |
| 37 | vldmia r2, {d2-d5} |
| 38 | vmul.s32 d10, d14, d0[0] |
| 39 | vmul.s32 d11, d14, d0[1] |
| 40 | vmul.s32 d12, d14, d1[0] |
| 41 | vmul.s32 d13, d14, d1[1] |
| 42 | vsra.s32 q1, q5, #14 |
| 43 | vsra.s32 q2, q6, #14 |
| 44 | subs r1, #4 |
| 45 | blt mc_finish |
| 46 | vstmia r2!, {d2-d5} |
| 47 | bgt 0b |
| 48 | nop |
| 49 | bxeq lr |
| 50 | |
| 51 | mc_finish: |
| 52 | vstmia r2!, {d2} |
| 53 | cmp r1, #-2 |
| 54 | vstmiage r2!, {d3} |
| 55 | cmp r1, #-1 |
| 56 | vstmiage r2!, {d4} |
| 57 | bx lr |
| 58 | |
| 59 | |
| 60 | .global mix_chan_rvb @ (int start, int count, int lv, int rv) |
| 61 | mix_chan_rvb: |
| 62 | vmov.32 d14[0], r2 |
| 63 | vmov.32 d14[1], r3 @ multipliers |
| 64 | mov r12, r0 |
| 65 | load_varadr r0, ChanBuf |
| 66 | load_varadr r3, sRVBStart |
| 67 | load_varadr r2, SSumLR |
| 68 | ldr r3, [r3] |
| 69 | add r0, r12, lsl #2 |
| 70 | add r2, r12, lsl #3 |
| 71 | add r3, r12, lsl #3 |
| 72 | 0: |
| 73 | vldmia r0!, {d0-d1} |
| 74 | vldmia r2, {d2-d5} |
| 75 | vldmia r3, {d6-d9} |
| 76 | vmul.s32 d10, d14, d0[0] |
| 77 | vmul.s32 d11, d14, d0[1] |
| 78 | vmul.s32 d12, d14, d1[0] |
| 79 | vmul.s32 d13, d14, d1[1] |
| 80 | vsra.s32 q1, q5, #14 |
| 81 | vsra.s32 q2, q6, #14 |
| 82 | vsra.s32 q3, q5, #14 |
| 83 | vsra.s32 q4, q6, #14 |
| 84 | subs r1, #4 |
| 85 | blt mcr_finish |
| 86 | vstmia r2!, {d2-d5} |
| 87 | vstmia r3!, {d6-d9} |
| 88 | bgt 0b |
| 89 | nop |
| 90 | bxeq lr |
| 91 | |
| 92 | mcr_finish: |
| 93 | vstmia r2!, {d2} |
| 94 | vstmia r3!, {d6} |
| 95 | cmp r1, #-2 |
| 96 | vstmiage r2!, {d3} |
| 97 | vstmiage r3!, {d7} |
| 98 | cmp r1, #-1 |
| 99 | vstmiage r2!, {d4} |
| 100 | vstmiage r3!, {d8} |
| 101 | bx lr |
| 102 | |
| 103 | #else |
| 104 | |
| 105 | .global mix_chan @ (int start, int count, int lv, int rv) |
| 106 | mix_chan: |
| 107 | stmfd sp!, {r4-r8,lr} |
| 108 | orr r3, r2, r3, lsl #16 |
| 109 | lsl r3, #1 @ packed multipliers << 1 |
| 110 | mov r12, r0 |
| 111 | load_varadr r0, ChanBuf |
| 112 | load_varadr r2, SSumLR |
| 113 | add r0, r12, lsl #2 |
| 114 | add r2, r12, lsl #3 |
| 115 | 0: |
| 116 | ldmia r0!, {r4,r5} |
| 117 | ldmia r2, {r6-r8,lr} |
| 118 | lsl r4, #1 @ adjust for mul |
| 119 | lsl r5, #1 |
| 120 | smlawb r6, r4, r3, r6 |
| 121 | smlawt r7, r4, r3, r7 |
| 122 | smlawb r8, r5, r3, r8 |
| 123 | smlawt lr, r5, r3, lr |
| 124 | subs r1, #2 |
| 125 | blt mc_finish |
| 126 | stmia r2!, {r6-r8,lr} |
| 127 | bgt 0b |
| 128 | ldmeqfd sp!, {r4-r8,pc} |
| 129 | |
| 130 | mc_finish: |
| 131 | stmia r2!, {r6,r7} |
| 132 | ldmfd sp!, {r4-r8,pc} |
| 133 | |
| 134 | |
| 135 | .global mix_chan_rvb @ (int start, int count, int lv, int rv) |
| 136 | mix_chan_rvb: |
| 137 | stmfd sp!, {r4-r8,lr} |
| 138 | orr lr, r2, r3, lsl #16 |
| 139 | lsl lr, #1 |
| 140 | load_varadr r3, sRVBStart |
| 141 | load_varadr r2, SSumLR |
| 142 | load_varadr r4, ChanBuf |
| 143 | ldr r3, [r3] |
| 144 | add r2, r2, r0, lsl #3 |
| 145 | add r3, r3, r0, lsl #3 |
| 146 | add r0, r4, r0, lsl #2 |
| 147 | 0: |
| 148 | ldr r4, [r0], #4 |
| 149 | ldmia r2, {r6,r7} |
| 150 | ldmia r3, {r8,r12} |
| 151 | lsl r4, #1 |
| 152 | smlawb r6, r4, lr, r6 @ supposedly takes single cycle? |
| 153 | smlawt r7, r4, lr, r7 |
| 154 | smlawb r8, r4, lr, r8 |
| 155 | smlawt r12,r4, lr, r12 |
| 156 | subs r1, #1 |
| 157 | stmia r2!, {r6,r7} |
| 158 | stmia r3!, {r8,r12} |
| 159 | bgt 0b |
| 160 | ldmfd sp!, {r4-r8,pc} |
| 161 | |
| 162 | #endif |
| 163 | |
| 164 | @ vim:filetype=armasm |