| 1 | /* |
| 2 | * vim:shiftwidth=2:expandtab |
| 3 | */ |
| 4 | #include <stdio.h> |
| 5 | #include <stdlib.h> |
| 6 | #include <assert.h> |
| 7 | |
| 8 | #include "sh2.h" |
| 9 | #include "compiler.h" |
| 10 | #include "../drc/cmn.h" |
| 11 | |
| 12 | #ifndef DRC_DEBUG |
| 13 | #define DRC_DEBUG 0 |
| 14 | #endif |
| 15 | |
| 16 | #if DRC_DEBUG |
| 17 | #include "mame/sh2dasm.h" |
| 18 | #include <platform/linux/host_dasm.h> |
| 19 | static int insns_compiled, hash_collisions, host_insn_count; |
| 20 | #endif |
| 21 | #if (DRC_DEBUG & 2) |
| 22 | static void *tcache_dsm_ptr = tcache; |
| 23 | static char sh2dasm_buff[64]; |
| 24 | #endif |
| 25 | |
| 26 | #define BLOCK_CYCLE_LIMIT 100 |
| 27 | |
| 28 | static void *tcache_ptr; |
| 29 | |
| 30 | #include "../drc/emit_x86.c" |
| 31 | |
| 32 | typedef enum { |
| 33 | SHR_R0 = 0, SHR_R15 = 15, |
| 34 | SHR_PC, SHR_PPC, SHR_PR, SHR_SR, |
| 35 | SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL, |
| 36 | } sh2_reg_e; |
| 37 | |
| 38 | typedef struct block_desc_ { |
| 39 | u32 addr; // SH2 PC address |
| 40 | void *tcache_ptr; // translated block for above PC |
| 41 | struct block_desc_ *next; // next block with the same PC hash |
| 42 | } block_desc; |
| 43 | |
| 44 | #define MAX_BLOCK_COUNT (4*1024) |
| 45 | static block_desc *block_table; |
| 46 | static int block_count; |
| 47 | |
| 48 | #define MAX_HASH_ENTRIES 1024 |
| 49 | #define HASH_MASK (MAX_HASH_ENTRIES - 1) |
| 50 | |
| 51 | extern void sh2_drc_entry(SH2 *sh2, void *block); |
| 52 | extern void sh2_drc_exit(void); |
| 53 | |
| 54 | // tmp |
| 55 | extern void __attribute__((regparm(2))) sh2_do_op(SH2 *sh2, int opcode); |
| 56 | static void __attribute__((regparm(1))) sh2_test_irq(SH2 *sh2); |
| 57 | |
| 58 | static void *dr_find_block(block_desc *tab, u32 addr) |
| 59 | { |
| 60 | for (tab = tab->next; tab != NULL; tab = tab->next) |
| 61 | if (tab->addr == addr) |
| 62 | break; |
| 63 | |
| 64 | if (tab != NULL) |
| 65 | return tab->tcache_ptr; |
| 66 | |
| 67 | printf("block miss for %08x\n", addr); |
| 68 | return NULL; |
| 69 | } |
| 70 | |
| 71 | static block_desc *dr_add_block(u32 addr, void *tcache_ptr) |
| 72 | { |
| 73 | block_desc *bd; |
| 74 | |
| 75 | if (block_count == MAX_BLOCK_COUNT) { |
| 76 | // FIXME: flush cache instead |
| 77 | printf("block descriptor overflow\n"); |
| 78 | exit(1); |
| 79 | } |
| 80 | |
| 81 | bd = &block_table[block_count]; |
| 82 | bd->addr = addr; |
| 83 | bd->tcache_ptr = tcache_ptr; |
| 84 | block_count++; |
| 85 | |
| 86 | return bd; |
| 87 | } |
| 88 | |
| 89 | #define HASH_FUNC(hash_tab, addr) \ |
| 90 | ((block_desc **)(hash_tab))[(addr) & HASH_MASK] |
| 91 | |
| 92 | // --------------------------------------------------------------- |
| 93 | |
| 94 | static void emit_move_r_imm32(sh2_reg_e dst, u32 imm) |
| 95 | { |
| 96 | int host_dst = reg_map_g2h[dst]; |
| 97 | int tmp = 0; |
| 98 | |
| 99 | if (host_dst != -1) |
| 100 | tmp = host_dst; |
| 101 | emith_move_r_imm(tmp, imm); |
| 102 | if (host_dst == -1) |
| 103 | emith_ctx_write(tmp, dst * 4); |
| 104 | } |
| 105 | |
| 106 | static void emit_move_r_r(sh2_reg_e dst, sh2_reg_e src) |
| 107 | { |
| 108 | int host_dst = reg_map_g2h[dst], host_src = reg_map_g2h[src]; |
| 109 | int tmp = 0; |
| 110 | |
| 111 | if (host_dst != -1 && host_src != -1) { |
| 112 | emith_move_r_r(host_dst, host_src); |
| 113 | return; |
| 114 | } |
| 115 | |
| 116 | if (host_src != -1) |
| 117 | tmp = host_src; |
| 118 | if (host_dst != -1) |
| 119 | tmp = host_dst; |
| 120 | |
| 121 | if (host_src == -1) |
| 122 | emith_ctx_read(tmp, src * 4); |
| 123 | if (host_dst == -1) |
| 124 | emith_ctx_write(tmp, dst * 4); |
| 125 | } |
| 126 | |
| 127 | static void emit_braf(sh2_reg_e reg, u32 pc) |
| 128 | { |
| 129 | int host_reg = reg_map_g2h[reg]; |
| 130 | if (host_reg == -1) { |
| 131 | emith_ctx_read(0, reg * 4); |
| 132 | } else |
| 133 | emith_move_r_r(0, host_reg); |
| 134 | emith_add_r_imm(0, pc); |
| 135 | |
| 136 | emith_ctx_write(0, SHR_PPC * 4); |
| 137 | } |
| 138 | |
| 139 | /* |
| 140 | static int sh2_translate_op4(int op) |
| 141 | { |
| 142 | switch (op & 0x000f) |
| 143 | { |
| 144 | case 0x0b: |
| 145 | default: |
| 146 | emith_pass_arg(2, sh2, op); |
| 147 | emith_call(sh2_do_op); |
| 148 | break; |
| 149 | } |
| 150 | |
| 151 | return 0; |
| 152 | } |
| 153 | */ |
| 154 | |
| 155 | #define DELAYED_OP \ |
| 156 | delayed_op = 2 |
| 157 | |
| 158 | #define CHECK_UNHANDLED_BITS(mask) { \ |
| 159 | if ((op & (mask)) != 0) \ |
| 160 | goto default_; \ |
| 161 | } |
| 162 | |
| 163 | static void *sh2_translate(SH2 *sh2, block_desc *other_block) |
| 164 | { |
| 165 | void *block_entry = tcache_ptr; |
| 166 | block_desc *this_block; |
| 167 | unsigned int pc = sh2->pc; |
| 168 | int op, delayed_op = 0, test_irq = 0; |
| 169 | int cycles = 0; |
| 170 | u32 tmp, tmp2; |
| 171 | |
| 172 | this_block = dr_add_block(pc, block_entry); |
| 173 | if (other_block != NULL) |
| 174 | this_block->next = other_block; |
| 175 | |
| 176 | HASH_FUNC(sh2->pc_hashtab, pc) = this_block; |
| 177 | |
| 178 | #if (DRC_DEBUG & 1) |
| 179 | printf("== %csh2 block #%d %08x -> %p\n", sh2->is_slave ? 's' : 'm', |
| 180 | block_count, pc, block_entry); |
| 181 | if (other_block != NULL) { |
| 182 | printf(" hash collision with %08x\n", other_block->addr); |
| 183 | hash_collisions++; |
| 184 | } |
| 185 | #endif |
| 186 | |
| 187 | while (cycles < BLOCK_CYCLE_LIMIT || delayed_op) |
| 188 | { |
| 189 | if (delayed_op > 0) |
| 190 | delayed_op--; |
| 191 | |
| 192 | op = p32x_sh2_read16(pc, sh2->is_slave); |
| 193 | |
| 194 | #if (DRC_DEBUG & 3) |
| 195 | insns_compiled++; |
| 196 | #if (DRC_DEBUG & 2) |
| 197 | DasmSH2(sh2dasm_buff, pc, op); |
| 198 | printf("%08x %04x %s\n", pc, op, sh2dasm_buff); |
| 199 | #endif |
| 200 | #endif |
| 201 | |
| 202 | pc += 2; |
| 203 | cycles++; |
| 204 | |
| 205 | switch ((op >> 12) & 0x0f) |
| 206 | { |
| 207 | case 0x00: |
| 208 | switch (op & 0x0f) { |
| 209 | case 0x03: |
| 210 | CHECK_UNHANDLED_BITS(0xd0); |
| 211 | // BRAF Rm 0000mmmm00100011 |
| 212 | // BSRF Rm 0000mmmm00000011 |
| 213 | DELAYED_OP; |
| 214 | if (!(op & 0x20)) |
| 215 | emit_move_r_imm32(SHR_PR, pc + 2); |
| 216 | emit_braf((op >> 8) & 0x0f, pc + 2); |
| 217 | cycles++; |
| 218 | goto end_op; |
| 219 | case 0x09: |
| 220 | CHECK_UNHANDLED_BITS(0xf0); |
| 221 | // NOP 0000000000001001 |
| 222 | goto end_op; |
| 223 | case 0x0b: |
| 224 | CHECK_UNHANDLED_BITS(0xd0); |
| 225 | DELAYED_OP; |
| 226 | if (!(op & 0x20)) { |
| 227 | // RTS 0000000000001011 |
| 228 | emit_move_r_r(SHR_PPC, SHR_PR); |
| 229 | cycles++; |
| 230 | } else { |
| 231 | // RTE 0000000000101011 |
| 232 | //emit_move_r_r(SHR_PC, SHR_PR); |
| 233 | emit_move_r_imm32(SHR_PC, pc - 2); |
| 234 | emith_pass_arg(2, sh2, op); |
| 235 | emith_call(sh2_do_op); |
| 236 | emit_move_r_r(SHR_PPC, SHR_PC); |
| 237 | test_irq = 1; |
| 238 | cycles += 3; |
| 239 | } |
| 240 | goto end_op; |
| 241 | } |
| 242 | goto default_; |
| 243 | |
| 244 | case 0x04: |
| 245 | switch (op & 0x0f) { |
| 246 | case 0x07: |
| 247 | if ((op & 0xf0) != 0) |
| 248 | goto default_; |
| 249 | // LDC.L @Rm+,SR 0100mmmm00000111 |
| 250 | test_irq = 1; |
| 251 | goto default_; |
| 252 | case 0x0b: |
| 253 | if ((op & 0xd0) != 0) |
| 254 | goto default_; |
| 255 | // JMP @Rm 0100mmmm00101011 |
| 256 | // JSR @Rm 0100mmmm00001011 |
| 257 | DELAYED_OP; |
| 258 | if (!(op & 0x20)) |
| 259 | emit_move_r_imm32(SHR_PR, pc + 2); |
| 260 | emit_move_r_r(SHR_PPC, (op >> 8) & 0x0f); |
| 261 | cycles++; |
| 262 | goto end_op; |
| 263 | case 0x0e: |
| 264 | if ((op & 0xf0) != 0) |
| 265 | goto default_; |
| 266 | // LDC Rm,SR 0100mmmm00001110 |
| 267 | test_irq = 1; |
| 268 | goto default_; |
| 269 | } |
| 270 | goto default_; |
| 271 | |
| 272 | case 0x08: |
| 273 | switch (op & 0x0f00) { |
| 274 | // BT/S label 10001101dddddddd |
| 275 | case 0x0d00: |
| 276 | // BF/S label 10001111dddddddd |
| 277 | case 0x0f00: |
| 278 | DELAYED_OP; |
| 279 | cycles--; |
| 280 | // fallthrough |
| 281 | // BT label 10001001dddddddd |
| 282 | case 0x0900: |
| 283 | // BF label 10001011dddddddd |
| 284 | case 0x0b00: |
| 285 | tmp = ((signed int)(op << 24) >> 23); |
| 286 | tmp2 = delayed_op ? SHR_PPC : SHR_PC; |
| 287 | emit_move_r_imm32(tmp2, pc + (delayed_op ? 2 : 0)); |
| 288 | emith_test_t(); |
| 289 | EMIT_CONDITIONAL(emit_move_r_imm32(tmp2, pc + tmp + 2), (op & 0x0200) ? 1 : 0); |
| 290 | cycles += 2; |
| 291 | if (!delayed_op) |
| 292 | goto end_block; |
| 293 | goto end_op; |
| 294 | } |
| 295 | goto default_; |
| 296 | |
| 297 | case 0x0a: |
| 298 | // BRA label 1010dddddddddddd |
| 299 | DELAYED_OP; |
| 300 | do_bra: |
| 301 | tmp = ((signed int)(op << 20) >> 19); |
| 302 | emit_move_r_imm32(SHR_PPC, pc + tmp + 2); |
| 303 | cycles++; |
| 304 | break; |
| 305 | |
| 306 | case 0x0b: |
| 307 | // BSR label 1011dddddddddddd |
| 308 | DELAYED_OP; |
| 309 | emit_move_r_imm32(SHR_PR, pc + 2); |
| 310 | goto do_bra; |
| 311 | |
| 312 | default: |
| 313 | default_: |
| 314 | emit_move_r_imm32(SHR_PC, pc - 2); |
| 315 | emith_pass_arg(2, sh2, op); |
| 316 | emith_call(sh2_do_op); |
| 317 | break; |
| 318 | } |
| 319 | |
| 320 | end_op: |
| 321 | if (delayed_op == 1) { |
| 322 | emit_move_r_r(SHR_PC, SHR_PPC); |
| 323 | break; |
| 324 | } |
| 325 | if (test_irq && delayed_op != 2) { |
| 326 | emith_pass_arg(1, sh2); |
| 327 | emith_call(sh2_test_irq); |
| 328 | break; |
| 329 | } |
| 330 | |
| 331 | #if (DRC_DEBUG & 2) |
| 332 | host_dasm(tcache_dsm_ptr, (char *)tcache_ptr - (char *)tcache_dsm_ptr); |
| 333 | tcache_dsm_ptr = tcache_ptr; |
| 334 | #endif |
| 335 | } |
| 336 | |
| 337 | end_block: |
| 338 | if ((char *)tcache_ptr - (char *)tcache > DRC_TCACHE_SIZE) { |
| 339 | printf("tcache overflow!\n"); |
| 340 | fflush(stdout); |
| 341 | exit(1); |
| 342 | } |
| 343 | |
| 344 | if (reg_map_g2h[SHR_SR] == -1) { |
| 345 | emith_ctx_sub(cycles << 12, SHR_SR * 4); |
| 346 | } else |
| 347 | emith_sub_r_imm(reg_map_g2h[SHR_SR], cycles << 12); |
| 348 | emith_jump(sh2_drc_exit); |
| 349 | |
| 350 | #if (DRC_DEBUG & 2) |
| 351 | host_dasm(tcache_dsm_ptr, (char *)tcache_ptr - (char *)tcache_dsm_ptr); |
| 352 | tcache_dsm_ptr = tcache_ptr; |
| 353 | #endif |
| 354 | #if (DRC_DEBUG & 1) |
| 355 | printf(" tcache %d/%d, hash collisions %d/%d, insns %d -> %d %.3f\n", |
| 356 | (char *)tcache_ptr - (char *)tcache, DRC_TCACHE_SIZE, |
| 357 | hash_collisions, block_count, insns_compiled, host_insn_count, |
| 358 | (double)host_insn_count / insns_compiled); |
| 359 | #endif |
| 360 | return block_entry; |
| 361 | |
| 362 | unimplemented: |
| 363 | // last op |
| 364 | #if (DRC_DEBUG & 2) |
| 365 | host_dasm(tcache_dsm_ptr, (char *)tcache_ptr - (char *)tcache_dsm_ptr); |
| 366 | tcache_dsm_ptr = tcache_ptr; |
| 367 | #endif |
| 368 | exit(1); |
| 369 | } |
| 370 | |
| 371 | void __attribute__((noinline)) sh2_drc_dispatcher(SH2 *sh2) |
| 372 | { |
| 373 | while (((signed int)sh2->sr >> 12) > 0) |
| 374 | { |
| 375 | block_desc *bd = HASH_FUNC(sh2->pc_hashtab, sh2->pc); |
| 376 | void *block = NULL; |
| 377 | |
| 378 | if (bd != NULL) { |
| 379 | if (bd->addr == sh2->pc) |
| 380 | block = bd->tcache_ptr; |
| 381 | else |
| 382 | block = dr_find_block(bd, sh2->pc); |
| 383 | } |
| 384 | |
| 385 | if (block == NULL) |
| 386 | block = sh2_translate(sh2, bd); |
| 387 | |
| 388 | #if (DRC_DEBUG & 4) |
| 389 | printf("= %csh2 enter %08x %p\n", sh2->is_slave ? 's' : 'm', sh2->pc, block); |
| 390 | #endif |
| 391 | sh2_drc_entry(sh2, block); |
| 392 | } |
| 393 | } |
| 394 | |
| 395 | void sh2_execute(SH2 *sh2, int cycles) |
| 396 | { |
| 397 | sh2->cycles_aim += cycles; |
| 398 | cycles = sh2->cycles_aim - sh2->cycles_done; |
| 399 | |
| 400 | // cycles are kept in SHR_SR unused bits (upper 20) |
| 401 | sh2->sr &= 0x3f3; |
| 402 | sh2->sr |= cycles << 12; |
| 403 | sh2_drc_dispatcher(sh2); |
| 404 | |
| 405 | sh2->cycles_done += cycles - ((signed int)sh2->sr >> 12); |
| 406 | } |
| 407 | |
| 408 | static void __attribute__((regparm(1))) sh2_test_irq(SH2 *sh2) |
| 409 | { |
| 410 | if (sh2->pending_irl > sh2->pending_int_irq) |
| 411 | sh2_irl_irq(sh2, sh2->pending_irl); |
| 412 | else |
| 413 | sh2_internal_irq(sh2, sh2->pending_int_irq, sh2->pending_int_vector); |
| 414 | } |
| 415 | |
| 416 | int sh2_drc_init(SH2 *sh2) |
| 417 | { |
| 418 | if (block_table == NULL) { |
| 419 | block_count = 0; |
| 420 | block_table = calloc(MAX_BLOCK_COUNT, sizeof(*block_table)); |
| 421 | if (block_table == NULL) |
| 422 | return -1; |
| 423 | |
| 424 | tcache_ptr = tcache; |
| 425 | #if (DRC_DEBUG & 1) |
| 426 | hash_collisions = 0; |
| 427 | #endif |
| 428 | } |
| 429 | |
| 430 | //assert(sh2->pc_hashtab == NULL); |
| 431 | sh2->pc_hashtab = calloc(sizeof(sh2->pc_hashtab[0]), MAX_HASH_ENTRIES); |
| 432 | if (sh2->pc_hashtab == NULL) |
| 433 | return -1; |
| 434 | |
| 435 | return 0; |
| 436 | } |
| 437 | |
| 438 | void sh2_drc_finish(SH2 *sh2) |
| 439 | { |
| 440 | if (block_table != NULL) { |
| 441 | free(block_table); |
| 442 | block_table = NULL; |
| 443 | } |
| 444 | |
| 445 | free(sh2->pc_hashtab); |
| 446 | sh2->pc_hashtab = NULL; |
| 447 | } |