| 1 | /*****************************************************************************\r |
| 2 | *\r |
| 3 | * sh2.c\r |
| 4 | * Portable Hitachi SH-2 (SH7600 family) emulator\r |
| 5 | *\r |
| 6 | * Copyright Juergen Buchmueller <pullmoll@t-online.de>,\r |
| 7 | * all rights reserved.\r |
| 8 | *\r |
| 9 | * - This source code is released as freeware for non-commercial purposes.\r |
| 10 | * - You are free to use and redistribute this code in modified or\r |
| 11 | * unmodified form, provided you list me in the credits.\r |
| 12 | * - If you modify this source code, you must add a notice to each modified\r |
| 13 | * source file that it has been changed. If you're a nice person, you\r |
| 14 | * will clearly mark each change too. :)\r |
| 15 | * - If you wish to use this for commercial purposes, please contact me at\r |
| 16 | * pullmoll@t-online.de\r |
| 17 | * - The author of this copywritten work reserves the right to change the\r |
| 18 | * terms of its usage and license at any time, including retroactively\r |
| 19 | * - This entire notice must remain in the source code.\r |
| 20 | *\r |
| 21 | * This work is based on <tiraniddo@hotmail.com> C/C++ implementation of\r |
| 22 | * the SH-2 CPU core and was adapted to the MAME CPU core requirements.\r |
| 23 | * Thanks also go to Chuck Mason <chukjr@sundail.net> and Olivier Galibert\r |
| 24 | * <galibert@pobox.com> for letting me peek into their SEMU code :-)\r |
| 25 | *\r |
| 26 | *****************************************************************************/\r |
| 27 | \r |
| 28 | /*****************************************************************************\r |
| 29 | Changes\r |
| 30 | 20051129 Mariusz Wojcieszek\r |
| 31 | - introduced memory_decrypted_read_word() for opcode fetching\r |
| 32 | \r |
| 33 | 20050813 Mariusz Wojcieszek\r |
| 34 | - fixed 64 bit / 32 bit division in division unit\r |
| 35 | \r |
| 36 | 20031015 O. Galibert\r |
| 37 | - dma fixes, thanks to sthief\r |
| 38 | \r |
| 39 | 20031013 O. Galibert, A. Giles\r |
| 40 | - timer fixes\r |
| 41 | - multi-cpu simplifications\r |
| 42 | \r |
| 43 | 20030915 O. Galibert\r |
| 44 | - fix DMA1 irq vector\r |
| 45 | - ignore writes to DRCRx\r |
| 46 | - fix cpu number issues\r |
| 47 | - fix slave/master recognition\r |
| 48 | - fix wrong-cpu-in-context problem with the timers\r |
| 49 | \r |
| 50 | 20021020 O. Galibert\r |
| 51 | - DMA implementation, lightly tested\r |
| 52 | - delay slot in debugger fixed\r |
| 53 | - add divide box mirrors\r |
| 54 | - Nicola-ify the indentation\r |
| 55 | - Uncrapify sh2_internal_*\r |
| 56 | - Put back nmi support that had been lost somehow\r |
| 57 | \r |
| 58 | 20020914 R. Belmont\r |
| 59 | - Initial SH2 internal timers implementation, based on code by O. Galibert.\r |
| 60 | Makes music work in galspanic4/s/s2, panic street, cyvern, other SKNS games.\r |
| 61 | - Fix to external division, thanks to "spice" on the E2J board.\r |
| 62 | Corrects behavior of s1945ii turret boss.\r |
| 63 | \r |
| 64 | 20020302 Olivier Galibert (galibert@mame.net)\r |
| 65 | - Fixed interrupt in delay slot\r |
| 66 | - Fixed rotcr\r |
| 67 | - Fixed div1\r |
| 68 | - Fixed mulu\r |
| 69 | - Fixed negc\r |
| 70 | \r |
| 71 | 20020301 R. Belmont\r |
| 72 | - Fixed external division\r |
| 73 | \r |
| 74 | 20020225 Olivier Galibert (galibert@mame.net)\r |
| 75 | - Fixed interrupt handling\r |
| 76 | \r |
| 77 | 20010207 Sylvain Glaize (mokona@puupuu.org)\r |
| 78 | \r |
| 79 | - Bug fix in INLINE void MOVBM(UINT32 m, UINT32 n) (see comment)\r |
| 80 | - Support of full 32 bit addressing (RB, RW, RL and WB, WW, WL functions)\r |
| 81 | reason : when the two high bits of the address are set, access is\r |
| 82 | done directly in the cache data array. The SUPER KANEKO NOVA SYSTEM\r |
| 83 | sets the stack pointer here, using these addresses as usual RAM access.\r |
| 84 | \r |
| 85 | No real cache support has been added.\r |
| 86 | - Read/Write memory format correction (_bew to _bedw) (see also SH2\r |
| 87 | definition in cpuintrf.c and DasmSH2(..) in sh2dasm.c )\r |
| 88 | \r |
| 89 | 20010623 James Forshaw (TyRaNiD@totalise.net)\r |
| 90 | \r |
| 91 | - Modified operation of sh2_exception. Done cause mame irq system is stupid, and\r |
| 92 | doesnt really seem designed for any more than 8 interrupt lines.\r |
| 93 | \r |
| 94 | 20010701 James Forshaw (TyRaNiD@totalise.net)\r |
| 95 | \r |
| 96 | - Fixed DIV1 operation. Q bit now correctly generated\r |
| 97 | \r |
| 98 | 20020218 Added save states (mokona@puupuu.org)\r |
| 99 | \r |
| 100 | *****************************************************************************/\r |
| 101 | \r |
| 102 | //#include "debugger.h"\r |
| 103 | //#include "sh2.h"\r |
| 104 | //#include "sh2comn.h"\r |
| 105 | #define INLINE static\r |
| 106 | \r |
| 107 | //CPU_DISASSEMBLE( sh2 );\r |
| 108 | \r |
| 109 | #ifndef USE_SH2DRC\r |
| 110 | \r |
| 111 | /* speed up delay loops, bail out of tight loops */\r |
| 112 | #define BUSY_LOOP_HACKS 1\r |
| 113 | \r |
| 114 | #define VERBOSE 0\r |
| 115 | \r |
| 116 | #define LOG(x) do { if (VERBOSE) logerror x; } while (0)\r |
| 117 | \r |
| 118 | //int sh2_icount;\r |
| 119 | SH2 *sh2;\r |
| 120 | \r |
| 121 | #if 0\r |
| 122 | INLINE UINT8 RB(offs_t A)\r |
| 123 | {\r |
| 124 | if (A >= 0xe0000000)\r |
| 125 | return sh2_internal_r(sh2->internal, (A & 0x1fc)>>2, 0xff << (((~A) & 3)*8)) >> (((~A) & 3)*8);\r |
| 126 | \r |
| 127 | if (A >= 0xc0000000)\r |
| 128 | return memory_read_byte_32be(sh2->program, A);\r |
| 129 | \r |
| 130 | if (A >= 0x40000000)\r |
| 131 | return 0xa5;\r |
| 132 | \r |
| 133 | return memory_read_byte_32be(sh2->program, A & AM);\r |
| 134 | }\r |
| 135 | \r |
| 136 | INLINE UINT16 RW(offs_t A)\r |
| 137 | {\r |
| 138 | if (A >= 0xe0000000)\r |
| 139 | return sh2_internal_r(sh2->internal, (A & 0x1fc)>>2, 0xffff << (((~A) & 2)*8)) >> (((~A) & 2)*8);\r |
| 140 | \r |
| 141 | if (A >= 0xc0000000)\r |
| 142 | return memory_read_word_32be(sh2->program, A);\r |
| 143 | \r |
| 144 | if (A >= 0x40000000)\r |
| 145 | return 0xa5a5;\r |
| 146 | \r |
| 147 | return memory_read_word_32be(sh2->program, A & AM);\r |
| 148 | }\r |
| 149 | \r |
| 150 | INLINE UINT32 RL(offs_t A)\r |
| 151 | {\r |
| 152 | if (A >= 0xe0000000)\r |
| 153 | return sh2_internal_r(sh2->internal, (A & 0x1fc)>>2, 0xffffffff);\r |
| 154 | \r |
| 155 | if (A >= 0xc0000000)\r |
| 156 | return memory_read_dword_32be(sh2->program, A);\r |
| 157 | \r |
| 158 | if (A >= 0x40000000)\r |
| 159 | return 0xa5a5a5a5;\r |
| 160 | \r |
| 161 | return memory_read_dword_32be(sh2->program, A & AM);\r |
| 162 | }\r |
| 163 | \r |
| 164 | INLINE void WB(offs_t A, UINT8 V)\r |
| 165 | {\r |
| 166 | \r |
| 167 | if (A >= 0xe0000000)\r |
| 168 | {\r |
| 169 | sh2_internal_w(sh2->internal, (A & 0x1fc)>>2, V << (((~A) & 3)*8), 0xff << (((~A) & 3)*8));\r |
| 170 | return;\r |
| 171 | }\r |
| 172 | \r |
| 173 | if (A >= 0xc0000000)\r |
| 174 | {\r |
| 175 | memory_write_byte_32be(sh2->program, A,V);\r |
| 176 | return;\r |
| 177 | }\r |
| 178 | \r |
| 179 | if (A >= 0x40000000)\r |
| 180 | return;\r |
| 181 | \r |
| 182 | memory_write_byte_32be(sh2->program, A & AM,V);\r |
| 183 | }\r |
| 184 | \r |
| 185 | INLINE void WW(offs_t A, UINT16 V)\r |
| 186 | {\r |
| 187 | if (A >= 0xe0000000)\r |
| 188 | {\r |
| 189 | sh2_internal_w(sh2->internal, (A & 0x1fc)>>2, V << (((~A) & 2)*8), 0xffff << (((~A) & 2)*8));\r |
| 190 | return;\r |
| 191 | }\r |
| 192 | \r |
| 193 | if (A >= 0xc0000000)\r |
| 194 | {\r |
| 195 | memory_write_word_32be(sh2->program, A,V);\r |
| 196 | return;\r |
| 197 | }\r |
| 198 | \r |
| 199 | if (A >= 0x40000000)\r |
| 200 | return;\r |
| 201 | \r |
| 202 | memory_write_word_32be(sh2->program, A & AM,V);\r |
| 203 | }\r |
| 204 | \r |
| 205 | INLINE void WL(offs_t A, UINT32 V)\r |
| 206 | {\r |
| 207 | if (A >= 0xe0000000)\r |
| 208 | {\r |
| 209 | sh2_internal_w(sh2->internal, (A & 0x1fc)>>2, V, 0xffffffff);\r |
| 210 | return;\r |
| 211 | }\r |
| 212 | \r |
| 213 | if (A >= 0xc0000000)\r |
| 214 | {\r |
| 215 | memory_write_dword_32be(sh2->program, A,V);\r |
| 216 | return;\r |
| 217 | }\r |
| 218 | \r |
| 219 | if (A >= 0x40000000)\r |
| 220 | return;\r |
| 221 | \r |
| 222 | memory_write_dword_32be(sh2->program, A & AM,V);\r |
| 223 | }\r |
| 224 | #endif\r |
| 225 | \r |
| 226 | /* code cycles t-bit\r |
| 227 | * 0011 nnnn mmmm 1100 1 -\r |
| 228 | * ADD Rm,Rn\r |
| 229 | */\r |
| 230 | INLINE void ADD(UINT32 m, UINT32 n)\r |
| 231 | {\r |
| 232 | sh2->r[n] += sh2->r[m];\r |
| 233 | }\r |
| 234 | \r |
| 235 | /* code cycles t-bit\r |
| 236 | * 0111 nnnn iiii iiii 1 -\r |
| 237 | * ADD #imm,Rn\r |
| 238 | */\r |
| 239 | INLINE void ADDI(UINT32 i, UINT32 n)\r |
| 240 | {\r |
| 241 | sh2->r[n] += (INT32)(INT16)(INT8)i;\r |
| 242 | }\r |
| 243 | \r |
| 244 | /* code cycles t-bit\r |
| 245 | * 0011 nnnn mmmm 1110 1 carry\r |
| 246 | * ADDC Rm,Rn\r |
| 247 | */\r |
| 248 | INLINE void ADDC(UINT32 m, UINT32 n)\r |
| 249 | {\r |
| 250 | UINT32 tmp0, tmp1;\r |
| 251 | \r |
| 252 | tmp1 = sh2->r[n] + sh2->r[m];\r |
| 253 | tmp0 = sh2->r[n];\r |
| 254 | sh2->r[n] = tmp1 + (sh2->sr & T);\r |
| 255 | if (tmp0 > tmp1)\r |
| 256 | sh2->sr |= T;\r |
| 257 | else\r |
| 258 | sh2->sr &= ~T;\r |
| 259 | if (tmp1 > sh2->r[n])\r |
| 260 | sh2->sr |= T;\r |
| 261 | }\r |
| 262 | \r |
| 263 | /* code cycles t-bit\r |
| 264 | * 0011 nnnn mmmm 1111 1 overflow\r |
| 265 | * ADDV Rm,Rn\r |
| 266 | */\r |
| 267 | INLINE void ADDV(UINT32 m, UINT32 n)\r |
| 268 | {\r |
| 269 | INT32 dest, src, ans;\r |
| 270 | \r |
| 271 | if ((INT32) sh2->r[n] >= 0)\r |
| 272 | dest = 0;\r |
| 273 | else\r |
| 274 | dest = 1;\r |
| 275 | if ((INT32) sh2->r[m] >= 0)\r |
| 276 | src = 0;\r |
| 277 | else\r |
| 278 | src = 1;\r |
| 279 | src += dest;\r |
| 280 | sh2->r[n] += sh2->r[m];\r |
| 281 | if ((INT32) sh2->r[n] >= 0)\r |
| 282 | ans = 0;\r |
| 283 | else\r |
| 284 | ans = 1;\r |
| 285 | ans += dest;\r |
| 286 | if (src == 0 || src == 2)\r |
| 287 | {\r |
| 288 | if (ans == 1)\r |
| 289 | sh2->sr |= T;\r |
| 290 | else\r |
| 291 | sh2->sr &= ~T;\r |
| 292 | }\r |
| 293 | else\r |
| 294 | sh2->sr &= ~T;\r |
| 295 | }\r |
| 296 | \r |
| 297 | /* code cycles t-bit\r |
| 298 | * 0010 nnnn mmmm 1001 1 -\r |
| 299 | * AND Rm,Rn\r |
| 300 | */\r |
| 301 | INLINE void AND(UINT32 m, UINT32 n)\r |
| 302 | {\r |
| 303 | sh2->r[n] &= sh2->r[m];\r |
| 304 | }\r |
| 305 | \r |
| 306 | \r |
| 307 | /* code cycles t-bit\r |
| 308 | * 1100 1001 iiii iiii 1 -\r |
| 309 | * AND #imm,R0\r |
| 310 | */\r |
| 311 | INLINE void ANDI(UINT32 i)\r |
| 312 | {\r |
| 313 | sh2->r[0] &= i;\r |
| 314 | }\r |
| 315 | \r |
| 316 | /* code cycles t-bit\r |
| 317 | * 1100 1101 iiii iiii 1 -\r |
| 318 | * AND.B #imm,@(R0,GBR)\r |
| 319 | */\r |
| 320 | INLINE void ANDM(UINT32 i)\r |
| 321 | {\r |
| 322 | UINT32 temp;\r |
| 323 | \r |
| 324 | sh2->ea = sh2->gbr + sh2->r[0];\r |
| 325 | temp = i & RB( sh2->ea );\r |
| 326 | WB( sh2->ea, temp );\r |
| 327 | sh2_icount -= 2;\r |
| 328 | }\r |
| 329 | \r |
| 330 | /* code cycles t-bit\r |
| 331 | * 1000 1011 dddd dddd 3/1 -\r |
| 332 | * BF disp8\r |
| 333 | */\r |
| 334 | INLINE void BF(UINT32 d)\r |
| 335 | {\r |
| 336 | if ((sh2->sr & T) == 0)\r |
| 337 | {\r |
| 338 | INT32 disp = ((INT32)d << 24) >> 24;\r |
| 339 | sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;\r |
| 340 | sh2_icount -= 2;\r |
| 341 | }\r |
| 342 | }\r |
| 343 | \r |
| 344 | /* code cycles t-bit\r |
| 345 | * 1000 1111 dddd dddd 3/1 -\r |
| 346 | * BFS disp8\r |
| 347 | */\r |
| 348 | INLINE void BFS(UINT32 d)\r |
| 349 | {\r |
| 350 | if ((sh2->sr & T) == 0)\r |
| 351 | {\r |
| 352 | INT32 disp = ((INT32)d << 24) >> 24;\r |
| 353 | sh2->delay = sh2->pc;\r |
| 354 | sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;\r |
| 355 | sh2_icount--;\r |
| 356 | }\r |
| 357 | }\r |
| 358 | \r |
| 359 | /* code cycles t-bit\r |
| 360 | * 1010 dddd dddd dddd 2 -\r |
| 361 | * BRA disp12\r |
| 362 | */\r |
| 363 | INLINE void BRA(UINT32 d)\r |
| 364 | {\r |
| 365 | INT32 disp = ((INT32)d << 20) >> 20;\r |
| 366 | \r |
| 367 | #if BUSY_LOOP_HACKS\r |
| 368 | if (disp == -2)\r |
| 369 | {\r |
| 370 | UINT32 next_opcode = RW(sh2->pc & AM);\r |
| 371 | /* BRA $\r |
| 372 | * NOP\r |
| 373 | */\r |
| 374 | if (next_opcode == 0x0009)\r |
| 375 | sh2_icount %= 3; /* cycles for BRA $ and NOP taken (3) */\r |
| 376 | }\r |
| 377 | #endif\r |
| 378 | sh2->delay = sh2->pc;\r |
| 379 | sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;\r |
| 380 | sh2_icount--;\r |
| 381 | }\r |
| 382 | \r |
| 383 | /* code cycles t-bit\r |
| 384 | * 0000 mmmm 0010 0011 2 -\r |
| 385 | * BRAF Rm\r |
| 386 | */\r |
| 387 | INLINE void BRAF(UINT32 m)\r |
| 388 | {\r |
| 389 | sh2->delay = sh2->pc;\r |
| 390 | sh2->pc += sh2->r[m] + 2;\r |
| 391 | sh2_icount--;\r |
| 392 | }\r |
| 393 | \r |
| 394 | /* code cycles t-bit\r |
| 395 | * 1011 dddd dddd dddd 2 -\r |
| 396 | * BSR disp12\r |
| 397 | */\r |
| 398 | INLINE void BSR(UINT32 d)\r |
| 399 | {\r |
| 400 | INT32 disp = ((INT32)d << 20) >> 20;\r |
| 401 | \r |
| 402 | sh2->pr = sh2->pc + 2;\r |
| 403 | sh2->delay = sh2->pc;\r |
| 404 | sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;\r |
| 405 | sh2_icount--;\r |
| 406 | }\r |
| 407 | \r |
| 408 | /* code cycles t-bit\r |
| 409 | * 0000 mmmm 0000 0011 2 -\r |
| 410 | * BSRF Rm\r |
| 411 | */\r |
| 412 | INLINE void BSRF(UINT32 m)\r |
| 413 | {\r |
| 414 | sh2->pr = sh2->pc + 2;\r |
| 415 | sh2->delay = sh2->pc;\r |
| 416 | sh2->pc += sh2->r[m] + 2;\r |
| 417 | sh2_icount--;\r |
| 418 | }\r |
| 419 | \r |
| 420 | /* code cycles t-bit\r |
| 421 | * 1000 1001 dddd dddd 3/1 -\r |
| 422 | * BT disp8\r |
| 423 | */\r |
| 424 | INLINE void BT(UINT32 d)\r |
| 425 | {\r |
| 426 | if ((sh2->sr & T) != 0)\r |
| 427 | {\r |
| 428 | INT32 disp = ((INT32)d << 24) >> 24;\r |
| 429 | sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;\r |
| 430 | sh2_icount -= 2;\r |
| 431 | }\r |
| 432 | }\r |
| 433 | \r |
| 434 | /* code cycles t-bit\r |
| 435 | * 1000 1101 dddd dddd 2/1 -\r |
| 436 | * BTS disp8\r |
| 437 | */\r |
| 438 | INLINE void BTS(UINT32 d)\r |
| 439 | {\r |
| 440 | if ((sh2->sr & T) != 0)\r |
| 441 | {\r |
| 442 | INT32 disp = ((INT32)d << 24) >> 24;\r |
| 443 | sh2->delay = sh2->pc;\r |
| 444 | sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;\r |
| 445 | sh2_icount--;\r |
| 446 | }\r |
| 447 | }\r |
| 448 | \r |
| 449 | /* code cycles t-bit\r |
| 450 | * 0000 0000 0010 1000 1 -\r |
| 451 | * CLRMAC\r |
| 452 | */\r |
| 453 | INLINE void CLRMAC(void)\r |
| 454 | {\r |
| 455 | sh2->mach = 0;\r |
| 456 | sh2->macl = 0;\r |
| 457 | }\r |
| 458 | \r |
| 459 | /* code cycles t-bit\r |
| 460 | * 0000 0000 0000 1000 1 -\r |
| 461 | * CLRT\r |
| 462 | */\r |
| 463 | INLINE void CLRT(void)\r |
| 464 | {\r |
| 465 | sh2->sr &= ~T;\r |
| 466 | }\r |
| 467 | \r |
| 468 | /* code cycles t-bit\r |
| 469 | * 0011 nnnn mmmm 0000 1 comparison result\r |
| 470 | * CMP_EQ Rm,Rn\r |
| 471 | */\r |
| 472 | INLINE void CMPEQ(UINT32 m, UINT32 n)\r |
| 473 | {\r |
| 474 | if (sh2->r[n] == sh2->r[m])\r |
| 475 | sh2->sr |= T;\r |
| 476 | else\r |
| 477 | sh2->sr &= ~T;\r |
| 478 | }\r |
| 479 | \r |
| 480 | /* code cycles t-bit\r |
| 481 | * 0011 nnnn mmmm 0011 1 comparison result\r |
| 482 | * CMP_GE Rm,Rn\r |
| 483 | */\r |
| 484 | INLINE void CMPGE(UINT32 m, UINT32 n)\r |
| 485 | {\r |
| 486 | if ((INT32) sh2->r[n] >= (INT32) sh2->r[m])\r |
| 487 | sh2->sr |= T;\r |
| 488 | else\r |
| 489 | sh2->sr &= ~T;\r |
| 490 | }\r |
| 491 | \r |
| 492 | /* code cycles t-bit\r |
| 493 | * 0011 nnnn mmmm 0111 1 comparison result\r |
| 494 | * CMP_GT Rm,Rn\r |
| 495 | */\r |
| 496 | INLINE void CMPGT(UINT32 m, UINT32 n)\r |
| 497 | {\r |
| 498 | if ((INT32) sh2->r[n] > (INT32) sh2->r[m])\r |
| 499 | sh2->sr |= T;\r |
| 500 | else\r |
| 501 | sh2->sr &= ~T;\r |
| 502 | }\r |
| 503 | \r |
| 504 | /* code cycles t-bit\r |
| 505 | * 0011 nnnn mmmm 0110 1 comparison result\r |
| 506 | * CMP_HI Rm,Rn\r |
| 507 | */\r |
| 508 | INLINE void CMPHI(UINT32 m, UINT32 n)\r |
| 509 | {\r |
| 510 | if ((UINT32) sh2->r[n] > (UINT32) sh2->r[m])\r |
| 511 | sh2->sr |= T;\r |
| 512 | else\r |
| 513 | sh2->sr &= ~T;\r |
| 514 | }\r |
| 515 | \r |
| 516 | /* code cycles t-bit\r |
| 517 | * 0011 nnnn mmmm 0010 1 comparison result\r |
| 518 | * CMP_HS Rm,Rn\r |
| 519 | */\r |
| 520 | INLINE void CMPHS(UINT32 m, UINT32 n)\r |
| 521 | {\r |
| 522 | if ((UINT32) sh2->r[n] >= (UINT32) sh2->r[m])\r |
| 523 | sh2->sr |= T;\r |
| 524 | else\r |
| 525 | sh2->sr &= ~T;\r |
| 526 | }\r |
| 527 | \r |
| 528 | \r |
| 529 | /* code cycles t-bit\r |
| 530 | * 0100 nnnn 0001 0101 1 comparison result\r |
| 531 | * CMP_PL Rn\r |
| 532 | */\r |
| 533 | INLINE void CMPPL(UINT32 n)\r |
| 534 | {\r |
| 535 | if ((INT32) sh2->r[n] > 0)\r |
| 536 | sh2->sr |= T;\r |
| 537 | else\r |
| 538 | sh2->sr &= ~T;\r |
| 539 | }\r |
| 540 | \r |
| 541 | /* code cycles t-bit\r |
| 542 | * 0100 nnnn 0001 0001 1 comparison result\r |
| 543 | * CMP_PZ Rn\r |
| 544 | */\r |
| 545 | INLINE void CMPPZ(UINT32 n)\r |
| 546 | {\r |
| 547 | if ((INT32) sh2->r[n] >= 0)\r |
| 548 | sh2->sr |= T;\r |
| 549 | else\r |
| 550 | sh2->sr &= ~T;\r |
| 551 | }\r |
| 552 | \r |
| 553 | /* code cycles t-bit\r |
| 554 | * 0010 nnnn mmmm 1100 1 comparison result\r |
| 555 | * CMP_STR Rm,Rn\r |
| 556 | */\r |
| 557 | INLINE void CMPSTR(UINT32 m, UINT32 n)\r |
| 558 | {\r |
| 559 | UINT32 temp;\r |
| 560 | INT32 HH, HL, LH, LL;\r |
| 561 | temp = sh2->r[n] ^ sh2->r[m];\r |
| 562 | HH = (temp >> 24) & 0xff;\r |
| 563 | HL = (temp >> 16) & 0xff;\r |
| 564 | LH = (temp >> 8) & 0xff;\r |
| 565 | LL = temp & 0xff;\r |
| 566 | if (HH && HL && LH && LL)\r |
| 567 | sh2->sr &= ~T;\r |
| 568 | else\r |
| 569 | sh2->sr |= T;\r |
| 570 | }\r |
| 571 | \r |
| 572 | \r |
| 573 | /* code cycles t-bit\r |
| 574 | * 1000 1000 iiii iiii 1 comparison result\r |
| 575 | * CMP/EQ #imm,R0\r |
| 576 | */\r |
| 577 | INLINE void CMPIM(UINT32 i)\r |
| 578 | {\r |
| 579 | UINT32 imm = (UINT32)(INT32)(INT16)(INT8)i;\r |
| 580 | \r |
| 581 | if (sh2->r[0] == imm)\r |
| 582 | sh2->sr |= T;\r |
| 583 | else\r |
| 584 | sh2->sr &= ~T;\r |
| 585 | }\r |
| 586 | \r |
| 587 | /* code cycles t-bit\r |
| 588 | * 0010 nnnn mmmm 0111 1 calculation result\r |
| 589 | * DIV0S Rm,Rn\r |
| 590 | */\r |
| 591 | INLINE void DIV0S(UINT32 m, UINT32 n)\r |
| 592 | {\r |
| 593 | if ((sh2->r[n] & 0x80000000) == 0)\r |
| 594 | sh2->sr &= ~Q;\r |
| 595 | else\r |
| 596 | sh2->sr |= Q;\r |
| 597 | if ((sh2->r[m] & 0x80000000) == 0)\r |
| 598 | sh2->sr &= ~M;\r |
| 599 | else\r |
| 600 | sh2->sr |= M;\r |
| 601 | if ((sh2->r[m] ^ sh2->r[n]) & 0x80000000)\r |
| 602 | sh2->sr |= T;\r |
| 603 | else\r |
| 604 | sh2->sr &= ~T;\r |
| 605 | }\r |
| 606 | \r |
| 607 | /* code cycles t-bit\r |
| 608 | * 0000 0000 0001 1001 1 0\r |
| 609 | * DIV0U\r |
| 610 | */\r |
| 611 | INLINE void DIV0U(void)\r |
| 612 | {\r |
| 613 | sh2->sr &= ~(M | Q | T);\r |
| 614 | }\r |
| 615 | \r |
| 616 | /* code cycles t-bit\r |
| 617 | * 0011 nnnn mmmm 0100 1 calculation result\r |
| 618 | * DIV1 Rm,Rn\r |
| 619 | */\r |
| 620 | INLINE void DIV1(UINT32 m, UINT32 n)\r |
| 621 | {\r |
| 622 | UINT32 tmp0;\r |
| 623 | UINT32 old_q;\r |
| 624 | \r |
| 625 | old_q = sh2->sr & Q;\r |
| 626 | if (0x80000000 & sh2->r[n])\r |
| 627 | sh2->sr |= Q;\r |
| 628 | else\r |
| 629 | sh2->sr &= ~Q;\r |
| 630 | \r |
| 631 | sh2->r[n] = (sh2->r[n] << 1) | (sh2->sr & T);\r |
| 632 | \r |
| 633 | if (!old_q)\r |
| 634 | {\r |
| 635 | if (!(sh2->sr & M))\r |
| 636 | {\r |
| 637 | tmp0 = sh2->r[n];\r |
| 638 | sh2->r[n] -= sh2->r[m];\r |
| 639 | if(!(sh2->sr & Q))\r |
| 640 | if(sh2->r[n] > tmp0)\r |
| 641 | sh2->sr |= Q;\r |
| 642 | else\r |
| 643 | sh2->sr &= ~Q;\r |
| 644 | else\r |
| 645 | if(sh2->r[n] > tmp0)\r |
| 646 | sh2->sr &= ~Q;\r |
| 647 | else\r |
| 648 | sh2->sr |= Q;\r |
| 649 | }\r |
| 650 | else\r |
| 651 | {\r |
| 652 | tmp0 = sh2->r[n];\r |
| 653 | sh2->r[n] += sh2->r[m];\r |
| 654 | if(!(sh2->sr & Q))\r |
| 655 | {\r |
| 656 | if(sh2->r[n] < tmp0)\r |
| 657 | sh2->sr &= ~Q;\r |
| 658 | else\r |
| 659 | sh2->sr |= Q;\r |
| 660 | }\r |
| 661 | else\r |
| 662 | {\r |
| 663 | if(sh2->r[n] < tmp0)\r |
| 664 | sh2->sr |= Q;\r |
| 665 | else\r |
| 666 | sh2->sr &= ~Q;\r |
| 667 | }\r |
| 668 | }\r |
| 669 | }\r |
| 670 | else\r |
| 671 | {\r |
| 672 | if (!(sh2->sr & M))\r |
| 673 | {\r |
| 674 | tmp0 = sh2->r[n];\r |
| 675 | sh2->r[n] += sh2->r[m];\r |
| 676 | if(!(sh2->sr & Q))\r |
| 677 | if(sh2->r[n] < tmp0)\r |
| 678 | sh2->sr |= Q;\r |
| 679 | else\r |
| 680 | sh2->sr &= ~Q;\r |
| 681 | else\r |
| 682 | if(sh2->r[n] < tmp0)\r |
| 683 | sh2->sr &= ~Q;\r |
| 684 | else\r |
| 685 | sh2->sr |= Q;\r |
| 686 | }\r |
| 687 | else\r |
| 688 | {\r |
| 689 | tmp0 = sh2->r[n];\r |
| 690 | sh2->r[n] -= sh2->r[m];\r |
| 691 | if(!(sh2->sr & Q))\r |
| 692 | if(sh2->r[n] > tmp0)\r |
| 693 | sh2->sr &= ~Q;\r |
| 694 | else\r |
| 695 | sh2->sr |= Q;\r |
| 696 | else\r |
| 697 | if(sh2->r[n] > tmp0)\r |
| 698 | sh2->sr |= Q;\r |
| 699 | else\r |
| 700 | sh2->sr &= ~Q;\r |
| 701 | }\r |
| 702 | }\r |
| 703 | \r |
| 704 | tmp0 = (sh2->sr & (Q | M));\r |
| 705 | if((!tmp0) || (tmp0 == 0x300)) /* if Q == M set T else clear T */\r |
| 706 | sh2->sr |= T;\r |
| 707 | else\r |
| 708 | sh2->sr &= ~T;\r |
| 709 | }\r |
| 710 | \r |
| 711 | /* DMULS.L Rm,Rn */\r |
| 712 | INLINE void DMULS(UINT32 m, UINT32 n)\r |
| 713 | {\r |
| 714 | UINT32 RnL, RnH, RmL, RmH, Res0, Res1, Res2;\r |
| 715 | UINT32 temp0, temp1, temp2, temp3;\r |
| 716 | INT32 tempm, tempn, fnLmL;\r |
| 717 | \r |
| 718 | tempn = (INT32) sh2->r[n];\r |
| 719 | tempm = (INT32) sh2->r[m];\r |
| 720 | if (tempn < 0)\r |
| 721 | tempn = 0 - tempn;\r |
| 722 | if (tempm < 0)\r |
| 723 | tempm = 0 - tempm;\r |
| 724 | if ((INT32) (sh2->r[n] ^ sh2->r[m]) < 0)\r |
| 725 | fnLmL = -1;\r |
| 726 | else\r |
| 727 | fnLmL = 0;\r |
| 728 | temp1 = (UINT32) tempn;\r |
| 729 | temp2 = (UINT32) tempm;\r |
| 730 | RnL = temp1 & 0x0000ffff;\r |
| 731 | RnH = (temp1 >> 16) & 0x0000ffff;\r |
| 732 | RmL = temp2 & 0x0000ffff;\r |
| 733 | RmH = (temp2 >> 16) & 0x0000ffff;\r |
| 734 | temp0 = RmL * RnL;\r |
| 735 | temp1 = RmH * RnL;\r |
| 736 | temp2 = RmL * RnH;\r |
| 737 | temp3 = RmH * RnH;\r |
| 738 | Res2 = 0;\r |
| 739 | Res1 = temp1 + temp2;\r |
| 740 | if (Res1 < temp1)\r |
| 741 | Res2 += 0x00010000;\r |
| 742 | temp1 = (Res1 << 16) & 0xffff0000;\r |
| 743 | Res0 = temp0 + temp1;\r |
| 744 | if (Res0 < temp0)\r |
| 745 | Res2++;\r |
| 746 | Res2 = Res2 + ((Res1 >> 16) & 0x0000ffff) + temp3;\r |
| 747 | if (fnLmL < 0)\r |
| 748 | {\r |
| 749 | Res2 = ~Res2;\r |
| 750 | if (Res0 == 0)\r |
| 751 | Res2++;\r |
| 752 | else\r |
| 753 | Res0 = (~Res0) + 1;\r |
| 754 | }\r |
| 755 | sh2->mach = Res2;\r |
| 756 | sh2->macl = Res0;\r |
| 757 | sh2_icount--;\r |
| 758 | }\r |
| 759 | \r |
| 760 | /* DMULU.L Rm,Rn */\r |
| 761 | INLINE void DMULU(UINT32 m, UINT32 n)\r |
| 762 | {\r |
| 763 | UINT32 RnL, RnH, RmL, RmH, Res0, Res1, Res2;\r |
| 764 | UINT32 temp0, temp1, temp2, temp3;\r |
| 765 | \r |
| 766 | RnL = sh2->r[n] & 0x0000ffff;\r |
| 767 | RnH = (sh2->r[n] >> 16) & 0x0000ffff;\r |
| 768 | RmL = sh2->r[m] & 0x0000ffff;\r |
| 769 | RmH = (sh2->r[m] >> 16) & 0x0000ffff;\r |
| 770 | temp0 = RmL * RnL;\r |
| 771 | temp1 = RmH * RnL;\r |
| 772 | temp2 = RmL * RnH;\r |
| 773 | temp3 = RmH * RnH;\r |
| 774 | Res2 = 0;\r |
| 775 | Res1 = temp1 + temp2;\r |
| 776 | if (Res1 < temp1)\r |
| 777 | Res2 += 0x00010000;\r |
| 778 | temp1 = (Res1 << 16) & 0xffff0000;\r |
| 779 | Res0 = temp0 + temp1;\r |
| 780 | if (Res0 < temp0)\r |
| 781 | Res2++;\r |
| 782 | Res2 = Res2 + ((Res1 >> 16) & 0x0000ffff) + temp3;\r |
| 783 | sh2->mach = Res2;\r |
| 784 | sh2->macl = Res0;\r |
| 785 | sh2_icount--;\r |
| 786 | }\r |
| 787 | \r |
| 788 | /* DT Rn */\r |
| 789 | INLINE void DT(UINT32 n)\r |
| 790 | {\r |
| 791 | sh2->r[n]--;\r |
| 792 | if (sh2->r[n] == 0)\r |
| 793 | sh2->sr |= T;\r |
| 794 | else\r |
| 795 | sh2->sr &= ~T;\r |
| 796 | #if BUSY_LOOP_HACKS\r |
| 797 | {\r |
| 798 | UINT32 next_opcode = RW(sh2->pc & AM);\r |
| 799 | /* DT Rn\r |
| 800 | * BF $-2\r |
| 801 | */\r |
| 802 | if (next_opcode == 0x8bfd)\r |
| 803 | {\r |
| 804 | while (sh2->r[n] > 1 && sh2_icount > 4)\r |
| 805 | {\r |
| 806 | sh2->r[n]--;\r |
| 807 | sh2_icount -= 4; /* cycles for DT (1) and BF taken (3) */\r |
| 808 | }\r |
| 809 | }\r |
| 810 | }\r |
| 811 | #endif\r |
| 812 | }\r |
| 813 | \r |
| 814 | /* EXTS.B Rm,Rn */\r |
| 815 | INLINE void EXTSB(UINT32 m, UINT32 n)\r |
| 816 | {\r |
| 817 | sh2->r[n] = ((INT32)sh2->r[m] << 24) >> 24;\r |
| 818 | }\r |
| 819 | \r |
| 820 | /* EXTS.W Rm,Rn */\r |
| 821 | INLINE void EXTSW(UINT32 m, UINT32 n)\r |
| 822 | {\r |
| 823 | sh2->r[n] = ((INT32)sh2->r[m] << 16) >> 16;\r |
| 824 | }\r |
| 825 | \r |
| 826 | /* EXTU.B Rm,Rn */\r |
| 827 | INLINE void EXTUB(UINT32 m, UINT32 n)\r |
| 828 | {\r |
| 829 | sh2->r[n] = sh2->r[m] & 0x000000ff;\r |
| 830 | }\r |
| 831 | \r |
| 832 | /* EXTU.W Rm,Rn */\r |
| 833 | INLINE void EXTUW(UINT32 m, UINT32 n)\r |
| 834 | {\r |
| 835 | sh2->r[n] = sh2->r[m] & 0x0000ffff;\r |
| 836 | }\r |
| 837 | \r |
| 838 | /* JMP @Rm */\r |
| 839 | INLINE void JMP(UINT32 m)\r |
| 840 | {\r |
| 841 | sh2->delay = sh2->pc;\r |
| 842 | sh2->pc = sh2->ea = sh2->r[m];\r |
| 843 | }\r |
| 844 | \r |
| 845 | /* JSR @Rm */\r |
| 846 | INLINE void JSR(UINT32 m)\r |
| 847 | {\r |
| 848 | sh2->delay = sh2->pc;\r |
| 849 | sh2->pr = sh2->pc + 2;\r |
| 850 | sh2->pc = sh2->ea = sh2->r[m];\r |
| 851 | sh2_icount--;\r |
| 852 | }\r |
| 853 | \r |
| 854 | \r |
| 855 | /* LDC Rm,SR */\r |
| 856 | INLINE void LDCSR(UINT32 m)\r |
| 857 | {\r |
| 858 | sh2->sr = sh2->r[m] & FLAGS;\r |
| 859 | sh2->test_irq = 1;\r |
| 860 | }\r |
| 861 | \r |
| 862 | /* LDC Rm,GBR */\r |
| 863 | INLINE void LDCGBR(UINT32 m)\r |
| 864 | {\r |
| 865 | sh2->gbr = sh2->r[m];\r |
| 866 | }\r |
| 867 | \r |
| 868 | /* LDC Rm,VBR */\r |
| 869 | INLINE void LDCVBR(UINT32 m)\r |
| 870 | {\r |
| 871 | sh2->vbr = sh2->r[m];\r |
| 872 | }\r |
| 873 | \r |
| 874 | /* LDC.L @Rm+,SR */\r |
| 875 | INLINE void LDCMSR(UINT32 m)\r |
| 876 | {\r |
| 877 | sh2->ea = sh2->r[m];\r |
| 878 | sh2->sr = RL( sh2->ea ) & FLAGS;\r |
| 879 | sh2->r[m] += 4;\r |
| 880 | sh2_icount -= 2;\r |
| 881 | sh2->test_irq = 1;\r |
| 882 | }\r |
| 883 | \r |
| 884 | /* LDC.L @Rm+,GBR */\r |
| 885 | INLINE void LDCMGBR(UINT32 m)\r |
| 886 | {\r |
| 887 | sh2->ea = sh2->r[m];\r |
| 888 | sh2->gbr = RL( sh2->ea );\r |
| 889 | sh2->r[m] += 4;\r |
| 890 | sh2_icount -= 2;\r |
| 891 | }\r |
| 892 | \r |
| 893 | /* LDC.L @Rm+,VBR */\r |
| 894 | INLINE void LDCMVBR(UINT32 m)\r |
| 895 | {\r |
| 896 | sh2->ea = sh2->r[m];\r |
| 897 | sh2->vbr = RL( sh2->ea );\r |
| 898 | sh2->r[m] += 4;\r |
| 899 | sh2_icount -= 2;\r |
| 900 | }\r |
| 901 | \r |
| 902 | /* LDS Rm,MACH */\r |
| 903 | INLINE void LDSMACH(UINT32 m)\r |
| 904 | {\r |
| 905 | sh2->mach = sh2->r[m];\r |
| 906 | }\r |
| 907 | \r |
| 908 | /* LDS Rm,MACL */\r |
| 909 | INLINE void LDSMACL(UINT32 m)\r |
| 910 | {\r |
| 911 | sh2->macl = sh2->r[m];\r |
| 912 | }\r |
| 913 | \r |
| 914 | /* LDS Rm,PR */\r |
| 915 | INLINE void LDSPR(UINT32 m)\r |
| 916 | {\r |
| 917 | sh2->pr = sh2->r[m];\r |
| 918 | }\r |
| 919 | \r |
| 920 | /* LDS.L @Rm+,MACH */\r |
| 921 | INLINE void LDSMMACH(UINT32 m)\r |
| 922 | {\r |
| 923 | sh2->ea = sh2->r[m];\r |
| 924 | sh2->mach = RL( sh2->ea );\r |
| 925 | sh2->r[m] += 4;\r |
| 926 | }\r |
| 927 | \r |
| 928 | /* LDS.L @Rm+,MACL */\r |
| 929 | INLINE void LDSMMACL(UINT32 m)\r |
| 930 | {\r |
| 931 | sh2->ea = sh2->r[m];\r |
| 932 | sh2->macl = RL( sh2->ea );\r |
| 933 | sh2->r[m] += 4;\r |
| 934 | }\r |
| 935 | \r |
| 936 | /* LDS.L @Rm+,PR */\r |
| 937 | INLINE void LDSMPR(UINT32 m)\r |
| 938 | {\r |
| 939 | sh2->ea = sh2->r[m];\r |
| 940 | sh2->pr = RL( sh2->ea );\r |
| 941 | sh2->r[m] += 4;\r |
| 942 | }\r |
| 943 | \r |
| 944 | /* MAC.L @Rm+,@Rn+ */\r |
| 945 | INLINE void MAC_L(UINT32 m, UINT32 n)\r |
| 946 | {\r |
| 947 | UINT32 RnL, RnH, RmL, RmH, Res0, Res1, Res2;\r |
| 948 | UINT32 temp0, temp1, temp2, temp3;\r |
| 949 | INT32 tempm, tempn, fnLmL;\r |
| 950 | \r |
| 951 | tempn = (INT32) RL( sh2->r[n] );\r |
| 952 | sh2->r[n] += 4;\r |
| 953 | tempm = (INT32) RL( sh2->r[m] );\r |
| 954 | sh2->r[m] += 4;\r |
| 955 | if ((INT32) (tempn ^ tempm) < 0)\r |
| 956 | fnLmL = -1;\r |
| 957 | else\r |
| 958 | fnLmL = 0;\r |
| 959 | if (tempn < 0)\r |
| 960 | tempn = 0 - tempn;\r |
| 961 | if (tempm < 0)\r |
| 962 | tempm = 0 - tempm;\r |
| 963 | temp1 = (UINT32) tempn;\r |
| 964 | temp2 = (UINT32) tempm;\r |
| 965 | RnL = temp1 & 0x0000ffff;\r |
| 966 | RnH = (temp1 >> 16) & 0x0000ffff;\r |
| 967 | RmL = temp2 & 0x0000ffff;\r |
| 968 | RmH = (temp2 >> 16) & 0x0000ffff;\r |
| 969 | temp0 = RmL * RnL;\r |
| 970 | temp1 = RmH * RnL;\r |
| 971 | temp2 = RmL * RnH;\r |
| 972 | temp3 = RmH * RnH;\r |
| 973 | Res2 = 0;\r |
| 974 | Res1 = temp1 + temp2;\r |
| 975 | if (Res1 < temp1)\r |
| 976 | Res2 += 0x00010000;\r |
| 977 | temp1 = (Res1 << 16) & 0xffff0000;\r |
| 978 | Res0 = temp0 + temp1;\r |
| 979 | if (Res0 < temp0)\r |
| 980 | Res2++;\r |
| 981 | Res2 = Res2 + ((Res1 >> 16) & 0x0000ffff) + temp3;\r |
| 982 | if (fnLmL < 0)\r |
| 983 | {\r |
| 984 | Res2 = ~Res2;\r |
| 985 | if (Res0 == 0)\r |
| 986 | Res2++;\r |
| 987 | else\r |
| 988 | Res0 = (~Res0) + 1;\r |
| 989 | }\r |
| 990 | if (sh2->sr & S)\r |
| 991 | {\r |
| 992 | Res0 = sh2->macl + Res0;\r |
| 993 | if (sh2->macl > Res0)\r |
| 994 | Res2++;\r |
| 995 | Res2 += (sh2->mach & 0x0000ffff);\r |
| 996 | if (((INT32) Res2 < 0) && (Res2 < 0xffff8000))\r |
| 997 | {\r |
| 998 | Res2 = 0x00008000;\r |
| 999 | Res0 = 0x00000000;\r |
| 1000 | }\r |
| 1001 | else if (((INT32) Res2 > 0) && (Res2 > 0x00007fff))\r |
| 1002 | {\r |
| 1003 | Res2 = 0x00007fff;\r |
| 1004 | Res0 = 0xffffffff;\r |
| 1005 | }\r |
| 1006 | sh2->mach = Res2;\r |
| 1007 | sh2->macl = Res0;\r |
| 1008 | }\r |
| 1009 | else\r |
| 1010 | {\r |
| 1011 | Res0 = sh2->macl + Res0;\r |
| 1012 | if (sh2->macl > Res0)\r |
| 1013 | Res2++;\r |
| 1014 | Res2 += sh2->mach;\r |
| 1015 | sh2->mach = Res2;\r |
| 1016 | sh2->macl = Res0;\r |
| 1017 | }\r |
| 1018 | sh2_icount -= 2;\r |
| 1019 | }\r |
| 1020 | \r |
| 1021 | /* MAC.W @Rm+,@Rn+ */\r |
| 1022 | INLINE void MAC_W(UINT32 m, UINT32 n)\r |
| 1023 | {\r |
| 1024 | INT32 tempm, tempn, dest, src, ans;\r |
| 1025 | UINT32 templ;\r |
| 1026 | \r |
| 1027 | tempn = (INT32) RW( sh2->r[n] );\r |
| 1028 | sh2->r[n] += 2;\r |
| 1029 | tempm = (INT32) RW( sh2->r[m] );\r |
| 1030 | sh2->r[m] += 2;\r |
| 1031 | templ = sh2->macl;\r |
| 1032 | tempm = ((INT32) (short) tempn * (INT32) (short) tempm);\r |
| 1033 | if ((INT32) sh2->macl >= 0)\r |
| 1034 | dest = 0;\r |
| 1035 | else\r |
| 1036 | dest = 1;\r |
| 1037 | if ((INT32) tempm >= 0)\r |
| 1038 | {\r |
| 1039 | src = 0;\r |
| 1040 | tempn = 0;\r |
| 1041 | }\r |
| 1042 | else\r |
| 1043 | {\r |
| 1044 | src = 1;\r |
| 1045 | tempn = 0xffffffff;\r |
| 1046 | }\r |
| 1047 | src += dest;\r |
| 1048 | sh2->macl += tempm;\r |
| 1049 | if ((INT32) sh2->macl >= 0)\r |
| 1050 | ans = 0;\r |
| 1051 | else\r |
| 1052 | ans = 1;\r |
| 1053 | ans += dest;\r |
| 1054 | if (sh2->sr & S)\r |
| 1055 | {\r |
| 1056 | if (ans == 1)\r |
| 1057 | {\r |
| 1058 | if (src == 0)\r |
| 1059 | sh2->macl = 0x7fffffff;\r |
| 1060 | if (src == 2)\r |
| 1061 | sh2->macl = 0x80000000;\r |
| 1062 | }\r |
| 1063 | }\r |
| 1064 | else\r |
| 1065 | {\r |
| 1066 | sh2->mach += tempn;\r |
| 1067 | if (templ > sh2->macl)\r |
| 1068 | sh2->mach += 1;\r |
| 1069 | }\r |
| 1070 | sh2_icount -= 2;\r |
| 1071 | }\r |
| 1072 | \r |
| 1073 | /* MOV Rm,Rn */\r |
| 1074 | INLINE void MOV(UINT32 m, UINT32 n)\r |
| 1075 | {\r |
| 1076 | sh2->r[n] = sh2->r[m];\r |
| 1077 | }\r |
| 1078 | \r |
| 1079 | /* MOV.B Rm,@Rn */\r |
| 1080 | INLINE void MOVBS(UINT32 m, UINT32 n)\r |
| 1081 | {\r |
| 1082 | sh2->ea = sh2->r[n];\r |
| 1083 | WB( sh2->ea, sh2->r[m] & 0x000000ff);\r |
| 1084 | }\r |
| 1085 | \r |
| 1086 | /* MOV.W Rm,@Rn */\r |
| 1087 | INLINE void MOVWS(UINT32 m, UINT32 n)\r |
| 1088 | {\r |
| 1089 | sh2->ea = sh2->r[n];\r |
| 1090 | WW( sh2->ea, sh2->r[m] & 0x0000ffff);\r |
| 1091 | }\r |
| 1092 | \r |
| 1093 | /* MOV.L Rm,@Rn */\r |
| 1094 | INLINE void MOVLS(UINT32 m, UINT32 n)\r |
| 1095 | {\r |
| 1096 | sh2->ea = sh2->r[n];\r |
| 1097 | WL( sh2->ea, sh2->r[m] );\r |
| 1098 | }\r |
| 1099 | \r |
| 1100 | /* MOV.B @Rm,Rn */\r |
| 1101 | INLINE void MOVBL(UINT32 m, UINT32 n)\r |
| 1102 | {\r |
| 1103 | sh2->ea = sh2->r[m];\r |
| 1104 | sh2->r[n] = (UINT32)(INT32)(INT16)(INT8) RB( sh2->ea );\r |
| 1105 | }\r |
| 1106 | \r |
| 1107 | /* MOV.W @Rm,Rn */\r |
| 1108 | INLINE void MOVWL(UINT32 m, UINT32 n)\r |
| 1109 | {\r |
| 1110 | sh2->ea = sh2->r[m];\r |
| 1111 | sh2->r[n] = (UINT32)(INT32)(INT16) RW( sh2->ea );\r |
| 1112 | }\r |
| 1113 | \r |
| 1114 | /* MOV.L @Rm,Rn */\r |
| 1115 | INLINE void MOVLL(UINT32 m, UINT32 n)\r |
| 1116 | {\r |
| 1117 | sh2->ea = sh2->r[m];\r |
| 1118 | sh2->r[n] = RL( sh2->ea );\r |
| 1119 | }\r |
| 1120 | \r |
| 1121 | /* MOV.B Rm,@-Rn */\r |
| 1122 | INLINE void MOVBM(UINT32 m, UINT32 n)\r |
| 1123 | {\r |
| 1124 | /* SMG : bug fix, was reading sh2->r[n] */\r |
| 1125 | UINT32 data = sh2->r[m] & 0x000000ff;\r |
| 1126 | \r |
| 1127 | sh2->r[n] -= 1;\r |
| 1128 | WB( sh2->r[n], data );\r |
| 1129 | }\r |
| 1130 | \r |
| 1131 | /* MOV.W Rm,@-Rn */\r |
| 1132 | INLINE void MOVWM(UINT32 m, UINT32 n)\r |
| 1133 | {\r |
| 1134 | UINT32 data = sh2->r[m] & 0x0000ffff;\r |
| 1135 | \r |
| 1136 | sh2->r[n] -= 2;\r |
| 1137 | WW( sh2->r[n], data );\r |
| 1138 | }\r |
| 1139 | \r |
| 1140 | /* MOV.L Rm,@-Rn */\r |
| 1141 | INLINE void MOVLM(UINT32 m, UINT32 n)\r |
| 1142 | {\r |
| 1143 | UINT32 data = sh2->r[m];\r |
| 1144 | \r |
| 1145 | sh2->r[n] -= 4;\r |
| 1146 | WL( sh2->r[n], data );\r |
| 1147 | }\r |
| 1148 | \r |
| 1149 | /* MOV.B @Rm+,Rn */\r |
| 1150 | INLINE void MOVBP(UINT32 m, UINT32 n)\r |
| 1151 | {\r |
| 1152 | sh2->r[n] = (UINT32)(INT32)(INT16)(INT8) RB( sh2->r[m] );\r |
| 1153 | if (n != m)\r |
| 1154 | sh2->r[m] += 1;\r |
| 1155 | }\r |
| 1156 | \r |
| 1157 | /* MOV.W @Rm+,Rn */\r |
| 1158 | INLINE void MOVWP(UINT32 m, UINT32 n)\r |
| 1159 | {\r |
| 1160 | sh2->r[n] = (UINT32)(INT32)(INT16) RW( sh2->r[m] );\r |
| 1161 | if (n != m)\r |
| 1162 | sh2->r[m] += 2;\r |
| 1163 | }\r |
| 1164 | \r |
| 1165 | /* MOV.L @Rm+,Rn */\r |
| 1166 | INLINE void MOVLP(UINT32 m, UINT32 n)\r |
| 1167 | {\r |
| 1168 | sh2->r[n] = RL( sh2->r[m] );\r |
| 1169 | if (n != m)\r |
| 1170 | sh2->r[m] += 4;\r |
| 1171 | }\r |
| 1172 | \r |
| 1173 | /* MOV.B Rm,@(R0,Rn) */\r |
| 1174 | INLINE void MOVBS0(UINT32 m, UINT32 n)\r |
| 1175 | {\r |
| 1176 | sh2->ea = sh2->r[n] + sh2->r[0];\r |
| 1177 | WB( sh2->ea, sh2->r[m] & 0x000000ff );\r |
| 1178 | }\r |
| 1179 | \r |
| 1180 | /* MOV.W Rm,@(R0,Rn) */\r |
| 1181 | INLINE void MOVWS0(UINT32 m, UINT32 n)\r |
| 1182 | {\r |
| 1183 | sh2->ea = sh2->r[n] + sh2->r[0];\r |
| 1184 | WW( sh2->ea, sh2->r[m] & 0x0000ffff );\r |
| 1185 | }\r |
| 1186 | \r |
| 1187 | /* MOV.L Rm,@(R0,Rn) */\r |
| 1188 | INLINE void MOVLS0(UINT32 m, UINT32 n)\r |
| 1189 | {\r |
| 1190 | sh2->ea = sh2->r[n] + sh2->r[0];\r |
| 1191 | WL( sh2->ea, sh2->r[m] );\r |
| 1192 | }\r |
| 1193 | \r |
| 1194 | /* MOV.B @(R0,Rm),Rn */\r |
| 1195 | INLINE void MOVBL0(UINT32 m, UINT32 n)\r |
| 1196 | {\r |
| 1197 | sh2->ea = sh2->r[m] + sh2->r[0];\r |
| 1198 | sh2->r[n] = (UINT32)(INT32)(INT16)(INT8) RB( sh2->ea );\r |
| 1199 | }\r |
| 1200 | \r |
| 1201 | /* MOV.W @(R0,Rm),Rn */\r |
| 1202 | INLINE void MOVWL0(UINT32 m, UINT32 n)\r |
| 1203 | {\r |
| 1204 | sh2->ea = sh2->r[m] + sh2->r[0];\r |
| 1205 | sh2->r[n] = (UINT32)(INT32)(INT16) RW( sh2->ea );\r |
| 1206 | }\r |
| 1207 | \r |
| 1208 | /* MOV.L @(R0,Rm),Rn */\r |
| 1209 | INLINE void MOVLL0(UINT32 m, UINT32 n)\r |
| 1210 | {\r |
| 1211 | sh2->ea = sh2->r[m] + sh2->r[0];\r |
| 1212 | sh2->r[n] = RL( sh2->ea );\r |
| 1213 | }\r |
| 1214 | \r |
| 1215 | /* MOV #imm,Rn */\r |
| 1216 | INLINE void MOVI(UINT32 i, UINT32 n)\r |
| 1217 | {\r |
| 1218 | sh2->r[n] = (UINT32)(INT32)(INT16)(INT8) i;\r |
| 1219 | }\r |
| 1220 | \r |
| 1221 | /* MOV.W @(disp8,PC),Rn */\r |
| 1222 | INLINE void MOVWI(UINT32 d, UINT32 n)\r |
| 1223 | {\r |
| 1224 | UINT32 disp = d & 0xff;\r |
| 1225 | sh2->ea = sh2->pc + disp * 2 + 2;\r |
| 1226 | sh2->r[n] = (UINT32)(INT32)(INT16) RW( sh2->ea );\r |
| 1227 | }\r |
| 1228 | \r |
| 1229 | /* MOV.L @(disp8,PC),Rn */\r |
| 1230 | INLINE void MOVLI(UINT32 d, UINT32 n)\r |
| 1231 | {\r |
| 1232 | UINT32 disp = d & 0xff;\r |
| 1233 | sh2->ea = ((sh2->pc + 2) & ~3) + disp * 4;\r |
| 1234 | sh2->r[n] = RL( sh2->ea );\r |
| 1235 | }\r |
| 1236 | \r |
| 1237 | /* MOV.B @(disp8,GBR),R0 */\r |
| 1238 | INLINE void MOVBLG(UINT32 d)\r |
| 1239 | {\r |
| 1240 | UINT32 disp = d & 0xff;\r |
| 1241 | sh2->ea = sh2->gbr + disp;\r |
| 1242 | sh2->r[0] = (UINT32)(INT32)(INT16)(INT8) RB( sh2->ea );\r |
| 1243 | }\r |
| 1244 | \r |
| 1245 | /* MOV.W @(disp8,GBR),R0 */\r |
| 1246 | INLINE void MOVWLG(UINT32 d)\r |
| 1247 | {\r |
| 1248 | UINT32 disp = d & 0xff;\r |
| 1249 | sh2->ea = sh2->gbr + disp * 2;\r |
| 1250 | sh2->r[0] = (INT32)(INT16) RW( sh2->ea );\r |
| 1251 | }\r |
| 1252 | \r |
| 1253 | /* MOV.L @(disp8,GBR),R0 */\r |
| 1254 | INLINE void MOVLLG(UINT32 d)\r |
| 1255 | {\r |
| 1256 | UINT32 disp = d & 0xff;\r |
| 1257 | sh2->ea = sh2->gbr + disp * 4;\r |
| 1258 | sh2->r[0] = RL( sh2->ea );\r |
| 1259 | }\r |
| 1260 | \r |
| 1261 | /* MOV.B R0,@(disp8,GBR) */\r |
| 1262 | INLINE void MOVBSG(UINT32 d)\r |
| 1263 | {\r |
| 1264 | UINT32 disp = d & 0xff;\r |
| 1265 | sh2->ea = sh2->gbr + disp;\r |
| 1266 | WB( sh2->ea, sh2->r[0] & 0x000000ff );\r |
| 1267 | }\r |
| 1268 | \r |
| 1269 | /* MOV.W R0,@(disp8,GBR) */\r |
| 1270 | INLINE void MOVWSG(UINT32 d)\r |
| 1271 | {\r |
| 1272 | UINT32 disp = d & 0xff;\r |
| 1273 | sh2->ea = sh2->gbr + disp * 2;\r |
| 1274 | WW( sh2->ea, sh2->r[0] & 0x0000ffff );\r |
| 1275 | }\r |
| 1276 | \r |
| 1277 | /* MOV.L R0,@(disp8,GBR) */\r |
| 1278 | INLINE void MOVLSG(UINT32 d)\r |
| 1279 | {\r |
| 1280 | UINT32 disp = d & 0xff;\r |
| 1281 | sh2->ea = sh2->gbr + disp * 4;\r |
| 1282 | WL( sh2->ea, sh2->r[0] );\r |
| 1283 | }\r |
| 1284 | \r |
| 1285 | /* MOV.B R0,@(disp4,Rn) */\r |
| 1286 | INLINE void MOVBS4(UINT32 d, UINT32 n)\r |
| 1287 | {\r |
| 1288 | UINT32 disp = d & 0x0f;\r |
| 1289 | sh2->ea = sh2->r[n] + disp;\r |
| 1290 | WB( sh2->ea, sh2->r[0] & 0x000000ff );\r |
| 1291 | }\r |
| 1292 | \r |
| 1293 | /* MOV.W R0,@(disp4,Rn) */\r |
| 1294 | INLINE void MOVWS4(UINT32 d, UINT32 n)\r |
| 1295 | {\r |
| 1296 | UINT32 disp = d & 0x0f;\r |
| 1297 | sh2->ea = sh2->r[n] + disp * 2;\r |
| 1298 | WW( sh2->ea, sh2->r[0] & 0x0000ffff );\r |
| 1299 | }\r |
| 1300 | \r |
| 1301 | /* MOV.L Rm,@(disp4,Rn) */\r |
| 1302 | INLINE void MOVLS4(UINT32 m, UINT32 d, UINT32 n)\r |
| 1303 | {\r |
| 1304 | UINT32 disp = d & 0x0f;\r |
| 1305 | sh2->ea = sh2->r[n] + disp * 4;\r |
| 1306 | WL( sh2->ea, sh2->r[m] );\r |
| 1307 | }\r |
| 1308 | \r |
| 1309 | /* MOV.B @(disp4,Rm),R0 */\r |
| 1310 | INLINE void MOVBL4(UINT32 m, UINT32 d)\r |
| 1311 | {\r |
| 1312 | UINT32 disp = d & 0x0f;\r |
| 1313 | sh2->ea = sh2->r[m] + disp;\r |
| 1314 | sh2->r[0] = (UINT32)(INT32)(INT16)(INT8) RB( sh2->ea );\r |
| 1315 | }\r |
| 1316 | \r |
| 1317 | /* MOV.W @(disp4,Rm),R0 */\r |
| 1318 | INLINE void MOVWL4(UINT32 m, UINT32 d)\r |
| 1319 | {\r |
| 1320 | UINT32 disp = d & 0x0f;\r |
| 1321 | sh2->ea = sh2->r[m] + disp * 2;\r |
| 1322 | sh2->r[0] = (UINT32)(INT32)(INT16) RW( sh2->ea );\r |
| 1323 | }\r |
| 1324 | \r |
| 1325 | /* MOV.L @(disp4,Rm),Rn */\r |
| 1326 | INLINE void MOVLL4(UINT32 m, UINT32 d, UINT32 n)\r |
| 1327 | {\r |
| 1328 | UINT32 disp = d & 0x0f;\r |
| 1329 | sh2->ea = sh2->r[m] + disp * 4;\r |
| 1330 | sh2->r[n] = RL( sh2->ea );\r |
| 1331 | }\r |
| 1332 | \r |
| 1333 | /* MOVA @(disp8,PC),R0 */\r |
| 1334 | INLINE void MOVA(UINT32 d)\r |
| 1335 | {\r |
| 1336 | UINT32 disp = d & 0xff;\r |
| 1337 | sh2->ea = ((sh2->pc + 2) & ~3) + disp * 4;\r |
| 1338 | sh2->r[0] = sh2->ea;\r |
| 1339 | }\r |
| 1340 | \r |
| 1341 | /* MOVT Rn */\r |
| 1342 | INLINE void MOVT(UINT32 n)\r |
| 1343 | {\r |
| 1344 | sh2->r[n] = sh2->sr & T;\r |
| 1345 | }\r |
| 1346 | \r |
| 1347 | /* MUL.L Rm,Rn */\r |
| 1348 | INLINE void MULL(UINT32 m, UINT32 n)\r |
| 1349 | {\r |
| 1350 | sh2->macl = sh2->r[n] * sh2->r[m];\r |
| 1351 | sh2_icount--;\r |
| 1352 | }\r |
| 1353 | \r |
| 1354 | /* MULS Rm,Rn */\r |
| 1355 | INLINE void MULS(UINT32 m, UINT32 n)\r |
| 1356 | {\r |
| 1357 | sh2->macl = (INT16) sh2->r[n] * (INT16) sh2->r[m];\r |
| 1358 | }\r |
| 1359 | \r |
| 1360 | /* MULU Rm,Rn */\r |
| 1361 | INLINE void MULU(UINT32 m, UINT32 n)\r |
| 1362 | {\r |
| 1363 | sh2->macl = (UINT16) sh2->r[n] * (UINT16) sh2->r[m];\r |
| 1364 | }\r |
| 1365 | \r |
| 1366 | /* NEG Rm,Rn */\r |
| 1367 | INLINE void NEG(UINT32 m, UINT32 n)\r |
| 1368 | {\r |
| 1369 | sh2->r[n] = 0 - sh2->r[m];\r |
| 1370 | }\r |
| 1371 | \r |
| 1372 | /* NEGC Rm,Rn */\r |
| 1373 | INLINE void NEGC(UINT32 m, UINT32 n)\r |
| 1374 | {\r |
| 1375 | UINT32 temp;\r |
| 1376 | \r |
| 1377 | temp = sh2->r[m];\r |
| 1378 | sh2->r[n] = -temp - (sh2->sr & T);\r |
| 1379 | if (temp || (sh2->sr & T))\r |
| 1380 | sh2->sr |= T;\r |
| 1381 | else\r |
| 1382 | sh2->sr &= ~T;\r |
| 1383 | }\r |
| 1384 | \r |
| 1385 | /* NOP */\r |
| 1386 | INLINE void NOP(void)\r |
| 1387 | {\r |
| 1388 | }\r |
| 1389 | \r |
| 1390 | /* NOT Rm,Rn */\r |
| 1391 | INLINE void NOT(UINT32 m, UINT32 n)\r |
| 1392 | {\r |
| 1393 | sh2->r[n] = ~sh2->r[m];\r |
| 1394 | }\r |
| 1395 | \r |
| 1396 | /* OR Rm,Rn */\r |
| 1397 | INLINE void OR(UINT32 m, UINT32 n)\r |
| 1398 | {\r |
| 1399 | sh2->r[n] |= sh2->r[m];\r |
| 1400 | }\r |
| 1401 | \r |
| 1402 | /* OR #imm,R0 */\r |
| 1403 | INLINE void ORI(UINT32 i)\r |
| 1404 | {\r |
| 1405 | sh2->r[0] |= i;\r |
| 1406 | sh2_icount -= 2;\r |
| 1407 | }\r |
| 1408 | \r |
| 1409 | /* OR.B #imm,@(R0,GBR) */\r |
| 1410 | INLINE void ORM(UINT32 i)\r |
| 1411 | {\r |
| 1412 | UINT32 temp;\r |
| 1413 | \r |
| 1414 | sh2->ea = sh2->gbr + sh2->r[0];\r |
| 1415 | temp = RB( sh2->ea );\r |
| 1416 | temp |= i;\r |
| 1417 | WB( sh2->ea, temp );\r |
| 1418 | }\r |
| 1419 | \r |
| 1420 | /* ROTCL Rn */\r |
| 1421 | INLINE void ROTCL(UINT32 n)\r |
| 1422 | {\r |
| 1423 | UINT32 temp;\r |
| 1424 | \r |
| 1425 | temp = (sh2->r[n] >> 31) & T;\r |
| 1426 | sh2->r[n] = (sh2->r[n] << 1) | (sh2->sr & T);\r |
| 1427 | sh2->sr = (sh2->sr & ~T) | temp;\r |
| 1428 | }\r |
| 1429 | \r |
| 1430 | /* ROTCR Rn */\r |
| 1431 | INLINE void ROTCR(UINT32 n)\r |
| 1432 | {\r |
| 1433 | UINT32 temp;\r |
| 1434 | temp = (sh2->sr & T) << 31;\r |
| 1435 | if (sh2->r[n] & T)\r |
| 1436 | sh2->sr |= T;\r |
| 1437 | else\r |
| 1438 | sh2->sr &= ~T;\r |
| 1439 | sh2->r[n] = (sh2->r[n] >> 1) | temp;\r |
| 1440 | }\r |
| 1441 | \r |
| 1442 | /* ROTL Rn */\r |
| 1443 | INLINE void ROTL(UINT32 n)\r |
| 1444 | {\r |
| 1445 | sh2->sr = (sh2->sr & ~T) | ((sh2->r[n] >> 31) & T);\r |
| 1446 | sh2->r[n] = (sh2->r[n] << 1) | (sh2->r[n] >> 31);\r |
| 1447 | }\r |
| 1448 | \r |
| 1449 | /* ROTR Rn */\r |
| 1450 | INLINE void ROTR(UINT32 n)\r |
| 1451 | {\r |
| 1452 | sh2->sr = (sh2->sr & ~T) | (sh2->r[n] & T);\r |
| 1453 | sh2->r[n] = (sh2->r[n] >> 1) | (sh2->r[n] << 31);\r |
| 1454 | }\r |
| 1455 | \r |
| 1456 | /* RTE */\r |
| 1457 | INLINE void RTE(void)\r |
| 1458 | {\r |
| 1459 | sh2->ea = sh2->r[15];\r |
| 1460 | sh2->delay = sh2->pc;\r |
| 1461 | sh2->pc = RL( sh2->ea );\r |
| 1462 | sh2->r[15] += 4;\r |
| 1463 | sh2->ea = sh2->r[15];\r |
| 1464 | sh2->sr = RL( sh2->ea ) & FLAGS;\r |
| 1465 | sh2->r[15] += 4;\r |
| 1466 | sh2_icount -= 3;\r |
| 1467 | sh2->test_irq = 1;\r |
| 1468 | }\r |
| 1469 | \r |
| 1470 | /* RTS */\r |
| 1471 | INLINE void RTS(void)\r |
| 1472 | {\r |
| 1473 | sh2->delay = sh2->pc;\r |
| 1474 | sh2->pc = sh2->ea = sh2->pr;\r |
| 1475 | sh2_icount--;\r |
| 1476 | }\r |
| 1477 | \r |
| 1478 | /* SETT */\r |
| 1479 | INLINE void SETT(void)\r |
| 1480 | {\r |
| 1481 | sh2->sr |= T;\r |
| 1482 | }\r |
| 1483 | \r |
| 1484 | /* SHAL Rn (same as SHLL) */\r |
| 1485 | INLINE void SHAL(UINT32 n)\r |
| 1486 | {\r |
| 1487 | sh2->sr = (sh2->sr & ~T) | ((sh2->r[n] >> 31) & T);\r |
| 1488 | sh2->r[n] <<= 1;\r |
| 1489 | }\r |
| 1490 | \r |
| 1491 | /* SHAR Rn */\r |
| 1492 | INLINE void SHAR(UINT32 n)\r |
| 1493 | {\r |
| 1494 | sh2->sr = (sh2->sr & ~T) | (sh2->r[n] & T);\r |
| 1495 | sh2->r[n] = (UINT32)((INT32)sh2->r[n] >> 1);\r |
| 1496 | }\r |
| 1497 | \r |
| 1498 | /* SHLL Rn (same as SHAL) */\r |
| 1499 | INLINE void SHLL(UINT32 n)\r |
| 1500 | {\r |
| 1501 | sh2->sr = (sh2->sr & ~T) | ((sh2->r[n] >> 31) & T);\r |
| 1502 | sh2->r[n] <<= 1;\r |
| 1503 | }\r |
| 1504 | \r |
| 1505 | /* SHLL2 Rn */\r |
| 1506 | INLINE void SHLL2(UINT32 n)\r |
| 1507 | {\r |
| 1508 | sh2->r[n] <<= 2;\r |
| 1509 | }\r |
| 1510 | \r |
| 1511 | /* SHLL8 Rn */\r |
| 1512 | INLINE void SHLL8(UINT32 n)\r |
| 1513 | {\r |
| 1514 | sh2->r[n] <<= 8;\r |
| 1515 | }\r |
| 1516 | \r |
| 1517 | /* SHLL16 Rn */\r |
| 1518 | INLINE void SHLL16(UINT32 n)\r |
| 1519 | {\r |
| 1520 | sh2->r[n] <<= 16;\r |
| 1521 | }\r |
| 1522 | \r |
| 1523 | /* SHLR Rn */\r |
| 1524 | INLINE void SHLR(UINT32 n)\r |
| 1525 | {\r |
| 1526 | sh2->sr = (sh2->sr & ~T) | (sh2->r[n] & T);\r |
| 1527 | sh2->r[n] >>= 1;\r |
| 1528 | }\r |
| 1529 | \r |
| 1530 | /* SHLR2 Rn */\r |
| 1531 | INLINE void SHLR2(UINT32 n)\r |
| 1532 | {\r |
| 1533 | sh2->r[n] >>= 2;\r |
| 1534 | }\r |
| 1535 | \r |
| 1536 | /* SHLR8 Rn */\r |
| 1537 | INLINE void SHLR8(UINT32 n)\r |
| 1538 | {\r |
| 1539 | sh2->r[n] >>= 8;\r |
| 1540 | }\r |
| 1541 | \r |
| 1542 | /* SHLR16 Rn */\r |
| 1543 | INLINE void SHLR16(UINT32 n)\r |
| 1544 | {\r |
| 1545 | sh2->r[n] >>= 16;\r |
| 1546 | }\r |
| 1547 | \r |
| 1548 | /* SLEEP */\r |
| 1549 | INLINE void SLEEP(void)\r |
| 1550 | {\r |
| 1551 | sh2->pc -= 2;\r |
| 1552 | sh2_icount -= 2;\r |
| 1553 | /* Wait_for_exception; */\r |
| 1554 | }\r |
| 1555 | \r |
| 1556 | /* STC SR,Rn */\r |
| 1557 | INLINE void STCSR(UINT32 n)\r |
| 1558 | {\r |
| 1559 | sh2->r[n] = sh2->sr;\r |
| 1560 | }\r |
| 1561 | \r |
| 1562 | /* STC GBR,Rn */\r |
| 1563 | INLINE void STCGBR(UINT32 n)\r |
| 1564 | {\r |
| 1565 | sh2->r[n] = sh2->gbr;\r |
| 1566 | }\r |
| 1567 | \r |
| 1568 | /* STC VBR,Rn */\r |
| 1569 | INLINE void STCVBR(UINT32 n)\r |
| 1570 | {\r |
| 1571 | sh2->r[n] = sh2->vbr;\r |
| 1572 | }\r |
| 1573 | \r |
| 1574 | /* STC.L SR,@-Rn */\r |
| 1575 | INLINE void STCMSR(UINT32 n)\r |
| 1576 | {\r |
| 1577 | sh2->r[n] -= 4;\r |
| 1578 | sh2->ea = sh2->r[n];\r |
| 1579 | WL( sh2->ea, sh2->sr );\r |
| 1580 | sh2_icount--;\r |
| 1581 | }\r |
| 1582 | \r |
| 1583 | /* STC.L GBR,@-Rn */\r |
| 1584 | INLINE void STCMGBR(UINT32 n)\r |
| 1585 | {\r |
| 1586 | sh2->r[n] -= 4;\r |
| 1587 | sh2->ea = sh2->r[n];\r |
| 1588 | WL( sh2->ea, sh2->gbr );\r |
| 1589 | sh2_icount--;\r |
| 1590 | }\r |
| 1591 | \r |
| 1592 | /* STC.L VBR,@-Rn */\r |
| 1593 | INLINE void STCMVBR(UINT32 n)\r |
| 1594 | {\r |
| 1595 | sh2->r[n] -= 4;\r |
| 1596 | sh2->ea = sh2->r[n];\r |
| 1597 | WL( sh2->ea, sh2->vbr );\r |
| 1598 | sh2_icount--;\r |
| 1599 | }\r |
| 1600 | \r |
| 1601 | /* STS MACH,Rn */\r |
| 1602 | INLINE void STSMACH(UINT32 n)\r |
| 1603 | {\r |
| 1604 | sh2->r[n] = sh2->mach;\r |
| 1605 | }\r |
| 1606 | \r |
| 1607 | /* STS MACL,Rn */\r |
| 1608 | INLINE void STSMACL(UINT32 n)\r |
| 1609 | {\r |
| 1610 | sh2->r[n] = sh2->macl;\r |
| 1611 | }\r |
| 1612 | \r |
| 1613 | /* STS PR,Rn */\r |
| 1614 | INLINE void STSPR(UINT32 n)\r |
| 1615 | {\r |
| 1616 | sh2->r[n] = sh2->pr;\r |
| 1617 | }\r |
| 1618 | \r |
| 1619 | /* STS.L MACH,@-Rn */\r |
| 1620 | INLINE void STSMMACH(UINT32 n)\r |
| 1621 | {\r |
| 1622 | sh2->r[n] -= 4;\r |
| 1623 | sh2->ea = sh2->r[n];\r |
| 1624 | WL( sh2->ea, sh2->mach );\r |
| 1625 | }\r |
| 1626 | \r |
| 1627 | /* STS.L MACL,@-Rn */\r |
| 1628 | INLINE void STSMMACL(UINT32 n)\r |
| 1629 | {\r |
| 1630 | sh2->r[n] -= 4;\r |
| 1631 | sh2->ea = sh2->r[n];\r |
| 1632 | WL( sh2->ea, sh2->macl );\r |
| 1633 | }\r |
| 1634 | \r |
| 1635 | /* STS.L PR,@-Rn */\r |
| 1636 | INLINE void STSMPR(UINT32 n)\r |
| 1637 | {\r |
| 1638 | sh2->r[n] -= 4;\r |
| 1639 | sh2->ea = sh2->r[n];\r |
| 1640 | WL( sh2->ea, sh2->pr );\r |
| 1641 | }\r |
| 1642 | \r |
| 1643 | /* SUB Rm,Rn */\r |
| 1644 | INLINE void SUB(UINT32 m, UINT32 n)\r |
| 1645 | {\r |
| 1646 | sh2->r[n] -= sh2->r[m];\r |
| 1647 | }\r |
| 1648 | \r |
| 1649 | /* SUBC Rm,Rn */\r |
| 1650 | INLINE void SUBC(UINT32 m, UINT32 n)\r |
| 1651 | {\r |
| 1652 | UINT32 tmp0, tmp1;\r |
| 1653 | \r |
| 1654 | tmp1 = sh2->r[n] - sh2->r[m];\r |
| 1655 | tmp0 = sh2->r[n];\r |
| 1656 | sh2->r[n] = tmp1 - (sh2->sr & T);\r |
| 1657 | if (tmp0 < tmp1)\r |
| 1658 | sh2->sr |= T;\r |
| 1659 | else\r |
| 1660 | sh2->sr &= ~T;\r |
| 1661 | if (tmp1 < sh2->r[n])\r |
| 1662 | sh2->sr |= T;\r |
| 1663 | }\r |
| 1664 | \r |
| 1665 | /* SUBV Rm,Rn */\r |
| 1666 | INLINE void SUBV(UINT32 m, UINT32 n)\r |
| 1667 | {\r |
| 1668 | INT32 dest, src, ans;\r |
| 1669 | \r |
| 1670 | if ((INT32) sh2->r[n] >= 0)\r |
| 1671 | dest = 0;\r |
| 1672 | else\r |
| 1673 | dest = 1;\r |
| 1674 | if ((INT32) sh2->r[m] >= 0)\r |
| 1675 | src = 0;\r |
| 1676 | else\r |
| 1677 | src = 1;\r |
| 1678 | src += dest;\r |
| 1679 | sh2->r[n] -= sh2->r[m];\r |
| 1680 | if ((INT32) sh2->r[n] >= 0)\r |
| 1681 | ans = 0;\r |
| 1682 | else\r |
| 1683 | ans = 1;\r |
| 1684 | ans += dest;\r |
| 1685 | if (src == 1)\r |
| 1686 | {\r |
| 1687 | if (ans == 1)\r |
| 1688 | sh2->sr |= T;\r |
| 1689 | else\r |
| 1690 | sh2->sr &= ~T;\r |
| 1691 | }\r |
| 1692 | else\r |
| 1693 | sh2->sr &= ~T;\r |
| 1694 | }\r |
| 1695 | \r |
| 1696 | /* SWAP.B Rm,Rn */\r |
| 1697 | INLINE void SWAPB(UINT32 m, UINT32 n)\r |
| 1698 | {\r |
| 1699 | UINT32 temp0, temp1;\r |
| 1700 | \r |
| 1701 | temp0 = sh2->r[m] & 0xffff0000;\r |
| 1702 | temp1 = (sh2->r[m] & 0x000000ff) << 8;\r |
| 1703 | sh2->r[n] = (sh2->r[m] >> 8) & 0x000000ff;\r |
| 1704 | sh2->r[n] = sh2->r[n] | temp1 | temp0;\r |
| 1705 | }\r |
| 1706 | \r |
| 1707 | /* SWAP.W Rm,Rn */\r |
| 1708 | INLINE void SWAPW(UINT32 m, UINT32 n)\r |
| 1709 | {\r |
| 1710 | UINT32 temp;\r |
| 1711 | \r |
| 1712 | temp = (sh2->r[m] >> 16) & 0x0000ffff;\r |
| 1713 | sh2->r[n] = (sh2->r[m] << 16) | temp;\r |
| 1714 | }\r |
| 1715 | \r |
| 1716 | /* TAS.B @Rn */\r |
| 1717 | INLINE void TAS(UINT32 n)\r |
| 1718 | {\r |
| 1719 | UINT32 temp;\r |
| 1720 | sh2->ea = sh2->r[n];\r |
| 1721 | /* Bus Lock enable */\r |
| 1722 | temp = RB( sh2->ea );\r |
| 1723 | if (temp == 0)\r |
| 1724 | sh2->sr |= T;\r |
| 1725 | else\r |
| 1726 | sh2->sr &= ~T;\r |
| 1727 | temp |= 0x80;\r |
| 1728 | /* Bus Lock disable */\r |
| 1729 | WB( sh2->ea, temp );\r |
| 1730 | sh2_icount -= 3;\r |
| 1731 | }\r |
| 1732 | \r |
| 1733 | /* TRAPA #imm */\r |
| 1734 | INLINE void TRAPA(UINT32 i)\r |
| 1735 | {\r |
| 1736 | UINT32 imm = i & 0xff;\r |
| 1737 | \r |
| 1738 | sh2->ea = sh2->vbr + imm * 4;\r |
| 1739 | \r |
| 1740 | sh2->r[15] -= 4;\r |
| 1741 | WL( sh2->r[15], sh2->sr );\r |
| 1742 | sh2->r[15] -= 4;\r |
| 1743 | WL( sh2->r[15], sh2->pc );\r |
| 1744 | \r |
| 1745 | sh2->pc = RL( sh2->ea );\r |
| 1746 | \r |
| 1747 | sh2_icount -= 7;\r |
| 1748 | }\r |
| 1749 | \r |
| 1750 | /* TST Rm,Rn */\r |
| 1751 | INLINE void TST(UINT32 m, UINT32 n)\r |
| 1752 | {\r |
| 1753 | if ((sh2->r[n] & sh2->r[m]) == 0)\r |
| 1754 | sh2->sr |= T;\r |
| 1755 | else\r |
| 1756 | sh2->sr &= ~T;\r |
| 1757 | }\r |
| 1758 | \r |
| 1759 | /* TST #imm,R0 */\r |
| 1760 | INLINE void TSTI(UINT32 i)\r |
| 1761 | {\r |
| 1762 | UINT32 imm = i & 0xff;\r |
| 1763 | \r |
| 1764 | if ((imm & sh2->r[0]) == 0)\r |
| 1765 | sh2->sr |= T;\r |
| 1766 | else\r |
| 1767 | sh2->sr &= ~T;\r |
| 1768 | }\r |
| 1769 | \r |
| 1770 | /* TST.B #imm,@(R0,GBR) */\r |
| 1771 | INLINE void TSTM(UINT32 i)\r |
| 1772 | {\r |
| 1773 | UINT32 imm = i & 0xff;\r |
| 1774 | \r |
| 1775 | sh2->ea = sh2->gbr + sh2->r[0];\r |
| 1776 | if ((imm & RB( sh2->ea )) == 0)\r |
| 1777 | sh2->sr |= T;\r |
| 1778 | else\r |
| 1779 | sh2->sr &= ~T;\r |
| 1780 | sh2_icount -= 2;\r |
| 1781 | }\r |
| 1782 | \r |
| 1783 | /* XOR Rm,Rn */\r |
| 1784 | INLINE void XOR(UINT32 m, UINT32 n)\r |
| 1785 | {\r |
| 1786 | sh2->r[n] ^= sh2->r[m];\r |
| 1787 | }\r |
| 1788 | \r |
| 1789 | /* XOR #imm,R0 */\r |
| 1790 | INLINE void XORI(UINT32 i)\r |
| 1791 | {\r |
| 1792 | UINT32 imm = i & 0xff;\r |
| 1793 | sh2->r[0] ^= imm;\r |
| 1794 | }\r |
| 1795 | \r |
| 1796 | /* XOR.B #imm,@(R0,GBR) */\r |
| 1797 | INLINE void XORM(UINT32 i)\r |
| 1798 | {\r |
| 1799 | UINT32 imm = i & 0xff;\r |
| 1800 | UINT32 temp;\r |
| 1801 | \r |
| 1802 | sh2->ea = sh2->gbr + sh2->r[0];\r |
| 1803 | temp = RB( sh2->ea );\r |
| 1804 | temp ^= imm;\r |
| 1805 | WB( sh2->ea, temp );\r |
| 1806 | sh2_icount -= 2;\r |
| 1807 | }\r |
| 1808 | \r |
| 1809 | /* XTRCT Rm,Rn */\r |
| 1810 | INLINE void XTRCT(UINT32 m, UINT32 n)\r |
| 1811 | {\r |
| 1812 | UINT32 temp;\r |
| 1813 | \r |
| 1814 | temp = (sh2->r[m] << 16) & 0xffff0000;\r |
| 1815 | sh2->r[n] = (sh2->r[n] >> 16) & 0x0000ffff;\r |
| 1816 | sh2->r[n] |= temp;\r |
| 1817 | }\r |
| 1818 | \r |
| 1819 | /*****************************************************************************\r |
| 1820 | * OPCODE DISPATCHERS\r |
| 1821 | *****************************************************************************/\r |
| 1822 | \r |
| 1823 | INLINE void op0000(UINT16 opcode)\r |
| 1824 | {\r |
| 1825 | switch (opcode & 0x3F)\r |
| 1826 | {\r |
| 1827 | case 0x00: NOP(); break;\r |
| 1828 | case 0x01: NOP(); break;\r |
| 1829 | case 0x02: STCSR(Rn); break;\r |
| 1830 | case 0x03: BSRF(Rn); break;\r |
| 1831 | case 0x04: MOVBS0(Rm, Rn); break;\r |
| 1832 | case 0x05: MOVWS0(Rm, Rn); break;\r |
| 1833 | case 0x06: MOVLS0(Rm, Rn); break;\r |
| 1834 | case 0x07: MULL(Rm, Rn); break;\r |
| 1835 | case 0x08: CLRT(); break;\r |
| 1836 | case 0x09: NOP(); break;\r |
| 1837 | case 0x0a: STSMACH(Rn); break;\r |
| 1838 | case 0x0b: RTS(); break;\r |
| 1839 | case 0x0c: MOVBL0(Rm, Rn); break;\r |
| 1840 | case 0x0d: MOVWL0(Rm, Rn); break;\r |
| 1841 | case 0x0e: MOVLL0(Rm, Rn); break;\r |
| 1842 | case 0x0f: MAC_L(Rm, Rn); break;\r |
| 1843 | \r |
| 1844 | case 0x10: NOP(); break;\r |
| 1845 | case 0x11: NOP(); break;\r |
| 1846 | case 0x12: STCGBR(Rn); break;\r |
| 1847 | case 0x13: NOP(); break;\r |
| 1848 | case 0x14: MOVBS0(Rm, Rn); break;\r |
| 1849 | case 0x15: MOVWS0(Rm, Rn); break;\r |
| 1850 | case 0x16: MOVLS0(Rm, Rn); break;\r |
| 1851 | case 0x17: MULL(Rm, Rn); break;\r |
| 1852 | case 0x18: SETT(); break;\r |
| 1853 | case 0x19: DIV0U(); break;\r |
| 1854 | case 0x1a: STSMACL(Rn); break;\r |
| 1855 | case 0x1b: SLEEP(); break;\r |
| 1856 | case 0x1c: MOVBL0(Rm, Rn); break;\r |
| 1857 | case 0x1d: MOVWL0(Rm, Rn); break;\r |
| 1858 | case 0x1e: MOVLL0(Rm, Rn); break;\r |
| 1859 | case 0x1f: MAC_L(Rm, Rn); break;\r |
| 1860 | \r |
| 1861 | case 0x20: NOP(); break;\r |
| 1862 | case 0x21: NOP(); break;\r |
| 1863 | case 0x22: STCVBR(Rn); break;\r |
| 1864 | case 0x23: BRAF(Rn); break;\r |
| 1865 | case 0x24: MOVBS0(Rm, Rn); break;\r |
| 1866 | case 0x25: MOVWS0(Rm, Rn); break;\r |
| 1867 | case 0x26: MOVLS0(Rm, Rn); break;\r |
| 1868 | case 0x27: MULL(Rm, Rn); break;\r |
| 1869 | case 0x28: CLRMAC(); break;\r |
| 1870 | case 0x29: MOVT(Rn); break;\r |
| 1871 | case 0x2a: STSPR(Rn); break;\r |
| 1872 | case 0x2b: RTE(); break;\r |
| 1873 | case 0x2c: MOVBL0(Rm, Rn); break;\r |
| 1874 | case 0x2d: MOVWL0(Rm, Rn); break;\r |
| 1875 | case 0x2e: MOVLL0(Rm, Rn); break;\r |
| 1876 | case 0x2f: MAC_L(Rm, Rn); break;\r |
| 1877 | \r |
| 1878 | case 0x30: NOP(); break;\r |
| 1879 | case 0x31: NOP(); break;\r |
| 1880 | case 0x32: NOP(); break;\r |
| 1881 | case 0x33: NOP(); break;\r |
| 1882 | case 0x34: MOVBS0(Rm, Rn); break;\r |
| 1883 | case 0x35: MOVWS0(Rm, Rn); break;\r |
| 1884 | case 0x36: MOVLS0(Rm, Rn); break;\r |
| 1885 | case 0x37: MULL(Rm, Rn); break;\r |
| 1886 | case 0x38: NOP(); break;\r |
| 1887 | case 0x39: NOP(); break;\r |
| 1888 | case 0x3c: MOVBL0(Rm, Rn); break;\r |
| 1889 | case 0x3d: MOVWL0(Rm, Rn); break;\r |
| 1890 | case 0x3e: MOVLL0(Rm, Rn); break;\r |
| 1891 | case 0x3f: MAC_L(Rm, Rn); break;\r |
| 1892 | case 0x3a: NOP(); break;\r |
| 1893 | case 0x3b: NOP(); break;\r |
| 1894 | \r |
| 1895 | \r |
| 1896 | \r |
| 1897 | }\r |
| 1898 | }\r |
| 1899 | \r |
| 1900 | INLINE void op0001(UINT16 opcode)\r |
| 1901 | {\r |
| 1902 | MOVLS4(Rm, opcode & 0x0f, Rn);\r |
| 1903 | }\r |
| 1904 | \r |
| 1905 | INLINE void op0010(UINT16 opcode)\r |
| 1906 | {\r |
| 1907 | switch (opcode & 15)\r |
| 1908 | {\r |
| 1909 | case 0: MOVBS(Rm, Rn); break;\r |
| 1910 | case 1: MOVWS(Rm, Rn); break;\r |
| 1911 | case 2: MOVLS(Rm, Rn); break;\r |
| 1912 | case 3: NOP(); break;\r |
| 1913 | case 4: MOVBM(Rm, Rn); break;\r |
| 1914 | case 5: MOVWM(Rm, Rn); break;\r |
| 1915 | case 6: MOVLM(Rm, Rn); break;\r |
| 1916 | case 7: DIV0S(Rm, Rn); break;\r |
| 1917 | case 8: TST(Rm, Rn); break;\r |
| 1918 | case 9: AND(Rm, Rn); break;\r |
| 1919 | case 10: XOR(Rm, Rn); break;\r |
| 1920 | case 11: OR(Rm, Rn); break;\r |
| 1921 | case 12: CMPSTR(Rm, Rn); break;\r |
| 1922 | case 13: XTRCT(Rm, Rn); break;\r |
| 1923 | case 14: MULU(Rm, Rn); break;\r |
| 1924 | case 15: MULS(Rm, Rn); break;\r |
| 1925 | }\r |
| 1926 | }\r |
| 1927 | \r |
| 1928 | INLINE void op0011(UINT16 opcode)\r |
| 1929 | {\r |
| 1930 | switch (opcode & 15)\r |
| 1931 | {\r |
| 1932 | case 0: CMPEQ(Rm, Rn); break;\r |
| 1933 | case 1: NOP(); break;\r |
| 1934 | case 2: CMPHS(Rm, Rn); break;\r |
| 1935 | case 3: CMPGE(Rm, Rn); break;\r |
| 1936 | case 4: DIV1(Rm, Rn); break;\r |
| 1937 | case 5: DMULU(Rm, Rn); break;\r |
| 1938 | case 6: CMPHI(Rm, Rn); break;\r |
| 1939 | case 7: CMPGT(Rm, Rn); break;\r |
| 1940 | case 8: SUB(Rm, Rn); break;\r |
| 1941 | case 9: NOP(); break;\r |
| 1942 | case 10: SUBC(Rm, Rn); break;\r |
| 1943 | case 11: SUBV(Rm, Rn); break;\r |
| 1944 | case 12: ADD(Rm, Rn); break;\r |
| 1945 | case 13: DMULS(Rm, Rn); break;\r |
| 1946 | case 14: ADDC(Rm, Rn); break;\r |
| 1947 | case 15: ADDV(Rm, Rn); break;\r |
| 1948 | }\r |
| 1949 | }\r |
| 1950 | \r |
| 1951 | INLINE void op0100(UINT16 opcode)\r |
| 1952 | {\r |
| 1953 | switch (opcode & 0x3F)\r |
| 1954 | {\r |
| 1955 | case 0x00: SHLL(Rn); break;\r |
| 1956 | case 0x01: SHLR(Rn); break;\r |
| 1957 | case 0x02: STSMMACH(Rn); break;\r |
| 1958 | case 0x03: STCMSR(Rn); break;\r |
| 1959 | case 0x04: ROTL(Rn); break;\r |
| 1960 | case 0x05: ROTR(Rn); break;\r |
| 1961 | case 0x06: LDSMMACH(Rn); break;\r |
| 1962 | case 0x07: LDCMSR(Rn); break;\r |
| 1963 | case 0x08: SHLL2(Rn); break;\r |
| 1964 | case 0x09: SHLR2(Rn); break;\r |
| 1965 | case 0x0a: LDSMACH(Rn); break;\r |
| 1966 | case 0x0b: JSR(Rn); break;\r |
| 1967 | case 0x0c: NOP(); break;\r |
| 1968 | case 0x0d: NOP(); break;\r |
| 1969 | case 0x0e: LDCSR(Rn); break;\r |
| 1970 | case 0x0f: MAC_W(Rm, Rn); break;\r |
| 1971 | \r |
| 1972 | case 0x10: DT(Rn); break;\r |
| 1973 | case 0x11: CMPPZ(Rn); break;\r |
| 1974 | case 0x12: STSMMACL(Rn); break;\r |
| 1975 | case 0x13: STCMGBR(Rn); break;\r |
| 1976 | case 0x14: NOP(); break;\r |
| 1977 | case 0x15: CMPPL(Rn); break;\r |
| 1978 | case 0x16: LDSMMACL(Rn); break;\r |
| 1979 | case 0x17: LDCMGBR(Rn); break;\r |
| 1980 | case 0x18: SHLL8(Rn); break;\r |
| 1981 | case 0x19: SHLR8(Rn); break;\r |
| 1982 | case 0x1a: LDSMACL(Rn); break;\r |
| 1983 | case 0x1b: TAS(Rn); break;\r |
| 1984 | case 0x1c: NOP(); break;\r |
| 1985 | case 0x1d: NOP(); break;\r |
| 1986 | case 0x1e: LDCGBR(Rn); break;\r |
| 1987 | case 0x1f: MAC_W(Rm, Rn); break;\r |
| 1988 | \r |
| 1989 | case 0x20: SHAL(Rn); break;\r |
| 1990 | case 0x21: SHAR(Rn); break;\r |
| 1991 | case 0x22: STSMPR(Rn); break;\r |
| 1992 | case 0x23: STCMVBR(Rn); break;\r |
| 1993 | case 0x24: ROTCL(Rn); break;\r |
| 1994 | case 0x25: ROTCR(Rn); break;\r |
| 1995 | case 0x26: LDSMPR(Rn); break;\r |
| 1996 | case 0x27: LDCMVBR(Rn); break;\r |
| 1997 | case 0x28: SHLL16(Rn); break;\r |
| 1998 | case 0x29: SHLR16(Rn); break;\r |
| 1999 | case 0x2a: LDSPR(Rn); break;\r |
| 2000 | case 0x2b: JMP(Rn); break;\r |
| 2001 | case 0x2c: NOP(); break;\r |
| 2002 | case 0x2d: NOP(); break;\r |
| 2003 | case 0x2e: LDCVBR(Rn); break;\r |
| 2004 | case 0x2f: MAC_W(Rm, Rn); break;\r |
| 2005 | \r |
| 2006 | case 0x30: NOP(); break;\r |
| 2007 | case 0x31: NOP(); break;\r |
| 2008 | case 0x32: NOP(); break;\r |
| 2009 | case 0x33: NOP(); break;\r |
| 2010 | case 0x34: NOP(); break;\r |
| 2011 | case 0x35: NOP(); break;\r |
| 2012 | case 0x36: NOP(); break;\r |
| 2013 | case 0x37: NOP(); break;\r |
| 2014 | case 0x38: NOP(); break;\r |
| 2015 | case 0x39: NOP(); break;\r |
| 2016 | case 0x3a: NOP(); break;\r |
| 2017 | case 0x3b: NOP(); break;\r |
| 2018 | case 0x3c: NOP(); break;\r |
| 2019 | case 0x3d: NOP(); break;\r |
| 2020 | case 0x3e: NOP(); break;\r |
| 2021 | case 0x3f: MAC_W(Rm, Rn); break;\r |
| 2022 | \r |
| 2023 | }\r |
| 2024 | }\r |
| 2025 | \r |
| 2026 | INLINE void op0101(UINT16 opcode)\r |
| 2027 | {\r |
| 2028 | MOVLL4(Rm, opcode & 0x0f, Rn);\r |
| 2029 | }\r |
| 2030 | \r |
| 2031 | INLINE void op0110(UINT16 opcode)\r |
| 2032 | {\r |
| 2033 | switch (opcode & 15)\r |
| 2034 | {\r |
| 2035 | case 0: MOVBL(Rm, Rn); break;\r |
| 2036 | case 1: MOVWL(Rm, Rn); break;\r |
| 2037 | case 2: MOVLL(Rm, Rn); break;\r |
| 2038 | case 3: MOV(Rm, Rn); break;\r |
| 2039 | case 4: MOVBP(Rm, Rn); break;\r |
| 2040 | case 5: MOVWP(Rm, Rn); break;\r |
| 2041 | case 6: MOVLP(Rm, Rn); break;\r |
| 2042 | case 7: NOT(Rm, Rn); break;\r |
| 2043 | case 8: SWAPB(Rm, Rn); break;\r |
| 2044 | case 9: SWAPW(Rm, Rn); break;\r |
| 2045 | case 10: NEGC(Rm, Rn); break;\r |
| 2046 | case 11: NEG(Rm, Rn); break;\r |
| 2047 | case 12: EXTUB(Rm, Rn); break;\r |
| 2048 | case 13: EXTUW(Rm, Rn); break;\r |
| 2049 | case 14: EXTSB(Rm, Rn); break;\r |
| 2050 | case 15: EXTSW(Rm, Rn); break;\r |
| 2051 | }\r |
| 2052 | }\r |
| 2053 | \r |
| 2054 | INLINE void op0111(UINT16 opcode)\r |
| 2055 | {\r |
| 2056 | ADDI(opcode & 0xff, Rn);\r |
| 2057 | }\r |
| 2058 | \r |
| 2059 | INLINE void op1000(UINT16 opcode)\r |
| 2060 | {\r |
| 2061 | switch ( opcode & (15<<8) )\r |
| 2062 | {\r |
| 2063 | case 0 << 8: MOVBS4(opcode & 0x0f, Rm); break;\r |
| 2064 | case 1 << 8: MOVWS4(opcode & 0x0f, Rm); break;\r |
| 2065 | case 2<< 8: NOP(); break;\r |
| 2066 | case 3<< 8: NOP(); break;\r |
| 2067 | case 4<< 8: MOVBL4(Rm, opcode & 0x0f); break;\r |
| 2068 | case 5<< 8: MOVWL4(Rm, opcode & 0x0f); break;\r |
| 2069 | case 6<< 8: NOP(); break;\r |
| 2070 | case 7<< 8: NOP(); break;\r |
| 2071 | case 8<< 8: CMPIM(opcode & 0xff); break;\r |
| 2072 | case 9<< 8: BT(opcode & 0xff); break;\r |
| 2073 | case 10<< 8: NOP(); break;\r |
| 2074 | case 11<< 8: BF(opcode & 0xff); break;\r |
| 2075 | case 12<< 8: NOP(); break;\r |
| 2076 | case 13<< 8: BTS(opcode & 0xff); break;\r |
| 2077 | case 14<< 8: NOP(); break;\r |
| 2078 | case 15<< 8: BFS(opcode & 0xff); break;\r |
| 2079 | }\r |
| 2080 | }\r |
| 2081 | \r |
| 2082 | \r |
| 2083 | INLINE void op1001(UINT16 opcode)\r |
| 2084 | {\r |
| 2085 | MOVWI(opcode & 0xff, Rn);\r |
| 2086 | }\r |
| 2087 | \r |
| 2088 | INLINE void op1010(UINT16 opcode)\r |
| 2089 | {\r |
| 2090 | BRA(opcode & 0xfff);\r |
| 2091 | }\r |
| 2092 | \r |
| 2093 | INLINE void op1011(UINT16 opcode)\r |
| 2094 | {\r |
| 2095 | BSR(opcode & 0xfff);\r |
| 2096 | }\r |
| 2097 | \r |
| 2098 | INLINE void op1100(UINT16 opcode)\r |
| 2099 | {\r |
| 2100 | switch (opcode & (15<<8))\r |
| 2101 | {\r |
| 2102 | case 0<<8: MOVBSG(opcode & 0xff); break;\r |
| 2103 | case 1<<8: MOVWSG(opcode & 0xff); break;\r |
| 2104 | case 2<<8: MOVLSG(opcode & 0xff); break;\r |
| 2105 | case 3<<8: TRAPA(opcode & 0xff); break;\r |
| 2106 | case 4<<8: MOVBLG(opcode & 0xff); break;\r |
| 2107 | case 5<<8: MOVWLG(opcode & 0xff); break;\r |
| 2108 | case 6<<8: MOVLLG(opcode & 0xff); break;\r |
| 2109 | case 7<<8: MOVA(opcode & 0xff); break;\r |
| 2110 | case 8<<8: TSTI(opcode & 0xff); break;\r |
| 2111 | case 9<<8: ANDI(opcode & 0xff); break;\r |
| 2112 | case 10<<8: XORI(opcode & 0xff); break;\r |
| 2113 | case 11<<8: ORI(opcode & 0xff); break;\r |
| 2114 | case 12<<8: TSTM(opcode & 0xff); break;\r |
| 2115 | case 13<<8: ANDM(opcode & 0xff); break;\r |
| 2116 | case 14<<8: XORM(opcode & 0xff); break;\r |
| 2117 | case 15<<8: ORM(opcode & 0xff); break;\r |
| 2118 | }\r |
| 2119 | }\r |
| 2120 | \r |
| 2121 | INLINE void op1101(UINT16 opcode)\r |
| 2122 | {\r |
| 2123 | MOVLI(opcode & 0xff, Rn);\r |
| 2124 | }\r |
| 2125 | \r |
| 2126 | INLINE void op1110(UINT16 opcode)\r |
| 2127 | {\r |
| 2128 | MOVI(opcode & 0xff, Rn);\r |
| 2129 | }\r |
| 2130 | \r |
| 2131 | INLINE void op1111(UINT16 opcode)\r |
| 2132 | {\r |
| 2133 | NOP();\r |
| 2134 | }\r |
| 2135 | \r |
| 2136 | #endif\r |