| 1 | #include <string.h> |
| 2 | |
| 3 | // MAME types |
| 4 | typedef signed char INT8; |
| 5 | typedef signed short INT16; |
| 6 | typedef signed int INT32; |
| 7 | typedef unsigned int UINT32; |
| 8 | typedef unsigned short UINT16; |
| 9 | typedef unsigned char UINT8; |
| 10 | |
| 11 | // pico memhandlers |
| 12 | unsigned int pico32x_read8(unsigned int a); |
| 13 | unsigned int pico32x_read16(unsigned int a); |
| 14 | unsigned int pico32x_read32(unsigned int a); |
| 15 | void pico32x_write8(unsigned int a, unsigned int d); |
| 16 | void pico32x_write16(unsigned int a, unsigned int d); |
| 17 | void pico32x_write32(unsigned int a, unsigned int d); |
| 18 | |
| 19 | #define RB pico32x_read8 |
| 20 | #define RW pico32x_read16 |
| 21 | #define RL pico32x_read32 |
| 22 | #define WB pico32x_write8 |
| 23 | #define WW pico32x_write16 |
| 24 | #define WL pico32x_write32 |
| 25 | |
| 26 | // some stuff from sh2comn.h |
| 27 | #define T 0x00000001 |
| 28 | #define S 0x00000002 |
| 29 | #define I 0x000000f0 |
| 30 | #define Q 0x00000100 |
| 31 | #define M 0x00000200 |
| 32 | |
| 33 | #define AM 0xc7ffffff |
| 34 | |
| 35 | #define FLAGS (M|Q|I|S|T) |
| 36 | |
| 37 | #define Rn ((opcode>>8)&15) |
| 38 | #define Rm ((opcode>>4)&15) |
| 39 | |
| 40 | #include "sh2.c" |
| 41 | |
| 42 | void sh2_reset(SH2 *sh2) |
| 43 | { |
| 44 | int save_is_slave; |
| 45 | // cpu_irq_callback save_irqcallback; |
| 46 | |
| 47 | // save_irqcallback = sh2->irq_callback; |
| 48 | save_is_slave = sh2->is_slave; |
| 49 | |
| 50 | memset(sh2, 0, sizeof(SH2)); |
| 51 | |
| 52 | sh2->is_slave = save_is_slave; |
| 53 | // sh2->irq_callback = save_irqcallback; |
| 54 | |
| 55 | sh2->pc = RL(0); |
| 56 | sh2->r[15] = RL(4); |
| 57 | sh2->sr = I; |
| 58 | |
| 59 | sh2->internal_irq_level = -1; |
| 60 | } |
| 61 | |
| 62 | /* Execute cycles - returns number of cycles actually run */ |
| 63 | int sh2_execute(SH2 *sh2_, int cycles) |
| 64 | { |
| 65 | sh2 = sh2_; |
| 66 | sh2_icount = cycles; |
| 67 | |
| 68 | do |
| 69 | { |
| 70 | UINT32 opcode; |
| 71 | |
| 72 | opcode = RW(sh2->pc); |
| 73 | |
| 74 | sh2->delay = 0; |
| 75 | sh2->pc += 2; |
| 76 | sh2->ppc = sh2->pc; |
| 77 | |
| 78 | switch (opcode & ( 15 << 12)) |
| 79 | { |
| 80 | case 0<<12: op0000(opcode); break; |
| 81 | case 1<<12: op0001(opcode); break; |
| 82 | case 2<<12: op0010(opcode); break; |
| 83 | case 3<<12: op0011(opcode); break; |
| 84 | case 4<<12: op0100(opcode); break; |
| 85 | case 5<<12: op0101(opcode); break; |
| 86 | case 6<<12: op0110(opcode); break; |
| 87 | case 7<<12: op0111(opcode); break; |
| 88 | case 8<<12: op1000(opcode); break; |
| 89 | case 9<<12: op1001(opcode); break; |
| 90 | case 10<<12: op1010(opcode); break; |
| 91 | case 11<<12: op1011(opcode); break; |
| 92 | case 12<<12: op1100(opcode); break; |
| 93 | case 13<<12: op1101(opcode); break; |
| 94 | case 14<<12: op1110(opcode); break; |
| 95 | default: op1111(opcode); break; |
| 96 | } |
| 97 | |
| 98 | if (sh2->test_irq && !sh2->delay) |
| 99 | { |
| 100 | // CHECK_PENDING_IRQ("mame_sh2_execute"); |
| 101 | sh2->test_irq = 0; |
| 102 | } |
| 103 | sh2_icount--; |
| 104 | } |
| 105 | while (sh2_icount > 0); |
| 106 | |
| 107 | return cycles - sh2_icount; |
| 108 | } |
| 109 | |
| 110 | void sh2_init(SH2 *sh2) |
| 111 | { |
| 112 | memset(sh2, 0, sizeof(*sh2)); |
| 113 | } |
| 114 | |
| 115 | |