| 1 | // stop compiling if NORECBUILD build (only for Visual Studio) |
| 2 | #if !(defined(_MSC_VER) && defined(PCSX2_NORECBUILD)) |
| 3 | |
| 4 | #include <stdio.h> |
| 5 | #include <string.h> |
| 6 | #include "ix86-64.h" |
| 7 | |
| 8 | /********************/ |
| 9 | /* FPU instructions */ |
| 10 | /********************/ |
| 11 | |
| 12 | /* fild m32 to fpu reg stack */ |
| 13 | void FILD32( uptr from ) |
| 14 | { |
| 15 | MEMADDR_OP(0, VAROP1(0xDB), false, 0, from, 0); |
| 16 | } |
| 17 | |
| 18 | /* fistp m32 from fpu reg stack */ |
| 19 | void FISTP32( uptr from ) |
| 20 | { |
| 21 | MEMADDR_OP(0, VAROP1(0xDB), false, 3, from, 0); |
| 22 | } |
| 23 | |
| 24 | /* fld m32 to fpu reg stack */ |
| 25 | void FLD32( uptr from ) |
| 26 | { |
| 27 | MEMADDR_OP(0, VAROP1(0xD9), false, 0, from, 0); |
| 28 | } |
| 29 | |
| 30 | // fld st(i) |
| 31 | void FLD(int st) { write16(0xc0d9+(st<<8)); } |
| 32 | |
| 33 | void FLD1() { write16(0xe8d9); } |
| 34 | void FLDL2E() { write16(0xead9); } |
| 35 | |
| 36 | /* fst m32 from fpu reg stack */ |
| 37 | void FST32( uptr to ) |
| 38 | { |
| 39 | MEMADDR_OP(0, VAROP1(0xD9), false, 2, to, 0); |
| 40 | } |
| 41 | |
| 42 | /* fstp m32 from fpu reg stack */ |
| 43 | void FSTP32( uptr to ) |
| 44 | { |
| 45 | MEMADDR_OP(0, VAROP1(0xD9), false, 3, to, 0); |
| 46 | } |
| 47 | |
| 48 | // fstp st(i) |
| 49 | void FSTP(int st) { write16(0xd8dd+(st<<8)); } |
| 50 | |
| 51 | /* fldcw fpu control word from m16 */ |
| 52 | void FLDCW( uptr from ) |
| 53 | { |
| 54 | MEMADDR_OP(0, VAROP1(0xD9), false, 5, from, 0); |
| 55 | } |
| 56 | |
| 57 | /* fnstcw fpu control word to m16 */ |
| 58 | void FNSTCW( uptr to ) |
| 59 | { |
| 60 | MEMADDR_OP(0, VAROP1(0xD9), false, 7, to, 0); |
| 61 | } |
| 62 | |
| 63 | void FNSTSWtoAX( void ) |
| 64 | { |
| 65 | write16( 0xE0DF ); |
| 66 | } |
| 67 | |
| 68 | void FXAM() |
| 69 | { |
| 70 | write16(0xe5d9); |
| 71 | } |
| 72 | |
| 73 | void FDECSTP() { write16(0xf6d9); } |
| 74 | void FRNDINT() { write16(0xfcd9); } |
| 75 | void FXCH(int st) { write16(0xc8d9+(st<<8)); } |
| 76 | void F2XM1() { write16(0xf0d9); } |
| 77 | void FSCALE() { write16(0xfdd9); } |
| 78 | |
| 79 | /* fadd ST(src) to fpu reg stack ST(0) */ |
| 80 | void FADD32Rto0( x86IntRegType src ) |
| 81 | { |
| 82 | write8( 0xD8 ); |
| 83 | write8( 0xC0 + src ); |
| 84 | } |
| 85 | |
| 86 | /* fadd ST(0) to fpu reg stack ST(src) */ |
| 87 | void FADD320toR( x86IntRegType src ) |
| 88 | { |
| 89 | write8( 0xDC ); |
| 90 | write8( 0xC0 + src ); |
| 91 | } |
| 92 | |
| 93 | /* fsub ST(src) to fpu reg stack ST(0) */ |
| 94 | void FSUB32Rto0( x86IntRegType src ) |
| 95 | { |
| 96 | write8( 0xD8 ); |
| 97 | write8( 0xE0 + src ); |
| 98 | } |
| 99 | |
| 100 | /* fsub ST(0) to fpu reg stack ST(src) */ |
| 101 | void FSUB320toR( x86IntRegType src ) |
| 102 | { |
| 103 | write8( 0xDC ); |
| 104 | write8( 0xE8 + src ); |
| 105 | } |
| 106 | |
| 107 | /* fsubp -> substract ST(0) from ST(1), store in ST(1) and POP stack */ |
| 108 | void FSUBP( void ) |
| 109 | { |
| 110 | write8( 0xDE ); |
| 111 | write8( 0xE9 ); |
| 112 | } |
| 113 | |
| 114 | /* fmul ST(src) to fpu reg stack ST(0) */ |
| 115 | void FMUL32Rto0( x86IntRegType src ) |
| 116 | { |
| 117 | write8( 0xD8 ); |
| 118 | write8( 0xC8 + src ); |
| 119 | } |
| 120 | |
| 121 | /* fmul ST(0) to fpu reg stack ST(src) */ |
| 122 | void FMUL320toR( x86IntRegType src ) |
| 123 | { |
| 124 | write8( 0xDC ); |
| 125 | write8( 0xC8 + src ); |
| 126 | } |
| 127 | |
| 128 | /* fdiv ST(src) to fpu reg stack ST(0) */ |
| 129 | void FDIV32Rto0( x86IntRegType src ) |
| 130 | { |
| 131 | write8( 0xD8 ); |
| 132 | write8( 0xF0 + src ); |
| 133 | } |
| 134 | |
| 135 | /* fdiv ST(0) to fpu reg stack ST(src) */ |
| 136 | void FDIV320toR( x86IntRegType src ) |
| 137 | { |
| 138 | write8( 0xDC ); |
| 139 | write8( 0xF8 + src ); |
| 140 | } |
| 141 | |
| 142 | void FDIV320toRP( x86IntRegType src ) |
| 143 | { |
| 144 | write8( 0xDE ); |
| 145 | write8( 0xF8 + src ); |
| 146 | } |
| 147 | |
| 148 | /* fadd m32 to fpu reg stack */ |
| 149 | void FADD32( uptr from ) |
| 150 | { |
| 151 | MEMADDR_OP(0, VAROP1(0xD8), false, 0, from, 0); |
| 152 | } |
| 153 | |
| 154 | /* fsub m32 to fpu reg stack */ |
| 155 | void FSUB32( uptr from ) |
| 156 | { |
| 157 | MEMADDR_OP(0, VAROP1(0xD8), false, 4, from, 0); |
| 158 | } |
| 159 | |
| 160 | /* fmul m32 to fpu reg stack */ |
| 161 | void FMUL32( uptr from ) |
| 162 | { |
| 163 | MEMADDR_OP(0, VAROP1(0xD8), false, 1, from, 0); |
| 164 | } |
| 165 | |
| 166 | /* fdiv m32 to fpu reg stack */ |
| 167 | void FDIV32( uptr from ) |
| 168 | { |
| 169 | MEMADDR_OP(0, VAROP1(0xD8), false, 6, from, 0); |
| 170 | } |
| 171 | |
| 172 | /* fabs fpu reg stack */ |
| 173 | void FABS( void ) |
| 174 | { |
| 175 | write16( 0xE1D9 ); |
| 176 | } |
| 177 | |
| 178 | /* fsqrt fpu reg stack */ |
| 179 | void FSQRT( void ) |
| 180 | { |
| 181 | write16( 0xFAD9 ); |
| 182 | } |
| 183 | |
| 184 | void FPATAN(void) { write16(0xf3d9); } |
| 185 | void FSIN(void) { write16(0xfed9); } |
| 186 | |
| 187 | /* fchs fpu reg stack */ |
| 188 | void FCHS( void ) |
| 189 | { |
| 190 | write16( 0xE0D9 ); |
| 191 | } |
| 192 | |
| 193 | /* fcomi st, st(i) */ |
| 194 | void FCOMI( x86IntRegType src ) |
| 195 | { |
| 196 | write8( 0xDB ); |
| 197 | write8( 0xF0 + src ); |
| 198 | } |
| 199 | |
| 200 | /* fcomip st, st(i) */ |
| 201 | void FCOMIP( x86IntRegType src ) |
| 202 | { |
| 203 | write8( 0xDF ); |
| 204 | write8( 0xF0 + src ); |
| 205 | } |
| 206 | |
| 207 | /* fucomi st, st(i) */ |
| 208 | void FUCOMI( x86IntRegType src ) |
| 209 | { |
| 210 | write8( 0xDB ); |
| 211 | write8( 0xE8 + src ); |
| 212 | } |
| 213 | |
| 214 | /* fucomip st, st(i) */ |
| 215 | void FUCOMIP( x86IntRegType src ) |
| 216 | { |
| 217 | write8( 0xDF ); |
| 218 | write8( 0xE8 + src ); |
| 219 | } |
| 220 | |
| 221 | /* fcom m32 to fpu reg stack */ |
| 222 | void FCOM32( uptr from ) |
| 223 | { |
| 224 | MEMADDR_OP(0, VAROP1(0xD8), false, 2, from, 0); |
| 225 | } |
| 226 | |
| 227 | /* fcomp m32 to fpu reg stack */ |
| 228 | void FCOMP32( uptr from ) |
| 229 | { |
| 230 | MEMADDR_OP(0, VAROP1(0xD8), false, 3, from, 0); |
| 231 | } |
| 232 | |
| 233 | #define FCMOV32( low, high ) \ |
| 234 | { \ |
| 235 | write8( low ); \ |
| 236 | write8( high + from ); \ |
| 237 | } |
| 238 | |
| 239 | void FCMOVB32( x86IntRegType from ) { FCMOV32( 0xDA, 0xC0 ); } |
| 240 | void FCMOVE32( x86IntRegType from ) { FCMOV32( 0xDA, 0xC8 ); } |
| 241 | void FCMOVBE32( x86IntRegType from ) { FCMOV32( 0xDA, 0xD0 ); } |
| 242 | void FCMOVU32( x86IntRegType from ) { FCMOV32( 0xDA, 0xD8 ); } |
| 243 | void FCMOVNB32( x86IntRegType from ) { FCMOV32( 0xDB, 0xC0 ); } |
| 244 | void FCMOVNE32( x86IntRegType from ) { FCMOV32( 0xDB, 0xC8 ); } |
| 245 | void FCMOVNBE32( x86IntRegType from ) { FCMOV32( 0xDB, 0xD0 ); } |
| 246 | void FCMOVNU32( x86IntRegType from ) { FCMOV32( 0xDB, 0xD8 ); } |
| 247 | |
| 248 | #endif |