| 1 | diff --git a/libpcsxcore/new_dynarec/emu_if.c b/libpcsxcore/new_dynarec/emu_if.c |
| 2 | index 10d99ba..1e097ae 100644 |
| 3 | --- a/libpcsxcore/new_dynarec/emu_if.c |
| 4 | +++ b/libpcsxcore/new_dynarec/emu_if.c |
| 5 | @@ -405,13 +407,17 @@ static void ari64_shutdown() |
| 6 | { |
| 7 | new_dynarec_cleanup(); |
| 8 | new_dyna_pcsx_mem_shutdown(); |
| 9 | + (void)ari64_execute; |
| 10 | } |
| 11 | |
| 12 | +extern void intExecuteT(); |
| 13 | +extern void intExecuteBlockT(); |
| 14 | + |
| 15 | R3000Acpu psxRec = { |
| 16 | ari64_init, |
| 17 | ari64_reset, |
| 18 | - ari64_execute, |
| 19 | - ari64_execute_until, |
| 20 | + intExecuteT, |
| 21 | + intExecuteBlockT, |
| 22 | ari64_clear, |
| 23 | ari64_notify, |
| 24 | ari64_apply_config, |
| 25 | @@ -481,7 +487,7 @@ static u32 memcheck_read(u32 a) |
| 26 | return *(u32 *)(psxM + (a & 0x1ffffc)); |
| 27 | } |
| 28 | |
| 29 | -#if 0 |
| 30 | +#if 1 |
| 31 | void do_insn_trace(void) |
| 32 | { |
| 33 | static psxRegisters oldregs; |
| 34 | diff --git a/libpcsxcore/new_dynarec/pcsxmem.c b/libpcsxcore/new_dynarec/pcsxmem.c |
| 35 | index bb471b6..8f68a3b 100644 |
| 36 | --- a/libpcsxcore/new_dynarec/pcsxmem.c |
| 37 | +++ b/libpcsxcore/new_dynarec/pcsxmem.c |
| 38 | @@ -272,6 +272,8 @@ static void write_biu(u32 value) |
| 39 | if (address != 0xfffe0130) |
| 40 | return; |
| 41 | |
| 42 | +extern u32 handler_cycle; |
| 43 | +handler_cycle = psxRegs.cycle; |
| 44 | switch (value) { |
| 45 | case 0x800: case 0x804: |
| 46 | unmap_ram_write(); |
| 47 | diff --git a/libpcsxcore/psxcounters.c b/libpcsxcore/psxcounters.c |
| 48 | index ff0efbc..4459644 100644 |
| 49 | --- a/libpcsxcore/psxcounters.c |
| 50 | +++ b/libpcsxcore/psxcounters.c |
| 51 | @@ -379,9 +379,12 @@ void psxRcntUpdate() |
| 52 | |
| 53 | /******************************************************************************/ |
| 54 | |
| 55 | +extern u32 handler_cycle; |
| 56 | + |
| 57 | void psxRcntWcount( u32 index, u32 value ) |
| 58 | { |
| 59 | verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value ); |
| 60 | +handler_cycle = psxRegs.cycle; |
| 61 | |
| 62 | _psxRcntWcount( index, value ); |
| 63 | psxRcntSet(); |
| 64 | @@ -390,6 +393,7 @@ void psxRcntWcount( u32 index, u32 value ) |
| 65 | void psxRcntWmode( u32 index, u32 value ) |
| 66 | { |
| 67 | verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value ); |
| 68 | +handler_cycle = psxRegs.cycle; |
| 69 | |
| 70 | _psxRcntWmode( index, value ); |
| 71 | _psxRcntWcount( index, 0 ); |
| 72 | @@ -401,6 +405,7 @@ void psxRcntWmode( u32 index, u32 value ) |
| 73 | void psxRcntWtarget( u32 index, u32 value ) |
| 74 | { |
| 75 | verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value ); |
| 76 | +handler_cycle = psxRegs.cycle; |
| 77 | |
| 78 | rcnts[index].target = value; |
| 79 | |
| 80 | @@ -413,6 +418,7 @@ void psxRcntWtarget( u32 index, u32 value ) |
| 81 | u32 psxRcntRcount( u32 index ) |
| 82 | { |
| 83 | u32 count; |
| 84 | +handler_cycle = psxRegs.cycle; |
| 85 | |
| 86 | count = _psxRcntRcount( index ); |
| 87 | |
| 88 | diff --git a/libpcsxcore/psxhw.c b/libpcsxcore/psxhw.c |
| 89 | index dbcb989..0716f5e 100644 |
| 90 | --- a/libpcsxcore/psxhw.c |
| 91 | +++ b/libpcsxcore/psxhw.c |
| 92 | @@ -373,13 +373,14 @@ void psxHwWrite8(u32 add, u8 value) { |
| 93 | case 0x1f801803: cdrWrite3(value); break; |
| 94 | |
| 95 | default: |
| 96 | + if (add < 0x1f802000) |
| 97 | psxHu8(add) = value; |
| 98 | #ifdef PSXHW_LOG |
| 99 | PSXHW_LOG("*Unknown 8bit write at address %x value %x\n", add, value); |
| 100 | #endif |
| 101 | return; |
| 102 | } |
| 103 | - psxHu8(add) = value; |
| 104 | + //psxHu8(add) = value; |
| 105 | #ifdef PSXHW_LOG |
| 106 | PSXHW_LOG("*Known 8bit write at address %x value %x\n", add, value); |
| 107 | #endif |
| 108 | @@ -504,6 +505,7 @@ void psxHwWrite16(u32 add, u16 value) { |
| 109 | return; |
| 110 | } |
| 111 | |
| 112 | + if (add < 0x1f802000) |
| 113 | psxHu16ref(add) = SWAPu16(value); |
| 114 | #ifdef PSXHW_LOG |
| 115 | PSXHW_LOG("*Unknown 16bit write at address %x value %x\n", add, value); |
| 116 | @@ -699,9 +701,9 @@ void psxHwWrite32(u32 add, u32 value) { |
| 117 | return; |
| 118 | |
| 119 | case 0x1f801820: |
| 120 | - mdecWrite0(value); break; |
| 121 | + mdecWrite0(value); return; |
| 122 | case 0x1f801824: |
| 123 | - mdecWrite1(value); break; |
| 124 | + mdecWrite1(value); return; |
| 125 | |
| 126 | case 0x1f801100: |
| 127 | #ifdef PSXHW_LOG |
| 128 | @@ -759,6 +761,7 @@ void psxHwWrite32(u32 add, u32 value) { |
| 129 | return; |
| 130 | } |
| 131 | |
| 132 | + if (add < 0x1f802000) |
| 133 | psxHu32ref(add) = SWAPu32(value); |
| 134 | #ifdef PSXHW_LOG |
| 135 | PSXHW_LOG("*Unknown 32bit write at address %x value %x\n", add, value); |
| 136 | diff --git a/libpcsxcore/psxinterpreter.c b/libpcsxcore/psxinterpreter.c |
| 137 | index e7e3269..8f4004d 100644 |
| 138 | --- a/libpcsxcore/psxinterpreter.c |
| 139 | +++ b/libpcsxcore/psxinterpreter.c |
| 140 | @@ -467,6 +467,8 @@ static void doBranch(u32 tar) { |
| 141 | psxRegs.pc += 4; |
| 142 | psxRegs.cycle += BIAS; |
| 143 | |
| 144 | + (void)tmp; |
| 145 | +#if 0 |
| 146 | // check for load delay |
| 147 | tmp = psxRegs.code >> 26; |
| 148 | switch (tmp) { |
| 149 | @@ -500,13 +502,15 @@ static void doBranch(u32 tar) { |
| 150 | } |
| 151 | break; |
| 152 | } |
| 153 | - |
| 154 | +#endif |
| 155 | psxBSC[psxRegs.code >> 26](); |
| 156 | |
| 157 | branch = 0; |
| 158 | psxRegs.pc = branchPC; |
| 159 | |
| 160 | + psxRegs.cycle += BIAS; |
| 161 | psxBranchTest(); |
| 162 | + psxRegs.cycle -= BIAS; |
| 163 | } |
| 164 | |
| 165 | /********************************************************* |
| 166 | @@ -616,12 +620,13 @@ void psxMULTU_stall() { |
| 167 | psxMULTU(); |
| 168 | } |
| 169 | |
| 170 | +#define doBranchNotTaken() do { psxRegs.cycle += BIAS; execI(); psxBranchTest(); psxRegs.cycle -= BIAS; } while(0) |
| 171 | /********************************************************* |
| 172 | * Register branch logic * |
| 173 | * Format: OP rs, offset * |
| 174 | *********************************************************/ |
| 175 | -#define RepZBranchi32(op) if(_i32(_rRs_) op 0) doBranch(_BranchTarget_); |
| 176 | -#define RepZBranchLinki32(op) { _SetLink(31); if(_i32(_rRs_) op 0) { doBranch(_BranchTarget_); } } |
| 177 | +#define RepZBranchi32(op) if(_i32(_rRs_) op 0) doBranch(_BranchTarget_); else doBranchNotTaken(); |
| 178 | +#define RepZBranchLinki32(op) { _SetLink(31); if(_i32(_rRs_) op 0) { doBranch(_BranchTarget_); } else doBranchNotTaken(); } |
| 179 | |
| 180 | void psxBGEZ() { RepZBranchi32(>=) } // Branch if Rs >= 0 |
| 181 | void psxBGEZAL() { RepZBranchLinki32(>=) } // Branch if Rs >= 0 and link |
| 182 | @@ -703,7 +708,7 @@ void psxRFE() { |
| 183 | * Register branch logic * |
| 184 | * Format: OP rs, rt, offset * |
| 185 | *********************************************************/ |
| 186 | -#define RepBranchi32(op) if(_i32(_rRs_) op _i32(_rRt_)) doBranch(_BranchTarget_); |
| 187 | +#define RepBranchi32(op) if(_i32(_rRs_) op _i32(_rRt_)) doBranch(_BranchTarget_); else doBranchNotTaken(); |
| 188 | |
| 189 | void psxBEQ() { RepBranchi32(==) } // Branch if Rs == Rt |
| 190 | void psxBNE() { RepBranchi32(!=) } // Branch if Rs != Rt |
| 191 | @@ -901,7 +907,7 @@ void MTC0(int reg, u32 val) { |
| 192 | } |
| 193 | } |
| 194 | |
| 195 | -void psxMTC0() { MTC0(_Rd_, _u32(_rRt_)); } |
| 196 | +void psxMTC0() { MTC0(_Rd_, _u32(_rRt_)); psxBranchTest(); } |
| 197 | void psxCTC0() { MTC0(_Rd_, _u32(_rRt_)); } |
| 198 | |
| 199 | /********************************************************* |
| 200 | @@ -1028,6 +1034,23 @@ void intExecuteBlock() { |
| 201 | while (!branch2) execI(); |
| 202 | } |
| 203 | |
| 204 | +extern void do_insn_trace(void); |
| 205 | + |
| 206 | +void intExecuteT() { |
| 207 | + for (;;) { |
| 208 | + do_insn_trace(); |
| 209 | + execI(); |
| 210 | + } |
| 211 | +} |
| 212 | + |
| 213 | +void intExecuteBlockT() { |
| 214 | + branch2 = 0; |
| 215 | + while (!branch2) { |
| 216 | + do_insn_trace(); |
| 217 | + execI(); |
| 218 | + } |
| 219 | +} |
| 220 | + |
| 221 | static void intClear(u32 Addr, u32 Size) { |
| 222 | } |
| 223 | |
| 224 | @@ -1050,7 +1073,7 @@ void intApplyConfig() { |
| 225 | assert(psxSPC[26] == psxDIV || psxSPC[26] == psxDIV_stall); |
| 226 | assert(psxSPC[27] == psxDIVU || psxSPC[27] == psxDIVU_stall); |
| 227 | |
| 228 | - if (Config.DisableStalls) { |
| 229 | + if (1) { |
| 230 | psxBSC[18] = psxCOP2; |
| 231 | psxBSC[50] = gteLWC2; |
| 232 | psxBSC[58] = gteSWC2; |
| 233 | @@ -1092,9 +1115,10 @@ void execI() { |
| 234 | if (Config.Debug) ProcessDebug(); |
| 235 | |
| 236 | psxRegs.pc += 4; |
| 237 | - psxRegs.cycle += BIAS; |
| 238 | |
| 239 | psxBSC[psxRegs.code >> 26](); |
| 240 | + |
| 241 | + psxRegs.cycle += BIAS; |
| 242 | } |
| 243 | |
| 244 | R3000Acpu psxInt = { |
| 245 | diff --git a/libpcsxcore/psxmem.c b/libpcsxcore/psxmem.c |
| 246 | index 46cee0c..c814587 100644 |
| 247 | --- a/libpcsxcore/psxmem.c |
| 248 | +++ b/libpcsxcore/psxmem.c |
| 249 | @@ -218,11 +218,13 @@ void psxMemShutdown() { |
| 250 | } |
| 251 | |
| 252 | static int writeok = 1; |
| 253 | +extern u32 last_io_addr; |
| 254 | |
| 255 | u8 psxMemRead8(u32 mem) { |
| 256 | char *p; |
| 257 | u32 t; |
| 258 | |
| 259 | + last_io_addr = mem; |
| 260 | t = mem >> 16; |
| 261 | if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) { |
| 262 | if ((mem & 0xffff) < 0x400) |
| 263 | @@ -248,6 +250,7 @@ u16 psxMemRead16(u32 mem) { |
| 264 | char *p; |
| 265 | u32 t; |
| 266 | |
| 267 | + last_io_addr = mem; |
| 268 | t = mem >> 16; |
| 269 | if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) { |
| 270 | if ((mem & 0xffff) < 0x400) |
| 271 | @@ -273,6 +276,7 @@ u32 psxMemRead32(u32 mem) { |
| 272 | char *p; |
| 273 | u32 t; |
| 274 | |
| 275 | + last_io_addr = mem; |
| 276 | t = mem >> 16; |
| 277 | if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) { |
| 278 | if ((mem & 0xffff) < 0x400) |
| 279 | @@ -298,6 +302,7 @@ void psxMemWrite8(u32 mem, u8 value) { |
| 280 | char *p; |
| 281 | u32 t; |
| 282 | |
| 283 | + last_io_addr = mem; |
| 284 | t = mem >> 16; |
| 285 | if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) { |
| 286 | if ((mem & 0xffff) < 0x400) |
| 287 | @@ -325,6 +330,7 @@ void psxMemWrite16(u32 mem, u16 value) { |
| 288 | char *p; |
| 289 | u32 t; |
| 290 | |
| 291 | + last_io_addr = mem; |
| 292 | t = mem >> 16; |
| 293 | if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) { |
| 294 | if ((mem & 0xffff) < 0x400) |
| 295 | @@ -352,6 +358,7 @@ void psxMemWrite32(u32 mem, u32 value) { |
| 296 | char *p; |
| 297 | u32 t; |
| 298 | |
| 299 | + last_io_addr = mem; |
| 300 | // if ((mem&0x1fffff) == 0x71E18 || value == 0x48088800) SysPrintf("t2fix!!\n"); |
| 301 | t = mem >> 16; |
| 302 | if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) { |
| 303 | @@ -381,6 +388,8 @@ void psxMemWrite32(u32 mem, u32 value) { |
| 304 | } else { |
| 305 | int i; |
| 306 | |
| 307 | +extern u32 handler_cycle; |
| 308 | +handler_cycle = psxRegs.cycle; |
| 309 | switch (value) { |
| 310 | case 0x800: case 0x804: |
| 311 | if (writeok == 0) break; |
| 312 | diff --git a/libpcsxcore/r3000a.c b/libpcsxcore/r3000a.c |
| 313 | index 7e6f16b..0114947 100644 |
| 314 | --- a/libpcsxcore/r3000a.c |
| 315 | +++ b/libpcsxcore/r3000a.c |
| 316 | @@ -120,6 +120,8 @@ void psxException(u32 code, u32 bd) { |
| 317 | } |
| 318 | |
| 319 | void psxBranchTest() { |
| 320 | + extern u32 irq_test_cycle; |
| 321 | + irq_test_cycle = psxRegs.cycle; |
| 322 | if ((psxRegs.cycle - psxNextsCounter) >= psxNextCounter) |
| 323 | psxRcntUpdate(); |
| 324 | |