| 1 | /* |
| 2 | * (C) GraÅžvydas "notaz" Ignotas, 2010-2011 |
| 3 | * |
| 4 | * This work is licensed under the terms of GNU GPL version 2 or later. |
| 5 | * See the COPYING file in the top-level directory. |
| 6 | */ |
| 7 | |
| 8 | #include <stdio.h> |
| 9 | #include "../psxhw.h" |
| 10 | #include "../cdrom.h" |
| 11 | #include "../mdec.h" |
| 12 | #include "../gpu.h" |
| 13 | #include "../psxmem_map.h" |
| 14 | #include "emu_if.h" |
| 15 | #include "pcsxmem.h" |
| 16 | |
| 17 | #ifdef __thumb__ |
| 18 | #error the dynarec is incompatible with Thumb functions, |
| 19 | #error please add -marm to compile flags |
| 20 | #endif |
| 21 | |
| 22 | //#define memprintf printf |
| 23 | #define memprintf(...) |
| 24 | |
| 25 | static uintptr_t *mem_readtab; |
| 26 | static uintptr_t *mem_writetab; |
| 27 | static uintptr_t mem_iortab[(1+2+4) * 0x1000 / 4]; |
| 28 | static uintptr_t mem_iowtab[(1+2+4) * 0x1000 / 4]; |
| 29 | static uintptr_t mem_ffrtab[(1+2+4) * 0x1000 / 4]; |
| 30 | static uintptr_t mem_ffwtab[(1+2+4) * 0x1000 / 4]; |
| 31 | //static uintptr_t mem_unmrtab[(1+2+4) * 0x1000 / 4]; |
| 32 | static uintptr_t mem_unmwtab[(1+2+4) * 0x1000 / 4]; |
| 33 | |
| 34 | static |
| 35 | #ifdef __clang__ |
| 36 | // When this is called in a loop, and 'h' is a function pointer, clang will crash. |
| 37 | __attribute__ ((noinline)) |
| 38 | #endif |
| 39 | void map_item(uintptr_t *out, const void *h, uintptr_t flag) |
| 40 | { |
| 41 | uintptr_t hv = (uintptr_t)h; |
| 42 | if (hv & 1) { |
| 43 | SysPrintf("FATAL: %p has LSB set\n", h); |
| 44 | abort(); |
| 45 | } |
| 46 | *out = (hv >> 1) | (flag << (sizeof(hv) * 8 - 1)); |
| 47 | } |
| 48 | |
| 49 | // size must be power of 2, at least 4k |
| 50 | #define map_l1_mem(tab, i, addr, size, base) \ |
| 51 | map_item(&tab[((u32)(addr) >> 12) + i], \ |
| 52 | (u8 *)(base) - (u32)((addr) + ((i << 12) & ~(size - 1))), 0) |
| 53 | |
| 54 | #define IOMEM32(a) (((a) & 0xfff) / 4) |
| 55 | #define IOMEM16(a) (0x1000/4 + (((a) & 0xfff) / 2)) |
| 56 | #define IOMEM8(a) (0x1000/4 + 0x1000/2 + ((a) & 0xfff)) |
| 57 | |
| 58 | u32 zero_mem[0x1000/4]; |
| 59 | static u32 ffff_mem[0x1000/4]; |
| 60 | |
| 61 | static u32 read_mem_dummy(u32 addr) |
| 62 | { |
| 63 | // use 'addr' and not 'address', yes the api is weird... |
| 64 | memprintf("unmapped r %08x @%08x %u\n", addr, psxRegs.pc, psxRegs.cycle); |
| 65 | return 0xffffffff; |
| 66 | } |
| 67 | |
| 68 | static void write_mem_dummy(u32 data) |
| 69 | { |
| 70 | if (!(psxRegs.CP0.n.SR & (1 << 16))) |
| 71 | memprintf("unmapped w %08x, %08x @%08x %u\n", |
| 72 | address, data, psxRegs.pc, psxRegs.cycle); |
| 73 | } |
| 74 | |
| 75 | /* IO handlers */ |
| 76 | static u32 io_read_sio16() |
| 77 | { |
| 78 | return sioRead8() | (sioRead8() << 8); |
| 79 | } |
| 80 | |
| 81 | static u32 io_read_sio32() |
| 82 | { |
| 83 | return sioRead8() | (sioRead8() << 8) | (sioRead8() << 16) | (sioRead8() << 24); |
| 84 | } |
| 85 | |
| 86 | static void io_write_sio16(u32 value) |
| 87 | { |
| 88 | sioWrite8((unsigned char)value); |
| 89 | sioWrite8((unsigned char)(value>>8)); |
| 90 | } |
| 91 | |
| 92 | static void io_write_sio32(u32 value) |
| 93 | { |
| 94 | sioWrite8((unsigned char)value); |
| 95 | sioWrite8((unsigned char)(value >> 8)); |
| 96 | sioWrite8((unsigned char)(value >> 16)); |
| 97 | sioWrite8((unsigned char)(value >> 24)); |
| 98 | } |
| 99 | |
| 100 | #if !defined(DRC_DBG) && defined(__arm__) |
| 101 | |
| 102 | static void map_rcnt_rcount0(u32 mode) |
| 103 | { |
| 104 | if (mode & 0x001) { // sync mode |
| 105 | map_item(&mem_iortab[IOMEM32(0x1100)], psxRcntRcount0, 1); |
| 106 | map_item(&mem_iortab[IOMEM16(0x1100)], psxRcntRcount0, 1); |
| 107 | } |
| 108 | else if (mode & 0x100) { // pixel clock |
| 109 | map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m1, 1); |
| 110 | map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m1, 1); |
| 111 | } |
| 112 | else { |
| 113 | map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m0, 1); |
| 114 | map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m0, 1); |
| 115 | } |
| 116 | } |
| 117 | |
| 118 | static void map_rcnt_rcount1(u32 mode) |
| 119 | { |
| 120 | if (mode & 0x001) { // sync mode |
| 121 | map_item(&mem_iortab[IOMEM32(0x1110)], psxRcntRcount1, 1); |
| 122 | map_item(&mem_iortab[IOMEM16(0x1110)], psxRcntRcount1, 1); |
| 123 | } |
| 124 | else if (mode & 0x100) { // hcnt |
| 125 | map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m1, 1); |
| 126 | map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m1, 1); |
| 127 | } |
| 128 | else { |
| 129 | map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m0, 1); |
| 130 | map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m0, 1); |
| 131 | } |
| 132 | } |
| 133 | |
| 134 | static void map_rcnt_rcount2(u32 mode) |
| 135 | { |
| 136 | if ((mode & 7) == 1 || (mode & 7) == 7) { // sync mode |
| 137 | map_item(&mem_iortab[IOMEM32(0x1120)], &psxH[0x1000], 0); |
| 138 | map_item(&mem_iortab[IOMEM16(0x1120)], &psxH[0x1000], 0); |
| 139 | } |
| 140 | else if (mode & 0x200) { // clk/8 |
| 141 | map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m1, 1); |
| 142 | map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m1, 1); |
| 143 | } |
| 144 | else { |
| 145 | map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m0, 1); |
| 146 | map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m0, 1); |
| 147 | } |
| 148 | } |
| 149 | |
| 150 | #else |
| 151 | #define map_rcnt_rcount0(mode) |
| 152 | #define map_rcnt_rcount1(mode) |
| 153 | #define map_rcnt_rcount2(mode) |
| 154 | #endif |
| 155 | |
| 156 | #define make_rcnt_funcs(i) \ |
| 157 | static u32 io_rcnt_read_mode##i() { return psxRcntRmode(i); } \ |
| 158 | static u32 io_rcnt_read_target##i() { return psxRcntRtarget(i); } \ |
| 159 | static void io_rcnt_write_count##i(u32 val) { psxRcntWcount(i, val & 0xffff); } \ |
| 160 | static void io_rcnt_write_mode##i(u32 val) { psxRcntWmode(i, val); map_rcnt_rcount##i(val); } \ |
| 161 | static void io_rcnt_write_target##i(u32 val) { psxRcntWtarget(i, val & 0xffff); } |
| 162 | |
| 163 | make_rcnt_funcs(0) |
| 164 | make_rcnt_funcs(1) |
| 165 | make_rcnt_funcs(2) |
| 166 | |
| 167 | #define make_dma_func(n) \ |
| 168 | static void io_write_chcr##n(u32 value) \ |
| 169 | { \ |
| 170 | HW_DMA##n##_CHCR = value; \ |
| 171 | if (value & 0x01000000 && HW_DMA_PCR & (8 << (n * 4))) { \ |
| 172 | psxDma##n(HW_DMA##n##_MADR, HW_DMA##n##_BCR, value); \ |
| 173 | } \ |
| 174 | } |
| 175 | |
| 176 | make_dma_func(0) |
| 177 | make_dma_func(1) |
| 178 | make_dma_func(2) |
| 179 | make_dma_func(3) |
| 180 | make_dma_func(4) |
| 181 | make_dma_func(6) |
| 182 | |
| 183 | static u32 io_spu_read8_even(u32 addr) |
| 184 | { |
| 185 | return SPU_readRegister(addr, psxRegs.cycle) & 0xff; |
| 186 | } |
| 187 | |
| 188 | static u32 io_spu_read8_odd(u32 addr) |
| 189 | { |
| 190 | return SPU_readRegister(addr, psxRegs.cycle) >> 8; |
| 191 | } |
| 192 | |
| 193 | static u32 io_spu_read16(u32 addr) |
| 194 | { |
| 195 | return SPU_readRegister(addr, psxRegs.cycle); |
| 196 | } |
| 197 | |
| 198 | static u32 io_spu_read32(u32 addr) |
| 199 | { |
| 200 | u32 ret; |
| 201 | ret = SPU_readRegister(addr, psxRegs.cycle); |
| 202 | ret |= SPU_readRegister(addr + 2, psxRegs.cycle) << 16; |
| 203 | return ret; |
| 204 | } |
| 205 | |
| 206 | static void io_spu_write16(u32 value) |
| 207 | { |
| 208 | // meh |
| 209 | SPU_writeRegister(address, value, psxRegs.cycle); |
| 210 | } |
| 211 | |
| 212 | static void io_spu_write32(u32 value) |
| 213 | { |
| 214 | SPUwriteRegister wfunc = SPU_writeRegister; |
| 215 | u32 a = address; |
| 216 | |
| 217 | wfunc(a, value & 0xffff, psxRegs.cycle); |
| 218 | wfunc(a + 2, value >> 16, psxRegs.cycle); |
| 219 | } |
| 220 | |
| 221 | static u32 io_gpu_read_status(void) |
| 222 | { |
| 223 | u32 v; |
| 224 | |
| 225 | // meh2, syncing for img bit, might want to avoid it.. |
| 226 | gpuSyncPluginSR(); |
| 227 | v = HW_GPU_STATUS; |
| 228 | |
| 229 | // XXX: because of large timeslices can't use hSyncCount, using rough |
| 230 | // approximization instead. Perhaps better use hcounter code here or something. |
| 231 | if (hSyncCount < 240 && (HW_GPU_STATUS & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS) |
| 232 | v |= PSXGPU_LCF & (psxRegs.cycle << 20); |
| 233 | return v; |
| 234 | } |
| 235 | |
| 236 | static void io_gpu_write_status(u32 value) |
| 237 | { |
| 238 | GPU_writeStatus(value); |
| 239 | gpuSyncPluginSR(); |
| 240 | } |
| 241 | |
| 242 | void new_dyna_pcsx_mem_isolate(int enable) |
| 243 | { |
| 244 | int i; |
| 245 | |
| 246 | // note: apparently 0xa0000000 uncached access still works, |
| 247 | // at least read does for sure, so assume write does too |
| 248 | memprintf("mem isolate %d\n", enable); |
| 249 | if (enable) { |
| 250 | for (i = 0; i < (0x800000 >> 12); i++) { |
| 251 | map_item(&mem_writetab[0x80000|i], mem_unmwtab, 1); |
| 252 | map_item(&mem_writetab[0x00000|i], mem_unmwtab, 1); |
| 253 | //map_item(&mem_writetab[0xa0000|i], mem_unmwtab, 1); |
| 254 | } |
| 255 | } |
| 256 | else { |
| 257 | for (i = 0; i < (0x800000 >> 12); i++) { |
| 258 | map_l1_mem(mem_writetab, i, 0x80000000, 0x200000, psxM); |
| 259 | map_l1_mem(mem_writetab, i, 0x00000000, 0x200000, psxM); |
| 260 | map_l1_mem(mem_writetab, i, 0xa0000000, 0x200000, psxM); |
| 261 | } |
| 262 | } |
| 263 | } |
| 264 | |
| 265 | static u32 read_biu(u32 addr) |
| 266 | { |
| 267 | if (addr != 0xfffe0130) |
| 268 | return read_mem_dummy(addr); |
| 269 | |
| 270 | memprintf("read_biu %08x @%08x %u\n", |
| 271 | psxRegs.biuReg, psxRegs.pc, psxRegs.cycle); |
| 272 | return psxRegs.biuReg; |
| 273 | } |
| 274 | |
| 275 | static void write_biu(u32 value) |
| 276 | { |
| 277 | if (address != 0xfffe0130) { |
| 278 | write_mem_dummy(value); |
| 279 | return; |
| 280 | } |
| 281 | |
| 282 | memprintf("write_biu %08x @%08x %u\n", value, psxRegs.pc, psxRegs.cycle); |
| 283 | psxRegs.biuReg = value; |
| 284 | } |
| 285 | |
| 286 | void new_dyna_pcsx_mem_load_state(void) |
| 287 | { |
| 288 | map_rcnt_rcount0(rcnts[0].mode); |
| 289 | map_rcnt_rcount1(rcnts[1].mode); |
| 290 | map_rcnt_rcount2(rcnts[2].mode); |
| 291 | } |
| 292 | |
| 293 | int pcsxmem_is_handler_dynamic(unsigned int addr) |
| 294 | { |
| 295 | if ((addr & 0xfffff000) != 0x1f801000) |
| 296 | return 0; |
| 297 | |
| 298 | addr &= 0xffff; |
| 299 | return addr == 0x1100 || addr == 0x1110 || addr == 0x1120; |
| 300 | } |
| 301 | |
| 302 | void new_dyna_pcsx_mem_init(void) |
| 303 | { |
| 304 | int i; |
| 305 | |
| 306 | memset(ffff_mem, 0xff, sizeof(ffff_mem)); |
| 307 | |
| 308 | // have to map these further to keep tcache close to .text |
| 309 | mem_readtab = psxMap(0x08000000, 0x200000 * sizeof(mem_readtab[0]), 0, MAP_TAG_LUTS); |
| 310 | if (mem_readtab == NULL) { |
| 311 | SysPrintf("failed to map mem tables\n"); |
| 312 | exit(1); |
| 313 | } |
| 314 | mem_writetab = mem_readtab + 0x100000; |
| 315 | |
| 316 | // 1st level lookup: |
| 317 | // 0: direct mem |
| 318 | // 1: use 2nd lookup |
| 319 | // 2nd level lookup: |
| 320 | // 0: direct mem variable |
| 321 | // 1: memhandler |
| 322 | |
| 323 | // default/unmapped memhandlers |
| 324 | for (i = 0; i < 0x100000; i++) { |
| 325 | //map_item(&mem_readtab[i], mem_unmrtab, 1); |
| 326 | map_l1_mem(mem_readtab, i, 0, 0x1000, ffff_mem); |
| 327 | map_item(&mem_writetab[i], mem_unmwtab, 1); |
| 328 | } |
| 329 | |
| 330 | // RAM and it's mirrors |
| 331 | for (i = 0; i < (0x800000 >> 12); i++) { |
| 332 | map_l1_mem(mem_readtab, i, 0x80000000, 0x200000, psxM); |
| 333 | map_l1_mem(mem_readtab, i, 0x00000000, 0x200000, psxM); |
| 334 | map_l1_mem(mem_readtab, i, 0xa0000000, 0x200000, psxM); |
| 335 | } |
| 336 | new_dyna_pcsx_mem_isolate(0); |
| 337 | |
| 338 | // BIOS and it's mirrors |
| 339 | for (i = 0; i < (0x80000 >> 12); i++) { |
| 340 | map_l1_mem(mem_readtab, i, 0x1fc00000, 0x80000, psxR); |
| 341 | map_l1_mem(mem_readtab, i, 0xbfc00000, 0x80000, psxR); |
| 342 | } |
| 343 | |
| 344 | // scratchpad |
| 345 | map_l1_mem(mem_readtab, 0, 0x1f800000, 0x1000, psxH); |
| 346 | map_l1_mem(mem_readtab, 0, 0x9f800000, 0x1000, psxH); |
| 347 | map_l1_mem(mem_writetab, 0, 0x1f800000, 0x1000, psxH); |
| 348 | map_l1_mem(mem_writetab, 0, 0x9f800000, 0x1000, psxH); |
| 349 | |
| 350 | // I/O |
| 351 | map_item(&mem_readtab[0x1f801000u >> 12], mem_iortab, 1); |
| 352 | map_item(&mem_readtab[0x9f801000u >> 12], mem_iortab, 1); |
| 353 | map_item(&mem_readtab[0xbf801000u >> 12], mem_iortab, 1); |
| 354 | map_item(&mem_writetab[0x1f801000u >> 12], mem_iowtab, 1); |
| 355 | map_item(&mem_writetab[0x9f801000u >> 12], mem_iowtab, 1); |
| 356 | map_item(&mem_writetab[0xbf801000u >> 12], mem_iowtab, 1); |
| 357 | |
| 358 | // L2 |
| 359 | // unmapped tables |
| 360 | for (i = 0; i < (1+2+4) * 0x1000 / 4; i++) |
| 361 | map_item(&mem_unmwtab[i], write_mem_dummy, 1); |
| 362 | |
| 363 | // fill IO tables |
| 364 | for (i = 0; i < 0x1000/4; i++) { |
| 365 | map_item(&mem_iortab[i], &psxH[0x1000], 0); |
| 366 | map_item(&mem_iowtab[i], &psxH[0x1000], 0); |
| 367 | } |
| 368 | for (; i < 0x1000/4 + 0x1000/2; i++) { |
| 369 | map_item(&mem_iortab[i], &psxH[0x1000], 0); |
| 370 | map_item(&mem_iowtab[i], &psxH[0x1000], 0); |
| 371 | } |
| 372 | for (; i < 0x1000/4 + 0x1000/2 + 0x1000; i++) { |
| 373 | map_item(&mem_iortab[i], &psxH[0x1000], 0); |
| 374 | map_item(&mem_iowtab[i], &psxH[0x1000], 0); |
| 375 | } |
| 376 | |
| 377 | map_item(&mem_iortab[IOMEM32(0x1040)], io_read_sio32, 1); |
| 378 | map_item(&mem_iortab[IOMEM32(0x1100)], psxRcntRcount0, 1); |
| 379 | map_item(&mem_iortab[IOMEM32(0x1104)], io_rcnt_read_mode0, 1); |
| 380 | map_item(&mem_iortab[IOMEM32(0x1108)], io_rcnt_read_target0, 1); |
| 381 | map_item(&mem_iortab[IOMEM32(0x1110)], psxRcntRcount1, 1); |
| 382 | map_item(&mem_iortab[IOMEM32(0x1114)], io_rcnt_read_mode1, 1); |
| 383 | map_item(&mem_iortab[IOMEM32(0x1118)], io_rcnt_read_target1, 1); |
| 384 | map_item(&mem_iortab[IOMEM32(0x1120)], psxRcntRcount2, 1); |
| 385 | map_item(&mem_iortab[IOMEM32(0x1124)], io_rcnt_read_mode2, 1); |
| 386 | map_item(&mem_iortab[IOMEM32(0x1128)], io_rcnt_read_target2, 1); |
| 387 | // map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1); |
| 388 | map_item(&mem_iortab[IOMEM32(0x1814)], io_gpu_read_status, 1); |
| 389 | map_item(&mem_iortab[IOMEM32(0x1820)], mdecRead0, 1); |
| 390 | map_item(&mem_iortab[IOMEM32(0x1824)], mdecRead1, 1); |
| 391 | |
| 392 | map_item(&mem_iortab[IOMEM16(0x1040)], io_read_sio16, 1); |
| 393 | map_item(&mem_iortab[IOMEM16(0x1044)], sioReadStat16, 1); |
| 394 | map_item(&mem_iortab[IOMEM16(0x1048)], sioReadMode16, 1); |
| 395 | map_item(&mem_iortab[IOMEM16(0x104a)], sioReadCtrl16, 1); |
| 396 | map_item(&mem_iortab[IOMEM16(0x104e)], sioReadBaud16, 1); |
| 397 | map_item(&mem_iortab[IOMEM16(0x1100)], psxRcntRcount0, 1); |
| 398 | map_item(&mem_iortab[IOMEM16(0x1104)], io_rcnt_read_mode0, 1); |
| 399 | map_item(&mem_iortab[IOMEM16(0x1108)], io_rcnt_read_target0, 1); |
| 400 | map_item(&mem_iortab[IOMEM16(0x1110)], psxRcntRcount1, 1); |
| 401 | map_item(&mem_iortab[IOMEM16(0x1114)], io_rcnt_read_mode1, 1); |
| 402 | map_item(&mem_iortab[IOMEM16(0x1118)], io_rcnt_read_target1, 1); |
| 403 | map_item(&mem_iortab[IOMEM16(0x1120)], psxRcntRcount2, 1); |
| 404 | map_item(&mem_iortab[IOMEM16(0x1124)], io_rcnt_read_mode2, 1); |
| 405 | map_item(&mem_iortab[IOMEM16(0x1128)], io_rcnt_read_target2, 1); |
| 406 | |
| 407 | map_item(&mem_iortab[IOMEM8(0x1040)], sioRead8, 1); |
| 408 | map_item(&mem_iortab[IOMEM8(0x1800)], cdrRead0, 1); |
| 409 | map_item(&mem_iortab[IOMEM8(0x1801)], cdrRead1, 1); |
| 410 | map_item(&mem_iortab[IOMEM8(0x1802)], cdrRead2, 1); |
| 411 | map_item(&mem_iortab[IOMEM8(0x1803)], cdrRead3, 1); |
| 412 | |
| 413 | for (i = 0x1c00; i < 0x2000; i += 2) { |
| 414 | map_item(&mem_iortab[IOMEM8(i)], io_spu_read8_even, 1); |
| 415 | map_item(&mem_iortab[IOMEM8(i+1)], io_spu_read8_odd, 1); |
| 416 | map_item(&mem_iortab[IOMEM16(i)], io_spu_read16, 1); |
| 417 | map_item(&mem_iortab[IOMEM32(i)], io_spu_read32, 1); |
| 418 | } |
| 419 | |
| 420 | // write(u32 data) |
| 421 | map_item(&mem_iowtab[IOMEM32(0x1040)], io_write_sio32, 1); |
| 422 | map_item(&mem_iowtab[IOMEM32(0x1070)], psxHwWriteIstat, 1); |
| 423 | map_item(&mem_iowtab[IOMEM32(0x1074)], psxHwWriteImask, 1); |
| 424 | map_item(&mem_iowtab[IOMEM32(0x1088)], io_write_chcr0, 1); |
| 425 | map_item(&mem_iowtab[IOMEM32(0x1098)], io_write_chcr1, 1); |
| 426 | map_item(&mem_iowtab[IOMEM32(0x10a8)], io_write_chcr2, 1); |
| 427 | map_item(&mem_iowtab[IOMEM32(0x10b8)], io_write_chcr3, 1); |
| 428 | map_item(&mem_iowtab[IOMEM32(0x10c8)], io_write_chcr4, 1); |
| 429 | map_item(&mem_iowtab[IOMEM32(0x10e8)], io_write_chcr6, 1); |
| 430 | map_item(&mem_iowtab[IOMEM32(0x10f4)], psxHwWriteDmaIcr32, 1); |
| 431 | map_item(&mem_iowtab[IOMEM32(0x1100)], io_rcnt_write_count0, 1); |
| 432 | map_item(&mem_iowtab[IOMEM32(0x1104)], io_rcnt_write_mode0, 1); |
| 433 | map_item(&mem_iowtab[IOMEM32(0x1108)], io_rcnt_write_target0, 1); |
| 434 | map_item(&mem_iowtab[IOMEM32(0x1110)], io_rcnt_write_count1, 1); |
| 435 | map_item(&mem_iowtab[IOMEM32(0x1114)], io_rcnt_write_mode1, 1); |
| 436 | map_item(&mem_iowtab[IOMEM32(0x1118)], io_rcnt_write_target1, 1); |
| 437 | map_item(&mem_iowtab[IOMEM32(0x1120)], io_rcnt_write_count2, 1); |
| 438 | map_item(&mem_iowtab[IOMEM32(0x1124)], io_rcnt_write_mode2, 1); |
| 439 | map_item(&mem_iowtab[IOMEM32(0x1128)], io_rcnt_write_target2, 1); |
| 440 | // map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1); |
| 441 | map_item(&mem_iowtab[IOMEM32(0x1814)], io_gpu_write_status, 1); |
| 442 | map_item(&mem_iowtab[IOMEM32(0x1820)], mdecWrite0, 1); |
| 443 | map_item(&mem_iowtab[IOMEM32(0x1824)], mdecWrite1, 1); |
| 444 | |
| 445 | map_item(&mem_iowtab[IOMEM16(0x1040)], io_write_sio16, 1); |
| 446 | map_item(&mem_iowtab[IOMEM16(0x1044)], sioWriteStat16, 1); |
| 447 | map_item(&mem_iowtab[IOMEM16(0x1048)], sioWriteMode16, 1); |
| 448 | map_item(&mem_iowtab[IOMEM16(0x104a)], sioWriteCtrl16, 1); |
| 449 | map_item(&mem_iowtab[IOMEM16(0x104e)], sioWriteBaud16, 1); |
| 450 | map_item(&mem_iowtab[IOMEM16(0x1070)], psxHwWriteIstat, 1); |
| 451 | map_item(&mem_iowtab[IOMEM16(0x1074)], psxHwWriteImask, 1); |
| 452 | map_item(&mem_iowtab[IOMEM16(0x1100)], io_rcnt_write_count0, 1); |
| 453 | map_item(&mem_iowtab[IOMEM16(0x1104)], io_rcnt_write_mode0, 1); |
| 454 | map_item(&mem_iowtab[IOMEM16(0x1108)], io_rcnt_write_target0, 1); |
| 455 | map_item(&mem_iowtab[IOMEM16(0x1110)], io_rcnt_write_count1, 1); |
| 456 | map_item(&mem_iowtab[IOMEM16(0x1114)], io_rcnt_write_mode1, 1); |
| 457 | map_item(&mem_iowtab[IOMEM16(0x1118)], io_rcnt_write_target1, 1); |
| 458 | map_item(&mem_iowtab[IOMEM16(0x1120)], io_rcnt_write_count2, 1); |
| 459 | map_item(&mem_iowtab[IOMEM16(0x1124)], io_rcnt_write_mode2, 1); |
| 460 | map_item(&mem_iowtab[IOMEM16(0x1128)], io_rcnt_write_target2, 1); |
| 461 | |
| 462 | map_item(&mem_iowtab[IOMEM8(0x1040)], sioWrite8, 1); |
| 463 | map_item(&mem_iowtab[IOMEM8(0x1800)], cdrWrite0, 1); |
| 464 | map_item(&mem_iowtab[IOMEM8(0x1801)], cdrWrite1, 1); |
| 465 | map_item(&mem_iowtab[IOMEM8(0x1802)], cdrWrite2, 1); |
| 466 | map_item(&mem_iowtab[IOMEM8(0x1803)], cdrWrite3, 1); |
| 467 | |
| 468 | for (i = 0x1c00; i < 0x2000; i += 2) { |
| 469 | map_item(&mem_iowtab[IOMEM16(i)], io_spu_write16, 1); |
| 470 | map_item(&mem_iowtab[IOMEM32(i)], io_spu_write32, 1); |
| 471 | } |
| 472 | |
| 473 | // misc |
| 474 | map_item(&mem_readtab[0xfffe0130u >> 12], mem_ffrtab, 1); |
| 475 | map_item(&mem_writetab[0xfffe0130u >> 12], mem_ffwtab, 1); |
| 476 | for (i = 0; i < 0x1000/4 + 0x1000/2 + 0x1000; i++) { |
| 477 | map_item(&mem_ffrtab[i], read_biu, 1); |
| 478 | map_item(&mem_ffwtab[i], write_biu, 1); |
| 479 | } |
| 480 | |
| 481 | mem_rtab = mem_readtab; |
| 482 | mem_wtab = mem_writetab; |
| 483 | |
| 484 | new_dyna_pcsx_mem_load_state(); |
| 485 | } |
| 486 | |
| 487 | void new_dyna_pcsx_mem_reset(void) |
| 488 | { |
| 489 | // plugins might change so update the pointers |
| 490 | map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1); |
| 491 | map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1); |
| 492 | } |
| 493 | |
| 494 | void new_dyna_pcsx_mem_shutdown(void) |
| 495 | { |
| 496 | psxUnmap(mem_readtab, 0x200000 * sizeof(mem_readtab[0]), MAP_TAG_LUTS); |
| 497 | mem_writetab = mem_readtab = NULL; |
| 498 | } |