| 1 | /* |
| 2 | * (C) GraÅžvydas "notaz" Ignotas, 2010-2011 |
| 3 | * |
| 4 | * This work is licensed under the terms of GNU GPL version 2 or later. |
| 5 | * See the COPYING file in the top-level directory. |
| 6 | */ |
| 7 | |
| 8 | #include <stdio.h> |
| 9 | #include <sys/mman.h> |
| 10 | #include "../psxhw.h" |
| 11 | #include "../cdrom.h" |
| 12 | #include "../mdec.h" |
| 13 | #include "emu_if.h" |
| 14 | #include "pcsxmem.h" |
| 15 | |
| 16 | //#define memprintf printf |
| 17 | #define memprintf(...) |
| 18 | |
| 19 | static u8 unmapped_mem[0x1000]; |
| 20 | int pcsx_ram_is_ro; |
| 21 | |
| 22 | static void read_mem8() |
| 23 | { |
| 24 | memprintf("ari64_read_mem8 %08x @%08x %u\n", address, psxRegs.pc, psxRegs.cycle); |
| 25 | readmem_word = psxMemRead8(address) & 0xff; |
| 26 | } |
| 27 | |
| 28 | static void read_mem16() |
| 29 | { |
| 30 | memprintf("ari64_read_mem16 %08x @%08x %u\n", address, psxRegs.pc, psxRegs.cycle); |
| 31 | readmem_word = psxMemRead16(address) & 0xffff; |
| 32 | } |
| 33 | |
| 34 | static void read_mem32() |
| 35 | { |
| 36 | memprintf("ari64_read_mem32 %08x @%08x %u\n", address, psxRegs.pc, psxRegs.cycle); |
| 37 | readmem_word = psxMemRead32(address); |
| 38 | } |
| 39 | |
| 40 | static void write_mem8() |
| 41 | { |
| 42 | memprintf("ari64_write_mem8 %08x, %02x @%08x %u\n", address, byte, psxRegs.pc, psxRegs.cycle); |
| 43 | psxMemWrite8(address, byte); |
| 44 | } |
| 45 | |
| 46 | static void write_mem16() |
| 47 | { |
| 48 | memprintf("ari64_write_mem16 %08x, %04x @%08x %u\n", address, hword, psxRegs.pc, psxRegs.cycle); |
| 49 | psxMemWrite16(address, hword); |
| 50 | } |
| 51 | |
| 52 | static void write_mem32() |
| 53 | { |
| 54 | memprintf("ari64_write_mem32 %08x, %08x @%08x %u\n", address, word, psxRegs.pc, psxRegs.cycle); |
| 55 | psxMemWrite32(address, word); |
| 56 | } |
| 57 | |
| 58 | static void read_mem_dummy() |
| 59 | { |
| 60 | readmem_word = 0; |
| 61 | } |
| 62 | |
| 63 | static void write_mem_dummy(u32 data) |
| 64 | { |
| 65 | memprintf("unmapped w %08x, %08x @%08x %u\n", address, data, psxRegs.pc, psxRegs.cycle); |
| 66 | } |
| 67 | |
| 68 | extern void ari_read_ram8(); |
| 69 | extern void ari_read_ram16(); |
| 70 | extern void ari_read_ram32(); |
| 71 | extern void ari_read_ram_mirror8(); |
| 72 | extern void ari_read_ram_mirror16(); |
| 73 | extern void ari_read_ram_mirror32(); |
| 74 | extern void ari_write_ram8(); |
| 75 | extern void ari_write_ram16(); |
| 76 | extern void ari_write_ram32(); |
| 77 | extern void ari_write_ram_mirror8(); |
| 78 | extern void ari_write_ram_mirror16(); |
| 79 | extern void ari_write_ram_mirror32(); |
| 80 | extern void ari_write_ram_mirror_ro32(); |
| 81 | extern void ari_read_bios8(); |
| 82 | extern void ari_read_bios16(); |
| 83 | extern void ari_read_bios32(); |
| 84 | extern void ari_read_io8(); |
| 85 | extern void ari_read_io16(); |
| 86 | extern void ari_read_io32(); |
| 87 | extern void ari_write_io8(); |
| 88 | extern void ari_write_io16(); |
| 89 | extern void ari_write_io32(); |
| 90 | |
| 91 | void (*readmem[0x10000])(); |
| 92 | void (*readmemb[0x10000])(); |
| 93 | void (*readmemh[0x10000])(); |
| 94 | void (*writemem[0x10000])(); |
| 95 | void (*writememb[0x10000])(); |
| 96 | void (*writememh[0x10000])(); |
| 97 | |
| 98 | static void write_biu_() |
| 99 | { |
| 100 | memprintf("write_biu %08x, %08x @%08x %u\n", address, word, psxRegs.pc, psxRegs.cycle); |
| 101 | |
| 102 | if (address != 0xfffe0130) |
| 103 | return; |
| 104 | |
| 105 | switch (word) { |
| 106 | case 0x800: case 0x804: |
| 107 | pcsx_ram_is_ro = 1; |
| 108 | break; |
| 109 | case 0: case 0x1e988: |
| 110 | pcsx_ram_is_ro = 0; |
| 111 | break; |
| 112 | default: |
| 113 | memprintf("write_biu: unexpected val: %08x\n", word); |
| 114 | break; |
| 115 | } |
| 116 | } |
| 117 | |
| 118 | /* IO handlers */ |
| 119 | static u32 io_read_sio16() |
| 120 | { |
| 121 | return sioRead8() | (sioRead8() << 8); |
| 122 | } |
| 123 | |
| 124 | static u32 io_read_sio32() |
| 125 | { |
| 126 | return sioRead8() | (sioRead8() << 8) | (sioRead8() << 16) | (sioRead8() << 24); |
| 127 | } |
| 128 | |
| 129 | static void io_write_sio16(u32 value) |
| 130 | { |
| 131 | sioWrite8((unsigned char)value); |
| 132 | sioWrite8((unsigned char)(value>>8)); |
| 133 | } |
| 134 | |
| 135 | static void io_write_sio32(u32 value) |
| 136 | { |
| 137 | sioWrite8((unsigned char)value); |
| 138 | sioWrite8((unsigned char)(value >> 8)); |
| 139 | sioWrite8((unsigned char)(value >> 16)); |
| 140 | sioWrite8((unsigned char)(value >> 24)); |
| 141 | } |
| 142 | |
| 143 | #define make_rcnt_funcs(i) \ |
| 144 | static u32 io_rcnt_read_count##i() { return psxRcntRcount(i); } \ |
| 145 | static u32 io_rcnt_read_mode##i() { return psxRcntRmode(i); } \ |
| 146 | static u32 io_rcnt_read_target##i() { return psxRcntRtarget(i); } \ |
| 147 | static void io_rcnt_write_count##i(u32 val) { psxRcntWcount(i, val & 0xffff); } \ |
| 148 | static void io_rcnt_write_mode##i(u32 val) { psxRcntWmode(i, val); } \ |
| 149 | static void io_rcnt_write_target##i(u32 val) { psxRcntWtarget(i, val & 0xffff); } |
| 150 | |
| 151 | make_rcnt_funcs(0) |
| 152 | make_rcnt_funcs(1) |
| 153 | make_rcnt_funcs(2) |
| 154 | |
| 155 | static void io_write_ireg16(u32 value) |
| 156 | { |
| 157 | if (Config.Sio) psxHu16ref(0x1070) |= 0x80; |
| 158 | if (Config.SpuIrq) psxHu16ref(0x1070) |= 0x200; |
| 159 | psxHu16ref(0x1070) &= psxHu16(0x1074) & value; |
| 160 | } |
| 161 | |
| 162 | static void io_write_imask16(u32 value) |
| 163 | { |
| 164 | psxHu16ref(0x1074) = value; |
| 165 | if (psxHu16ref(0x1070) & value) |
| 166 | new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1); |
| 167 | } |
| 168 | |
| 169 | static void io_write_ireg32(u32 value) |
| 170 | { |
| 171 | if (Config.Sio) psxHu32ref(0x1070) |= 0x80; |
| 172 | if (Config.SpuIrq) psxHu32ref(0x1070) |= 0x200; |
| 173 | psxHu32ref(0x1070) &= psxHu32(0x1074) & value; |
| 174 | } |
| 175 | |
| 176 | static void io_write_imask32(u32 value) |
| 177 | { |
| 178 | psxHu32ref(0x1074) = value; |
| 179 | if (psxHu32ref(0x1070) & value) |
| 180 | new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1); |
| 181 | } |
| 182 | |
| 183 | static void io_write_dma_icr32(u32 value) |
| 184 | { |
| 185 | u32 tmp = value & 0x00ff803f; |
| 186 | tmp |= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000; |
| 187 | if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000) |
| 188 | || tmp & HW_DMA_ICR_BUS_ERROR) { |
| 189 | if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT)) |
| 190 | psxHu32ref(0x1070) |= SWAP32(8); |
| 191 | tmp |= HW_DMA_ICR_IRQ_SENT; |
| 192 | } |
| 193 | HW_DMA_ICR = SWAPu32(tmp); |
| 194 | } |
| 195 | |
| 196 | #define make_dma_func(n) \ |
| 197 | static void io_write_chcr##n(u32 value) \ |
| 198 | { \ |
| 199 | HW_DMA##n##_CHCR = value; \ |
| 200 | if (value & 0x01000000 && HW_DMA_PCR & (8 << (n * 4))) { \ |
| 201 | psxDma##n(HW_DMA##n##_MADR, HW_DMA##n##_BCR, value); \ |
| 202 | } \ |
| 203 | } |
| 204 | |
| 205 | make_dma_func(0) |
| 206 | make_dma_func(1) |
| 207 | make_dma_func(2) |
| 208 | make_dma_func(3) |
| 209 | make_dma_func(4) |
| 210 | make_dma_func(6) |
| 211 | |
| 212 | static void io_spu_write16(u32 value) |
| 213 | { |
| 214 | // meh |
| 215 | SPU_writeRegister(address, value); |
| 216 | } |
| 217 | |
| 218 | static void io_spu_write32(u32 value) |
| 219 | { |
| 220 | SPUwriteRegister wfunc = SPU_writeRegister; |
| 221 | u32 a = address; |
| 222 | |
| 223 | wfunc(a, value & 0xffff); |
| 224 | wfunc(a + 2, value >> 16); |
| 225 | } |
| 226 | |
| 227 | /* IO tables for 1000-1880 */ |
| 228 | #define IOADR8(a) ((a) & 0xfff) |
| 229 | #define IOADR16(a) (((a) & 0xfff) >> 1) |
| 230 | #define IOADR32(a) (((a) & 0xfff) >> 2) |
| 231 | |
| 232 | static const void *io_read8 [0x880] = { |
| 233 | [IOADR8(0x1040)] = sioRead8, |
| 234 | [IOADR8(0x1800)] = cdrRead0, |
| 235 | [IOADR8(0x1801)] = cdrRead1, |
| 236 | [IOADR8(0x1802)] = cdrRead2, |
| 237 | [IOADR8(0x1803)] = cdrRead3, |
| 238 | }; |
| 239 | static const void *io_read16[0x880/2] = { |
| 240 | [IOADR16(0x1040)] = io_read_sio16, |
| 241 | [IOADR16(0x1044)] = sioReadStat16, |
| 242 | [IOADR16(0x1048)] = sioReadMode16, |
| 243 | [IOADR16(0x104a)] = sioReadCtrl16, |
| 244 | [IOADR16(0x104e)] = sioReadBaud16, |
| 245 | [IOADR16(0x1100)] = io_rcnt_read_count0, |
| 246 | [IOADR16(0x1104)] = io_rcnt_read_mode0, |
| 247 | [IOADR16(0x1108)] = io_rcnt_read_target0, |
| 248 | [IOADR16(0x1110)] = io_rcnt_read_count1, |
| 249 | [IOADR16(0x1114)] = io_rcnt_read_mode1, |
| 250 | [IOADR16(0x1118)] = io_rcnt_read_target1, |
| 251 | [IOADR16(0x1120)] = io_rcnt_read_count2, |
| 252 | [IOADR16(0x1124)] = io_rcnt_read_mode2, |
| 253 | [IOADR16(0x1128)] = io_rcnt_read_target2, |
| 254 | }; |
| 255 | static const void *io_read32[0x880/4] = { |
| 256 | [IOADR32(0x1040)] = io_read_sio32, |
| 257 | [IOADR32(0x1100)] = io_rcnt_read_count0, |
| 258 | [IOADR32(0x1104)] = io_rcnt_read_mode0, |
| 259 | [IOADR32(0x1108)] = io_rcnt_read_target0, |
| 260 | [IOADR32(0x1110)] = io_rcnt_read_count1, |
| 261 | [IOADR32(0x1114)] = io_rcnt_read_mode1, |
| 262 | [IOADR32(0x1118)] = io_rcnt_read_target1, |
| 263 | [IOADR32(0x1120)] = io_rcnt_read_count2, |
| 264 | [IOADR32(0x1124)] = io_rcnt_read_mode2, |
| 265 | [IOADR32(0x1128)] = io_rcnt_read_target2, |
| 266 | // [IOADR32(0x1810)] = GPU_readData, |
| 267 | // [IOADR32(0x1814)] = GPU_readStatus, |
| 268 | [IOADR32(0x1820)] = mdecRead0, |
| 269 | [IOADR32(0x1824)] = mdecRead1, |
| 270 | }; |
| 271 | // write(u32 val) |
| 272 | static const void *io_write8 [0x880] = { |
| 273 | [IOADR8(0x1040)] = sioWrite8, |
| 274 | [IOADR8(0x1800)] = cdrWrite0, |
| 275 | [IOADR8(0x1801)] = cdrWrite1, |
| 276 | [IOADR8(0x1802)] = cdrWrite2, |
| 277 | [IOADR8(0x1803)] = cdrWrite3, |
| 278 | }; |
| 279 | static const void *io_write16[0x880/2] = { |
| 280 | [IOADR16(0x1040)] = io_write_sio16, |
| 281 | [IOADR16(0x1044)] = sioWriteStat16, |
| 282 | [IOADR16(0x1048)] = sioWriteMode16, |
| 283 | [IOADR16(0x104a)] = sioWriteCtrl16, |
| 284 | [IOADR16(0x104e)] = sioWriteBaud16, |
| 285 | [IOADR16(0x1070)] = io_write_ireg16, |
| 286 | [IOADR16(0x1074)] = io_write_imask16, |
| 287 | [IOADR16(0x1100)] = io_rcnt_write_count0, |
| 288 | [IOADR16(0x1104)] = io_rcnt_write_mode0, |
| 289 | [IOADR16(0x1108)] = io_rcnt_write_target0, |
| 290 | [IOADR16(0x1110)] = io_rcnt_write_count1, |
| 291 | [IOADR16(0x1114)] = io_rcnt_write_mode1, |
| 292 | [IOADR16(0x1118)] = io_rcnt_write_target1, |
| 293 | [IOADR16(0x1120)] = io_rcnt_write_count2, |
| 294 | [IOADR16(0x1124)] = io_rcnt_write_mode2, |
| 295 | [IOADR16(0x1128)] = io_rcnt_write_target2, |
| 296 | }; |
| 297 | static const void *io_write32[0x880/4] = { |
| 298 | [IOADR32(0x1040)] = io_write_sio32, |
| 299 | [IOADR32(0x1070)] = io_write_ireg32, |
| 300 | [IOADR32(0x1074)] = io_write_imask32, |
| 301 | [IOADR32(0x1088)] = io_write_chcr0, |
| 302 | [IOADR32(0x1098)] = io_write_chcr1, |
| 303 | [IOADR32(0x10a8)] = io_write_chcr2, |
| 304 | [IOADR32(0x10b8)] = io_write_chcr3, |
| 305 | [IOADR32(0x10c8)] = io_write_chcr4, |
| 306 | [IOADR32(0x10e8)] = io_write_chcr6, |
| 307 | [IOADR32(0x10f4)] = io_write_dma_icr32, |
| 308 | [IOADR32(0x1100)] = io_rcnt_write_count0, |
| 309 | [IOADR32(0x1104)] = io_rcnt_write_mode0, |
| 310 | [IOADR32(0x1108)] = io_rcnt_write_target0, |
| 311 | [IOADR32(0x1110)] = io_rcnt_write_count1, |
| 312 | [IOADR32(0x1114)] = io_rcnt_write_mode1, |
| 313 | [IOADR32(0x1118)] = io_rcnt_write_target1, |
| 314 | [IOADR32(0x1120)] = io_rcnt_write_count2, |
| 315 | [IOADR32(0x1124)] = io_rcnt_write_mode2, |
| 316 | [IOADR32(0x1128)] = io_rcnt_write_target2, |
| 317 | // [IOADR32(0x1810)] = GPU_writeData, |
| 318 | // [IOADR32(0x1814)] = GPU_writeStatus, |
| 319 | [IOADR32(0x1820)] = mdecWrite0, |
| 320 | [IOADR32(0x1824)] = mdecWrite1, |
| 321 | }; |
| 322 | |
| 323 | // this has to be in .bss to link into dynarec_local |
| 324 | struct { |
| 325 | void *tab_read8; |
| 326 | void *tab_read16; |
| 327 | void *tab_read32; |
| 328 | void *tab_write8; |
| 329 | void *tab_write16; |
| 330 | void *tab_write32; |
| 331 | void *spu_readf; |
| 332 | void *spu_writef; |
| 333 | } nd_pcsx_io; |
| 334 | |
| 335 | static u32 *mem_readtab; |
| 336 | static u32 *mem_writetab; |
| 337 | static u32 mem_iortab[(1+2+4) * 0x1000 / 4]; |
| 338 | static u32 mem_iowtab[(1+2+4) * 0x1000 / 4]; |
| 339 | static u32 mem_ffwtab[(1+2+4) * 0x1000 / 4]; |
| 340 | //static u32 mem_unmrtab[(1+2+4) * 0x1000 / 4]; |
| 341 | static u32 mem_unmwtab[(1+2+4) * 0x1000 / 4]; |
| 342 | |
| 343 | static void map_item(u32 *out, const void *h, u32 flag) |
| 344 | { |
| 345 | u32 hv = (u32)h; |
| 346 | if (hv & 1) |
| 347 | fprintf(stderr, "%p has LSB set\n", h); |
| 348 | *out = (hv >> 1) | (flag << 31); |
| 349 | } |
| 350 | |
| 351 | // size must be power of 2, at least 4k |
| 352 | #define map_l1_mem(tab, i, addr, size, base) \ |
| 353 | map_item(&tab[((addr)>>12) + i], (u8 *)(base) - (u32)(addr) - ((i << 12) & ~(size - 1)), 0) |
| 354 | |
| 355 | #define IOMEM32(a) (((a) & 0xfff) / 4) |
| 356 | #define IOMEM16(a) (0x1000/4 + (((a) & 0xfff) / 2)) |
| 357 | #define IOMEM8(a) (0x1000/4 + 0x1000/2 + ((a) & 0xfff)) |
| 358 | |
| 359 | static void map_ram_write(void) |
| 360 | { |
| 361 | int i; |
| 362 | |
| 363 | for (i = 0; i < (0x800000 >> 12); i++) { |
| 364 | map_l1_mem(mem_writetab, i, 0x80000000, 0x200000, psxM); |
| 365 | map_l1_mem(mem_writetab, i, 0x00000000, 0x200000, psxM); |
| 366 | map_l1_mem(mem_writetab, i, 0xa0000000, 0x200000, psxM); |
| 367 | } |
| 368 | } |
| 369 | |
| 370 | static void unmap_ram_write(void) |
| 371 | { |
| 372 | int i; |
| 373 | |
| 374 | for (i = 0; i < (0x800000 >> 12); i++) { |
| 375 | map_item(&mem_writetab[0x80000|i], mem_unmwtab, 1); |
| 376 | map_item(&mem_writetab[0x00000|i], mem_unmwtab, 1); |
| 377 | map_item(&mem_writetab[0xa0000|i], mem_unmwtab, 1); |
| 378 | } |
| 379 | } |
| 380 | |
| 381 | static void write_biu(u32 value) |
| 382 | { |
| 383 | memprintf("write_biu %08x, %08x @%08x %u\n", address, value, psxRegs.pc, psxRegs.cycle); |
| 384 | |
| 385 | if (address != 0xfffe0130) |
| 386 | return; |
| 387 | |
| 388 | switch (value) { |
| 389 | case 0x800: case 0x804: |
| 390 | unmap_ram_write(); |
| 391 | break; |
| 392 | case 0: case 0x1e988: |
| 393 | map_ram_write(); |
| 394 | break; |
| 395 | default: |
| 396 | printf("write_biu: unexpected val: %08x\n", value); |
| 397 | break; |
| 398 | } |
| 399 | } |
| 400 | |
| 401 | void new_dyna_pcsx_mem_init(void) |
| 402 | { |
| 403 | int i; |
| 404 | #if 1 |
| 405 | // have to map these further to keep tcache close to .text |
| 406 | mem_readtab = mmap((void *)0x08000000, 0x200000 * 4, PROT_READ | PROT_WRITE, |
| 407 | MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); |
| 408 | if (mem_readtab == MAP_FAILED) { |
| 409 | fprintf(stderr, "failed to map mem tables\n"); |
| 410 | exit(1); |
| 411 | } |
| 412 | mem_writetab = mem_readtab + 0x100000; |
| 413 | |
| 414 | // 1st level lookup: |
| 415 | // 0: direct mem |
| 416 | // 1: use 2nd lookup |
| 417 | // 2nd level lookup: |
| 418 | // 0: direct mem variable |
| 419 | // 1: memhandler |
| 420 | |
| 421 | // default/unmapped memhandlers |
| 422 | for (i = 0; i < 0x100000; i++) { |
| 423 | //map_item(&mem_readtab[i], mem_unmrtab, 1); |
| 424 | map_l1_mem(mem_readtab, i, 0, 0x1000, unmapped_mem); |
| 425 | map_item(&mem_writetab[i], mem_unmwtab, 1); |
| 426 | } |
| 427 | |
| 428 | // RAM and it's mirrors |
| 429 | for (i = 0; i < (0x800000 >> 12); i++) { |
| 430 | map_l1_mem(mem_readtab, i, 0x80000000, 0x200000, psxM); |
| 431 | map_l1_mem(mem_readtab, i, 0x00000000, 0x200000, psxM); |
| 432 | map_l1_mem(mem_readtab, i, 0xa0000000, 0x200000, psxM); |
| 433 | } |
| 434 | map_ram_write(); |
| 435 | |
| 436 | // BIOS and it's mirrors |
| 437 | for (i = 0; i < (0x80000 >> 12); i++) { |
| 438 | map_l1_mem(mem_readtab, i, 0x1fc00000, 0x80000, psxR); |
| 439 | map_l1_mem(mem_readtab, i, 0xbfc00000, 0x80000, psxR); |
| 440 | } |
| 441 | |
| 442 | // scratchpad |
| 443 | map_l1_mem(mem_readtab, 0, 0x1f800000, 0x1000, psxH); |
| 444 | map_l1_mem(mem_writetab, 0, 0x1f800000, 0x1000, psxH); |
| 445 | |
| 446 | // I/O |
| 447 | map_item(&mem_readtab[0x1f801000 >> 12], mem_iortab, 1); |
| 448 | map_item(&mem_writetab[0x1f801000 >> 12], mem_iowtab, 1); |
| 449 | |
| 450 | // L2 |
| 451 | // unmapped tables |
| 452 | for (i = 0; i < (1+2+4) * 0x1000 / 4; i++) |
| 453 | map_item(&mem_unmwtab[i], write_mem_dummy, 1); |
| 454 | |
| 455 | // fill IO tables |
| 456 | for (i = 0; i < 0x1000/4; i++) { |
| 457 | map_item(&mem_iortab[i], &psxH[0x1000], 0); |
| 458 | map_item(&mem_iowtab[i], &psxH[0x1000], 0); |
| 459 | } |
| 460 | for (; i < 0x1000/4 + 0x1000/2; i++) { |
| 461 | map_item(&mem_iortab[i], &psxH[0x1000], 0); |
| 462 | map_item(&mem_iowtab[i], &psxH[0x1000], 0); |
| 463 | } |
| 464 | for (; i < 0x1000/4 + 0x1000/2 + 0x1000; i++) { |
| 465 | map_item(&mem_iortab[i], &psxH[0x1000], 0); |
| 466 | map_item(&mem_iowtab[i], &psxH[0x1000], 0); |
| 467 | } |
| 468 | |
| 469 | map_item(&mem_iortab[IOMEM32(0x1040)], io_read_sio32, 1); |
| 470 | map_item(&mem_iortab[IOMEM32(0x1100)], io_rcnt_read_count0, 1); |
| 471 | map_item(&mem_iortab[IOMEM32(0x1104)], io_rcnt_read_mode0, 1); |
| 472 | map_item(&mem_iortab[IOMEM32(0x1108)], io_rcnt_read_target0, 1); |
| 473 | map_item(&mem_iortab[IOMEM32(0x1110)], io_rcnt_read_count1, 1); |
| 474 | map_item(&mem_iortab[IOMEM32(0x1114)], io_rcnt_read_mode1, 1); |
| 475 | map_item(&mem_iortab[IOMEM32(0x1118)], io_rcnt_read_target1, 1); |
| 476 | map_item(&mem_iortab[IOMEM32(0x1120)], io_rcnt_read_count2, 1); |
| 477 | map_item(&mem_iortab[IOMEM32(0x1124)], io_rcnt_read_mode2, 1); |
| 478 | map_item(&mem_iortab[IOMEM32(0x1128)], io_rcnt_read_target2, 1); |
| 479 | // map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1); |
| 480 | // map_item(&mem_iortab[IOMEM32(0x1814)], GPU_readStatus, 1); |
| 481 | map_item(&mem_iortab[IOMEM32(0x1820)], mdecRead0, 1); |
| 482 | map_item(&mem_iortab[IOMEM32(0x1824)], mdecRead1, 1); |
| 483 | |
| 484 | map_item(&mem_iortab[IOMEM16(0x1040)], io_read_sio16, 1); |
| 485 | map_item(&mem_iortab[IOMEM16(0x1044)], sioReadStat16, 1); |
| 486 | map_item(&mem_iortab[IOMEM16(0x1048)], sioReadMode16, 1); |
| 487 | map_item(&mem_iortab[IOMEM16(0x104a)], sioReadCtrl16, 1); |
| 488 | map_item(&mem_iortab[IOMEM16(0x104e)], sioReadBaud16, 1); |
| 489 | map_item(&mem_iortab[IOMEM16(0x1100)], io_rcnt_read_count0, 1); |
| 490 | map_item(&mem_iortab[IOMEM16(0x1104)], io_rcnt_read_mode0, 1); |
| 491 | map_item(&mem_iortab[IOMEM16(0x1108)], io_rcnt_read_target0, 1); |
| 492 | map_item(&mem_iortab[IOMEM16(0x1110)], io_rcnt_read_count1, 1); |
| 493 | map_item(&mem_iortab[IOMEM16(0x1114)], io_rcnt_read_mode1, 1); |
| 494 | map_item(&mem_iortab[IOMEM16(0x1118)], io_rcnt_read_target1, 1); |
| 495 | map_item(&mem_iortab[IOMEM16(0x1120)], io_rcnt_read_count2, 1); |
| 496 | map_item(&mem_iortab[IOMEM16(0x1124)], io_rcnt_read_mode2, 1); |
| 497 | map_item(&mem_iortab[IOMEM16(0x1128)], io_rcnt_read_target2, 1); |
| 498 | |
| 499 | map_item(&mem_iortab[IOMEM8(0x1040)], sioRead8, 1); |
| 500 | map_item(&mem_iortab[IOMEM8(0x1800)], cdrRead0, 1); |
| 501 | map_item(&mem_iortab[IOMEM8(0x1801)], cdrRead1, 1); |
| 502 | map_item(&mem_iortab[IOMEM8(0x1802)], cdrRead2, 1); |
| 503 | map_item(&mem_iortab[IOMEM8(0x1803)], cdrRead3, 1); |
| 504 | |
| 505 | // write(u32 data) |
| 506 | map_item(&mem_iowtab[IOMEM32(0x1040)], io_write_sio32, 1); |
| 507 | map_item(&mem_iowtab[IOMEM32(0x1070)], io_write_ireg32, 1); |
| 508 | map_item(&mem_iowtab[IOMEM32(0x1074)], io_write_imask32, 1); |
| 509 | map_item(&mem_iowtab[IOMEM32(0x1088)], io_write_chcr0, 1); |
| 510 | map_item(&mem_iowtab[IOMEM32(0x1098)], io_write_chcr1, 1); |
| 511 | map_item(&mem_iowtab[IOMEM32(0x10a8)], io_write_chcr2, 1); |
| 512 | map_item(&mem_iowtab[IOMEM32(0x10b8)], io_write_chcr3, 1); |
| 513 | map_item(&mem_iowtab[IOMEM32(0x10c8)], io_write_chcr4, 1); |
| 514 | map_item(&mem_iowtab[IOMEM32(0x10e8)], io_write_chcr6, 1); |
| 515 | map_item(&mem_iowtab[IOMEM32(0x10f4)], io_write_dma_icr32, 1); |
| 516 | map_item(&mem_iowtab[IOMEM32(0x1100)], io_rcnt_write_count0, 1); |
| 517 | map_item(&mem_iowtab[IOMEM32(0x1104)], io_rcnt_write_mode0, 1); |
| 518 | map_item(&mem_iowtab[IOMEM32(0x1108)], io_rcnt_write_target0, 1); |
| 519 | map_item(&mem_iowtab[IOMEM32(0x1110)], io_rcnt_write_count1, 1); |
| 520 | map_item(&mem_iowtab[IOMEM32(0x1114)], io_rcnt_write_mode1, 1); |
| 521 | map_item(&mem_iowtab[IOMEM32(0x1118)], io_rcnt_write_target1, 1); |
| 522 | map_item(&mem_iowtab[IOMEM32(0x1120)], io_rcnt_write_count2, 1); |
| 523 | map_item(&mem_iowtab[IOMEM32(0x1124)], io_rcnt_write_mode2, 1); |
| 524 | map_item(&mem_iowtab[IOMEM32(0x1128)], io_rcnt_write_target2, 1); |
| 525 | // map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1); |
| 526 | // map_item(&mem_iowtab[IOMEM32(0x1814)], GPU_writeStatus, 1); |
| 527 | map_item(&mem_iowtab[IOMEM32(0x1820)], mdecWrite0, 1); |
| 528 | map_item(&mem_iowtab[IOMEM32(0x1824)], mdecWrite1, 1); |
| 529 | |
| 530 | map_item(&mem_iowtab[IOMEM16(0x1040)], io_write_sio16, 1); |
| 531 | map_item(&mem_iowtab[IOMEM16(0x1044)], sioWriteStat16, 1); |
| 532 | map_item(&mem_iowtab[IOMEM16(0x1048)], sioWriteMode16, 1); |
| 533 | map_item(&mem_iowtab[IOMEM16(0x104a)], sioWriteCtrl16, 1); |
| 534 | map_item(&mem_iowtab[IOMEM16(0x104e)], sioWriteBaud16, 1); |
| 535 | map_item(&mem_iowtab[IOMEM16(0x1070)], io_write_ireg16, 1); |
| 536 | map_item(&mem_iowtab[IOMEM16(0x1074)], io_write_imask16, 1); |
| 537 | map_item(&mem_iowtab[IOMEM16(0x1100)], io_rcnt_write_count0, 1); |
| 538 | map_item(&mem_iowtab[IOMEM16(0x1104)], io_rcnt_write_mode0, 1); |
| 539 | map_item(&mem_iowtab[IOMEM16(0x1108)], io_rcnt_write_target0, 1); |
| 540 | map_item(&mem_iowtab[IOMEM16(0x1110)], io_rcnt_write_count1, 1); |
| 541 | map_item(&mem_iowtab[IOMEM16(0x1114)], io_rcnt_write_mode1, 1); |
| 542 | map_item(&mem_iowtab[IOMEM16(0x1118)], io_rcnt_write_target1, 1); |
| 543 | map_item(&mem_iowtab[IOMEM16(0x1120)], io_rcnt_write_count2, 1); |
| 544 | map_item(&mem_iowtab[IOMEM16(0x1124)], io_rcnt_write_mode2, 1); |
| 545 | map_item(&mem_iowtab[IOMEM16(0x1128)], io_rcnt_write_target2, 1); |
| 546 | |
| 547 | map_item(&mem_iowtab[IOMEM8(0x1040)], sioWrite8, 1); |
| 548 | map_item(&mem_iowtab[IOMEM8(0x1800)], cdrWrite0, 1); |
| 549 | map_item(&mem_iowtab[IOMEM8(0x1801)], cdrWrite1, 1); |
| 550 | map_item(&mem_iowtab[IOMEM8(0x1802)], cdrWrite2, 1); |
| 551 | map_item(&mem_iowtab[IOMEM8(0x1803)], cdrWrite3, 1); |
| 552 | |
| 553 | for (i = 0x1c00; i < 0x1e00; i += 2) { |
| 554 | map_item(&mem_iowtab[IOMEM16(i)], io_spu_write16, 1); |
| 555 | map_item(&mem_iowtab[IOMEM32(i)], io_spu_write32, 1); |
| 556 | } |
| 557 | |
| 558 | // misc |
| 559 | map_item(&mem_writetab[0xfffe0130 >> 12], mem_ffwtab, 1); |
| 560 | for (i = 0; i < 0x1000/4 + 0x1000/2 + 0x1000; i++) |
| 561 | map_item(&mem_ffwtab[i], write_biu, 1); |
| 562 | |
| 563 | mem_rtab = mem_readtab; |
| 564 | mem_wtab = mem_writetab; |
| 565 | #endif |
| 566 | /// |
| 567 | // default/unmapped handlers |
| 568 | for (i = 0; i < 0x10000; i++) { |
| 569 | readmemb[i] = read_mem8; |
| 570 | readmemh[i] = read_mem16; |
| 571 | readmem[i] = read_mem32; |
| 572 | writememb[i] = write_mem8; |
| 573 | writememh[i] = write_mem16; |
| 574 | writemem[i] = write_mem32; |
| 575 | #if 1 |
| 576 | readmemb[i] = readmemh[i] = readmem[i] = read_mem_dummy; |
| 577 | writememb[i] = writememh[i] = writemem[i] = write_mem_dummy; |
| 578 | #endif |
| 579 | } |
| 580 | |
| 581 | #if 1 |
| 582 | // RAM mirrors |
| 583 | for (i = 0; i < 0x80; i++) { |
| 584 | readmemb[i] = readmemb[0x8000|i] = readmemb[0xa000|i] = ari_read_ram_mirror8; |
| 585 | readmemh[i] = readmemh[0x8000|i] = readmemh[0xa000|i] = ari_read_ram_mirror16; |
| 586 | readmem[i] = readmem [0x8000|i] = readmem [0xa000|i] = ari_read_ram_mirror32; |
| 587 | writememb[i] = writememb[0x8000|i] = writememb[0xa000|i] = ari_write_ram_mirror8; |
| 588 | writememh[i] = writememh[0x8000|i] = writememh[0xa000|i] = ari_write_ram_mirror16; |
| 589 | writemem[i] = writemem [0x8000|i] = writemem [0xa000|i] = ari_write_ram_mirror32; |
| 590 | } |
| 591 | |
| 592 | // stupid BIOS RAM check |
| 593 | writemem[0] = ari_write_ram_mirror_ro32; |
| 594 | pcsx_ram_is_ro = 0; |
| 595 | |
| 596 | // RAM direct |
| 597 | for (i = 0x8000; i < 0x8020; i++) { |
| 598 | readmemb[i] = ari_read_ram8; |
| 599 | readmemh[i] = ari_read_ram16; |
| 600 | readmem[i] = ari_read_ram32; |
| 601 | } |
| 602 | |
| 603 | // BIOS and it's mirrors |
| 604 | for (i = 0x1fc0; i < 0x1fc8; i++) { |
| 605 | readmemb[i] = readmemb[0x8000|i] = readmemb[0xa000|i] = ari_read_bios8; |
| 606 | readmemh[i] = readmemh[0x8000|i] = readmemh[0xa000|i] = ari_read_bios16; |
| 607 | readmem[i] = readmem[0x8000|i] = readmem[0xa000|i] = ari_read_bios32; |
| 608 | } |
| 609 | |
| 610 | // I/O |
| 611 | readmemb[0x1f80] = ari_read_io8; |
| 612 | readmemh[0x1f80] = ari_read_io16; |
| 613 | readmem[0x1f80] = ari_read_io32; |
| 614 | writememb[0x1f80] = ari_write_io8; |
| 615 | writememh[0x1f80] = ari_write_io16; |
| 616 | writemem[0x1f80] = ari_write_io32; |
| 617 | |
| 618 | writemem[0xfffe] = write_biu_; |
| 619 | #endif |
| 620 | |
| 621 | // fill IO tables |
| 622 | nd_pcsx_io.tab_read8 = io_read8; |
| 623 | nd_pcsx_io.tab_read16 = io_read16; |
| 624 | nd_pcsx_io.tab_read32 = io_read32; |
| 625 | nd_pcsx_io.tab_write8 = io_write8; |
| 626 | nd_pcsx_io.tab_write16 = io_write16; |
| 627 | nd_pcsx_io.tab_write32 = io_write32; |
| 628 | } |
| 629 | |
| 630 | void new_dyna_pcsx_mem_reset(void) |
| 631 | { |
| 632 | int i; |
| 633 | |
| 634 | // plugins might change so update the pointers |
| 635 | map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1); |
| 636 | map_item(&mem_iortab[IOMEM32(0x1814)], GPU_readStatus, 1); |
| 637 | |
| 638 | for (i = 0x1c00; i < 0x1e00; i += 2) |
| 639 | map_item(&mem_iortab[IOMEM16(i)], SPU_readRegister, 1); |
| 640 | |
| 641 | map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1); |
| 642 | map_item(&mem_iowtab[IOMEM32(0x1814)], GPU_writeStatus, 1); |
| 643 | |
| 644 | nd_pcsx_io.spu_readf = SPU_readRegister; |
| 645 | nd_pcsx_io.spu_writef = SPU_writeRegister; |
| 646 | |
| 647 | io_read32[IOADR32(0x1810)] = GPU_readData; |
| 648 | io_read32[IOADR32(0x1814)] = GPU_readStatus; |
| 649 | io_write32[IOADR32(0x1810)] = GPU_writeData; |
| 650 | io_write32[IOADR32(0x1814)] = GPU_writeStatus; |
| 651 | } |
| 652 | |