| 1 | /* FCE Ultra - NES/Famicom Emulator |
| 2 | * |
| 3 | * Copyright notice for this file: |
| 4 | * Copyright (C) 2002 Ben Parnell |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 19 | */ |
| 20 | |
| 21 | typedef struct { |
| 22 | int32 count; /* Cycle counter */ |
| 23 | int32 tcount; /* Temporary cycle counter */ |
| 24 | uint16 PC; /* I'll change this to uint32 later... */ |
| 25 | /* I'll need to AND PC after increments to 0xFFFF */ |
| 26 | /* when I do, though. Perhaps an IPC() macro? */ |
| 27 | uint8 A,X,Y,S,P,mooPI; |
| 28 | uint8 DB; /* Data bus "cache" for reads from certain areas */ |
| 29 | uint8 IRQlow; /* Simulated IRQ pin held low(or is it high?). */ |
| 30 | uint8 jammed; |
| 31 | } X6502; |
| 32 | |
| 33 | extern X6502 X; |
| 34 | |
| 35 | #define N_FLAG 0x80 |
| 36 | #define V_FLAG 0x40 |
| 37 | #define U_FLAG 0x20 |
| 38 | #define B_FLAG 0x10 |
| 39 | #define D_FLAG 0x08 |
| 40 | #define I_FLAG 0x04 |
| 41 | #define Z_FLAG 0x02 |
| 42 | #define C_FLAG 0x01 |
| 43 | |
| 44 | extern uint32 timestamp; |
| 45 | extern void FP_FASTAPASS(1) (*MapIRQHook)(int a); |
| 46 | |
| 47 | #define NTSC_CPU 1789772.7272727272727272 |
| 48 | #define PAL_CPU 1662607.125 |
| 49 | |
| 50 | #define FCEU_IQEXT 0x01 |
| 51 | #define FCEU_IQNMI 0x08 |
| 52 | #define FCEU_IQDPCM 0x10 |
| 53 | #define FCEU_IQFCOUNT 0x20 |
| 54 | #define FCEU_IQTEMP 0x80 |
| 55 | // from 0.98.15 |
| 56 | #define FCEU_IQEXT2 0x02 |
| 57 | |
| 58 | #if defined(DEBUG_ASM_6502) |
| 59 | #define TriggerIRQ TriggerIRQ_d |
| 60 | #define TriggerNMI TriggerNMI_d |
| 61 | #define X6502_Init X6502_Init_c |
| 62 | #define X6502_Run X6502_Run_d |
| 63 | #define X6502_Reset X6502_Reset_d |
| 64 | #define X6502_Power X6502_Power_d |
| 65 | #define X6502_AddCycles X6502_AddCycles_d |
| 66 | #define X6502_IRQBegin X6502_IRQBegin_d |
| 67 | #define X6502_IRQEnd X6502_IRQEnd_d |
| 68 | #define X6502_Rebase X6502_Rebase_d |
| 69 | #define X6502_GetCycleCount() g_cnt |
| 70 | #define X6502_C |
| 71 | #define X6502_A |
| 72 | #define X6502_D |
| 73 | |
| 74 | #elif defined(ASM_6502) |
| 75 | #define TriggerIRQ TriggerIRQ_a |
| 76 | #define TriggerNMI TriggerNMI_a |
| 77 | #define X6502_Init() |
| 78 | #define X6502_Reset X6502_Reset_a |
| 79 | #define X6502_Power X6502_Power_a |
| 80 | #define X6502_AddCycles X6502_AddCycles_a |
| 81 | //#define X6502_IRQBegin X6502_IRQBegin_a |
| 82 | //#define X6502_IRQEnd X6502_IRQEnd_a |
| 83 | #define X6502_IRQBegin(w) nes_registers[4]|=w<<8 |
| 84 | #define X6502_IRQEnd(w) nes_registers[4]&=~(w<<8) |
| 85 | #define X6502_Rebase X6502_Rebase_a |
| 86 | #define X6502_GetCycleCount() ((int32)nes_registers[7]>>16) |
| 87 | #define X6502_A |
| 88 | |
| 89 | #define X6502_Run(c) \ |
| 90 | { \ |
| 91 | int32 cycles = (c) << 4; /* *16 */ \ |
| 92 | if (PAL) cycles -= (c); /* *15 */ \ |
| 93 | nes_registers[7]+=cycles<<16; \ |
| 94 | cycles=(int32)nes_registers[7]>>16; \ |
| 95 | if (cycles > 0) { \ |
| 96 | X6502_Run_a(); \ |
| 97 | cycles -= (int32)nes_registers[7]>>16; \ |
| 98 | FCEU_SoundCPUHook(cycles); \ |
| 99 | } \ |
| 100 | } |
| 101 | |
| 102 | #else |
| 103 | #define TriggerIRQ TriggerIRQ_c |
| 104 | #define TriggerNMI TriggerNMI_c |
| 105 | #define X6502_Init X6502_Init_c |
| 106 | #define X6502_Reset X6502_Reset_c |
| 107 | #define X6502_Power X6502_Power_c |
| 108 | #define X6502_AddCycles X6502_AddCycles_c |
| 109 | #define X6502_IRQBegin X6502_IRQBegin_c |
| 110 | #define X6502_IRQEnd X6502_IRQEnd_c |
| 111 | #define X6502_Rebase(...) |
| 112 | #define X6502_GetCycleCount() X.count |
| 113 | #define X6502_C |
| 114 | |
| 115 | #define X6502_Run(c) \ |
| 116 | { \ |
| 117 | int32 cycles = (c) << 4; /* *16 */ \ |
| 118 | if (PAL) cycles -= (c); /* *15 */ \ |
| 119 | X.count+=cycles; \ |
| 120 | if (X.count > 0) X6502_Run_c(); \ |
| 121 | } |
| 122 | #define X6502_C |
| 123 | #endif |
| 124 | |
| 125 | // c |
| 126 | #ifdef X6502_C |
| 127 | void TriggerIRQ_c(void); |
| 128 | void TriggerNMI_c(void); |
| 129 | void X6502_Init_c(void); |
| 130 | void X6502_Run_c(void); |
| 131 | void X6502_Reset_c(void); |
| 132 | void X6502_Power_c(void); |
| 133 | void FASTAPASS(1) X6502_AddCycles_c(int x); |
| 134 | void FASTAPASS(1) X6502_IRQBegin_c(int w); |
| 135 | void FASTAPASS(1) X6502_IRQEnd_c(int w); |
| 136 | #endif |
| 137 | |
| 138 | // asm |
| 139 | #ifdef X6502_A |
| 140 | extern uint32 nes_registers[0x10]; |
| 141 | extern uint32 pc_base; |
| 142 | void TriggerIRQ_a(void); |
| 143 | void TriggerNMI_a(void); |
| 144 | void X6502_Run_a(void); |
| 145 | void X6502_Reset_a(void); |
| 146 | void X6502_Power_a(void); |
| 147 | void X6502_AddCycles_a(int x); |
| 148 | void X6502_IRQBegin_a(int w); |
| 149 | void X6502_IRQEnd_a(int w); |
| 150 | void X6502_Rebase_a(void); |
| 151 | #endif |
| 152 | |
| 153 | // debug |
| 154 | #ifdef X6502_D |
| 155 | extern int32 g_cnt; |
| 156 | void TriggerIRQ_d(void); |
| 157 | void TriggerNMI_d(void); |
| 158 | void X6502_Run_d(int32 c); |
| 159 | void X6502_Reset_d(void); |
| 160 | void X6502_Power_d(void); |
| 161 | void X6502_AddCycles_d(int x); |
| 162 | void X6502_IRQBegin_d(int w); |
| 163 | void X6502_IRQEnd_d(int w); |
| 164 | void X6502_Rebase_d(void); |
| 165 | #endif |
| 166 | |