4 // --------------------- Opcodes 0x1000+ ---------------------
\r
5 // Emit a Move opcode, 00xxdddd ddssssss
\r
12 // Get source and target EA
\r
14 tea =(op&0x01c0)>>3;
\r
15 tea|=(op&0x0e00)>>9;
\r
17 if (tea>=8 && tea<0x10) movea=1;
\r
19 // Find size extension
\r
23 case 0x1000: size=0; break;
\r
24 case 0x3000: size=1; break;
\r
25 case 0x2000: size=2; break;
\r
28 if (movea && size<1) return 1; // movea.b is invalid
\r
30 // See if we can do this opcode:
\r
31 if (EaCanRead (sea,size)==0) return 1;
\r
32 if (EaCanWrite(tea )==0) return 1;
\r
35 if (tea<0x38) use&=~0x0e00; // Use same handler for register ?0-7
\r
37 if (tea>=0x18 && tea<0x28 && (tea&7)==7) use|=0x0e00; // Specific handler for (a7)+ and -(a7)
\r
39 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
41 OpStart(op); Cycles=4;
\r
43 EaCalc(0,0x003f,sea,size);
\r
44 EaRead(0, 0,sea,size);
\r
46 ot(" adds r1,r0,#0 ;@ Defines NZ, clears CV\n");
\r
48 if (movea==0) ot(" mrs r9,cpsr ;@ r9=NZCV flags\n");
\r
51 if (movea) size=2; // movea always expands to 32-bits
\r
53 EaCalc (0,0x0e00,tea,size);
\r
54 EaWrite(0, 1,tea,size);
\r
60 // --------------------- Opcodes 0x41c0+ ---------------------
\r
61 // Emit an Lea opcode, 0100nnn1 11aaaaaa
\r
68 tea=(op&0x0e00)>>9; tea|=8;
\r
70 if (EaCanRead(sea,-1)==0) return 1; // See if we can do this opcode:
\r
73 use&=~0x0e00; // Also use 1 handler for target ?0-7
\r
74 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
76 OpStart(op); Cycles=4;
\r
78 EaCalc (1,0x003f,sea,0); // Lea
\r
79 EaCalc (0,0x0e00,tea,2);
\r
80 EaWrite(0, 1,tea,2);
\r
85 if (sea< 0x18) Cycles+=4;
\r
86 else if (sea==0x30) Cycles+=12;
\r
95 // --------------------- Opcodes 0x40c0+ ---------------------
\r
97 // Pack our flags into r1, in SR/CCR register format
\r
99 void OpFlagsToReg(int high)
\r
101 ot(" mov r1,r9,lsr #28 ;@ ____NZCV\n");
\r
102 ot(" eor r0,r1,r1,ror #1 ;@ Bit 0=C^V\n");
\r
103 ot(" tst r0,#1 ;@ 1 if C!=V\n");
\r
104 ot(" eorne r1,r1,#3 ;@ ____NZVC\n");
\r
106 ot(" ldrb r0,[r7,#0x45] ;@ X bit\n");
\r
107 if (high) ot(" ldrb r2,[r7,#0x44] ;@ Include SR high\n");
\r
108 ot(" and r0,r0,#0x02\n");
\r
109 if (high) ot(" orr r1,r1,r2,lsl #8\n");
\r
110 ot(" orr r1,r1,r0,lsl #3 ;@ ___XNZVC\n");
\r
114 // Convert SR/CRR register in r0 to our flags
\r
116 void OpRegToFlags(int high)
\r
118 ot(" eor r1,r0,r0,ror #1 ;@ Bit 0=C^V\n");
\r
119 ot(" mov r2,r0,lsr #3 ;@ r2=___XN\n");
\r
120 ot(" tst r1,#1 ;@ 1 if C!=V\n");
\r
121 ot(" eorne r0,r0,#3 ;@ ___XNZCV\n");
\r
122 ot(" strb r2,[r7,#0x45] ;@ Store X bit\n");
\r
123 ot(" mov r9,r0,lsl #28 ;@ r9=NZCV...\n");
\r
127 ot(" mov r0,r0,ror #8\n");
\r
128 ot(" strb r0,[r7,#0x44] ;@ Store SR high\n");
\r
133 static void SuperCheck(int op)
\r
135 ot(" ldrb r0,[r7,#0x44] ;@ Get SR high\n");
\r
136 ot(" tst r0,#0x20 ;@ Check we are in supervisor mode\n");
\r
137 ot(" beq WrongMode%.4x ;@ No\n",op);
\r
141 static void SuperEnd(int op)
\r
143 ot("WrongMode%.4x%s\n",op,ms?"":":");
\r
144 ot(";@ todo - cause an exception\n");
\r
148 // Move SR opcode, 01000tt0 11aaaaaa move to SR
\r
149 int OpMoveSr(int op)
\r
160 if (EaCanWrite(ea)==0) return 1; // See if we can do this opcode:
\r
163 default: return 1; // todo
\r
166 if (EaCanRead(ea,size)==0) return 1; // See if we can do this opcode:
\r
171 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
174 if (type==0) Cycles=8;
\r
175 else if (type==1) Cycles=6;
\r
178 if (Amatch && ea==0x3c) Cycles-=4; // Correct?
\r
180 if (type==0 || type==3) SuperCheck(op);
\r
182 if (type==0 || type==1)
\r
184 OpFlagsToReg(type==0);
\r
185 EaCalc (0,0x003f,ea,size);
\r
186 EaWrite(0, 1,ea,size);
\r
189 if (type==2 || type==3)
\r
191 EaCalc(0,0x003f,ea,size);
\r
192 EaRead(0, 0,ea,size);
\r
193 OpRegToFlags(type==3);
\r
194 if (type==3) CheckInterrupt();
\r
199 if (type==0 || type==3) SuperEnd(op);
\r
205 // Ori/Andi/Eori $nnnn,sr 0000t0t0 01111100
\r
206 int OpArithSr(int op)
\r
211 type=(op>>9)&5; if (type==4) return 1;
\r
216 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
218 OpStart(op); Cycles=16;
\r
222 EaCalc(0,0x003f,ea,size);
\r
223 EaRead(0, 10,ea,size);
\r
225 OpFlagsToReg(size);
\r
226 if (type==0) ot(" orr r0,r1,r10\n");
\r
227 if (type==1) ot(" and r0,r1,r10\n");
\r
228 if (type==5) ot(" eor r0,r1,r10\n");
\r
229 OpRegToFlags(size);
\r
230 if (size) CheckInterrupt();
\r
238 // --------------------- Opcodes 0x4850+ ---------------------
\r
239 // Emit an Pea opcode, 01001000 01aaaaaa
\r
245 ea=op&0x003f; if (ea<0x10) return 1; // Swap opcode
\r
246 if (EaCanRead(ea,-1)==0) return 1; // See if we can do this opcode:
\r
249 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
251 OpStart(op); Cycles=20;
\r
253 EaCalc (1,0x003f, ea,0);
\r
255 ot(" ldr r0,[r7,#0x3c]\n");
\r
256 ot(" sub r0,r0,#4 ;@ Predecrement A7\n");
\r
257 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
\r
259 MemHandler(1,2); // Write 32-bit
\r
267 // --------------------- Opcodes 0x4880+ ---------------------
\r
268 // Emit a Movem opcode, 01001d00 1xeeeeee regmask
\r
269 int OpMovem(int op)
\r
271 int size=0,ea=0,cea=0,dir=0;
\r
272 int use=0,decr=0,change=0;
\r
274 size=((op>>6)&1)+1;
\r
276 dir=(op>>10)&1; // Direction
\r
278 if (ea<0x10 || ea>0x39) return 1; // Invalid EA
\r
279 if ((ea&0x38)==0x18 || (ea&0x38)==0x20) change=1;
\r
280 if ((ea&0x38)==0x20) decr=1; // -(An), bitfield is decr
\r
282 // See if we can do this opcode:
\r
283 if (EaCanWrite(ea)==0) return 1;
\r
285 cea=ea; if (change) cea=0x10;
\r
288 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
292 ot(" stmdb sp!,{r9} ;@ Push r9\n");
\r
293 ot(" ldrh r11,[r4],#2 ;@ r11=register mask\n");
\r
296 ot(";@ Get the address into r9:\n");
\r
297 EaCalc(9,0x003f,cea,size);
\r
299 ot(";@ r10=Register Index*4:\n");
\r
300 if (decr) ot(" mov r10,#0x3c ;@ order reversed for -(An)\n");
\r
301 else ot(" mov r10,#0\n");
\r
304 ot("MoreReg%.4x%s\n",op, ms?"":":");
\r
306 ot(" tst r11,#1\n");
\r
307 ot(" beq SkipReg%.4x\n",op);
\r
310 if (decr) ot(" sub r9,r9,#%d ;@ Pre-decrement address\n",1<<size);
\r
314 ot(" ;@ Copy memory to register:\n",1<<size);
\r
315 EaRead (9,0,ea,size);
\r
316 ot(" str r0,[r7,r10] ;@ Save value into Dn/An\n");
\r
320 ot(" ;@ Copy register to memory:\n",1<<size);
\r
321 ot(" ldr r1,[r7,r10] ;@ Load value from Dn/An\n");
\r
322 EaWrite(9,1,ea,size);
\r
325 if (decr==0) ot(" add r9,r9,#%d ;@ Post-increment address\n",1<<size);
\r
327 ot(" sub r5,r5,#%d ;@ Take some cycles\n",2<<size);
\r
329 ot("SkipReg%.4x%s\n",op, ms?"":":");
\r
330 ot(" movs r11,r11,lsr #1;@ Shift mask:\n");
\r
331 ot(" add r10,r10,#%d ;@ r10=Next Register\n",decr?-4:4);
\r
332 ot(" bne MoreReg%.4x\n",op);
\r
337 ot(";@ Write back address:\n");
\r
338 EaCalc (0,0x0007,8|(ea&7),2);
\r
339 EaWrite(0, 9,8|(ea&7),2);
\r
342 ot(" ldmia sp!,{r9} ;@ Pop r9\n");
\r
346 else if (ea<0x18) Cycles=16; // (a0)
\r
347 else if (ea<0x20) Cycles= 0; // (a0)+ ?
\r
348 else if (ea<0x28) Cycles= 8; //-(a0)
\r
349 else if (ea<0x30) Cycles=24; // ($3333,a0)
\r
350 else if (ea<0x38) Cycles=28; // ($33,a0,d3.w*2)
\r
351 else if (ea<0x39) Cycles=24; // $3333.w
\r
352 else if (ea<0x3a) Cycles=28; // $33333333.l
\r
359 // --------------------- Opcodes 0x4e60+ ---------------------
\r
360 // Emit a Move USP opcode, 01001110 0110dnnn move An to/from USP
\r
361 int OpMoveUsp(int op)
\r
365 dir=(op>>3)&1; // Direction
\r
366 use=op&~0x0007; // Use same opcode for all An
\r
368 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
370 OpStart(op); Cycles=4;
\r
372 ot(" ldrb r0,[r7,#0x44] ;@ Get SR\n");
\r
373 ot(" tst r0,#0x20 ;@ Check we are in supervisor mode\n");
\r
374 ot(" beq WrongMode%.4x ;@ No\n",op);
\r
379 EaCalc (0,0x0007,8,2);
\r
380 ot(" ldr r1,[r7,#0x48] ;@ Get from USP\n\n");
\r
385 EaCalc (0,0x0007,8,2);
\r
387 ot(" str r0,[r7,#0x48] ;@ Put in USP\n\n");
\r
392 ot("WrongMode%.4x%s\n",op,ms?"":":");
\r
393 ot(";@ todo - cause an exception\n");
\r
399 // --------------------- Opcodes 0x7000+ ---------------------
\r
400 // Emit a Move Quick opcode, 0111nnn0 dddddddd moveq #dd,Dn
\r
401 int OpMoveq(int op)
\r
405 use=op&0xf100; // Use same opcode for all values
\r
406 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
408 OpStart(op); Cycles=4;
\r
410 ot(" movs r0,r8,asl #24\n");
\r
411 ot(" and r1,r8,#0x0e00\n");
\r
412 ot(" mov r0,r0,asr #24 ;@ Sign extended Quick value\n");
\r
413 ot(" mrs r9,cpsr ;@ r9=NZ flags\n");
\r
414 ot(" str r0,[r7,r1,lsr #7] ;@ Store into Dn\n");
\r
422 // --------------------- Opcodes 0xc140+ ---------------------
\r
423 // Emit a Exchange opcode:
\r
424 // 1100ttt1 01000sss exg ds,dt
\r
425 // 1100ttt1 01001sss exg as,at
\r
426 // 1100ttt1 10001sss exg as,dt
\r
433 if (type!=0x40 && type!=0x48 && type!=0x88) return 1; // Not an exg opcode
\r
435 use=op&0xf1f8; // Use same opcode for all values
\r
436 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
438 OpStart(op); Cycles=6;
\r
440 ot(" and r10,r8,#0x0e00 ;@ Find T register\n");
\r
441 ot(" and r11,r8,#0x000f ;@ Find S register\n");
\r
442 if (type==0x48) ot(" orr r10,r10,#0x1000 ;@ T is an address register\n");
\r
444 ot(" ldr r0,[r7,r10,lsr #7] ;@ Get T\n");
\r
445 ot(" ldr r1,[r7,r11,lsl #2] ;@ Get S\n");
\r
447 ot(" str r0,[r7,r11,lsl #2] ;@ T->S\n");
\r
448 ot(" str r1,[r7,r10,lsr #7] ;@ S->T\n");
\r