2 // This file is part of the Cyclone 68000 Emulator
\r
4 // Copyright (c) 2004,2011 FinalDave (emudave (at) gmail.com)
\r
5 // Copyright (c) 2005-2011 Gražvydas "notaz" Ignotas (notasas (at) gmail.com)
\r
7 // This code is licensed under the GNU General Public License version 2.0 and the MAME License.
\r
8 // You can choose the license that has the most advantages for you.
\r
10 // SVN repository can be found at http://code.google.com/p/cyclone68000/
\r
15 static FILE *AsmFile=NULL;
\r
17 static int CycloneVer=0x0099; // Version number of library
\r
18 int *CyJump=NULL; // Jump table
\r
19 int ms=USE_MS_SYNTAX; // If non-zero, output in Microsoft ARMASM format
\r
20 const char * const Narm[4]={ "b", "h","",""}; // Normal ARM Extensions for operand sizes 0,1,2
\r
21 const char * const Sarm[4]={"sb","sh","",""}; // Sign-extend ARM Extensions for operand sizes 0,1,2
\r
22 int Cycles; // Current cycles for opcode
\r
23 int pc_dirty; // something changed PC during processing
\r
26 // opcodes often used by games
\r
27 static const unsigned short hot_opcodes[] = {
\r
30 0x51c8, // dbra Dn, $2
\r
31 0x4a38, // tst.b $0.w
\r
32 0xd040, // add.w Dn, Dn
\r
33 0x4a79, // tst.w $0.l
\r
34 0x0240, // andi.w #$0, D0
\r
35 0x2038, // move.l $0.w, D0
\r
36 0xb0b8, // cmp.l $0.w, D0
\r
38 0x30c0, // move.w D0, (A0)+
\r
39 0x3028, // move.w ($0,A0), D0
\r
40 0x0c40, // cmpi.w #$0, D0
\r
41 0x0c79, // cmpi.w #$0, $0.l
\r
44 0x3000, // move.w D0, D0
\r
45 0x0839, // btst #$0, $0.l
\r
46 0x7000, // moveq #$0, D0
\r
47 0x3040, // movea.w D0, A0
\r
48 0x0838, // btst #$0, $0.w
\r
49 0x4a39, // tst.b $0.l
\r
50 0x33d8, // move.w (A0)+, $0.l
\r
52 0xb038, // cmp.b $0.w, D0
\r
53 0x3039, // move.w $0.l, D0
\r
57 0x5e40, // addq.w #7, D0
\r
58 0x1039, // move.b $0.l, D0
\r
59 0x20c0, // move.l D0, (A0)+
\r
60 0x1018, // move.b (A0)+, D0
\r
61 0x30d0, // move.w (A0), (A0)+
\r
62 0x3080, // move.w D0, (A0)
\r
63 0x3018, // move.w (A0)+, D0
\r
64 0xc040, // and.w D0, D0
\r
65 0x3180, // move.w D0, (A0,D0.w)
\r
66 0x1198, // move.b (A0)+, (A0,D0.w)
\r
71 0x41f0, // lea (A0,D0.w), A0
\r
72 0x4a28, // tst.b ($0,A0)
\r
73 0x0828, // btst #$0, ($0,A0)
\r
74 0x0640, // addi.w #$0, D0
\r
75 0x10c0, // move.b D0, (A0)+
\r
76 0x10d8, // move.b (A0)+, (A0)+
\r
78 #define hot_opcode_count (int)(sizeof(hot_opcodes) / sizeof(hot_opcodes[0]))
\r
80 static int is_op_hot(int op)
\r
83 for (i = 0; i < hot_opcode_count; i++)
\r
84 if (op == hot_opcodes[i])
\r
89 void ot(const char *format, ...)
\r
94 // notaz: stop me from leaving newlines in the middle of format string
\r
95 // and generating bad code
\r
96 for(i=0, len=strlen(format); i < len && format[i] != '\n'; i++);
\r
97 if(i < len-1 && format[len-1] != '\n') printf("\nWARNING: possible improper newline placement:\n%s\n", format);
\r
99 if (format[0] == ' ' && format[1] == ' ' && format[2] != ' ' && format[2] != '.')
\r
102 va_start(valist,format);
\r
103 if (AsmFile) vfprintf(AsmFile,format,valist);
\r
109 if (ms) ot(" LTORG\n");
\r
110 else ot(" .ltorg\n");
\r
113 #if (CYCLONE_FOR_GENESIS == 2)
\r
114 // r12=ptr to tas in table, trashes r0,r1
\r
115 static void ChangeTAS(int norm)
\r
117 ot(" ldr r0,=Op4ad0%s\n",norm?"_":"");
\r
118 ot(" mov r1,#8\n");
\r
119 ot("setrtas_loop%i0%s ;@ 4ad0-4ad7\n",norm,ms?"":":");
\r
120 ot(" subs r1,r1,#1\n");
\r
121 ot(" str r0,[r12],#4\n");
\r
122 ot(" bne setrtas_loop%i0\n",norm);
\r
123 ot(" ldr r0,=Op4ad8%s\n",norm?"_":"");
\r
124 ot(" mov r1,#7\n");
\r
125 ot("setrtas_loop%i1%s ;@ 4ad8-4ade\n",norm,ms?"":":");
\r
126 ot(" subs r1,r1,#1\n");
\r
127 ot(" str r0,[r12],#4\n");
\r
128 ot(" bne setrtas_loop%i1\n",norm);
\r
129 ot(" ldr r0,=Op4adf%s\n",norm?"_":"");
\r
130 ot(" str r0,[r12],#4\n");
\r
131 ot(" ldr r0,=Op4ae0%s\n",norm?"_":"");
\r
132 ot(" mov r1,#7\n");
\r
133 ot("setrtas_loop%i2%s ;@ 4ae0-4ae6\n",norm,ms?"":":");
\r
134 ot(" subs r1,r1,#1\n");
\r
135 ot(" str r0,[r12],#4\n");
\r
136 ot(" bne setrtas_loop%i2\n",norm);
\r
137 ot(" ldr r0,=Op4ae7%s\n",norm?"_":"");
\r
138 ot(" str r0,[r12],#4\n");
\r
139 ot(" ldr r0,=Op4ae8%s\n",norm?"_":"");
\r
140 ot(" mov r1,#8\n");
\r
141 ot("setrtas_loop%i3%s ;@ 4ae8-4aef\n",norm,ms?"":":");
\r
142 ot(" subs r1,r1,#1\n");
\r
143 ot(" str r0,[r12],#4\n");
\r
144 ot(" bne setrtas_loop%i3\n",norm);
\r
145 ot(" ldr r0,=Op4af0%s\n",norm?"_":"");
\r
146 ot(" mov r1,#8\n");
\r
147 ot("setrtas_loop%i4%s ;@ 4af0-4af7\n",norm,ms?"":":");
\r
148 ot(" subs r1,r1,#1\n");
\r
149 ot(" str r0,[r12],#4\n");
\r
150 ot(" bne setrtas_loop%i4\n",norm);
\r
151 ot(" ldr r0,=Op4af8%s\n",norm?"_":"");
\r
152 ot(" str r0,[r12],#4\n");
\r
153 ot(" ldr r0,=Op4af9%s\n",norm?"_":"");
\r
154 ot(" str r0,[r12],#4\n");
\r
158 #if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO
\r
159 static void AddressErrorWrapper(char rw, const char *dataprg, int iw)
\r
161 ot("ExceptionAddressError_%c_%s%s\n", rw, dataprg, ms?"":":");
\r
162 ot(" ldr r1,[r7,#0x44]\n");
\r
163 ot(" mov r6,#0x%02x\n", iw);
\r
164 ot(" mov r11,r0\n");
\r
165 ot(" tst r1,#0x20\n");
\r
166 ot(" orrne r6,r6,#4\n");
\r
167 ot(" b ExceptionAddressError\n");
\r
174 #if MEMHANDLERS_NEED_PC
\r
176 ot(" str r4,[r7,#0x40] ;@ Save PC\n");
\r
181 static void PrintFramework()
\r
183 int state_flags_to_check = 1; // stopped
\r
185 state_flags_to_check |= 2; // tracing
\r
188 state_flags_to_check |= 0x10; // halted
\r
191 ot(";@ --------------------------- Framework --------------------------\n");
\r
192 if (ms) ot("CycloneRun\n");
\r
193 else ot("CycloneRun:\n");
\r
195 ot(" stmdb sp!,{r4-r8,r10,r11,lr}\n");
\r
197 ot(" mov r7,r0 ;@ r7 = Pointer to Cpu Context\n");
\r
198 ot(" ;@ r0-3 = Temporary registers\n");
\r
199 ot(" ldrb r10,[r7,#0x46] ;@ r10 = Flags (NZCV)\n");
\r
200 ot(" ldr r6,=CycloneJumpTab ;@ r6 = Opcode Jump table\n");
\r
201 ot(" ldr r5,[r7,#0x5c] ;@ r5 = Cycles\n");
\r
202 ot(" ldr r4,[r7,#0x40] ;@ r4 = Current PC + Memory Base\n");
\r
203 ot(" ;@ r8 = Current Opcode\n");
\r
204 ot(" ldr r1,[r7,#0x44] ;@ Get SR high T_S__III and irq level\n");
\r
205 ot(" mov r10,r10,lsl #28;@ r10 = Flags 0xf0000000, cpsr format\n");
\r
206 ot(" ;@ r11 = Source value / Memory Base\n");
\r
207 ot(" str r6,[r7,#0x54] ;@ make a copy to avoid literal pools\n");
\r
209 #if (CYCLONE_FOR_GENESIS == 2) || EMULATE_TRACE
\r
210 ot(" mov r2,#0\n");
\r
211 ot(" str r2,[r7,#0x98] ;@ clear custom CycloneEnd\n");
\r
213 ot(";@ CheckInterrupt:\n");
\r
214 ot(" movs r0,r1,lsr #24 ;@ Get IRQ level\n"); // same as ldrb r0,[r7,#0x47]
\r
215 ot(" beq NoInts0\n");
\r
216 ot(" cmp r0,#6 ;@ irq>6 ?\n");
\r
217 ot(" andle r1,r1,#7 ;@ Get interrupt mask\n");
\r
218 ot(" cmple r0,r1 ;@ irq<=6: Is irq<=mask ?\n");
\r
219 ot(" bgt CycloneDoInterrupt\n");
\r
220 ot("NoInts0%s\n", ms?"":":");
\r
222 ot(";@ Check if our processor is in special state\n");
\r
223 ot(";@ and jump to opcode handler if not\n");
\r
224 ot(" ldr r0,[r7,#0x58] ;@ state_flags\n");
\r
225 ot(" ldrh r8,[r4],#2 ;@ Fetch first opcode\n");
\r
226 ot(" tst r0,#0x%02x ;@ special state?\n", state_flags_to_check);
\r
227 ot(" ldreq pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");
\r
229 ot("CycloneSpecial%s\n", ms?"":":");
\r
231 ot(" tst r0,#2 ;@ tracing?\n");
\r
232 ot(" bne CycloneDoTrace\n");
\r
234 ot(";@ stopped or halted\n");
\r
235 ot(" mov r5,#0\n");
\r
236 ot(" str r5,[r7,#0x5C] ;@ eat all cycles\n");
\r
237 ot(" ldmia sp!,{r4-r8,r10,r11,pc} ;@ we are stopped, do nothing!\n");
\r
241 ot(";@ We come back here after execution\n");
\r
242 ot("CycloneEnd%s\n", ms?"":":");
\r
243 ot(" sub r4,r4,#2\n");
\r
244 ot("CycloneEndNoBack%s\n", ms?"":":");
\r
245 #if (CYCLONE_FOR_GENESIS == 2) || EMULATE_TRACE
\r
246 ot(" ldr r1,[r7,#0x98]\n");
\r
247 ot(" mov r10,r10,lsr #28\n");
\r
248 ot(" tst r1,r1\n");
\r
249 ot(" bxne r1 ;@ jump to alternative CycloneEnd\n");
\r
251 ot(" mov r10,r10,lsr #28\n");
\r
253 ot(" str r4,[r7,#0x40] ;@ Save Current PC + Memory Base\n");
\r
254 ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");
\r
255 ot(" strb r10,[r7,#0x46] ;@ Save Flags (NZCV)\n");
\r
256 ot(" ldmia sp!,{r4-r8,r10,r11,pc}\n");
\r
261 ot("CycloneInit%s\n", ms?"":":");
\r
262 #if COMPRESS_JUMPTABLE
\r
263 ot(";@ decompress jump table\n");
\r
264 ot(" ldr r12,=CycloneJumpTab\n");
\r
265 ot(" add r0,r12,#0xe000*4 ;@ ctrl code pointer\n");
\r
266 ot(" ldr r1,[r0,#-4]\n");
\r
267 ot(" tst r1,r1\n");
\r
268 ot(" movne pc,lr ;@ already uncompressed\n");
\r
269 ot(" add r3,r12,#0xa000*4 ;@ handler table pointer, r12=dest\n");
\r
270 ot("unc_loop%s\n", ms?"":":");
\r
271 ot(" ldrh r1,[r0],#2\n");
\r
272 ot(" and r2,r1,#0xf\n");
\r
273 ot(" bic r1,r1,#0xf\n");
\r
274 ot(" ldr r1,[r3,r1,lsr #2] ;@ r1=handler\n");
\r
275 ot(" cmp r2,#0xf\n");
\r
276 ot(" addeq r2,r2,#1 ;@ 0xf is really 0x10\n");
\r
277 ot(" tst r2,r2\n");
\r
278 ot(" ldreqh r2,[r0],#2 ;@ counter is in next word\n");
\r
279 ot(" tst r2,r2\n");
\r
280 ot(" beq unc_finish ;@ done decompressing\n");
\r
281 ot(" tst r1,r1\n");
\r
282 ot(" addeq r12,r12,r2,lsl #2 ;@ 0 handler means we should skip those bytes\n");
\r
283 ot(" beq unc_loop\n");
\r
284 ot("unc_loop_in%s\n", ms?"":":");
\r
285 ot(" subs r2,r2,#1\n");
\r
286 ot(" str r1,[r12],#4\n");
\r
287 ot(" bgt unc_loop_in\n");
\r
288 ot(" b unc_loop\n");
\r
289 ot("unc_finish%s\n", ms?"":":");
\r
290 ot(" ldr r12,=CycloneJumpTab\n");
\r
291 ot(" ;@ set a-line and f-line handlers\n");
\r
292 ot(" add r0,r12,#0xa000*4\n");
\r
293 ot(" ldr r1,[r0,#4] ;@ a-line handler\n");
\r
294 ot(" ldr r3,[r0,#8] ;@ f-line handler\n");
\r
295 ot(" mov r2,#0x1000\n");
\r
296 ot("unc_fill3%s\n", ms?"":":");
\r
297 ot(" subs r2,r2,#1\n");
\r
298 ot(" str r1,[r0],#4\n");
\r
299 ot(" bgt unc_fill3\n");
\r
300 ot(" add r0,r12,#0xf000*4\n");
\r
301 ot(" mov r2,#0x1000\n");
\r
302 ot("unc_fill4%s\n", ms?"":":");
\r
303 ot(" subs r2,r2,#1\n");
\r
304 ot(" str r3,[r0],#4\n");
\r
305 ot(" bgt unc_fill4\n");
\r
309 ot(";@ do nothing\n");
\r
315 ot("CycloneReset%s\n", ms?"":":");
\r
316 ot(" stmfd sp!,{r7,lr}\n");
\r
317 ot(" mov r7,r0\n");
\r
318 ot(" mov r0,#0\n");
\r
319 ot(" str r0,[r7,#0x58] ;@ state_flags\n");
\r
320 ot(" str r0,[r7,#0x48] ;@ OSP\n");
\r
321 ot(" mov r1,#0x27 ;@ Supervisor mode\n");
\r
322 ot(" strb r1,[r7,#0x44] ;@ set SR high\n");
\r
323 ot(" strb r0,[r7,#0x47] ;@ IRQ\n");
\r
325 ot(" str r0,[r7,#0x3c] ;@ Stack pointer\n");
\r
326 ot(" mov r0,#0\n");
\r
327 ot(" str r0,[r7,#0x60] ;@ Membase\n");
\r
328 ot(" mov r0,#4\n");
\r
330 #ifdef MEMHANDLERS_DIRECT_PREFIX
\r
331 ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);
\r
333 ot(" mov lr,pc\n");
\r
334 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");
\r
336 ot(" str r0,[r7,#0x40] ;@ PC + base\n");
\r
337 ot(" ldmfd sp!,{r7,pc}\n");
\r
341 // 68k: XNZVC, ARM: NZCV
\r
342 ot("CycloneSetSr%s\n", ms?"":":");
\r
343 ot(" mov r2,r1,lsr #8\n");
\r
344 // ot(" ldrb r3,[r0,#0x44] ;@ get SR high\n");
\r
345 // ot(" eor r3,r3,r2\n");
\r
346 // ot(" tst r3,#0x20\n");
\r
348 ot(" and r2,r2,#0xa7 ;@ only defined bits\n");
\r
350 ot(" and r2,r2,#0x27 ;@ only defined bits\n");
\r
352 ot(" strb r2,[r0,#0x44] ;@ set SR high\n");
\r
353 ot(" mov r2,r1,lsl #25\n");
\r
354 ot(" str r2,[r0,#0x4c] ;@ the X flag\n");
\r
355 ot(" bic r2,r1,#0xf3\n");
\r
356 ot(" tst r1,#1\n");
\r
357 ot(" orrne r2,r2,#2\n");
\r
358 ot(" tst r1,#2\n");
\r
359 ot(" orrne r2,r2,#1\n");
\r
360 ot(" strb r2,[r0,#0x46] ;@ flags\n");
\r
365 ot("CycloneGetSr%s\n", ms?"":":");
\r
366 ot(" ldrb r1,[r0,#0x46] ;@ flags\n");
\r
367 ot(" bic r2,r1,#0xf3\n");
\r
368 ot(" tst r1,#1\n");
\r
369 ot(" orrne r2,r2,#2\n");
\r
370 ot(" tst r1,#2\n");
\r
371 ot(" orrne r2,r2,#1\n");
\r
372 ot(" ldr r1,[r0,#0x4c] ;@ the X flag\n");
\r
373 ot(" tst r1,#0x20000000\n");
\r
374 ot(" orrne r2,r2,#0x10\n");
\r
375 ot(" ldrb r1,[r0,#0x44] ;@ the SR high\n");
\r
376 ot(" orr r0,r2,r1,lsl #8\n");
\r
381 ot("CyclonePack%s\n", ms?"":":");
\r
382 ot(" stmfd sp!,{r4,r5,lr}\n");
\r
383 ot(" mov r4,r0\n");
\r
384 ot(" mov r5,r1\n");
\r
385 ot(" mov r3,#16\n");
\r
386 ot(";@ 0x00-0x3f: DA registers\n");
\r
387 ot("c_pack_loop%s\n",ms?"":":");
\r
388 ot(" ldr r1,[r0],#4\n");
\r
389 ot(" subs r3,r3,#1\n");
\r
390 ot(" str r1,[r5],#4\n");
\r
391 ot(" bne c_pack_loop\n");
\r
392 ot(";@ 0x40: PC\n");
\r
393 ot(" ldr r0,[r4,#0x40] ;@ PC + Memory Base\n");
\r
394 ot(" ldr r1,[r4,#0x60] ;@ Memory base\n");
\r
395 ot(" sub r0,r0,r1\n");
\r
396 ot(" str r0,[r5],#4\n");
\r
397 ot(";@ 0x44: SR\n");
\r
398 ot(" mov r0,r4\n");
\r
399 ot(" bl CycloneGetSr\n");
\r
400 ot(" strh r0,[r5],#2\n");
\r
401 ot(";@ 0x46: IRQ level\n");
\r
402 ot(" ldrb r0,[r4,#0x47]\n");
\r
403 ot(" strb r0,[r5],#2\n");
\r
404 ot(";@ 0x48: other SP\n");
\r
405 ot(" ldr r0,[r4,#0x48]\n");
\r
406 ot(" str r0,[r5],#4\n");
\r
407 ot(";@ 0x4c: CPU state flags\n");
\r
408 ot(" ldr r0,[r4,#0x58]\n");
\r
409 ot(" str r0,[r5],#4\n");
\r
410 ot(" ldmfd sp!,{r4,r5,pc}\n");
\r
414 ot("CycloneUnpack%s\n", ms?"":":");
\r
415 ot(" stmfd sp!,{r5,r7,lr}\n");
\r
416 ot(" mov r7,r0\n");
\r
417 ot(" movs r5,r1\n");
\r
418 ot(" beq c_unpack_do_pc\n");
\r
419 ot(" mov r3,#16\n");
\r
420 ot(";@ 0x00-0x3f: DA registers\n");
\r
421 ot("c_unpack_loop%s\n",ms?"":":");
\r
422 ot(" ldr r1,[r5],#4\n");
\r
423 ot(" subs r3,r3,#1\n");
\r
424 ot(" str r1,[r0],#4\n");
\r
425 ot(" bne c_unpack_loop\n");
\r
426 ot(";@ 0x40: PC\n");
\r
427 ot(" ldr r0,[r5],#4 ;@ PC\n");
\r
428 ot(" str r0,[r7,#0x40] ;@ handle later\n");
\r
429 ot(";@ 0x44: SR\n");
\r
430 ot(" ldrh r1,[r5],#2\n");
\r
431 ot(" mov r0,r7\n");
\r
432 ot(" bl CycloneSetSr\n");
\r
433 ot(";@ 0x46: IRQ level\n");
\r
434 ot(" ldrb r0,[r5],#2\n");
\r
435 ot(" strb r0,[r7,#0x47]\n");
\r
436 ot(";@ 0x48: other SP\n");
\r
437 ot(" ldr r0,[r5],#4\n");
\r
438 ot(" str r0,[r7,#0x48]\n");
\r
439 ot(";@ 0x4c: CPU state flags\n");
\r
440 ot(" ldr r0,[r5],#4\n");
\r
441 ot(" str r0,[r7,#0x58]\n");
\r
442 ot("c_unpack_do_pc%s\n",ms?"":":");
\r
443 ot(" ldr r0,[r7,#0x40] ;@ unbased PC\n");
\r
444 #if USE_CHECKPC_CALLBACK
\r
445 ot(" mov r1,#0\n");
\r
446 ot(" str r1,[r7,#0x60] ;@ Memory base\n");
\r
447 #ifdef MEMHANDLERS_DIRECT_PREFIX
\r
448 ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);
\r
450 ot(" mov lr,pc\n");
\r
451 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");
\r
454 ot(" ldr r1,[r7,#0x60] ;@ Memory base\n");
\r
455 ot(" add r0,r0,r1 ;@ r0 = Memory Base + New PC\n");
\r
457 ot(" str r0,[r7,#0x40] ;@ PC + Memory Base\n");
\r
458 ot(" ldmfd sp!,{r5,r7,pc}\n");
\r
462 ot("CycloneFlushIrq%s\n", ms?"":":");
\r
463 ot(" ldr r1,[r0,#0x44] ;@ Get SR high T_S__III and irq level\n");
\r
464 ot(" mov r2,r1,lsr #24 ;@ Get IRQ level\n"); // same as ldrb r0,[r7,#0x47]
\r
465 ot(" cmp r2,#6 ;@ irq>6 ?\n");
\r
466 ot(" andle r1,r1,#7 ;@ Get interrupt mask\n");
\r
467 ot(" cmple r2,r1 ;@ irq<=6: Is irq<=mask ?\n");
\r
468 ot(" movle r0,#0\n");
\r
469 ot(" bxle lr ;@ no ints\n");
\r
471 ot(" stmdb sp!,{r4,r5,r7,r8,r10,r11,lr}\n");
\r
472 ot(" mov r7,r0\n");
\r
473 ot(" mov r0,r2\n");
\r
474 ot(" ldrb r10,[r7,#0x46] ;@ r10 = Flags (NZCV)\n");
\r
475 ot(" mov r5,#0\n");
\r
476 ot(" ldr r4,[r7,#0x40] ;@ r4 = Current PC + Memory Base\n");
\r
477 ot(" mov r10,r10,lsl #28 ;@ r10 = Flags 0xf0000000, cpsr format\n");
\r
478 ot(" adr r2,CycloneFlushIrqEnd\n");
\r
479 ot(" str r2,[r7,#0x98] ;@ set custom CycloneEnd\n");
\r
480 ot(" b CycloneDoInterrupt\n");
\r
482 ot("CycloneFlushIrqEnd%s\n", ms?"":":");
\r
483 ot(" rsb r0,r5,#0\n");
\r
484 ot(" str r4,[r7,#0x40] ;@ Save Current PC + Memory Base\n");
\r
485 ot(" strb r10,[r7,#0x46] ;@ Save Flags (NZCV)\n");
\r
486 ot(" ldmia sp!,{r4,r5,r7,r8,r10,r11,lr}\n");
\r
492 ot("CycloneSetRealTAS%s\n", ms?"":":");
\r
493 #if (CYCLONE_FOR_GENESIS == 2)
\r
494 ot(" ldr r12,=CycloneJumpTab\n");
\r
495 ot(" tst r0,r0\n");
\r
496 ot(" add r12,r12,#0x4a00*4\n");
\r
497 ot(" add r12,r12,#0x00d0*4\n");
\r
498 ot(" beq setrtas_off\n");
\r
501 ot("setrtas_off%s\n",ms?"":":");
\r
511 ot(";@ DoInterrupt - r0=IRQ level\n");
\r
512 ot("CycloneDoInterruptGoBack%s\n", ms?"":":");
\r
513 ot(" sub r4,r4,#2\n");
\r
514 ot("CycloneDoInterrupt%s\n", ms?"":":");
\r
515 ot(" bic r8,r8,#0xff000000\n");
\r
516 ot(" orr r8,r8,r0,lsl #29 ;@ abuse r8\n");
\r
518 // Steps are from "M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL", p. 6-4
\r
519 // but their order is based on http://pasti.fxatari.com/68kdocs/68kPrefetch.html
\r
520 // 1. Make a temporary copy of the status register and set the status register for exception processing.
\r
521 ot(" ldr r2,[r7,#0x58] ;@ state flags\n");
\r
522 ot(" and r0,r0,#7\n");
\r
523 ot(" orr r3,r0,#0x20 ;@ Supervisor mode + IRQ level\n");
\r
524 ot(" bic r2,r2,#3 ;@ clear stopped and trace states\n");
\r
525 #if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO
\r
526 ot(" orr r2,r2,#4 ;@ set activity bit: 'not processing instruction'\n");
\r
528 ot(" str r2,[r7,#0x58]\n");
\r
529 ot(" ldrb r6,[r7,#0x44] ;@ Get old SR high, abuse r6\n");
\r
530 ot(" strb r3,[r7,#0x44] ;@ Put new SR high\n");
\r
533 // 3. Save the current processor context.
\r
534 ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");
\r
535 ot(" ldr r11,[r7,#0x3c] ;@ Get A7\n");
\r
536 ot(" tst r6,#0x20\n");
\r
537 ot(";@ get our SP:\n");
\r
538 ot(" ldreq r2,[r7,#0x48] ;@ ...or OSP as our stack pointer\n");
\r
539 ot(" streq r11,[r7,#0x48]\n");
\r
540 ot(" moveq r11,r2\n");
\r
541 ot(";@ Push old PC onto stack\n");
\r
542 ot(" sub r0,r11,#4 ;@ Predecremented A7\n");
\r
543 ot(" sub r1,r4,r1 ;@ r1 = Old PC\n");
\r
545 ot(";@ Push old SR:\n");
\r
546 ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");
\r
547 ot(" mov r1,r10,lsr #28 ;@ ____NZCV\n");
\r
548 ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");
\r
549 ot(" tst r2,#1 ;@ 1 if C!=V\n");
\r
550 ot(" eorne r1,r1,#3 ;@ ____NZVC\n");
\r
551 ot(" and r0,r0,#0x20000000\n");
\r
552 ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");
\r
553 ot(" orr r1,r1,r6,lsl #8 ;@ Include old SR high\n");
\r
554 ot(" sub r0,r11,#6 ;@ Predecrement A7\n");
\r
555 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
\r
556 MemHandler(1,1,0,0); // already checked for address error by prev MemHandler
\r
559 // 2. Obtain the exception vector.
\r
560 ot(" mov r11,r8,lsr #29\n");
\r
561 ot(" mov r0,r11\n");
\r
562 #if USE_INT_ACK_CALLBACK
\r
563 ot(";@ call IrqCallback if it is defined\n");
\r
564 #if INT_ACK_NEEDS_STUFF
\r
565 ot(" str r4,[r7,#0x40] ;@ Save PC\n");
\r
566 ot(" mov r1,r10,lsr #28\n");
\r
567 ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");
\r
568 ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");
\r
570 ot(" ldr r3,[r7,#0x8c] ;@ IrqCallback\n");
\r
571 ot(" add lr,pc,#4*3\n");
\r
572 ot(" tst r3,r3\n");
\r
573 ot(" streqb r3,[r7,#0x47] ;@ just clear IRQ if there is no callback\n");
\r
574 ot(" mvneq r0,#0 ;@ and simulate -1 return\n");
\r
576 #if INT_ACK_CHANGES_CYCLES
\r
577 ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");
\r
579 ot(";@ get IRQ vector address:\n");
\r
580 ot(" cmn r0,#1 ;@ returned -1?\n");
\r
581 ot(" addeq r0,r11,#0x18 ;@ use autovector then\n");
\r
582 ot(" cmn r0,#2 ;@ returned -2?\n"); // should be safe as above add should never result in -2
\r
583 ot(" moveq r0,#0x18 ;@ use spurious interrupt then\n");
\r
584 #else // !USE_INT_ACK_CALLBACK
\r
585 ot(";@ Clear irq:\n");
\r
586 ot(" mov r2,#0\n");
\r
587 ot(" strb r2,[r7,#0x47]\n");
\r
588 ot(" add r0,r0,#0x18 ;@ use autovector\n");
\r
590 ot(" mov r0,r0,lsl #2 ;@ get vector address\n");
\r
592 ot(" ldr r11,[r7,#0x60] ;@ Get Memory base\n");
\r
593 ot(";@ Read IRQ Vector:\n");
\r
594 MemHandler(0,2,0,0);
\r
595 ot(" tst r0,r0 ;@ uninitialized int vector?\n");
\r
596 ot(" moveq r0,#0x3c\n");
\r
597 #ifdef MEMHANDLERS_DIRECT_PREFIX
\r
598 ot(" bleq %sread32 ;@ Call read32(r0) handler\n", MEMHANDLERS_DIRECT_PREFIX);
\r
600 ot(" moveq lr,pc\n");
\r
601 ot(" ldreq pc,[r7,#0x70] ;@ Call read32(r0) handler\n");
\r
603 #if USE_CHECKPC_CALLBACK
\r
604 ot(" add lr,pc,#4\n");
\r
605 ot(" add r0,r0,r11 ;@ r0 = Memory Base + New PC\n");
\r
606 #ifdef MEMHANDLERS_DIRECT_PREFIX
\r
607 ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);
\r
609 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");
\r
611 #if EMULATE_ADDRESS_ERRORS_JUMP
\r
612 ot(" mov r4,r0\n");
\r
614 ot(" bic r4,r0,#1\n");
\r
617 ot(" add r4,r0,r11 ;@ r4 = Memory Base + New PC\n");
\r
618 #if EMULATE_ADDRESS_ERRORS_JUMP
\r
619 ot(" bic r4,r4,#1\n");
\r
624 // 4. Obtain a new context and resume instruction processing.
\r
625 // note: the obtain part was already done in previous steps
\r
626 #if EMULATE_ADDRESS_ERRORS_JUMP
\r
627 ot(" tst r4,#1\n");
\r
628 ot(" bne ExceptionAddressError_r_prg_r4\n");
\r
630 ot(" ldr r6,[r7,#0x54]\n");
\r
631 ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");
\r
632 ot(" subs r5,r5,#44 ;@ Subtract cycles\n");
\r
633 ot(" ldrge pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");
\r
634 ot(" b CycloneEnd\n");
\r
638 // trashes all temp regs
\r
639 ot("Exception%s\n", ms?"":":");
\r
640 ot(" ;@ Cause an Exception - Vector number in r0\n");
\r
641 ot(" mov r11,lr ;@ Preserve ARM return address\n");
\r
642 ot(" bic r8,r8,#0xff000000\n");
\r
643 ot(" orr r8,r8,r0,lsl #24 ;@ abuse r8\n");
\r
645 // 1. Make a temporary copy of the status register and set the status register for exception processing.
\r
646 ot(" ldr r6,[r7,#0x44] ;@ Get old SR high, abuse r6\n");
\r
647 ot(" ldr r2,[r7,#0x58] ;@ state flags\n");
\r
648 ot(" and r3,r6,#0x27 ;@ clear trace and unused flags\n");
\r
649 ot(" orr r3,r3,#0x20 ;@ set supervisor mode\n");
\r
650 ot(" bic r2,r2,#3 ;@ clear stopped and trace states\n");
\r
651 ot(" str r2,[r7,#0x58]\n");
\r
652 ot(" strb r3,[r7,#0x44] ;@ Put new SR high\n");
\r
655 // 3. Save the current processor context.
\r
656 ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");
\r
657 ot(" tst r6,#0x20\n");
\r
658 ot(";@ get our SP:\n");
\r
659 ot(" ldreq r2,[r7,#0x48] ;@ ...or OSP as our stack pointer\n");
\r
660 ot(" streq r0,[r7,#0x48]\n");
\r
661 ot(" moveq r0,r2\n");
\r
662 ot(";@ Push old PC onto stack\n");
\r
663 ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");
\r
664 ot(" sub r0,r0,#4 ;@ Predecremented A7\n");
\r
665 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
\r
666 ot(" sub r1,r4,r1 ;@ r1 = Old PC\n");
\r
668 ot(";@ Push old SR:\n");
\r
669 ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");
\r
670 ot(" mov r1,r10,lsr #28 ;@ ____NZCV\n");
\r
671 ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");
\r
672 ot(" tst r2,#1 ;@ 1 if C!=V\n");
\r
673 ot(" eorne r1,r1,#3 ;@ ____NZVC\n");
\r
674 ot(" and r0,r0,#0x20000000\n");
\r
675 ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");
\r
676 ot(" ldr r0,[r7,#0x3c] ;@ A7\n");
\r
677 ot(" orr r1,r1,r6,lsl #8 ;@ Include SR high\n");
\r
678 ot(" sub r0,r0,#2 ;@ Predecrement A7\n");
\r
679 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
\r
680 MemHandler(1,1,0,0);
\r
683 // 2. Obtain the exception vector
\r
684 ot(";@ Read Exception Vector:\n");
\r
685 ot(" mov r0,r8,lsr #24\n");
\r
686 ot(" mov r0,r0,lsl #2\n");
\r
687 MemHandler(0,2,0,0);
\r
688 ot(" ldr r3,[r7,#0x60] ;@ Get Memory base\n");
\r
689 #if USE_CHECKPC_CALLBACK
\r
690 ot(" add lr,pc,#4\n");
\r
691 ot(" add r0,r0,r3 ;@ r0 = Memory Base + New PC\n");
\r
692 #ifdef MEMHANDLERS_DIRECT_PREFIX
\r
693 ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);
\r
695 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");
\r
697 #if EMULATE_ADDRESS_ERRORS_JUMP
\r
698 ot(" mov r4,r0\n");
\r
700 ot(" bic r4,r0,#1\n");
\r
703 ot(" add r4,r0,r3 ;@ r4 = Memory Base + New PC\n");
\r
704 #if EMULATE_ADDRESS_ERRORS_JUMP
\r
705 ot(" bic r4,r4,#1\n");
\r
710 // 4. Resume execution.
\r
711 #if EMULATE_ADDRESS_ERRORS_JUMP
\r
712 ot(" tst r4,#1\n");
\r
713 ot(" bne ExceptionAddressError_r_prg_r4\n");
\r
715 ot(" ldr r6,[r7,#0x54]\n");
\r
716 ot(" bx r11 ;@ Return\n");
\r
720 #if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO
\r
721 // first some wrappers: I see no point inlining this code,
\r
722 // as it will be executed in really rare cases.
\r
723 AddressErrorWrapper('r', "data", 0x11);
\r
724 AddressErrorWrapper('r', "prg", 0x12);
\r
725 AddressErrorWrapper('w', "data", 0x01);
\r
726 // there are no program writes
\r
727 // cpu space is only for bus errors?
\r
728 ot("ExceptionAddressError_r_prg_r4%s\n", ms?"":":");
\r
729 ot(" ldr r1,[r7,#0x44]\n");
\r
730 ot(" ldr r3,[r7,#0x60] ;@ Get Memory base\n");
\r
731 ot(" mov r6,#0x12\n");
\r
732 ot(" sub r11,r4,r3\n");
\r
733 ot(" tst r1,#0x20\n");
\r
734 ot(" orrne r6,r6,#4\n");
\r
737 ot("ExceptionAddressError%s\n", ms?"":":");
\r
738 ot(";@ r6 - info word (without instruction/not bit), r11 - faulting address\n");
\r
740 // 1. Make a temporary copy of the status register and set the status register for exception processing.
\r
741 ot(" ldrb r0,[r7,#0x44] ;@ Get old SR high\n");
\r
742 ot(" ldr r2,[r7,#0x58] ;@ state flags\n");
\r
743 ot(" and r3,r0,#0x27 ;@ clear trace and unused flags\n");
\r
744 ot(" orr r3,r3,#0x20 ;@ set supervisor mode\n");
\r
745 ot(" strb r3,[r7,#0x44] ;@ Put new SR high\n");
\r
746 ot(" bic r2,r2,#3 ;@ clear stopped and trace states\n");
\r
747 ot(" tst r2,#4\n");
\r
748 ot(" orrne r6,r6,#8 ;@ complete info word\n");
\r
749 ot(" orr r2,r2,#4 ;@ set activity bit: 'not processing instruction'\n");
\r
751 ot(" tst r2,#8\n");
\r
752 ot(" orrne r2,r2,#0x10 ;@ HALT\n");
\r
753 ot(" orr r2,r2,#8 ;@ processing address error\n");
\r
754 ot(" str r2,[r7,#0x58]\n");
\r
755 ot(" movne r5,#0\n");
\r
756 ot(" bne CycloneEndNoBack ;@ bye bye\n");
\r
758 ot(" str r2,[r7,#0x58]\n");
\r
760 ot(" and r10,r10,#0xf0000000\n");
\r
761 ot(" orr r10,r10,r0,lsl #4 ;@ some preparations for SR push\n");
\r
764 // 3. Save the current processor context + additional information.
\r
765 ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");
\r
766 ot(" tst r10,#0x200\n");
\r
767 ot(";@ get our SP:\n");
\r
768 ot(" ldreq r2,[r7,#0x48] ;@ ...or OSP as our stack pointer\n");
\r
769 ot(" streq r0,[r7,#0x48]\n");
\r
770 ot(" moveq r0,r2\n");
\r
772 ot(";@ Push old PC onto stack\n");
\r
773 ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");
\r
774 ot(" sub r0,r0,#4 ;@ Predecremented A7\n");
\r
775 ot(" sub r1,r4,r1 ;@ r1 = Old PC\n");
\r
776 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
\r
777 MemHandler(1,2,0,EMULATE_HALT);
\r
779 ot(";@ Push old SR:\n");
\r
780 ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");
\r
781 ot(" mov r1,r10,ror #28 ;@ ____NZCV\n");
\r
782 ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");
\r
783 ot(" tst r2,#1 ;@ 1 if C!=V\n");
\r
784 ot(" eorne r1,r1,#3 ;@ ____NZVC\n");
\r
785 ot(" and r0,r0,#0x20000000\n");
\r
786 ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");
\r
787 ot(" ldr r0,[r7,#0x3c] ;@ A7\n");
\r
788 ot(" and r10,r10,#0xf0000000\n");
\r
789 ot(" sub r0,r0,#2 ;@ Predecrement A7\n");
\r
790 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
\r
791 MemHandler(1,1,0,0);
\r
792 // IR (instruction register)
\r
793 ot(";@ Push IR:\n");
\r
794 ot(" ldr r0,[r7,#0x3c] ;@ A7\n");
\r
795 ot(" mov r1,r8\n");
\r
796 ot(" sub r0,r0,#2 ;@ Predecrement A7\n");
\r
797 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
\r
798 MemHandler(1,1,0,0);
\r
800 ot(";@ Push address:\n");
\r
801 ot(" ldr r0,[r7,#0x3c] ;@ A7\n");
\r
802 ot(" mov r1,r11\n");
\r
803 ot(" sub r0,r0,#4 ;@ Predecrement A7\n");
\r
804 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
\r
805 MemHandler(1,2,0,0);
\r
806 // information word
\r
807 ot(";@ Push info word:\n");
\r
808 ot(" ldr r0,[r7,#0x3c] ;@ A7\n");
\r
809 ot(" mov r1,r6\n");
\r
810 ot(" sub r0,r0,#2 ;@ Predecrement A7\n");
\r
811 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
\r
812 MemHandler(1,1,0,0);
\r
815 // 2. Obtain the exception vector
\r
816 ot(";@ Read Exception Vector:\n");
\r
817 ot(" mov r0,#0x0c\n");
\r
818 MemHandler(0,2,0,0);
\r
819 ot(" ldr r3,[r7,#0x60] ;@ Get Memory base\n");
\r
820 #if USE_CHECKPC_CALLBACK
\r
821 ot(" add lr,pc,#4\n");
\r
822 ot(" add r0,r0,r3 ;@ r0 = Memory Base + New PC\n");
\r
823 #ifdef MEMHANDLERS_DIRECT_PREFIX
\r
824 ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);
\r
826 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");
\r
828 ot(" mov r4,r0\n");
\r
830 ot(" add r4,r0,r3 ;@ r4 = Memory Base + New PC\n");
\r
834 #if EMULATE_ADDRESS_ERRORS_JUMP && EMULATE_HALT
\r
835 ot(" tst r4,#1\n");
\r
836 ot(" bne ExceptionAddressError_r_prg_r4\n");
\r
838 ot(" bic r4,r4,#1\n");
\r
841 // 4. Resume execution.
\r
842 ot(" ldr r6,[r7,#0x54]\n");
\r
843 ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");
\r
844 ot(" subs r5,r5,#50 ;@ Subtract cycles\n");
\r
845 ot(" ldrge pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");
\r
846 ot(" b CycloneEnd\n");
\r
852 // expects srh and irq level in r1, next opcode already fetched to r8
\r
853 ot("CycloneDoTraceWithChecks%s\n", ms?"":":");
\r
854 ot(" ldr r0,[r7,#0x58]\n");
\r
855 ot(" cmp r5,#0\n");
\r
856 ot(" orr r0,r0,#2 ;@ go to trace mode\n");
\r
857 ot(" str r0,[r7,#0x58]\n");
\r
858 ot(" blt CycloneEnd\n"); // should take care of situation where we come here when already tracing
\r
859 ot(";@ CheckInterrupt:\n");
\r
860 ot(" movs r0,r1,lsr #24 ;@ Get IRQ level\n");
\r
861 ot(" beq CycloneDoTrace\n");
\r
862 ot(" cmp r0,#6 ;@ irq>6 ?\n");
\r
863 ot(" andle r1,r1,#7 ;@ Get interrupt mask\n");
\r
864 ot(" cmple r0,r1 ;@ irq<=6: Is irq<=mask ?\n");
\r
865 ot(" bgt CycloneDoInterruptGoBack\n");
\r
868 // expects next opcode to be already fetched to r8
\r
869 ot("CycloneDoTrace%s\n", ms?"":":");
\r
870 ot(" str r5,[r7,#0x9c] ;@ save cycles\n");
\r
871 ot(" ldr r1,[r7,#0x98]\n");
\r
872 ot(" mov r5,#0\n");
\r
873 ot(" str r1,[r7,#0xa0]\n");
\r
874 ot(" adr r0,TraceEnd\n");
\r
875 ot(" str r0,[r7,#0x98] ;@ store TraceEnd as CycloneEnd hadler\n");
\r
876 ot(" ldr pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");
\r
879 ot("TraceEnd%s\n", ms?"":":");
\r
880 ot(" ldr r2,[r7,#0x58]\n");
\r
881 ot(" ldr r0,[r7,#0x9c] ;@ restore cycles\n");
\r
882 ot(" ldr r1,[r7,#0xa0] ;@ old CycloneEnd handler\n");
\r
883 ot(" mov r10,r10,lsl #28\n");
\r
884 ot(" add r5,r0,r5\n");
\r
885 ot(" str r1,[r7,#0x98]\n");
\r
886 ot(";@ still tracing?\n"); // exception might have happend
\r
887 ot(" tst r2,#2\n");
\r
888 ot(" beq TraceDisabled\n");
\r
889 ot(";@ trace exception\n");
\r
890 #if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO
\r
891 ot(" ldr r1,[r7,#0x58]\n");
\r
892 ot(" mov r0,#9\n");
\r
893 ot(" orr r1,r1,#4 ;@ set activity bit: 'not processing instruction'\n");
\r
894 ot(" str r1,[r7,#0x58]\n");
\r
896 ot(" mov r0,#9\n");
\r
898 ot(" bl Exception\n");
\r
899 ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");
\r
900 ot(" subs r5,r5,#34 ;@ Subtract cycles\n");
\r
901 ot(" ldrge pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");
\r
902 ot(" b CycloneEnd\n");
\r
904 ot("TraceDisabled%s\n", ms?"":":");
\r
905 ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");
\r
906 ot(" cmp r5,#0\n");
\r
907 ot(" ldrge pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");
\r
908 ot(" b CycloneEnd\n");
\r
913 // ---------------------------------------------------------------------------
\r
914 // Call Read(r0), Write(r0,r1) or Fetch(r0)
\r
915 // Trashes r0-r3,r12,lr
\r
916 int MemHandler(int type,int size,int addrreg,int need_addrerr_check)
\r
918 int func=0x68+type*0xc+(size<<2); // Find correct offset
\r
921 #if MEMHANDLERS_NEED_FLAGS
\r
922 ot(" mov r3,r10,lsr #28\n");
\r
923 ot(" strb r3,[r7,#0x46] ;@ Save Flags (NZCV)\n");
\r
927 #if (MEMHANDLERS_ADDR_MASK & 0xff000000)
\r
928 ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0xff000000);
\r
931 #if (MEMHANDLERS_ADDR_MASK & 0x00ff0000)
\r
932 ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0x00ff0000);
\r
935 #if (MEMHANDLERS_ADDR_MASK & 0x0000ff00)
\r
936 ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0x0000ff00);
\r
939 #if (MEMHANDLERS_ADDR_MASK & 0x000000ff)
\r
940 ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0x000000ff);
\r
944 #if EMULATE_ADDRESS_ERRORS_IO
\r
945 if (size > 0 && need_addrerr_check)
\r
947 ot(" add lr,pc,#4*%i\n", addrreg==0?2:3); // helps to prevent interlocks
\r
948 if (addrreg != 0) ot(" mov r0,r%i\n", addrreg);
\r
949 ot(" tst r0,#1 ;@ address error?\n");
\r
951 case 0: ot(" bne ExceptionAddressError_r_data\n"); break;
\r
952 case 1: ot(" bne ExceptionAddressError_w_data\n"); break;
\r
953 case 2: ot(" bne ExceptionAddressError_r_prg\n"); break;
\r
959 sprintf(what, "%s%d", type==0 ? "read" : (type==1 ? "write" : "fetch"), 8<<size);
\r
960 #ifdef MEMHANDLERS_DIRECT_PREFIX
\r
962 ot(" mov r0,r%i\n", addrreg);
\r
963 ot(" bl %s%s ;@ Call ", MEMHANDLERS_DIRECT_PREFIX, what);
\r
964 (void)func; // avoid warning
\r
968 ot(" add lr,pc,#4\n");
\r
969 ot(" mov r0,r%i\n", addrreg);
\r
972 ot(" mov lr,pc\n");
\r
973 ot(" ldr pc,[r7,#0x%x] ;@ Call ",func);
\r
976 // Document what we are calling:
\r
977 if (type==1) ot("%s(r0,r1)",what);
\r
978 else ot("%s(r0)", what);
\r
981 #if MEMHANDLERS_CHANGE_FLAGS
\r
982 ot(" ldrb r10,[r7,#0x46] ;@ r10 = Load Flags (NZCV)\n");
\r
983 ot(" mov r10,r10,lsl #28\n");
\r
985 #if MEMHANDLERS_CHANGE_PC
\r
986 ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");
\r
992 static void PrintOpcodes()
\r
996 printf("Creating Opcodes: [");
\r
998 ot(";@ ---------------------------- Opcodes ---------------------------\n");
\r
1000 // Emit null opcode:
\r
1001 ot("Op____%s ;@ Called if an opcode is not recognised\n", ms?"":":");
\r
1002 #if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO
\r
1003 ot(" ldr r1,[r7,#0x58]\n");
\r
1004 ot(" sub r4,r4,#2\n");
\r
1005 ot(" orr r1,r1,#4 ;@ set activity bit: 'not processing instruction'\n");
\r
1006 ot(" str r1,[r7,#0x58]\n");
\r
1008 ot(" sub r4,r4,#2\n");
\r
1010 #if USE_UNRECOGNIZED_CALLBACK
\r
1011 ot(" str r4,[r7,#0x40] ;@ Save PC\n");
\r
1012 ot(" mov r1,r10,lsr #28\n");
\r
1013 ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");
\r
1014 ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");
\r
1015 ot(" ldr r11,[r7,#0x94] ;@ UnrecognizedCallback\n");
\r
1016 ot(" tst r11,r11\n");
\r
1017 ot(" movne lr,pc\n");
\r
1018 ot(" movne pc,r11 ;@ call UnrecognizedCallback if it is defined\n");
\r
1019 ot(" ldrb r10,[r7,#0x46] ;@ r10 = Load Flags (NZCV)\n");
\r
1020 ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");
\r
1021 ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");
\r
1022 ot(" mov r10,r10,lsl #28\n");
\r
1023 ot(" tst r0,r0\n");
\r
1024 ot(" moveq r0,#4\n");
\r
1025 ot(" bleq Exception\n");
\r
1027 ot(" mov r0,#4\n");
\r
1028 ot(" bl Exception\n");
\r
1034 // Unrecognised a-line and f-line opcodes throw an exception:
\r
1035 ot("Op__al%s ;@ Unrecognised a-line opcode\n", ms?"":":");
\r
1036 ot(" sub r4,r4,#2\n");
\r
1037 #if USE_AFLINE_CALLBACK
\r
1038 ot(" str r4,[r7,#0x40] ;@ Save PC\n");
\r
1039 ot(" mov r1,r10,lsr #28\n");
\r
1040 ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");
\r
1041 ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");
\r
1042 ot(" ldr r11,[r7,#0x94] ;@ UnrecognizedCallback\n");
\r
1043 ot(" tst r11,r11\n");
\r
1044 ot(" movne lr,pc\n");
\r
1045 ot(" movne pc,r11 ;@ call UnrecognizedCallback if it is defined\n");
\r
1046 ot(" ldrb r10,[r7,#0x46] ;@ r10 = Load Flags (NZCV)\n");
\r
1047 ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");
\r
1048 ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");
\r
1049 ot(" mov r10,r10,lsl #28\n");
\r
1050 ot(" tst r0,r0\n");
\r
1051 ot(" moveq r0,#0x0a\n");
\r
1052 ot(" bleq Exception\n");
\r
1054 ot(" mov r0,#0x0a\n");
\r
1055 ot(" bl Exception\n");
\r
1061 ot("Op__fl%s ;@ Unrecognised f-line opcode\n", ms?"":":");
\r
1062 ot(" sub r4,r4,#2\n");
\r
1063 #if USE_AFLINE_CALLBACK
\r
1064 ot(" str r4,[r7,#0x40] ;@ Save PC\n");
\r
1065 ot(" mov r1,r10,lsr #28\n");
\r
1066 ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");
\r
1067 ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");
\r
1068 ot(" ldr r11,[r7,#0x94] ;@ UnrecognizedCallback\n");
\r
1069 ot(" tst r11,r11\n");
\r
1070 ot(" movne lr,pc\n");
\r
1071 ot(" movne pc,r11 ;@ call UnrecognizedCallback if it is defined\n");
\r
1072 ot(" ldrb r10,[r7,#0x46] ;@ r10 = Load Flags (NZCV)\n");
\r
1073 ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");
\r
1074 ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");
\r
1075 ot(" mov r10,r10,lsl #28\n");
\r
1076 ot(" tst r0,r0\n");
\r
1077 ot(" moveq r0,#0x0b\n");
\r
1078 ot(" bleq Exception\n");
\r
1080 ot(" mov r0,#0x0b\n");
\r
1081 ot(" bl Exception\n");
\r
1088 for (op=0;op<hot_opcode_count;op++)
\r
1089 OpAny(hot_opcodes[op]);
\r
1091 for (op=0;op<0x10000;op++)
\r
1093 if ((op&0xfff)==0) { printf("%x",op>>12); fflush(stdout); } // Update progress
\r
1095 if (!is_op_hot(op))
\r
1105 static void ott(const char *str, int par, const char *nl, int nlp, int counter, int size)
\r
1108 case 0: if((counter&7)==0) ot(ms?" dcb ":" .byte "); break;
\r
1109 case 1: if((counter&7)==0) ot(ms?" dcw ":" .hword "); break;
\r
1110 case 2: if((counter&7)==0) ot(ms?" dcd ":" .long "); break;
\r
1113 if((counter&7)==7) ot(nl,nlp); else ot(",");
\r
1116 static void PrintJumpTable()
\r
1118 int i=0,op=0,len=0;
\r
1120 ot(";@ -------------------------- Jump Table --------------------------\n");
\r
1122 // space for decompressed table
\r
1123 ot(ms?" area |.data|, data\n":" .data\n .align 4\n\n");
\r
1125 #if COMPRESS_JUMPTABLE
\r
1126 int handlers=0,reps=0,*indexes,ip,u,out;
\r
1127 // use some weird compression on the jump table
\r
1128 indexes=(int *)malloc(0x10000*4);
\r
1129 if(!indexes) { printf("ERROR: out of memory\n"); exit(1); }
\r
1132 ot("CycloneJumpTab%s\n", ms?"":":");
\r
1134 for(i = 0; i < 0xa000/8; i++)
\r
1135 ot(" dcd 0,0,0,0,0,0,0,0\n");
\r
1137 ot(" .rept 0x%x\n .long 0,0,0,0,0,0,0,0\n .endr\n", 0xa000/8);
\r
1139 // hanlers live in "a-line" part of the table
\r
1140 // first output nop,a-line,f-line handlers
\r
1141 ot(ms?" dcd Op____,Op__al,Op__fl,":" .long Op____,Op__al,Op__fl,");
\r
1144 for(i=0;i<len;i++)
\r
1148 for(u=i-1; u>=0; u--) if(op == CyJump[u]) break; // already done with this op?
\r
1149 if(u==-1 && op >= 0) {
\r
1150 ott("Op%.4x",op," ;@ %.4x\n",i,handlers,2);
\r
1151 indexes[op] = handlers;
\r
1156 fseek(AsmFile, -1, SEEK_CUR); // remove last comma
\r
1157 for(i = 8-(handlers&7); i > 0; i--)
\r
1162 for(i = (0x4000-handlers)/8; i > 0; i--)
\r
1163 ot(" dcd 0,0,0,0,0,0,0,0\n");
\r
1165 ot(ms?"":" .rept 0x%x\n .long 0,0,0,0,0,0,0,0\n .endr\n", (0x4000-handlers)/8);
\r
1167 printf("total distinct hanlers: %i\n",handlers);
\r
1169 for(i=0,ip=0; i < 0xf000; i++, ip++) {
\r
1172 // it must skip a-line area, because we keep our data there
\r
1173 ott("0x%.4x", handlers<<4, "\n",0,ip++,1);
\r
1174 ott("0x%.4x", 0x1000, "\n",0,ip,1);
\r
1178 for(reps=1; i < 0xf000; i++, reps++) if(op != CyJump[i+1]) break;
\r
1179 if(op>=0) out=indexes[op]<<4; else out=0; // unrecognised
\r
1180 if(reps <= 0xe || reps==0x10) {
\r
1181 if(reps!=0x10) out|=reps; else out|=0xf; // 0xf means 0x10 (0xf appeared to be unused anyway)
\r
1182 ott("0x%.4x", out, "\n",0,ip,1);
\r
1184 ott("0x%.4x", out, "\n",0,ip++,1);
\r
1185 ott("0x%.4x", reps,"\n",0,ip,1);
\r
1188 if(ip&1) ott("0x%.4x", 0, "\n",0,ip++,1);
\r
1189 if(ip&7) fseek(AsmFile, -1, SEEK_CUR); // remove last comma
\r
1191 for(i = 8-(ip&7); i > 0; i--)
\r
1196 for(i = (0x2000-ip/2)/8+1; i > 0; i--)
\r
1197 ot(" dcd 0,0,0,0,0,0,0,0\n");
\r
1199 ot(" .rept 0x%x\n .long 0,0,0,0,0,0,0,0\n .endr\n", (0x2000-ip/2)/8+1);
\r
1204 ot("CycloneJumpTab%s\n", ms?"":":");
\r
1205 len=0xfffe; // Hmmm, armasm 2.50.8684 messes up with a 0x10000 long jump table
\r
1206 // notaz: same thing with GNU as 2.9-psion-98r2 (reloc overflow)
\r
1207 // this is due to COFF objects using only 2 bytes for reloc count
\r
1209 for (i=0;i<len;i++)
\r
1213 if(op>=0) ott("Op%.4x",op," ;@ %.4x\n",i-7,i,2);
\r
1214 else if(op==-2) ott("Op__al",0, " ;@ %.4x\n",i-7,i,2);
\r
1215 else if(op==-3) ott("Op__fl",0, " ;@ %.4x\n",i-7,i,2);
\r
1216 else ott("Op____",0, " ;@ %.4x\n",i-7,i,2);
\r
1218 if(i&7) fseek(AsmFile, -1, SEEK_CUR); // remove last comma
\r
1221 ot(";@ notaz: we don't want to crash if we run into those 2 missing opcodes\n");
\r
1222 ot(";@ so we leave this pattern to patch it later\n");
\r
1223 ot("%s 0x78563412\n", ms?" dcd":" .long");
\r
1224 ot("%s 0x56341290\n", ms?" dcd":" .long");
\r
1228 static int CycloneMake()
\r
1231 const char *name="Cyclone.s";
\r
1232 const char *globl=ms?"export":".global";
\r
1234 // Open the assembly file
\r
1235 if (ms) name="Cyclone.asm";
\r
1236 AsmFile=fopen(name,"wt"); if (AsmFile==NULL) return 1;
\r
1238 printf("Making %s...\n",name);
\r
1240 ot("\n;@ Cyclone 68000 Emulator v%x.%.3x - Assembler Output\n\n",CycloneVer>>12,CycloneVer&0xfff);
\r
1242 ot(";@ Copyright (c) 2004,2011 FinalDave (emudave (at) gmail.com)\n");
\r
1243 ot(";@ Copyright (c) 2005-2011 Gražvydas \"notaz\" Ignotas (notasas (at) gmail.com)\n\n");
\r
1245 ot(";@ This code is licensed under the GNU General Public License version 2.0 and the MAME License.\n");
\r
1246 ot(";@ You can choose the license that has the most advantages for you.\n\n");
\r
1247 ot(";@ SVN repository can be found at http://code.google.com/p/cyclone68000/\n\n");
\r
1249 CyJump=(int *)malloc(0x40000); if (CyJump==NULL) return 1;
\r
1250 memset(CyJump,0xff,0x40000); // Init to -1
\r
1251 for(i=0xa000; i<0xb000; i++) CyJump[i] = -2; // a-line emulation
\r
1252 for(i=0xf000; i<0x10000; i++) CyJump[i] = -3; // f-line emulation
\r
1254 ot(ms?" area |.text|, code\n":" .text\n .align 4\n\n");
\r
1255 ot(" %s CycloneInit\n",globl);
\r
1256 ot(" %s CycloneReset\n",globl);
\r
1257 ot(" %s CycloneRun\n",globl);
\r
1258 ot(" %s CycloneSetSr\n",globl);
\r
1259 ot(" %s CycloneGetSr\n",globl);
\r
1260 ot(" %s CycloneFlushIrq\n",globl);
\r
1261 ot(" %s CyclonePack\n",globl);
\r
1262 ot(" %s CycloneUnpack\n",globl);
\r
1263 ot(" %s CycloneVer\n",globl);
\r
1264 #if (CYCLONE_FOR_GENESIS == 2)
\r
1265 ot(" %s CycloneSetRealTAS\n",globl);
\r
1266 ot(" %s CycloneDoInterrupt\n",globl);
\r
1267 ot(" %s CycloneDoTrace\n",globl);
\r
1268 ot(" %s CycloneJumpTab\n",globl);
\r
1269 ot(" %s Op____\n",globl);
\r
1270 ot(" %s Op6001\n",globl);
\r
1271 ot(" %s Op6601\n",globl);
\r
1272 ot(" %s Op6701\n",globl);
\r
1275 ot(ms?"CycloneVer dcd 0x":"CycloneVer: .long 0x");
\r
1276 ot("%.4x\n",CycloneVer);
\r
1282 printf("~%i ARM instructions used for opcode handlers\n", arm_op_count);
\r
1285 if (ms) ot(" END\n");
\r
1287 ot("\n\n;@ vim:filetype=armasm\n");
\r
1289 fclose(AsmFile); AsmFile=NULL;
\r
1292 printf("Assembling...\n");
\r
1293 // Assemble the file
\r
1294 if (ms) system("armasm Cyclone.asm");
\r
1295 else system("as -o Cyclone.o Cyclone.s");
\r
1296 printf("Done!\n\n");
\r
1305 printf("\n Cyclone 68000 Emulator v%x.%.3x - Core Creator\n\n",CycloneVer>>12,CycloneVer&0xfff);
\r
1307 // Make GAS or ARMASM version
\r