3 @ Memory I/O handlers for Sega/Mega CD emulation
4 @ (c) Copyright 2007, Grazvydas "notaz" Ignotas
8 .equiv PCM_STEP_SHIFT, 11
16 .macro mk_m68k_jump_table on sz @ operation name, size
17 .long m_m68k_&\on&\sz&_bios @ 0x000000 - 0x01ffff
18 .long m_m68k_&\on&\sz&_prgbank @ 0x020000 - 0x03ffff
19 .long m_&\on&_null, m_&\on&_null @ 0x040000 - 0x07ffff
20 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x080000 - 0x0fffff
21 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x100000 - 0x17ffff
22 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x180000 - 0x1fffff
23 .long m_m68k_&\on&\sz&_wordram0_2M @ 0x200000 - 0x21ffff
24 .long m_m68k_&\on&\sz&_wordram1_2M @ 0x220000 - 0x23ffff
25 .long m_&\on&_null, m_&\on&_null @ 0x240000 - 0x27ffff
26 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x280000 - 0x2fffff
27 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x300000
28 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0x3fffff
29 .long m_m68k_&\on&\sz&_bcram_size @ 0x400000
30 .long m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x420000
31 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0x4fffff
32 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x500000
33 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0x5fffff
34 .long m_m68k_&\on&\sz&_bcram @ 0x600000
35 .long m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x620000
36 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0x6fffff
37 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x700000
38 .long m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0x7dffff
39 .long m_m68k_&\on&\sz&_bcram_reg @ 0x7e0000
40 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x800000
41 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0x8fffff
42 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x900000
43 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0x9fffff
44 .long m_m68k_&\on&\sz&_system_io @ 0xa00000 - 0xa1ffff
45 .long m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0xa20000 - 0xa7ffff
46 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0xa80000 - 0xafffff
47 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0xb00000
48 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0xbfffff
49 .long m_m68k_&\on&\sz&_vdp, m_m68k_&\on&\sz&_vdp, m_m68k_&\on&\sz&_vdp, m_m68k_&\on&\sz&_vdp @ 0xc00000
50 .long m_m68k_&\on&\sz&_vdp, m_m68k_&\on&\sz&_vdp, m_m68k_&\on&\sz&_vdp, m_m68k_&\on&\sz&_vdp @ - 0xcfffff
51 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0xd00000
52 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0xdfffff
53 .long m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram @ 0xe00000
54 .long m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram @ - 0xefffff
55 .long m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram @ 0xf00000
56 .long m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram @ - 0xffffff
59 .macro mk_s68k_jump_table on sz @ operation name, size
60 .long m_s68k_&\on&\sz&_prg, m_s68k_&\on&\sz&_prg, m_s68k_&\on&\sz&_prg, m_s68k_&\on&\sz&_prg @ 0x000000 - 0x07ffff
61 .long m_s68k_&\on&\sz&_wordram_2M @ 0x080000 - 0x09ffff
62 .long m_s68k_&\on&\sz&_wordram_2M @ 0x0a0000 - 0x0bffff
63 .long m_&\on&_null @ 0x0c0000 - 0x0dffff, 1M area
64 .long m_&\on&_null @ 0x0e0000 - 0x0fffff
68 @ the jumptables themselves.
69 m_m68k_read8_table: mk_m68k_jump_table read 8
70 m_m68k_read16_table: mk_m68k_jump_table read 16
71 m_m68k_read32_table: mk_m68k_jump_table read 32
72 m_m68k_write8_table: mk_m68k_jump_table write 8
73 m_m68k_write16_table: mk_m68k_jump_table write 16
74 m_m68k_write32_table: mk_m68k_jump_table write 32
76 m_s68k_read8_table: mk_s68k_jump_table read 8
77 m_s68k_read16_table: mk_s68k_jump_table read 16
78 m_s68k_read32_table: mk_s68k_jump_table read 32
79 m_s68k_write8_table: mk_s68k_jump_table write 8
80 m_s68k_write16_table: mk_s68k_jump_table write 16
81 m_s68k_write32_table: mk_s68k_jump_table write 32
83 m_s68k_decode_write_table:
84 .long m_s68k_write8_2M_decode_b0_m0
85 .long m_s68k_write16_2M_decode_b0_m0
86 .long m_s68k_write32_2M_decode_b0_m0
87 .long m_s68k_write8_2M_decode_b0_m1
88 .long m_s68k_write16_2M_decode_b0_m1
89 .long m_s68k_write32_2M_decode_b0_m1
90 .long m_s68k_write8_2M_decode_b0_m2
91 .long m_s68k_write16_2M_decode_b0_m2
92 .long m_s68k_write32_2M_decode_b0_m2
93 .long m_s68k_write8_2M_decode_b1_m0
94 .long m_s68k_write16_2M_decode_b1_m0
95 .long m_s68k_write32_2M_decode_b1_m0
96 .long m_s68k_write8_2M_decode_b1_m1
97 .long m_s68k_write16_2M_decode_b1_m1
98 .long m_s68k_write32_2M_decode_b1_m1
99 .long m_s68k_write8_2M_decode_b1_m2
100 .long m_s68k_write16_2M_decode_b1_m2
101 .long m_s68k_write32_2M_decode_b1_m2
104 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
109 .global PicoMemResetCD
110 .global PicoMemResetCDdecode
111 .global PicoReadM68k8
112 .global PicoReadM68k16
113 .global PicoReadM68k32
114 .global PicoWriteM68k8
115 .global PicoWriteM68k16
116 .global PicoWriteM68k32
117 .global PicoReadS68k8
118 .global PicoReadS68k16
119 .global PicoReadS68k32
120 .global PicoWriteS68k8
121 .global PicoWriteS68k16
122 .global PicoWriteS68k32
124 @ externs, just for reference
128 .extern PicoVideoRead
129 .extern Read_CDC_Host
130 .extern m68k_reg_write8
134 .extern s68k_reg_read16
136 .extern gfx_cd_write16
137 .extern s68k_reg_write8
138 .extern s68k_poll_adclk
140 .extern s68k_poll_detect
142 .extern m_m68k_read8_misc
143 .extern m_m68k_write8_misc
146 @ r0=reg3, r1-r3=temp
147 .macro mk_update_table on sz @ operation name, size
148 @ we only set word-ram handlers
149 ldr r1, =m_m68k_&\on&\sz&_table
150 ldr r12,=m_s68k_&\on&\sz&_table
155 ldr r2, =m_m68k_&\on&\sz&_wordram0_2M
156 ldr r3, =m_s68k_&\on&\sz&_wordram_2M
159 ldr r2, =m_&\on&_null
170 ldr r2, =m_m68k_&\on&\sz&_wordram0_1M_b0
171 ldr r3, =m_m68k_&\on&\sz&_wordram1_1M_b0
174 ldr r3, =m_s68k_&\on&\sz&_wordram_1M_b1
176 ldr r2, =m_s68k_&\on&\sz&_wordram_2M_decode_b1
184 ldr r2, =m_m68k_&\on&\sz&_wordram0_1M_b1
185 ldr r3, =m_m68k_&\on&\sz&_wordram1_1M_b1
188 ldr r3, =m_s68k_&\on&\sz&_wordram_1M_b0
190 ldr r2, =m_s68k_&\on&\sz&_wordram_2M_decode_b0
201 mk_update_table read 8
202 mk_update_table read 16
203 mk_update_table read 32
204 mk_update_table write 8
205 mk_update_table write 16
206 mk_update_table write 32
210 PicoMemResetCDdecode: @reg3
212 bxeq lr @ we should not be called in 2M mode
213 ldr r1, =m_s68k_write8_table
214 ldr r3, =m_s68k_decode_write_table
218 moveq r2, #2 @ mode3 is same as mode2?
220 addeq r2, r2, #3 @ bank1 (r2=0..5)
221 add r2, r2, r2, lsl #1 @ *= 3
222 add r2, r3, r2, lsl #2
223 ldmia r2, {r0,r3,r12}
226 str r3, [r1, #4*4+8*4]
227 str r3, [r1, #5*4+8*4]
228 str r12,[r1, #4*4+8*4*2]
229 str r12,[r1, #5*4+8*4*2]
235 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
237 .macro mk_entry_m68k table
239 bic r0, r0, #0xff000000
240 and r3, r0, #0x00fe0000
241 ldr pc, [r2, r3, lsr #15]
244 PicoReadM68k8: @ u32 a
245 mk_entry_m68k m_m68k_read8_table
247 PicoReadM68k16: @ u32 a
248 mk_entry_m68k m_m68k_read16_table
250 PicoReadM68k32: @ u32 a
251 mk_entry_m68k m_m68k_read32_table
253 PicoWriteM68k8: @ u32 a, u8 d
254 mk_entry_m68k m_m68k_write8_table
256 PicoWriteM68k16: @ u32 a, u16 d
257 mk_entry_m68k m_m68k_write16_table
259 PicoWriteM68k32: @ u32 a, u32 d
260 mk_entry_m68k m_m68k_write32_table
263 .macro mk_entry_s68k on sz
264 bic r0, r0, #0xff000000
266 blt m_s68k_&\on&\sz&_prg
268 ldrlt r2, =m_s68k_&\on&\sz&_table
269 andlt r3, r0, #0x000e0000
270 ldrlt pc, [r2, r3, lsr #15]
272 orr r3, r3, #0x00008000
274 bge m_s68k_&\on&\sz&_regs
276 bge m_s68k_&\on&\sz&_pcm
278 bge m_s68k_&\on&\sz&_backup
283 PicoReadS68k8: @ u32 a
286 PicoReadS68k16: @ u32 a
287 mk_entry_s68k read 16
289 PicoReadS68k32: @ u32 a
290 mk_entry_s68k read 32
292 PicoWriteS68k8: @ u32 a, u8 d
293 mk_entry_s68k write 8
295 PicoWriteS68k16: @ u32 a, u16 d
296 mk_entry_s68k write 16
298 PicoWriteS68k32: @ u32 a, u32 d
299 mk_entry_s68k write 32
304 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
308 @ r0=addr[in,out], r1,r2=tmp
310 ands r1, r0, #0x01c000
311 ldrne pc, [pc, r1, lsr #12]
312 beq 0f @ most common?
322 and r1, r0, #0x7e00 @ col
323 and r2, r0, #0x01fc @ row
325 orr r1, r2, r1, ror #13
328 and r1, r0, #0x3f00 @ col
329 and r2, r0, #0x00fc @ row
331 orr r1, r2, r1, ror #12
334 and r1, r0, #0x1f80 @ col
335 and r2, r0, #0x007c @ row
336 orr r1, r2, r1, ror #11
338 orr r1, r1, r2, lsr #6
341 and r1, r0, #0xfc00 @ col
342 and r2, r0, #0x03fc @ row
343 orr r1, r2, r1, ror #14
346 orr r0, r0, r1, ror #26 @ rol 4+2
350 @ r0=prt1, r1=ptr2; unaligned ptr MUST be r0
356 moveq r0, r0, ror #16
357 orrne r0, r1, r0, lsl #16
361 @ r0=prt1, r1=data, r2=ptr2; unaligned ptr MUST be r0
366 movne r1, r1, lsr #16
372 .macro bcram_reg_rw is_read addr_check
373 rsb r0, r0, #0x800000
374 ldr r2, =(Pico+0x22200)
375 cmp r0, #(0x800000-\addr_check)
381 add r2, r2, #0x110000
382 add r2, r2, #0x002200
391 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
400 ldr r1, =(Pico+0x22200)
401 bic r0, r0, #0xfe0000
408 m_m68k_read8_prgbank:
409 ldr r1, =(Pico+0x22200)
413 orr r3, r2, #0x002200
416 and r3, r3, #0x00030000
417 cmp r3, #0x00010000 @ have bus or in reset state?
420 and r2, r2, #0xc0000000 @ r3 & 0xC0
421 add r1, r1, r2, lsr #12
426 m_m68k_read8_wordram0_2M: @ 0x200000 - 0x21ffff
427 m_m68k_read8_wordram1_2M: @ 0x220000 - 0x23ffff
428 ldr r1, =(Pico+0x22200)
429 sub r0, r0, #0x160000 @ map to our offset, which is 0x0a0000
436 m_m68k_read8_wordram0_1M_b0: @ 0x200000 - 0x21ffff
437 ldr r1, =(Pico+0x22200)
438 sub r0, r0, #0x140000 @ map to our offset, which is 0x0c0000
445 m_m68k_read8_wordram0_1M_b1: @ 0x200000 - 0x21ffff
446 ldr r1, =(Pico+0x22200)
447 sub r0, r0, #0x120000 @ map to our offset, which is 0x0e0000
454 m_m68k_read8_wordram1_1M_b0: @ 0x220000 - 0x23ffff, cell arranged
456 ldr r1, =(Pico+0x22200)
457 add r0, r0, #0x0c0000
464 m_m68k_read8_wordram1_1M_b1: @ 0x220000 - 0x23ffff, cell arranged
466 ldr r1, =(Pico+0x22200)
467 add r0, r0, #0x0e0000
474 m_m68k_read8_bcram_size: @ 0x400000
482 movne r0, #3 @ pretend to be a 64k cart (8<<3)
486 m_m68k_read8_bcram: @ 0x600000 - 0x61ffff
488 bic r0, r0, #0xfe0000
499 m_m68k_read8_bcram_reg: @ 0x7fffff
500 bcram_reg_rw 1, 0x7fffff
503 m_m68k_read8_system_io:
504 bic r2, r0, #0xfe0000
507 bne m_m68k_read8_misc @ now from Pico/Memory.s
509 ldr r1, =(Pico+0x22200)
511 ldr r1, [r1] @ Pico.mcd (used everywhere)
513 ldrlt pc, [pc, r0, lsl #2]
515 .long m_m68k_read8_r00
516 .long m_m68k_read8_r01
517 .long m_m68k_read8_r02
518 .long m_m68k_read8_r03
519 .long m_m68k_read8_r04
520 .long m_read_null @ unused bits
521 .long m_m68k_read8_r06
522 .long m_m68k_read8_r07
523 .long m_m68k_read8_r08
524 .long m_m68k_read8_r09
525 .long m_read_null @ reserved
527 .long m_m68k_read8_r0c
528 .long m_m68k_read8_r0d
530 add r1, r1, #0x110000
532 and r0, r0, #0x04000000 @ we need irq2 mask state
536 add r1, r1, #0x110000
537 add r1, r1, #0x002200
538 ldrb r0, [r1, #2] @ Pico_mcd->m.busreq
541 add r1, r1, #0x110000
545 add r1, r1, #0x110000
547 add r1, r1, #0x002200
550 tst r1, #2 @ DMNA pending?
556 add r1, r1, #0x110000
560 ldrb r0, [r1, #0x73] @ IRQ vector
567 bl Read_CDC_Host @ TODO: make it local
574 add r1, r1, #0x110000
575 add r1, r1, #0x002200
576 ldr r0, [r1, #0x14] @ Pico_mcd->m.timer_stopwatch
580 add r1, r1, #0x110000
581 add r1, r1, #0x002200
589 add r1, r1, #0x110000
597 cmp r2, #0xa00000 @ Z80 RAM?
599 @ ldreq r2, =z80Read8
604 bl OtherRead16 @ non-MCD version should be ok too
614 bxne lr @ invalid read
617 bl PicoVideoRead @ TODO: implement it in asm
626 bic r0, r0, #0xff0000
632 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
636 ldr r1, =(Pico+0x22200)
637 bic r0, r0, #0xfe0000
644 m_m68k_read16_prgbank:
645 ldr r1, =(Pico+0x22200)
649 orr r3, r2, #0x002200
652 and r3, r3, #0x00030000
653 cmp r3, #0x00010000 @ have bus or in reset state?
656 and r2, r2, #0xc0000000 @ r3 & 0xC0
657 add r1, r1, r2, lsr #12
662 m_m68k_read16_wordram0_2M: @ 0x200000 - 0x21ffff
663 m_m68k_read16_wordram1_2M: @ 0x220000 - 0x23ffff
664 ldr r1, =(Pico+0x22200)
665 sub r0, r0, #0x160000 @ map to our offset, which is 0x0a0000
672 m_m68k_read16_wordram0_1M_b0: @ 0x200000 - 0x21ffff
673 ldr r1, =(Pico+0x22200)
674 sub r0, r0, #0x140000 @ map to our offset, which is 0x0c0000
681 m_m68k_read16_wordram0_1M_b1: @ 0x200000 - 0x21ffff
682 ldr r1, =(Pico+0x22200)
683 sub r0, r0, #0x120000 @ map to our offset, which is 0x0e0000
690 m_m68k_read16_wordram1_1M_b0: @ 0x220000 - 0x23ffff, cell arranged
691 @ Warning: read32 relies on NOT using r3 and r12 here
693 ldr r1, =(Pico+0x22200)
694 add r0, r0, #0x0c0000
701 m_m68k_read16_wordram1_1M_b1: @ 0x220000 - 0x23ffff, cell arranged
703 ldr r1, =(Pico+0x22200)
704 add r0, r0, #0x0e0000
711 m_m68k_read16_bcram_size: @ 0x400000
718 movne r0, #3 @ pretend to be a 64k cart
722 @ m_m68k_read16_bcram: @ 0x600000 - 0x61ffff
723 .equiv m_m68k_read16_bcram, m_m68k_read8_bcram
726 m_m68k_read16_bcram_reg: @ 0x7fffff
727 bcram_reg_rw 1, 0x7ffffe
730 m_m68k_read16_system_io:
731 bic r1, r0, #0xfe0000
734 bne m_m68k_read16_misc
736 m_m68k_read16_m68k_regs:
737 ldr r1, =(Pico+0x22200)
739 ldr r1, [r1] @ Pico.mcd (used everywhere)
741 ldrlt pc, [pc, r0, lsl #1]
743 .long m_m68k_read16_r00
744 .long m_m68k_read16_r02
745 .long m_m68k_read16_r04
746 .long m_m68k_read16_r06
747 .long m_m68k_read16_r08
748 .long m_read_null @ reserved
749 .long m_m68k_read16_r0c
751 add r1, r1, #0x110000
753 add r1, r1, #0x002200
754 ldrb r1, [r1, #2] @ Pico_mcd->m.busreq
755 and r0, r0, #0x04000000 @ we need irq2 mask state
756 orr r0, r1, r0, lsr #11
759 add r1, r1, #0x110000
762 add r1, r1, #0x002200
765 orr r0, r2, r0, lsl #8
766 tst r1, #2 @ DMNA pending?
772 add r1, r1, #0x110000
777 ldrh r0, [r1, #0x72] @ IRQ vector
783 add r1, r1, #0x110000
784 add r1, r1, #0x002200
790 addlt r1, r1, #0x110000
796 orr r0, r0, r1, lsl #8
809 bxne lr @ invalid read
816 bic r0, r0, #0xff0000
822 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
826 ldr r1, =(Pico+0x22200)
827 bic r0, r0, #0xfe0000
834 m_m68k_read32_prgbank:
835 ldr r1, =(Pico+0x22200)
839 orr r3, r2, #0x002200
842 and r3, r3, #0x00030000
843 cmp r3, #0x00010000 @ have bus or in reset state?
846 and r2, r2, #0xc0000000 @ r3 & 0xC0
847 add r1, r1, r2, lsr #12
852 m_m68k_read32_wordram0_2M: @ 0x200000 - 0x21ffff
853 m_m68k_read32_wordram1_2M: @ 0x220000 - 0x23ffff
854 ldr r1, =(Pico+0x22200)
855 sub r0, r0, #0x160000 @ map to our offset, which is 0x0a0000
862 m_m68k_read32_wordram0_1M_b0: @ 0x200000 - 0x21ffff
863 ldr r1, =(Pico+0x22200)
864 sub r0, r0, #0x140000 @ map to our offset, which is 0x0c0000
871 m_m68k_read32_wordram0_1M_b1: @ 0x200000 - 0x21ffff
872 ldr r1, =(Pico+0x22200)
873 sub r0, r0, #0x120000 @ map to our offset, which is 0x0e0000
880 m_m68k_read32_wordram1_1M_b0: @ 0x220000 - 0x23ffff, cell arranged
882 bne m_m68k_read32_wordram1_1M_b0_unal
884 ldr r1, =(Pico+0x22200)
885 add r0, r0, #0x0c0000
890 m_m68k_read32_wordram1_1M_b0_unal:
891 @ hopefully this doesn't happen too often
894 bl m_m68k_read16_wordram1_1M_b0 @ must not trash r12 and r3
898 bl m_m68k_read16_wordram1_1M_b0
899 orr r0, r0, r3, lsl #16
903 m_m68k_read32_wordram1_1M_b1: @ 0x220000 - 0x23ffff, cell arranged
905 bne m_m68k_read32_wordram1_1M_b1_unal
907 ldr r1, =(Pico+0x22200)
908 add r0, r0, #0x0e0000
913 m_m68k_read32_wordram1_1M_b1_unal:
916 bl m_m68k_read16_wordram1_1M_b1 @ must not trash r12 and r3
920 bl m_m68k_read16_wordram1_1M_b1
921 orr r0, r0, r3, lsl #16
925 m_m68k_read32_bcram_size: @ 0x400000
932 movne r0, #0x30000 @ pretend to be a 64k cart
936 m_m68k_read32_bcram: @ 0x600000 - 0x61ffff, not likely to be called
939 bl m_m68k_read8_bcram
943 bl m_m68k_read8_bcram
944 orr r0, r0, r3, lsl #16
948 m_m68k_read32_bcram_reg: @ 0x7fffff
949 bcram_reg_rw 1, 0x7ffffc
952 @ it is not very practical to use long access on hw registers, so I assume it is not used too much.
953 m_m68k_read32_system_io:
954 bic r1, r0, #0xfe0000
957 bne m_m68k_read32_misc
960 blt m_m68k_read32_misc
964 @ I have seen the range 0x0e-0x2f accessed quite frequently with long i/o, so here is some code for that
966 ldr r1, =(Pico+0x22200)
969 orr r2, r2, r2, lsl #16
970 add r1, r1, #0x110000
972 and r1, r2, r0 @ data is big-endian read as little, have to byteswap
973 and r0, r2, r0, lsr #8
974 orr r0, r0, r1, lsl #8
980 bl m_m68k_read16_system_io
982 bl m_m68k_read16_system_io
984 orr r0, r0, r1, lsl #16
991 bxne lr @ invalid read
999 orr r0, r0, r1, lsl #16
1005 bic r0, r0, #0xff0000
1012 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1017 m_m68k_write8_bcram_size: @ 0x400000
1021 m_m68k_write8_prgbank:
1022 ldr r2, =(Pico+0x22200)
1026 orr r3, r12, #0x002200
1029 and r3, r3, #0x00030000
1030 cmp r3, #0x00010000 @ have bus or in reset state?
1032 and r12,r12,#0xc0000000 @ r3 & 0xC0
1033 add r2, r2, r12, lsr #12
1038 m_m68k_write8_wordram0_2M: @ 0x200000 - 0x21ffff
1039 m_m68k_write8_wordram1_2M: @ 0x220000 - 0x23ffff
1040 ldr r2, =(Pico+0x22200)
1041 sub r0, r0, #0x160000 @ map to our offset, which is 0x0a0000
1048 m_m68k_write8_wordram0_1M_b0: @ 0x200000 - 0x21ffff
1049 ldr r2, =(Pico+0x22200)
1050 sub r0, r0, #0x140000 @ map to our offset, which is 0x0c0000
1057 m_m68k_write8_wordram0_1M_b1: @ 0x200000 - 0x21ffff
1058 ldr r2, =(Pico+0x22200)
1059 sub r0, r0, #0x120000 @ map to our offset, which is 0x0e0000
1066 m_m68k_write8_wordram1_1M_b0: @ 0x220000 - 0x23ffff, cell arranged
1069 ldr r2, =(Pico+0x22200)
1070 add r0, r0, #0x0c0000
1077 m_m68k_write8_wordram1_1M_b1: @ 0x220000 - 0x23ffff, cell arranged
1080 ldr r2, =(Pico+0x22200)
1081 add r0, r0, #0x0e0000
1088 m_m68k_write8_bcram: @ 0x600000 - 0x61ffff
1089 @ can't use r3 or r12, because of write32
1091 bic r0, r0, #0xfe0000
1095 add r0, r2, r0, lsr #1
1096 ldr r2, =(Pico+0x22200)
1099 add r2, r2, #0x110000
1100 add r2, r2, #0x002200
1102 tst r2, #1 @ check bcram reg
1107 strb r0, [r2, #0x0e] @ SRam.changed = 1
1111 m_m68k_write8_bcram_reg: @ 0x7fffff
1112 bcram_reg_rw 0, 0x7fffff
1115 m_m68k_write8_system_io:
1116 bic r2, r0, #0xfe0000
1122 b m_m68k_write8_misc
1134 orr r1, r1, r1, lsl #8 @ byte access gets mirrored
1140 bic r0, r0, #0xff0000
1146 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1149 m_m68k_write16_bios:
1150 m_m68k_write16_bcram_size: @ 0x400000
1154 m_m68k_write16_prgbank:
1155 ldr r2, =(Pico+0x22200)
1159 orr r3, r12, #0x002200
1162 and r3, r3, #0x00030000
1163 cmp r3, #0x00010000 @ have bus or in reset state?
1165 and r12,r12,#0xc0000000 @ r3 & 0xC0
1166 add r2, r2, r12, lsr #12
1171 m_m68k_write16_wordram0_2M: @ 0x200000 - 0x21ffff
1172 m_m68k_write16_wordram1_2M: @ 0x220000 - 0x23ffff
1173 ldr r2, =(Pico+0x22200)
1174 sub r0, r0, #0x160000 @ map to our offset, which is 0x0a0000
1181 m_m68k_write16_wordram0_1M_b0: @ 0x200000 - 0x21ffff
1182 ldr r2, =(Pico+0x22200)
1183 sub r0, r0, #0x140000 @ map to our offset, which is 0x0c0000
1190 m_m68k_write16_wordram0_1M_b1: @ 0x200000 - 0x21ffff
1191 ldr r2, =(Pico+0x22200)
1192 sub r0, r0, #0x120000 @ map to our offset, which is 0x0e0000
1199 m_m68k_write16_wordram1_1M_b0: @ 0x220000 - 0x23ffff, cell arranged
1200 @ Warning: write32 relies on NOT using r12 and and keeping data in r3
1203 ldr r1, =(Pico+0x22200)
1204 add r0, r0, #0x0c0000
1211 m_m68k_write16_wordram1_1M_b1: @ 0x220000 - 0x23ffff, cell arranged
1214 ldr r1, =(Pico+0x22200)
1215 add r0, r0, #0x0e0000
1222 @ m_m68k_write16_bcram: @ 0x600000 - 0x61ffff
1223 .equiv m_m68k_write16_bcram, m_m68k_write8_bcram
1226 m_m68k_write16_bcram_reg: @ 0x7fffff
1227 bcram_reg_rw 0, 0x7ffffe
1230 m_m68k_write16_system_io:
1232 bic r2, r0, #0xfe0000
1237 m_m68k_write16_regs:
1240 beq m_m68k_write16_regs_spec
1243 stmfd sp!,{r2,r3,lr}
1246 ldmfd sp!,{r0,r1,lr}
1249 m_m68k_write16_regs_spec: @ special case
1250 ldr r2, =(Pico+0x22200)
1251 ldr r3, =s68k_poll_adclk
1254 add r0, r0, #0x00000e
1256 strb r1, [r2, r0] @ if (a == 0xe) s68k_regs[0x0e] = d >> 8;
1262 ldr r0, =PicoCpuCS68k
1263 str r1, [r0, #0x58] @ push s68k out of stopped state
1277 b SN76496Write @ lsb goes to 0x11
1282 bic r0, r0, #0xff0000
1288 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1291 m_m68k_write32_bios:
1292 m_m68k_write32_bcram_size: @ 0x400000
1296 m_m68k_write32_prgbank:
1297 ldr r2, =(Pico+0x22200)
1301 orr r3, r12, #0x002200
1304 and r3, r3, #0x00030000
1305 cmp r3, #0x00010000 @ have bus or in reset state?
1307 and r12,r12,#0xc0000000 @ r3 & 0xC0
1308 add r2, r2, r12, lsr #12
1313 m_m68k_write32_wordram0_2M: @ 0x200000 - 0x21ffff
1314 m_m68k_write32_wordram1_2M: @ 0x220000 - 0x23ffff
1315 ldr r2, =(Pico+0x22200)
1316 sub r0, r0, #0x160000 @ map to our offset, which is 0x0a0000
1323 m_m68k_write32_wordram0_1M_b0: @ 0x200000 - 0x21ffff
1324 ldr r2, =(Pico+0x22200)
1325 sub r0, r0, #0x140000 @ map to our offset, which is 0x0c0000
1332 m_m68k_write32_wordram0_1M_b1: @ 0x200000 - 0x21ffff
1333 ldr r2, =(Pico+0x22200)
1334 sub r0, r0, #0x120000 @ map to our offset, which is 0x0e0000
1341 m_m68k_write32_wordram1_1M_b0: @ 0x220000 - 0x23ffff, cell arranged
1343 bne m_m68k_write32_wordram1_1M_b0_unal
1346 ldr r2, =(Pico+0x22200)
1347 add r0, r0, #0x0c0000
1353 m_m68k_write32_wordram1_1M_b0_unal:
1354 @ hopefully this doesn't happen too often
1358 bl m_m68k_write16_wordram1_1M_b0 @ must not trash r12 and keep data in r3
1362 b m_m68k_write16_wordram1_1M_b0
1365 m_m68k_write32_wordram1_1M_b1: @ 0x220000 - 0x23ffff, cell arranged
1367 bne m_m68k_write32_wordram1_1M_b1_unal
1370 ldr r2, =(Pico+0x22200)
1371 add r0, r0, #0x0e0000
1377 m_m68k_write32_wordram1_1M_b1_unal:
1381 bl m_m68k_write16_wordram1_1M_b1 @ same as above
1385 b m_m68k_write16_wordram1_1M_b1
1388 m_m68k_write32_bcram: @ 0x600000 - 0x61ffff, not likely to be called
1392 bl m_m68k_write8_bcram
1395 bl m_m68k_write8_bcram
1399 m_m68k_write32_bcram_reg: @ 0x7fffff
1400 bcram_reg_rw 0, 0x7ffffc
1404 @ it is not very practical to use long access on hw registers, so I assume it is not used too much.
1405 m_m68k_write32_system_io:
1406 bic r2, r0, #0xfe0000
1409 bne m_m68k_write32_misc
1414 bge m_m68k_write32_regs_comm
1416 bge m_m68k_write32_regs_spec @ hits the nasty comm reg qiurk
1419 stmfd sp!,{r0,r1,lr}
1432 ldmfd sp!,{r0,r1,lr}
1436 m_m68k_write32_regs_comm: @ Handle the 0x10-0x1f range
1437 ldr r0, =(Pico+0x22200)
1440 orr r3, r3, r3, lsl #16
1441 add r0, r0, #0x110000
1442 and r12,r3, r1, ror #16 @ data is big-endian to be written as little, have to byteswap
1443 and r1, r3, r1, ror #24
1444 orr r1, r1, r12,lsl #8 @ end of byteswap
1447 ldr r3, =s68k_poll_adclk
1449 movne r1, r1, lsr #16
1453 ldr r0, =PicoCpuCS68k @ remove poll detected state for s68k
1459 m_m68k_write32_misc:
1461 stmfd sp!,{r0,r1,lr}
1464 ldmfd sp!,{r0,r1,lr}
1468 m_m68k_write32_regs_spec:
1470 stmfd sp!,{r0,r1,lr}
1472 bl m_m68k_write16_regs
1473 ldmfd sp!,{r0,r1,lr}
1475 b m_m68k_write16_regs
1484 moveq r0, r1, lsr #16
1485 beq SN76496Write @ which game is crazy enough to do that?
1486 stmfd sp!,{r0,r1,lr}
1489 ldmfd sp!,{r0,r1,lr}
1496 bic r0, r0, #0xff0000
1504 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1506 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1509 .macro m_s68k_read8_ram map_addr
1510 ldr r1, =(Pico+0x22200)
1514 add r0, r0, #\map_addr @ map to our address
1520 .macro m_s68k_read8_wordram_2M_decode map_addr
1521 ldr r2, =(Pico+0x22200)
1524 movs r0, r0, lsr #1 @ +4-6 <<16
1525 add r2, r2, #\map_addr @ map to our address
1527 movcc r0, r0, lsr #4
1533 m_s68k_read8_prg: @ 0x000000 - 0x07ffff
1534 m_s68k_read8_wordram_2M: @ 0x080000 - 0x0bffff
1535 m_s68k_read8_wordram_1M_b1: @ 0x0c0000 - 0x0dffff, maps to 0x0e0000
1536 m_s68k_read8_ram 0x020000
1539 m_s68k_read8_wordram_2M_decode_b0: @ 0x080000 - 0x0bffff
1540 m_s68k_read8_wordram_2M_decode 0x080000 @ + ^ / 2
1543 m_s68k_read8_wordram_2M_decode_b1: @ 0x080000 - 0x0bffff
1544 m_s68k_read8_wordram_2M_decode 0x0a0000 @ + ^ / 2
1547 m_s68k_read8_wordram_1M_b0: @ 0x0c0000 - 0x0dffff (same as our offset :)
1551 m_s68k_read8_backup: @ 0xfe0000 - 0xfe3fff (repeated?)
1552 @ must not trash r3 and r12
1553 ldr r1, =(Pico+0x22200)
1556 bic r0, r0, #0xff0000
1557 bic r0, r0, #0x00e000
1558 add r1, r1, #0x110000
1559 add r1, r1, #0x000200
1565 @ must not trash r3 and r12
1566 ldr r1, =(Pico+0x22200)
1567 bic r0, r0, #0xff0000
1568 @ bic r0, r0, #0x008000
1571 orr r2, r2, #0x002200
1573 bge m_s68k_read8_pcm_ram
1577 orr r2, r2, #(0x48+8) @ pcm.ch + addr_offset
1580 ldr r1, [r1, r2, lsl #2]
1582 moveq r0, r1, lsr #PCM_STEP_SHIFT
1583 movne r0, r1, lsr #(PCM_STEP_SHIFT+8)
1587 m_s68k_read8_pcm_ram:
1590 add r1, r1, #0x100000 @ pcm_ram
1591 and r2, r2, #0x0f000000 @ bank
1592 add r1, r1, r2, lsr #12
1593 bic r0, r0, #0x00e000
1600 bic r0, r0, #0xff0000
1601 bic r0, r0, #0x008000
1606 cmp r2, #(0x30-0x0e)
1607 blo m_s68k_read8_comm
1610 ldrlo r2, =gfx_cd_read
1611 ldrhs r2, =s68k_reg_read16
1618 moveq r0, r0, lsr #8
1623 ldr r1, =(Pico+0x22200)
1625 add r1, r1, #0x110000
1630 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1633 .macro m_s68k_read16_ram map_addr
1634 ldr r1, =(Pico+0x22200)
1638 add r0, r0, #\map_addr @ map to our address
1644 .macro m_s68k_read16_wordram_2M_decode map_addr
1645 ldr r2, =(Pico+0x22200)
1648 mov r0, r0, lsr #1 @ +4-6 <<16
1649 add r2, r2, #\map_addr @ map to our address
1651 orr r0, r0, r0, lsl #4
1657 m_s68k_read16_prg: @ 0x000000 - 0x07ffff
1658 m_s68k_read16_wordram_2M: @ 0x080000 - 0x0bffff
1659 m_s68k_read16_wordram_1M_b1: @ 0x0c0000 - 0x0dffff, maps to 0x0e0000
1660 m_s68k_read16_ram 0x020000
1663 m_s68k_read16_wordram_2M_decode_b0: @ 0x080000 - 0x0bffff
1664 m_s68k_read16_wordram_2M_decode 0x080000
1667 m_s68k_read16_wordram_2M_decode_b1: @ 0x080000 - 0x0bffff
1668 m_s68k_read16_wordram_2M_decode 0x0a0000
1671 m_s68k_read16_wordram_1M_b0: @ 0x0c0000 - 0x0dffff (same as our offset :)
1675 @ m_s68k_read16_backup: @ 0xfe0000 - 0xfe3fff (repeated?)
1676 @ bram is not meant to be accessed by words, does any game do this?
1677 .equiv m_s68k_read16_backup, m_s68k_read8_backup
1680 @ m_s68k_read16_pcm:
1681 @ pcm is on 8-bit bus, would this be same as byte access?
1682 .equiv m_s68k_read16_pcm, m_s68k_read8_pcm
1686 bic r0, r0, #0xff0000
1687 bic r0, r0, #0x008000
1688 bic r0, r0, #0x000001
1701 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1704 .macro m_s68k_read32_ram map_addr
1705 ldr r1, =(Pico+0x22200)
1709 add r0, r0, #\map_addr @ map to our address
1715 .macro m_s68k_read32_wordram_2M_decode map_addr
1716 ldr r2, =(Pico+0x22200)
1719 mov r0, r0, lsr #1 @ +4-6 <<16
1720 add r2, r2, #\map_addr @ map to our address
1723 ldrneb r0, [r2, #-1]
1725 orr r1, r1, r1, lsl #4
1727 orr r0, r0, r0, lsl #4
1729 orr r0, r0, r1, lsl #16
1734 m_s68k_read32_prg: @ 0x000000 - 0x07ffff
1735 m_s68k_read32_wordram_2M: @ 0x080000 - 0x0bffff
1736 m_s68k_read32_wordram_1M_b1: @ 0x0c0000 - 0x0dffff, maps to 0x0e0000
1737 m_s68k_read32_ram 0x020000
1740 m_s68k_read32_wordram_2M_decode_b0: @ 0x080000 - 0x0bffff
1741 m_s68k_read32_wordram_2M_decode 0x080000
1744 m_s68k_read32_wordram_2M_decode_b1: @ 0x080000 - 0x0bffff
1745 m_s68k_read32_wordram_2M_decode 0x0a0000
1748 m_s68k_read32_wordram_1M_b0: @ 0x0c0000 - 0x0dffff (same as our offset :)
1752 m_s68k_read32_backup: @ 0xfe0000 - 0xfe3fff (repeated?)
1753 @ bram is not meant to be accessed by words, does any game do this?
1756 bl m_s68k_read8_backup @ must preserve r3 and r12
1760 bl m_s68k_read8_backup
1761 orr r0, r0, r3, lsl #16
1768 bl m_s68k_read8_pcm @ must preserve r3 and r12
1773 orr r0, r0, r3, lsl #16
1778 bic r0, r0, #0xff0000
1779 bic r0, r0, #0x008000
1780 bic r0, r0, #0x000001
1787 blo m_s68k_read32_regs_gfx
1793 orr r0, r0, r1, lsl #16
1797 m_s68k_read32_regs_gfx:
1803 orr r0, r0, r1, lsl #16
1808 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1811 .macro m_s68k_write8_ram map_addr
1812 ldr r2, =(Pico+0x22200)
1816 add r0, r0, #\map_addr @ map to our address
1822 .macro m_s68k_write8_2M_decode map_addr
1823 ldr r2, =(Pico+0x22200)
1826 movs r0, r0, lsr #1 @ +4-6 <<16
1827 add r2, r2, #\map_addr @ map to our address
1830 .macro m_s68k_write8_2M_decode_m0 map_addr @ mode off
1831 m_s68k_write8_2M_decode \map_addr
1834 movcc r1, r1, lsl #4
1838 cmp r0, r3 @ avoid writing if result is same
1843 .macro m_s68k_write8_2M_decode_m1 map_addr @ mode underwrite
1846 m_s68k_write8_2M_decode \map_addr
1848 movcc r1, r1, lsl #4
1859 .macro m_s68k_write8_2M_decode_m2 map_addr @ mode overwrite
1862 m_s68k_write8_2M_decode_m0 \map_addr @ same as in off mode
1867 m_s68k_write8_prg: @ 0x000000 - 0x07ffff
1868 ldr r2, =(Pico+0x22200)
1871 add r3, r0, #0x020000 @ map to our address
1872 add r12,r2, #0x110000
1874 and r12,r12,#0x00ff0000 @ wp
1880 m_s68k_write8_wordram_2M: @ 0x080000 - 0x0bffff
1881 m_s68k_write8_wordram_1M_b1: @ 0x0c0000 - 0x0dffff, maps to 0x0e0000
1882 m_s68k_write8_ram 0x020000
1885 m_s68k_write8_2M_decode_b0_m0: @ 0x080000 - 0x0bffff
1886 m_s68k_write8_2M_decode_m0 0x080000
1888 m_s68k_write8_2M_decode_b0_m1:
1889 m_s68k_write8_2M_decode_m1 0x080000
1891 m_s68k_write8_2M_decode_b0_m2:
1892 m_s68k_write8_2M_decode_m2 0x080000
1894 m_s68k_write8_2M_decode_b1_m0:
1895 m_s68k_write8_2M_decode_m0 0x0a0000
1897 m_s68k_write8_2M_decode_b1_m1:
1898 m_s68k_write8_2M_decode_m1 0x0a0000
1900 m_s68k_write8_2M_decode_b1_m2:
1901 m_s68k_write8_2M_decode_m2 0x0a0000
1904 m_s68k_write8_wordram_1M_b0: @ 0x0c0000 - 0x0dffff (same as our offset :)
1908 m_s68k_write8_backup: @ 0xfe0000 - 0xfe3fff (repeated?)
1909 @ must not trash r3 and r12
1910 ldr r2, =(Pico+0x22200)
1913 bic r0, r0, #0xff0000
1914 bic r0, r0, #0x00e000
1915 add r2, r2, #0x110000
1916 add r2, r2, #0x000200
1920 strb r0, [r1, #0x0e] @ SRam.changed = 1
1925 bic r0, r0, #0xff0000
1927 movlt r0, r0, lsr #1
1933 m_s68k_write8_pcm_ram:
1934 ldr r3, =(Pico+0x22200)
1935 bic r0, r0, #0x00e000
1938 add r2, r3, #0x110000
1939 add r2, r2, #0x002200
1940 add r2, r2, #0x000040
1942 add r3, r3, #0x100000 @ pcm_ram
1943 and r2, r2, #0x0f000000 @ bank
1944 add r3, r3, r2, lsr #12
1950 bic r0, r0, #0xff0000
1951 bic r0, r0, #0x008000
1959 orr r1, r1, r1, lsl #8
1963 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1966 .macro m_s68k_write16_ram map_addr
1967 ldr r2, =(Pico+0x22200)
1971 add r0, r0, #\map_addr @ map to our address
1977 .macro m_s68k_write16_2M_decode map_addr
1978 ldr r2, =(Pico+0x22200)
1981 mov r0, r0, lsr #1 @ +4-6 <<16
1982 add r2, r2, #\map_addr @ map to our address
1985 .macro m_s68k_write16_2M_decode_m0 map_addr @ mode off
1986 m_s68k_write16_2M_decode \map_addr
1988 orr r1, r1, r1, lsr #4
1993 .macro m_s68k_write16_2M_decode_m1 map_addr @ mode underwrite
1994 bics r1, r1, #0xf000
1995 bicnes r1, r1, #0x00f0
1997 orr r1, r1, r1, lsr #4
1998 m_s68k_write16_2M_decode \map_addr
2010 .macro m_s68k_write16_2M_decode_m2 map_addr @ mode overwrite
2011 bics r1, r1, #0xf000
2012 bicnes r1, r1, #0x00f0
2014 orr r1, r1, r1, lsr #4
2015 m_s68k_write16_2M_decode \map_addr
2029 m_s68k_write16_prg: @ 0x000000 - 0x07ffff
2030 ldr r2, =(Pico+0x22200)
2033 add r3, r0, #0x020000 @ map to our address
2034 add r12,r2, #0x110000
2036 and r12,r12,#0x00ff0000 @ wp
2042 m_s68k_write16_wordram_2M: @ 0x080000 - 0x0bffff
2043 m_s68k_write16_wordram_1M_b1: @ 0x0c0000 - 0x0dffff, maps to 0x0e0000
2044 m_s68k_write16_ram 0x020000
2047 m_s68k_write16_2M_decode_b0_m0: @ 0x080000 - 0x0bffff
2048 m_s68k_write16_2M_decode_m0 0x080000
2050 m_s68k_write16_2M_decode_b0_m1:
2051 m_s68k_write16_2M_decode_m1 0x080000
2053 m_s68k_write16_2M_decode_b0_m2:
2054 m_s68k_write16_2M_decode_m2 0x080000
2056 m_s68k_write16_2M_decode_b1_m0:
2057 m_s68k_write16_2M_decode_m0 0x0a0000
2059 m_s68k_write16_2M_decode_b1_m1:
2060 m_s68k_write16_2M_decode_m1 0x0a0000
2062 m_s68k_write16_2M_decode_b1_m2:
2063 m_s68k_write16_2M_decode_m2 0x0a0000
2066 m_s68k_write16_wordram_1M_b0: @ 0x0c0000 - 0x0dffff (same as our offset :)
2067 m_s68k_write16_ram 0
2070 @ m_s68k_write16_backup:
2071 .equiv m_s68k_write16_backup, m_s68k_write8_backup
2074 @ m_s68k_write16_pcm:
2075 .equiv m_s68k_write16_pcm, m_s68k_write8_pcm
2078 m_s68k_write16_regs:
2079 bic r0, r0, #0xff0000
2080 bic r0, r0, #0x008000
2086 beq m_s68k_write16_regs_spec
2092 stmfd sp!,{r2,r3,lr}
2095 ldmfd sp!,{r0,r1,lr}
2098 m_s68k_write16_regs_spec: @ special case
2099 ldr r2, =(Pico+0x22200)
2102 add r0, r0, #0x00000f
2103 strb r1, [r2, r0] @ if (a == 0xe) s68k_regs[0xf] = d;
2107 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
2110 .macro m_s68k_write32_ram map_addr
2111 ldr r2, =(Pico+0x22200)
2115 add r0, r0, #\map_addr @ map to our address
2121 .macro m_s68k_write32_2M_decode map_addr
2122 ldr r2, =(Pico+0x22200)
2125 mov r0, r0, lsr #1 @ +4-6 <<16
2126 add r2, r2, #\map_addr @ map to our address
2129 .macro m_s68k_write32_2M_decode_m0 map_addr @ mode off
2130 m_s68k_write32_2M_decode \map_addr
2131 bic r1, r1, #0x000000f0
2132 bic r1, r1, #0x00f00000
2133 orr r1, r1, r1, lsr #4
2137 strneb r1, [r2, #-1]
2142 .macro m_s68k_write32_2M_decode_m1 map_addr @ mode underwrite
2143 bics r1, r1, #0x000000f0
2144 bicnes r1, r1, #0x0000f000
2145 bicnes r1, r1, #0x00f00000
2146 bicnes r1, r1, #0xf0000000
2148 orr r1, r1, r1, lsr #4
2149 m_s68k_write32_2M_decode \map_addr
2152 ldrneb r0, [r2, #-1]
2154 and r12,r1, #0x0000000f
2155 orr r0, r0, r3, lsl #16
2156 orrne r0, r0, #0x80000000 @ remember addr lsb bit
2160 andeq r12,r1, #0x000000f0
2163 andeq r12,r1, #0x000f0000
2166 andeq r12,r1, #0x00f00000
2169 strneb r0, [r2, #-1]
2176 .macro m_s68k_write32_2M_decode_m2 map_addr @ mode overwrite
2177 bics r1, r1, #0x000000f0
2178 bicnes r1, r1, #0x0000f000
2179 bicnes r1, r1, #0x00f00000
2180 bicnes r1, r1, #0xf0000000
2182 orr r1, r1, r1, lsr #4
2183 m_s68k_write32_2M_decode \map_addr
2186 ldrneb r0, [r2, #-1]
2188 orrne r1, r1, #0x80000000 @ remember addr lsb bit
2189 orr r0, r0, r3, lsl #16
2191 andeq r12,r0, #0x0000000f
2194 andeq r12,r0, #0x000000f0
2197 andeq r12,r0, #0x000f0000
2200 andeq r12,r0, #0x00f00000
2205 strneb r1, [r2, #-1]
2214 m_s68k_write32_prg: @ 0x000000 - 0x07ffff
2215 ldr r2, =(Pico+0x22200)
2218 add r3, r0, #0x020000 @ map to our address
2219 add r12,r2, #0x110000
2221 and r12,r12,#0x00ff0000 @ wp
2230 m_s68k_write32_wordram_2M: @ 0x080000 - 0x0bffff
2231 m_s68k_write32_wordram_1M_b1: @ 0x0c0000 - 0x0dffff, maps to 0x0e0000
2232 m_s68k_write32_ram 0x020000
2235 m_s68k_write32_2M_decode_b0_m0: @ 0x080000 - 0x0bffff
2236 m_s68k_write32_2M_decode_m0 0x080000
2238 m_s68k_write32_2M_decode_b0_m1:
2239 m_s68k_write32_2M_decode_m1 0x080000
2241 m_s68k_write32_2M_decode_b0_m2:
2242 m_s68k_write32_2M_decode_m2 0x080000
2244 m_s68k_write32_2M_decode_b1_m0:
2245 m_s68k_write32_2M_decode_m0 0x0a0000
2247 m_s68k_write32_2M_decode_b1_m1:
2248 m_s68k_write32_2M_decode_m1 0x0a0000
2250 m_s68k_write32_2M_decode_b1_m2:
2251 m_s68k_write32_2M_decode_m2 0x0a0000
2254 m_s68k_write32_wordram_1M_b0: @ 0x0c0000 - 0x0dffff (same as our offset :)
2255 m_s68k_write32_ram 0
2258 m_s68k_write32_backup:
2263 bl m_s68k_write8_backup @ must preserve r3 and r12
2267 b m_s68k_write8_backup
2271 bic r0, r0, #0xff0000
2273 blt m_s68k_write32_pcm_reg
2278 m_s68k_write32_pcm_ram:
2279 ldr r3, =(Pico+0x22200)
2280 bic r0, r0, #0x00e000
2283 add r2, r3, #0x110000
2284 add r2, r2, #0x002200
2285 add r2, r2, #0x000040
2287 add r3, r3, #0x100000 @ pcm_ram
2288 and r2, r2, #0x0f000000 @ bank
2289 add r3, r3, r2, lsr #12
2296 m_s68k_write32_pcm_reg:
2298 stmfd sp!,{r0,r1,lr}
2301 ldmfd sp!,{r0,r1,lr}
2306 m_s68k_write32_regs:
2307 bic r0, r0, #0xff0000
2308 bic r0, r0, #0x008000
2314 blo m_s68k_write32_regs_gfx
2317 beq m_s68k_write32_regs_spec @ hits 0x0f
2320 beq m_s68k_write32_regs_comm
2322 stmfd sp!,{r0,r1,lr}
2335 ldmfd sp!,{r0,r1,lr}
2339 m_s68k_write32_regs_gfx:
2340 stmfd sp!,{r0,r1,lr}
2343 ldmfd sp!,{r0,r1,lr}
2347 m_s68k_write32_regs_comm: @ Handle the 0x20-0x2f range
2348 ldr r2, =(Pico+0x22200)
2351 orr r3, r3, r3, lsl #16
2352 add r2, r2, #0x110000
2353 and r12,r3, r1, ror #16 @ data is big-endian to be written as little, have to byteswap
2354 and r1, r3, r1, ror #24
2355 orr r1, r1, r12,lsl #8 @ end of byteswap
2358 movne r1, r1, lsr #16
2362 m_s68k_write32_regs_spec:
2363 stmfd sp!,{r0,r1,lr}
2365 bl m_s68k_write16_regs
2366 ldmfd sp!,{r0,r1,lr}
2368 b m_s68k_write16_regs