5 // Pack our flags into r1, in SR/CCR register format
\r
7 void OpFlagsToReg(int high)
\r
9 ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");
\r
10 ot(" mov r1,r9,lsr #28 ;@ ____NZCV\n");
\r
11 ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");
\r
12 ot(" tst r2,#1 ;@ 1 if C!=V\n");
\r
13 ot(" eorne r1,r1,#3 ;@ ____NZVC\n");
\r
15 if (high) ot(" ldrb r2,[r7,#0x44] ;@ Include SR high\n");
\r
16 ot(" and r0,r0,#0x20000000\n");
\r
17 ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");
\r
18 if (high) ot(" orr r1,r1,r2,lsl #8\n");
\r
22 // Convert SR/CRR register in r0 to our flags
\r
24 void OpRegToFlags(int high)
\r
26 ot(" eor r1,r0,r0,ror #1 ;@ Bit 0=C^V\n");
\r
27 ot(" mov r2,r0,lsl #25\n");
\r
28 ot(" tst r1,#1 ;@ 1 if C!=V\n");
\r
29 ot(" eorne r0,r0,#3 ;@ ___XNZCV\n");
\r
30 ot(" str r2,[r7,#0x4c] ;@ Store X bit\n");
\r
31 ot(" mov r9,r0,lsl #28 ;@ r9=NZCV...\n");
\r
35 ot(" mov r0,r0,ror #8\n");
\r
36 ot(" and r0,r0,#0xa7 ;@ only take defined bits\n");
\r
37 ot(" strb r0,[r7,#0x44] ;@ Store SR high\n");
\r
42 // checks for supervisor bit, if not set, jumps to SuperEnd()
\r
43 // also sets r11 to SR high value, SuperChange() uses this
\r
44 void SuperCheck(int op)
\r
46 ot(" ldr r11,[r7,#0x44] ;@ Get SR high\n");
\r
47 ot(" tst r11,#0x20 ;@ Check we are in supervisor mode\n");
\r
48 ot(" beq WrongPrivilegeMode ;@ No\n");
\r
54 ot(";@ ----------\n");
\r
55 ot(";@ tried execute privileged instruction in user mode\n");
\r
56 ot("WrongPrivilegeMode%s\n",ms?"":":");
\r
57 ot(" sub r4,r4,#2 ;@ last opcode wasn't executed - go back\n");
\r
58 ot(" mov r0,#0x20 ;@ privilege violation\n");
\r
59 ot(" bl Exception\n");
\r
64 // does OSP and A7 swapping if needed
\r
65 // new or old SR (not the one already in [r7,#0x44]) should be passed in r11
\r
67 void SuperChange(int op,int load_srh)
\r
69 ot(";@ A7 <-> OSP?\n");
\r
71 ot(" ldr r0,[r7,#0x44] ;@ Get other SR high\n");
\r
72 ot(" eor r0,r0,r11\n");
\r
73 ot(" tst r0,#0x20\n");
\r
74 ot(" beq no_sp_swap%.4x\n",op);
\r
75 ot(" ;@ swap OSP and A7:\n");
\r
76 ot(" ldr r11,[r7,#0x3C] ;@ Get A7\n");
\r
77 ot(" ldr r0, [r7,#0x48] ;@ Get OSP\n");
\r
78 ot(" str r11,[r7,#0x48]\n");
\r
79 ot(" str r0, [r7,#0x3C]\n");
\r
80 ot("no_sp_swap%.4x%s\n", op, ms?"":":");
\r
85 // --------------------- Opcodes 0x1000+ ---------------------
\r
86 // Emit a Move opcode, 00xxdddd ddssssss
\r
93 // Get source and target EA
\r
95 tea =(op&0x01c0)>>3;
\r
96 tea|=(op&0x0e00)>>9;
\r
98 if (tea>=8 && tea<0x10) movea=1;
\r
100 // Find size extension
\r
104 case 0x1000: size=0; break;
\r
105 case 0x3000: size=1; break;
\r
106 case 0x2000: size=2; break;
\r
109 if (size<1 && (movea || EaAn(sea))) return 1; // move.b An,* and movea.b * are invalid
\r
111 // See if we can do this opcode:
\r
112 if (EaCanRead (sea,size)==0) return 1;
\r
113 if (EaCanWrite(tea )==0) return 1;
\r
115 use=OpBase(op,size);
\r
116 if (tea<0x38) use&=~0x0e00; // Use same handler for register ?0-7
\r
118 if (tea==0x1f || tea==0x27) use|=0x0e00; // Specific handler for (a7)+ and -(a7)
\r
120 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
122 OpStart(op,sea,tea); Cycles=4;
\r
124 EaCalcRead(-1,1,sea,size,0x003f);
\r
128 ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");
\r
129 ot(" mrs r9,cpsr ;@ r9=NZCV flags\n");
\r
133 if (movea) size=2; // movea always expands to 32-bits
\r
136 EaCalc (10,0x0e00,tea,size,0,0);
\r
137 if ((tea&0x38)==0x20 && size==2) { // -(An)
\r
138 ot(" mov r11,r1\n");
\r
139 ot(" add r0,r10,#2\n");
\r
140 EaWrite(0, 1,tea,1,0x0e00,0,0);
\r
141 EaWrite(10, 11,tea,1,0x0e00,1);
\r
143 EaWrite(0, 1,tea,size,0x0e00,0,0);
\r
146 EaCalc (0,0x0e00,tea,size,0,0);
\r
147 EaWrite(0, 1,tea,size,0x0e00,0,0);
\r
150 #if CYCLONE_FOR_GENESIS && !MEMHANDLERS_CHANGE_CYCLES
\r
151 // this is a bit hacky
\r
152 if ((tea==0x39||(tea&0x38)==0x10)&&size>=1)
\r
153 ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");
\r
156 if((tea&0x38)==0x20) Cycles-=2; // less cycles when dest is -(An)
\r
162 // --------------------- Opcodes 0x41c0+ ---------------------
\r
163 // Emit an Lea opcode, 0100nnn1 11aaaaaa
\r
170 tea=(op&0x0e00)>>9; tea|=8;
\r
172 if (EaCanRead(sea,-1)==0) return 1; // See if we can do this opcode
\r
175 use&=~0x0e00; // Also use 1 handler for target ?0-7
\r
176 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
178 OpStart(op,sea,tea);
\r
180 EaCalc (1,0x003f,sea,0); // Lea
\r
181 EaCalc (0,0x0e00,tea,2);
\r
182 EaWrite(0, 1,tea,2,0x0e00);
\r
184 Cycles=Ea_add_ns(g_lea_cycle_table,sea);
\r
191 // --------------------- Opcodes 0x40c0+ ---------------------
\r
192 // Move SR opcode, 01000tt0 11aaaaaa move SR
\r
193 int OpMoveSr(int op)
\r
198 type=(op>>9)&3; // from SR, from CCR, to CCR, to SR
\r
201 if(EaAn(ea)) return 1; // can't use An regs
\r
206 if (EaCanWrite(ea)==0) return 1; // See if we can do this opcode:
\r
210 return 1; // no such op in 68000
\r
213 if (EaCanRead(ea,size)==0) return 1; // See if we can do this opcode:
\r
217 use=OpBase(op,size);
\r
218 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
222 if (type==0) Cycles=(ea>=8)?8:6;
\r
224 if (type==3) SuperCheck(op); // 68000 model allows reading whole SR in user mode (but newer models don't)
\r
226 if (type==0 || type==1)
\r
228 OpFlagsToReg(type==0);
\r
229 EaCalc (0,0x003f,ea,size,0,0);
\r
230 EaWrite(0, 1,ea,size,0x003f,0,0);
\r
233 if (type==2 || type==3)
\r
235 EaCalcReadNoSE(-1,0,ea,size,0x003f);
\r
236 OpRegToFlags(type==3);
\r
239 CheckInterrupt(op);
\r
249 // Ori/Andi/Eori $nnnn,sr 0000t0t0 01111100
\r
250 int OpArithSr(int op)
\r
255 type=(op>>9)&5; if (type==4) return 1;
\r
256 size=(op>>6)&1; // ccr or sr?
\r
259 use=OpBase(op,size);
\r
260 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
262 OpStart(op,ea); Cycles=16;
\r
264 if (size) SuperCheck(op);
\r
266 EaCalc(10,0x003f,ea,size);
\r
267 EaRead(10, 10,ea,size,0x003f);
\r
269 OpFlagsToReg(size);
\r
270 if (type==0) ot(" orr r0,r1,r10\n");
\r
271 if (type==1) ot(" and r0,r1,r10\n");
\r
272 if (type==5) ot(" eor r0,r1,r10\n");
\r
273 OpRegToFlags(size);
\r
276 CheckInterrupt(op);
\r
284 // --------------------- Opcodes 0x4850+ ---------------------
\r
285 // Emit an Pea opcode, 01001000 01aaaaaa
\r
291 ea=op&0x003f; if (ea<0x10) return 1; // Swap opcode
\r
292 if (EaCanRead(ea,-1)==0) return 1; // See if we can do this opcode:
\r
295 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
299 ot(" ldr r10,[r7,#0x3c]\n");
\r
300 EaCalc (1,0x003f, ea,0);
\r
302 ot(" sub r0,r10,#4 ;@ Predecrement A7\n");
\r
303 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
\r
305 MemHandler(1,2); // Write 32-bit
\r
308 Cycles=6+Ea_add_ns(g_pea_cycle_table,ea);
\r
315 // --------------------- Opcodes 0x4880+ ---------------------
\r
316 // Emit a Movem opcode, 01001d00 1xeeeeee regmask
\r
317 int OpMovem(int op)
\r
319 int size=0,ea=0,cea=0,dir=0;
\r
320 int use=0,decr=0,change=0;
\r
322 size=((op>>6)&1)+1; // word, long
\r
324 dir=(op>>10)&1; // Direction (1==ea2reg)
\r
327 if (ea<0x10 || ea>0x3b || (ea&0x38)==0x20) return 1; // Invalid EA
\r
329 if (ea<0x10 || ea>0x39 || (ea&0x38)==0x18) return 1;
\r
332 if ((ea&0x38)==0x18 || (ea&0x38)==0x20) change=1;
\r
333 if ((ea&0x38)==0x20) decr=1; // -(An), bitfield is decr
\r
335 cea=ea; if (change) cea=0x10;
\r
337 use=OpBase(op,size);
\r
338 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
342 ot(" ldrh r11,[r4],#2 ;@ r11=register mask\n");
\r
344 ot(";@ r10=Register Index*4:\n");
\r
345 if (decr) ot(" mov r10,#0x40 ;@ order reversed for -(An)\n");
\r
346 else ot(" mov r10,#-4\n");
\r
349 ot(";@ Get the address into r6:\n");
\r
350 EaCalc(6,0x003f,cea,size);
\r
353 ot(" tst r11,r11\n"); // sanity check
\r
354 ot(" beq NoRegs%.4x\n",op);
\r
357 ot("Movemloop%.4x%s\n",op, ms?"":":");
\r
358 ot(" add r10,r10,#%d ;@ r10=Next Register\n",decr?-4:4);
\r
359 ot(" movs r11,r11,lsr #1\n");
\r
360 ot(" bcc Movemloop%.4x\n",op);
\r
363 if (decr) ot(" sub r6,r6,#%d ;@ Pre-decrement address\n",1<<size);
\r
367 ot(" ;@ Copy memory to register:\n",1<<size);
\r
368 EaRead (6,0,ea,size,0x003f);
\r
369 ot(" str r0,[r7,r10] ;@ Save value into Dn/An\n");
\r
373 ot(" ;@ Copy register to memory:\n",1<<size);
\r
374 ot(" ldr r1,[r7,r10] ;@ Load value from Dn/An\n");
\r
375 EaWrite(6,1,ea,size,0x003f);
\r
378 if (decr==0) ot(" add r6,r6,#%d ;@ Post-increment address\n",1<<size);
\r
380 ot(" sub r5,r5,#%d ;@ Take some cycles\n",2<<size);
\r
381 ot(" tst r11,r11\n");
\r
382 ot(" bne Movemloop%.4x\n",op);
\r
387 ot(";@ Write back address:\n");
\r
388 EaCalc (0,0x0007,8|(ea&7),2);
\r
389 EaWrite(0, 6,8|(ea&7),2,0x0007);
\r
392 ot("NoRegs%.4x%s\n",op, ms?"":":");
\r
393 ot(" ldr r6,=CycloneJumpTab ;@ restore Opcode Jump table\n");
\r
397 if (ea==0x3a) Cycles=16; // ($nn,PC)
\r
398 else if (ea==0x3b) Cycles=18; // ($nn,pc,Rn)
\r
404 Cycles+=Ea_add_ns(g_movem_cycle_table,ea);
\r
413 // --------------------- Opcodes 0x4e60+ ---------------------
\r
414 // Emit a Move USP opcode, 01001110 0110dnnn move An to/from USP
\r
415 int OpMoveUsp(int op)
\r
419 dir=(op>>3)&1; // Direction
\r
420 use=op&~0x0007; // Use same opcode for all An
\r
422 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
424 OpStart(op); Cycles=4;
\r
430 ot(" ldr r1,[r7,#0x48] ;@ Get from USP\n\n");
\r
431 EaCalc (0,0x000f,8,2,1);
\r
432 EaWrite(0, 1,8,2,0x000f,1);
\r
436 EaCalc (0,0x000f,8,2,1);
\r
437 EaRead (0, 0,8,2,0x000f,1);
\r
438 ot(" str r0,[r7,#0x48] ;@ Put in USP\n\n");
\r
446 // --------------------- Opcodes 0x7000+ ---------------------
\r
447 // Emit a Move Quick opcode, 0111nnn0 dddddddd moveq #dd,Dn
\r
448 int OpMoveq(int op)
\r
452 use=op&0xf100; // Use same opcode for all values
\r
453 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
455 OpStart(op); Cycles=4;
\r
457 ot(" movs r0,r8,asl #24\n");
\r
458 ot(" and r1,r8,#0x0e00\n");
\r
459 ot(" mov r0,r0,asr #24 ;@ Sign extended Quick value\n");
\r
460 ot(" mrs r9,cpsr ;@ r9=NZ flags\n");
\r
461 ot(" str r0,[r7,r1,lsr #7] ;@ Store into Dn\n");
\r
469 // --------------------- Opcodes 0xc140+ ---------------------
\r
470 // Emit a Exchange opcode:
\r
471 // 1100ttt1 01000sss exg ds,dt
\r
472 // 1100ttt1 01001sss exg as,at
\r
473 // 1100ttt1 10001sss exg as,dt
\r
480 if (type!=0x40 && type!=0x48 && type!=0x88) return 1; // Not an exg opcode
\r
482 use=op&0xf1f8; // Use same opcode for all values
\r
483 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
485 OpStart(op); Cycles=6;
\r
487 ot(" and r10,r8,#0x0e00 ;@ Find T register\n");
\r
488 ot(" and r11,r8,#0x000f ;@ Find S register\n");
\r
489 if (type==0x48) ot(" orr r10,r10,#0x1000 ;@ T is an address register\n");
\r
491 ot(" ldr r0,[r7,r10,lsr #7] ;@ Get T\n");
\r
492 ot(" ldr r1,[r7,r11,lsl #2] ;@ Get S\n");
\r
494 ot(" str r0,[r7,r11,lsl #2] ;@ T->S\n");
\r
495 ot(" str r1,[r7,r10,lsr #7] ;@ S->T\n");
\r
503 // ------------------------- movep -------------------------------
\r
504 // 0000ddd1 0z001sss
\r
505 // 0000sss1 1z001ddd (to mem)
\r
506 int OpMovep(int op)
\r
509 int size=1,use=0,dir,aadd=0;
\r
512 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler (for all dests, srcs)
\r
515 ea = (op&0x0007)|0x28;
\r
516 rea= (op&0x0e00)>>9;
\r
519 // Find size extension
\r
520 if(op&0x0040) size=2;
\r
524 if(dir) { // reg to mem
\r
525 EaCalcReadNoSE(-1,11,rea,size,0x0e00);
\r
527 EaCalc(10,0x000f,ea,size);
\r
528 if(size==2) { // if operand is long
\r
529 ot(" mov r1,r11,lsr #24 ;@ first byte\n");
\r
530 EaWrite(10,1,ea,0,0x000f); // store first byte
\r
531 ot(" add r0,r10,#%i\n",(aadd+=2));
\r
532 ot(" mov r1,r11,lsr #16 ;@ second byte\n");
\r
533 EaWrite(0,1,ea,0,0x000f); // store second byte
\r
534 ot(" add r0,r10,#%i\n",(aadd+=2));
\r
536 ot(" mov r0,r10\n");
\r
538 ot(" mov r1,r11,lsr #8 ;@ first or third byte\n");
\r
539 EaWrite(0,1,ea,0,0x000f);
\r
540 ot(" add r0,r10,#%i\n",(aadd+=2));
\r
541 ot(" and r1,r11,#0xff\n");
\r
542 EaWrite(0,1,ea,0,0x000f);
\r
543 } else { // mem to reg
\r
544 EaCalc(10,0x000f,ea,size,1);
\r
545 EaRead(10,11,ea,0,0x000f,1); // read first byte
\r
546 ot(" add r0,r10,#2\n");
\r
547 EaRead(0,1,ea,0,0x000f,1); // read second byte
\r
548 if(size==2) { // if operand is long
\r
549 ot(" orr r11,r11,r1,lsr #8 ;@ second byte\n");
\r
550 ot(" add r0,r10,#4\n");
\r
551 EaRead(0,1,ea,0,0x000f,1);
\r
552 ot(" orr r11,r11,r1,lsr #16 ;@ third byte\n");
\r
553 ot(" add r0,r10,#6\n");
\r
554 EaRead(0,1,ea,0,0x000f,1);
\r
555 ot(" orr r1,r11,r1,lsr #24 ;@ fourth byte\n");
\r
557 ot(" orr r1,r11,r1,lsr #8 ;@ second byte\n");
\r
559 // store the result
\r
560 EaCalc(11,0x0e00,rea,size,1); // reg number -> r11
\r
561 EaWrite(11,1,rea,size,0x0e00,1);
\r
564 Cycles=(size==2)?24:16;
\r
570 // Emit a Stop/Reset opcodes, 01001110 011100t0 imm
\r
571 int OpStopReset(int op)
\r
573 int type=(op>>1)&1; // stop/reset
\r
580 // copy immediate to SR, stop the CPU and eat all remaining cycles.
\r
581 ot(" ldrh r0,[r4],#2 ;@ Fetch the immediate\n");
\r
587 ot(" mov r0,#1\n");
\r
588 ot(" str r0,[r7,#0x58] ;@ stopped\n");
\r
591 ot(" mov r5,#0 ;@ eat cycles\n");
\r
598 #if USE_RESET_CALLBACK
\r
599 ot(" str r4,[r7,#0x40] ;@ Save PC\n");
\r
600 ot(" mov r1,r9,lsr #28\n");
\r
601 ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");
\r
602 ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");
\r
603 ot(" ldr r11,[r7,#0x90] ;@ ResetCallback\n");
\r
604 ot(" tst r11,r11\n");
\r
605 ot(" movne lr,pc\n");
\r
606 ot(" bxne r11 ;@ call ResetCallback if it is defined\n");
\r
607 ot(" ldrb r9,[r7,#0x46] ;@ r9 = Load Flags (NZCV)\n");
\r
608 ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");
\r
609 ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");
\r
610 ot(" mov r9,r9,lsl #28\n");
\r