1 // basic, incomplete SSP160x (SSP1601?) interpreter
5 * most names taken from MAME code
9 * desc: Constant register with all bits set (0xffff).
13 * desc: Generic register. When set, updates P (P = X * Y * 2) ??
17 * desc: Generic register. When set, updates P (P = X * Y * 2) ??
25 * desc: Status register. From MAME: bits 0-9 are CONTROL, other FLAG
27 * 210 - RPL (?) "Loop size". If non-zero, makes (rX+) and (rX-) respectively
28 * modulo-increment and modulo-decrement. The value shows which
29 * power of 2 to use, i.e. 4 means modulo by 16.
30 * (e: fir16_32.sc, IIR_4B.SC, DECIM.SC)
32 * 5 - GP0_0 (ST5?) Changed before acessing PM0 (affects banking?).
33 * 6 - GP0_1 (ST6?) Cleared before acessing PM0 (affects banking?). Set after.
34 * datasheet says these (5,6) bits correspond to hardware pins.
35 * 7 - IE (?) Not directly used by SVP code (never set, but preserved)?
36 * 8 - OP (?) Not used by SVP code (only cleared)? (MAME: saturated value
37 * (probably means clamping? i.e. 0x7ffc + 9 -> 0x7fff))
38 * 9 - MACS (?) Not used by SVP code (only cleared)? (e: "mac shift")
39 * a - GPI_0 Interrupt 0 enable/status?
40 * b - GPI_1 Interrupt 1 enable/status?
41 * c - L L flag. Carry?
43 * e - OV Overflow flag.
44 * f - N Negative flag.
45 * seen directly changing code sequences:
46 * ldi ST, 0 ld A, ST ld A, ST ld A, ST ldi st, 20h
47 * ldi ST, 60h ori A, 60h and A, E8h and A, E8h
48 * ld ST, A ld ST, A ori 3
53 * desc: hw stack of 6 levels (according to datasheet)
57 * desc: Program counter.
61 * desc: multiply result register. Updated after mp* instructions,
62 * or writes to X or Y (P = X * Y * 2) ??
63 * probably affected by MACS bit in ST.
65 * 8. "PM0" (PM from PMAR name from Tasco's docs)
67 * desc: Programmable Memory access register.
68 * On reset, or when one (both?) GP0 bits are clear,
69 * acts as some additional status reg?
73 * desc: Programmable Memory access register.
74 * This reg. is only used as PMAR.
78 * desc: Programmable Memory access register.
79 * This reg. is only used as PMAR.
83 * desc: eXternal STate. Mapped to a15000 at 68k side.
84 * Can be programmed as PMAR? (only seen in test mode code)
88 * desc: Programmable Memory access register.
89 * This reg. is only used as PMAR. The most used PMAR by VR.
93 * 14. "PMC" (PMC from PMAC name from Tasco's docs)
95 * desc: Programmable Memory access Control. Set using 2 16bit writes,
96 * first address, then mode word. After setting PMAC, PMAR sould
97 * be accessed to program it.
101 * desc: Accumulator Low. 16 least significant bits of accumulator (not 100% sure)
102 * (normally reading acc (ld X, A) you get 16 most significant bits).
105 * There are 8 8-bit pointer registers rX. r0-r3 (ri) point to RAM0, r4-r7 (rj) point to RAM1.
106 * They can be accessed directly, or 2 indirection levels can be used [ (rX), ((rX)) ],
107 * which work similar to * and ** operators in C, only they use different memory banks and
108 * ((rX)) also does post-increment. First indirection level (rX) accesses RAMx, second accesses
109 * program memory at address read from (rX), and increments value in (rX).
111 * r0,r1,r2,r4,r5,r6 can be modified [ex: ldi r0, 5].
112 * 3 modifiers can be applied (optional):
113 * + : post-increment [ex: ld a, (r0+) ]. Can be made modulo-increment by setting RPL bits in ST.
114 * - : post-decrement. Can be made modulo-decrement by setting RPL bits in ST (not sure).
115 * +!: post-increment, unaffected by RPL (probably).
116 * These are only used on 1st indirection level, so things like [ld a, ((r0+))] and [ld X, r6-]
117 * ar probably invalid.
119 * r3 and r7 are special and can not be changed (at least Samsung samples and SVP code never do).
120 * They are fixed to the start of their RAM banks. (They are probably changeable for ssp1605+,
121 * Samsung's old DSP page claims that).
122 * 1 of these 4 modifiers must be used (short form direct addressing?):
123 * |00: RAMx[0] [ex: (r3|00), 0] (based on sample code)
125 * |10: RAMx[2] ? maybe 10h? accortding to Div_c_dp.sc, 2
131 * mld (rj), (ri) [, b]
132 * operation: A = 0; P = (rj) * (ri)
133 * notes: based on IIR_4B.SC sample. flags? what is b???
134 * TODO: figure out if (rj) and (ri) get loaded in X and Y
136 * mpya (rj), (ri) [, b]
137 * name: multiply and add?
138 * operation: A += P; P = (rj) * (ri)
141 * name: multiply and subtract?
142 * notes: not used by VR code.
144 * ld a, * doesn't affect flags! (e: A_LAW.SC, Div_c_dp.sc)
147 * 000000 - 1fffff ROM, accessable by both
148 * 200000 - 2fffff unused?
149 * 300000 - 30ffff DRAM, both
150 * 310000 - 31ffff cleared, but never(?) accessed?
151 * 320000 - 38ffff unused?
152 * 390000 - 3907ff IRAM. can only be accessed by ssp?
154 * 30fe02 - 0 if SVP busy, 1 if done (set by SVP, checked and cleared by 68k)
155 * 30fe06 - also sync related.
156 * 30fe08 - job number [1-12] for SVP. 0 means nothing. Set by 68k, read-cleared by SVP.
158 * Assumptions in this code
159 * P is not directly writeable
160 * flags correspond to full 32bit accumulator
161 * only Z and N status flags are emulated (others unused by SVP)
162 * modifiers for 'OP a, ri' are ignored (invalid?/not used by SVP)
163 * modifiers '+' and '+!' act the same (this is most likely wrong)
164 * 'ld d, (a)' loads from program ROM
167 #include "../../PicoInt.h"
169 #define u32 unsigned int
172 #define rX ssp->gr[SSP_X].h
173 #define rY ssp->gr[SSP_Y].h
174 #define rA ssp->gr[SSP_A].h
175 #define rST ssp->gr[SSP_ST].h // 4
176 #define rSTACK ssp->gr[SSP_STACK].h
177 #define rPC ssp->gr[SSP_PC].h
178 #define rP ssp->gr[SSP_P]
179 #define rPM0 ssp->gr[SSP_PM0].h // 8
180 #define rPM1 ssp->gr[SSP_PM1].h
181 #define rPM2 ssp->gr[SSP_PM2].h
182 #define rXST ssp->gr[SSP_XST].h
183 #define rPM4 ssp->gr[SSP_PM4].h // 12
185 #define rPMC ssp->gr[SSP_PMC] // will keep addr in .h, mode in .l
186 #define rAL ssp->gr[SSP_A].l
188 #define rA32 ssp->gr[SSP_A].v
191 #define IJind (((op>>6)&4)|(op&3))
193 #define GET_PC() (PC - (unsigned short *)svp->iram_rom)
194 #define GET_PPC_OFFS() ((unsigned int)PC - (unsigned int)svp->iram_rom - 2)
195 #define SET_PC(d) PC = (unsigned short *)svp->iram_rom + d
197 #define REG_READ(r) (((r) <= 4) ? ssp->gr[r].h : read_handlers[r]())
198 #define REG_WRITE(r,d) { \
200 if (r1 >= 4) write_handlers[r1](d); \
201 else if (r1 > 0) ssp->gr[r1].h = d; \
205 #define FLAG_L (1<<0xc)
206 #define FLAG_Z (1<<0xd)
207 #define FLAG_V (1<<0xe)
208 #define FLAG_N (1<<0xf)
210 // update ZN according to 32bit ACC.
212 rST &= ~(FLAG_Z|FLAG_N); \
213 if (!rA32) rST |= FLAG_Z; \
214 else rST |= (rA32>>16)&FLAG_N;
216 // it seems SVP code never checks for L and OV, so we leave them out.
217 // rST |= (t>>4)&FLAG_L;
219 rST &= ~(FLAG_L|FLAG_Z|FLAG_V|FLAG_N); \
220 if (!t) rST |= FLAG_Z; \
221 else rST |= t&FLAG_N; \
223 // standard cond processing.
224 // again, only Z and N is checked, as SVP doesn't seem to use any other conds.
227 case 0x00: cond = 1; break; /* always true */ \
228 case 0x50: cond = !((rST ^ (op<<5)) & FLAG_Z); break; /* Z matches f(?) bit */ \
229 case 0x70: cond = !((rST ^ (op<<7)) & FLAG_N); break; /* N matches f(?) bit */ \
230 default:elprintf(EL_SVP, "unimplemented cond @ %04x", GET_PPC_OFFS()); break; \
233 // ops with accumulator.
234 // how is low word really affected by these?
235 // nearly sure 'ld A' doesn't affect flags
239 #define OP_SUBA(x) { \
240 u32 t = (ssp->gr[SSP_A].v >> 16) - (x); \
242 ssp->gr[SSP_A].h = t; \
245 #define OP_CMPA(x) { \
246 u32 t = (ssp->gr[SSP_A].v >> 16) - (x); \
250 #define OP_ADDA(x) { \
251 u32 t = (ssp->gr[SSP_A].v >> 16) + (x); \
253 ssp->gr[SSP_A].h = t; \
257 ssp->gr[SSP_A].v &= (x) << 16; \
261 ssp->gr[SSP_A].v |= (x) << 16; \
265 ssp->gr[SSP_A].v ^= (x) << 16; \
269 static ssp1601_t *ssp = NULL;
270 static unsigned short *PC;
273 static int running = 0;
274 static int last_iram = 0;
276 // -----------------------------------------------------
277 // register i/o handlers
280 static u32 read_unknown(void)
282 elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: unknown read @ %04x", GET_PPC_OFFS());
286 static void write_unknown(u32 d)
288 elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: unknown write @ %04x", GET_PPC_OFFS());
292 static void write_ST(u32 d)
295 elprintf(EL_SVP, "ssp16: RPL %i -> %i @ %04x", rST&7, d&7, GET_PPC_OFFS());
302 static u32 read_STACK(void)
304 //elprintf(EL_SVP, "pop %i @ %04x", rSTACK, GET_PPC_OFFS());
306 if ((short)rSTACK < 0) {
308 elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: stack underflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
310 return ssp->stack[rSTACK];
313 static void write_STACK(u32 d)
317 elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: stack overflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
320 ssp->stack[rSTACK++] = d;
324 static u32 read_PC(void)
329 static void write_PC(u32 d)
336 static u32 read_P(void)
338 rP.v = (u32)rX * rY * 2;
342 // -----------------------------------------------------
344 static void iram_write(int addr, u32 d, int reg, int inc)
346 if ((addr&0xfc00) != 0x8000)
347 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid IRAM addr: %04x", addr<<1);
348 elprintf(EL_SVP, "ssp IRAM w [%06x] %04x (inc %i)", (addr<<1)&0x7ff, d, inc);
349 ((unsigned short *)svp->iram_rom)[addr&0x3ff] = d;
350 ssp->pmac_write[reg] += inc<<16;
353 int lil[32] = { 0, }, lilp = 0;
355 static void debug_dump2file(const char *fname, void *mem, int len);
357 static u32 pm_io(int reg, int write, u32 d)
359 if (ssp->emu_status & SSP_PMC_SET) {
360 elprintf(EL_SVP, "PM%i (%c) set to %08x @ %04x", reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
361 ssp->pmac_read[write ? reg + 6 : reg] = rPMC.v;
362 ssp->emu_status &= ~SSP_PMC_SET;
363 if ((rPMC.v & 0x7f) == 0x1c && (rPMC.v & 0x7fff0000) == 0) {
364 elprintf(EL_SVP, "IRAM copy from %06x", (ssp->RAM1[0]-1)<<1);
369 for (i = 0; i < 32; i++) {
370 if (lil[i] == last_iram) break;
373 sprintf(buff, "iramrom_%04x.bin", last_iram);
374 debug_dump2file(buff, svp->iram_rom, sizeof(svp->iram_rom));
380 last_iram = (ssp->RAM1[0]-1)<<1;
386 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
388 // if (ssp->pmac_read[reg] != 0)
389 if (reg == 4 || (rST & 0x60))
391 #define CADDR ((((mode<<16)&0x7f0000)|addr)<<1)
394 int mode = ssp->pmac_write[reg]&0xffff;
395 int addr = ssp->pmac_write[reg]>>16;
397 case 0x0018: elprintf(EL_SVP, "ssp DRAM w [%06x] %04x", CADDR, d);
398 ((unsigned short *)svp->dram)[addr] = d;
400 case 0x0818: elprintf(EL_SVP, "ssp DRAM w [%06x] %04x (inc 1)", CADDR, d);
401 ((unsigned short *)svp->dram)[addr] = d;
402 ssp->pmac_write[reg] += 1<<16;
404 case 0x081c: iram_write(addr, d, reg, 1); break; // checked: used by code @ 0902
405 case 0x101c: iram_write(addr, d, reg, 2); break; // checked: used by code @ 3b7c
406 case 0x4018: elprintf(EL_SVP, "ssp DRAM w [%06x] %04x (cell inc)", CADDR, d);
407 ((unsigned short *)svp->dram)[addr] = d;
408 ssp->pmac_write[reg] += (addr&1) ? (31<<16) : (1<<16);
410 default: elprintf(EL_SVP|EL_ANOMALY, "ssp PM%i unhandled write mode %04x, [%06x] %04x @ %04x",
411 reg, mode, CADDR, d, GET_PPC_OFFS()); break;
416 int mode = ssp->pmac_read[reg]&0xffff;
417 int addr = ssp->pmac_read[reg]>>16;
421 case 0x0809: elprintf(EL_SVP, "ssp ROM r [%06x] %04x", CADDR,
422 ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)]);
423 // possibly correct, the first word read is some sort of counter, sane values in ROM
424 ssp->pmac_read[reg] += 1<<16;
425 d = ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)];
427 case 0x0018: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x", CADDR, ((unsigned short *)svp->dram)[addr]);
428 d = ((unsigned short *)svp->dram)[addr]; // checked
430 case 0x0818: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x (inc 1)", CADDR, ((unsigned short *)svp->dram)[addr]);
431 ssp->pmac_read[reg] += 1<<16;
432 d = ((unsigned short *)svp->dram)[addr];
434 case 0x3018: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x (inc 32)", CADDR, ((unsigned short *)svp->dram)[addr]);
435 ssp->pmac_read[reg] += 32<<16;
436 d = ((unsigned short *)svp->dram)[addr];
438 case 0xa818: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x (dec 16)", CADDR, ((unsigned short *)svp->dram)[addr]);
439 ssp->pmac_read[reg] -= 16<<16;
440 d = ((unsigned short *)svp->dram)[addr];
442 case 0xb818: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x (dec 128?)", CADDR, ((unsigned short *)svp->dram)[addr]);
443 ssp->pmac_read[reg] -= 128<<16;
444 d = ((unsigned short *)svp->dram)[addr];
446 default: elprintf(EL_SVP|EL_ANOMALY, "ssp PM%i unhandled read mode %04x, [%06x] @ %04x",
447 reg, mode, CADDR, GET_PPC_OFFS());
453 // PMC value corresponds to last PMR accessed (not sure).
454 rPMC.v = ssp->pmac_read[write ? reg + 6 : reg];
463 static u32 read_PM0(void)
465 u32 d = pm_io(0, 0, 0);
466 if (d != (u32)-1) return d;
467 if (GET_PPC_OFFS() != 0x800 || rPM0 != 0) // debug
468 elprintf(EL_SVP, "PM0 raw r %04x @ %04x", rPM0, GET_PPC_OFFS());
472 static void write_PM0(u32 d)
474 u32 r = pm_io(0, 1, d);
475 if (r != (u32)-1) return;
476 elprintf(EL_SVP, "PM0 raw w %04x @ %04x", d, GET_PPC_OFFS());
477 // rPM0 = d; // ignore
481 static u32 read_PM1(void)
483 u32 d = pm_io(1, 0, 0);
484 if (d != (u32)-1) return d;
486 elprintf(EL_SVP, "PM1 raw r %04x @ %04x", rPM1, GET_PPC_OFFS());
490 static void write_PM1(u32 d)
492 u32 r = pm_io(1, 1, d);
493 if (r != (u32)-1) return;
495 elprintf(EL_SVP, "PM1 raw w %04x @ %04x", d, GET_PPC_OFFS());
500 static u32 read_PM2(void)
502 u32 d = pm_io(2, 0, 0);
503 if (d != (u32)-1) return d;
505 elprintf(EL_SVP, "PM2 raw r %04x @ %04x", rPM2, GET_PPC_OFFS());
509 static void write_PM2(u32 d)
511 u32 r = pm_io(2, 1, d);
512 if (r != (u32)-1) return;
514 elprintf(EL_SVP, "PM2 raw w %04x @ %04x", d, GET_PPC_OFFS());
519 static u32 read_XST(void)
522 u32 d = pm_io(3, 0, 0);
523 if (d != (u32)-1) return d;
525 elprintf(EL_SVP, "XST raw r %04x @ %04x", rXST, GET_PPC_OFFS());
529 static void write_XST(u32 d)
532 u32 r = pm_io(3, 1, d);
533 if (r != (u32)-1) return;
535 elprintf(EL_SVP, "XST raw w %04x @ %04x", d, GET_PPC_OFFS());
540 static u32 read_PM4(void)
542 u32 d = pm_io(4, 0, 0);
544 switch (GET_PPC_OFFS()) {
545 case 0x0854: ssp->emu_status |= SSP_30FE08_WAIT; elprintf(EL_SVP, "det TIGHT loop: [30fe08]"); break;
546 case 0x4f12: ssp->emu_status |= SSP_30FE06_WAIT; elprintf(EL_SVP, "det TIGHT loop: [30fe06]"); break;
549 if (d != (u32)-1) return d;
551 elprintf(EL_SVP, "PM4 raw r %04x @ %04x", rPM4, GET_PPC_OFFS());
555 static void write_PM4(u32 d)
557 u32 r = pm_io(4, 1, d);
558 if (r != (u32)-1) return;
560 elprintf(EL_SVP, "PM4 raw w %04x @ %04x", d, GET_PPC_OFFS());
565 static u32 read_PMC(void)
567 elprintf(EL_SVP, "PMC r %08x @ %04x", rPMC.v, GET_PPC_OFFS());
568 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
569 if (ssp->emu_status & SSP_PMC_SET)
570 elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
571 ssp->emu_status |= SSP_PMC_SET;
572 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
575 ssp->emu_status |= SSP_PMC_HAVE_ADDR;
580 static void write_PMC(u32 d)
582 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
583 if (ssp->emu_status & SSP_PMC_SET)
584 elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
585 ssp->emu_status |= SSP_PMC_SET;
586 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
589 ssp->emu_status |= SSP_PMC_HAVE_ADDR;
595 static u32 read_AL(void)
597 // TODO: figure out what's up with those blind reads..
601 static void write_AL(u32 d)
607 typedef u32 (*read_func_t)(void);
608 typedef void (*write_func_t)(u32 d);
610 static read_func_t read_handlers[16] =
612 read_unknown, read_unknown, read_unknown, read_unknown, // -, X, Y, A
613 read_unknown, // 4 ST
622 read_unknown, // 13 gr13
627 static write_func_t write_handlers[16] =
629 write_unknown, write_unknown, write_unknown, write_unknown, // -, X, Y, A
630 // write_unknown, // 4 ST
631 write_ST, // 4 ST (debug hook)
634 write_unknown, // 7 P
640 write_unknown, // 13 gr13
645 // -----------------------------------------------------
646 // pointer register handlers
649 #define ptr1_read(op) ptr1_read_(op&3,(op>>6)&4,(op<<1)&0x18)
651 static u32 ptr1_read_(int ri, int isj2, int modi3)
653 //int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
654 u32 mask, add = 0, t = ri | isj2 | modi3;
655 unsigned char *rp = NULL;
661 case 0x02: return ssp->RAM0[ssp->r0[t&3]];
662 case 0x03: return ssp->RAM0[0];
665 case 0x06: return ssp->RAM1[ssp->r1[t&3]];
666 case 0x07: return ssp->RAM1[0];
670 case 0x0a: return ssp->RAM0[ssp->r0[t&3]++];
671 case 0x0b: return ssp->RAM0[1];
674 case 0x0e: return ssp->RAM1[ssp->r1[t&3]++];
675 case 0x0f: return ssp->RAM1[1];
679 case 0x12: rp = &ssp->r0[t&3]; t = ssp->RAM0[*rp];
680 if (!(rST&7)) { (*rp)--; return t; }
681 add = -1; goto modulo;
682 case 0x13: return ssp->RAM0[2];
685 case 0x16: rp = &ssp->r1[t&3]; t = ssp->RAM1[*rp];
686 if (!(rST&7)) { (*rp)--; return t; }
687 add = -1; goto modulo;
688 case 0x17: return ssp->RAM1[2];
692 case 0x1a: rp = &ssp->r0[t&3]; t = ssp->RAM0[*rp];
693 if (!(rST&7)) { (*rp)++; return t; }
694 add = 1; goto modulo;
695 case 0x1b: return ssp->RAM0[3];
698 case 0x1e: rp = &ssp->r1[t&3]; t = ssp->RAM1[*rp];
699 if (!(rST&7)) { (*rp)++; return t; }
700 add = 1; goto modulo;
701 case 0x1f: return ssp->RAM1[3];
707 mask = (1 << (rST&7)) - 1;
708 *rp = (*rp & ~mask) | ((*rp + add) & mask);
712 static void ptr1_write(int op, u32 d)
714 int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
720 case 0x02: ssp->RAM0[ssp->r0[t&3]] = d; return;
721 case 0x03: ssp->RAM0[0] = d; return;
724 case 0x06: ssp->RAM1[ssp->r1[t&3]] = d; return;
725 case 0x07: ssp->RAM1[0] = d; return;
733 case 0x1a: ssp->RAM0[ssp->r0[t&3]++] = d; return;
734 case 0x0b: ssp->RAM0[1] = d; return;
740 case 0x1e: ssp->RAM1[ssp->r1[t&3]++] = d; return;
741 case 0x0f: ssp->RAM1[1] = d; return;
745 case 0x12: ssp->RAM0[ssp->r0[t&3]--] = d; return;
746 case 0x13: ssp->RAM0[2] = d; return;
749 case 0x16: ssp->RAM1[ssp->r1[t&3]--] = d; return;
750 case 0x17: ssp->RAM1[2] = d; return;
752 case 0x1b: ssp->RAM0[3] = d; return;
753 case 0x1f: ssp->RAM1[3] = d; return;
757 static u32 ptr2_read(int op)
759 int mv = 0, t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
765 case 0x02: mv = ssp->RAM0[ssp->r0[t&3]]++; break;
766 case 0x03: mv = ssp->RAM0[0]++; break;
769 case 0x06: mv = ssp->RAM1[ssp->r1[t&3]]++; break;
770 case 0x07: mv = ssp->RAM1[0]++; break;
772 case 0x0b: mv = ssp->RAM0[1]++; break;
773 case 0x0f: mv = ssp->RAM1[1]++; break;
775 case 0x13: mv = ssp->RAM0[2]++; break;
776 case 0x17: mv = ssp->RAM1[2]++; break;
778 case 0x1b: mv = ssp->RAM0[3]++; break;
779 case 0x1f: mv = ssp->RAM1[3]++; break;
780 default: elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid mod in ((rX))? @ %04x", GET_PPC_OFFS());
784 return ((unsigned short *)svp->iram_rom)[mv];
788 // -----------------------------------------------------
790 void ssp1601_reset(ssp1601_t *l_ssp)
794 ssp->gr[SSP_GR0].v = 0xffff0000;
796 rSTACK = 0; // ? using ascending stack
801 static void debug_dump(void)
803 printf("GR0: %04x X: %04x Y: %04x A: %08x\n", ssp->gr[SSP_GR0].h, rX, rY, ssp->gr[SSP_A].v);
804 printf("PC: %04x (%04x) P: %08x\n", GET_PC(), GET_PC() << 1, ssp->gr[SSP_P].v);
805 printf("PM0: %04x PM1: %04x PM2: %04x\n", rPM0, rPM1, rPM2);
806 printf("XST: %04x PM4: %04x PMC: %08x\n", rXST, rPM4, ssp->gr[SSP_PMC].v);
807 printf(" ST: %04x %c%c%c%c, GP0_0 %i, GP0_1 %i\n", rST, rST&FLAG_N?'N':'n', rST&FLAG_V?'V':'v',
808 rST&FLAG_Z?'Z':'z', rST&FLAG_L?'L':'l', (rST>>5)&1, (rST>>6)&1);
809 printf("STACK: %i %04x %04x %04x %04x %04x %04x\n", rSTACK, ssp->stack[0], ssp->stack[1],
810 ssp->stack[2], ssp->stack[3], ssp->stack[4], ssp->stack[5]);
811 printf("r0-r2: %02x %02x %02x r4-r6: %02x %02x %02x\n", rIJ[0], rIJ[1], rIJ[2], rIJ[4], rIJ[5], rIJ[6]);
812 elprintf(EL_SVP, "cycles: %i, emu_status: %x", g_cycles, ssp->emu_status);
815 static void debug_dump_mem(void)
819 for (h = 0; h < 32; h++)
821 if (h == 16) printf("RAM1\n");
822 printf("%03x:", h*16);
823 for (i = 0; i < 16; i++)
824 printf(" %04x", ssp->RAM[h*16+i]);
829 static void debug_dump2file(const char *fname, void *mem, int len)
831 FILE *f = fopen(fname, "wb");
832 unsigned short *p = mem;
835 for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
836 fwrite(mem, 1, len, f);
838 for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
839 printf("dumped to %s\n", fname);
842 printf("dump failed\n");
845 static int bpts[10] = { 0, };
847 static void debug(unsigned int pc, unsigned int op)
849 static char buffo[64] = {0,};
850 char buff[64] = {0,};
854 for (i = 0; i < 10; i++)
855 if (pc != 0 && bpts[i] == pc) {
856 printf("breakpoint %i\n", i);
863 printf("%04x (%02x) @ %04x\n", op, op >> 9, pc<<1);
869 fgets(buff, sizeof(buff), stdin);
870 if (buff[0] == '\n') strcpy(buff, buffo);
871 else strcpy(buffo, buff);
876 case 'r': running = 1; return;
879 case 'x': debug_dump(); break;
880 case 'm': debug_dump_mem(); break;
882 char *baddr = buff + 2;
884 if (buff[3] == ' ') { i = buff[2] - '0'; baddr = buff + 4; }
885 bpts[i] = strtol(baddr, NULL, 16) >> 1;
886 printf("breakpoint %i set @ %04x\n", i, bpts[i]<<1);
890 sprintf(buff, "iramrom_%04x.bin", last_iram);
891 debug_dump2file(buff, svp->iram_rom, sizeof(svp->iram_rom));
892 debug_dump2file("dram.bin", svp->dram, sizeof(svp->dram));
894 default: printf("unknown command\n"); break;
899 void ssp1601_run(int cycles)
905 while (g_cycles > 0 && !(ssp->emu_status&0xc000))
911 debug(GET_PC()-1, op);
916 if (op == 0) break; // nop
917 if (op == ((SSP_A<<4)|SSP_P)) { // A <- P
918 // not sure. MAME claims that only hi word is transfered.
919 read_P(); // update P
920 ssp->gr[SSP_A].v = ssp->gr[SSP_P].v;
924 tmpv = REG_READ(op & 0x0f);
925 REG_WRITE((op & 0xf0) >> 4, tmpv);
930 case 0x01: tmpv = ptr1_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break;
933 case 0x02: tmpv = REG_READ((op & 0xf0) >> 4); ptr1_write(op, tmpv); break;
936 case 0x04: tmpv = *PC++; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
939 case 0x05: tmpv = ptr2_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break;
942 case 0x06: tmpv = *PC++; ptr1_write(op, tmpv); break;
945 case 0x07: ssp->RAM[op & 0x1ff] = rA; break;
948 case 0x09: tmpv = rIJ[(op&3)|((op>>6)&4)]; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
951 case 0x0a: rIJ[(op&3)|((op>>6)&4)] = REG_READ((op & 0xf0) >> 4); break;
957 case 0x0f: rIJ[(op>>8)&7] = op; break;
963 if (cond) { int new_PC = *PC++; write_STACK(GET_PC()); write_PC(new_PC); }
969 case 0x25: tmpv = ((unsigned short *)svp->iram_rom)[rA]; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
975 if (cond) { int new_PC = *PC++; write_PC(new_PC); }
986 case 2: rA32 >>= 1; break; // shr
987 case 3: rA32 <<= 1; break; // shl
988 case 6: rA32 = -(int)rA32; break; // neg
989 case 7: if ((int)rA32 < 0) rA32 = -(int)rA32; break; // abs
990 default: elprintf(EL_SVP, "ssp16: unhandled mod %i @ %04x", op&7, GET_PPC_OFFS());
1000 // very uncertain about this one. What about b?
1001 if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp16: FIXME: no b bit @ %04x", GET_PPC_OFFS());
1002 read_P(); // update P
1003 ssp->gr[SSP_A].v -= ssp->gr[SSP_P].v; // maybe only upper word?
1004 // UPD_ACC_ZN // I've seen code checking flags after this
1005 rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
1006 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
1009 // mpya (rj), (ri), b
1011 // dunno if this is correct. What about b?
1012 if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp16: FIXME: no b bit @ %04x", GET_PPC_OFFS());
1013 read_P(); // update P
1014 ssp->gr[SSP_A].v += ssp->gr[SSP_P].v; // maybe only upper word?
1016 rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
1017 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
1020 // mld (rj), (ri), b
1022 // dunno if this is correct. What about b?
1023 if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp16: FIXME: no b bit @ %04x", GET_PPC_OFFS());
1024 ssp->gr[SSP_A].v = 0; // maybe only upper word?
1026 rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
1027 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
1031 case 0x10: tmpv = REG_READ(op & 0x0f); OP_SUBA(tmpv); break;
1032 case 0x30: tmpv = REG_READ(op & 0x0f); OP_CMPA(tmpv); break;
1033 case 0x40: tmpv = REG_READ(op & 0x0f); OP_ADDA(tmpv); break;
1034 case 0x50: tmpv = REG_READ(op & 0x0f); OP_ANDA(tmpv); break;
1035 case 0x60: tmpv = REG_READ(op & 0x0f); OP_ORA (tmpv); break;
1036 case 0x70: tmpv = REG_READ(op & 0x0f); OP_EORA(tmpv); break;
1039 case 0x11: tmpv = ptr1_read(op); OP_SUBA(tmpv); break;
1040 case 0x31: tmpv = ptr1_read(op); OP_CMPA(tmpv); break;
1041 case 0x41: tmpv = ptr1_read(op); OP_ADDA(tmpv); break;
1042 case 0x51: tmpv = ptr1_read(op); OP_ANDA(tmpv); break;
1043 case 0x61: tmpv = ptr1_read(op); OP_ORA (tmpv); break;
1044 case 0x71: tmpv = ptr1_read(op); OP_EORA(tmpv); break;
1047 case 0x03: tmpv = ssp->RAM[op & 0x1ff]; OP_LDA (tmpv); break;
1048 case 0x13: tmpv = ssp->RAM[op & 0x1ff]; OP_SUBA(tmpv); break;
1049 case 0x33: tmpv = ssp->RAM[op & 0x1ff]; OP_CMPA(tmpv); break;
1050 case 0x43: tmpv = ssp->RAM[op & 0x1ff]; OP_ADDA(tmpv); break;
1051 case 0x53: tmpv = ssp->RAM[op & 0x1ff]; OP_ANDA(tmpv); break;
1052 case 0x63: tmpv = ssp->RAM[op & 0x1ff]; OP_ORA (tmpv); break;
1053 case 0x73: tmpv = ssp->RAM[op & 0x1ff]; OP_EORA(tmpv); break;
1056 case 0x14: tmpv = *PC++; OP_SUBA(tmpv); break;
1057 case 0x34: tmpv = *PC++; OP_CMPA(tmpv); break;
1058 case 0x44: tmpv = *PC++; OP_ADDA(tmpv); break;
1059 case 0x54: tmpv = *PC++; OP_ANDA(tmpv); break;
1060 case 0x64: tmpv = *PC++; OP_ORA (tmpv); break;
1061 case 0x74: tmpv = *PC++; OP_EORA(tmpv); break;
1064 case 0x15: tmpv = ptr2_read(op); OP_SUBA(tmpv); break;
1065 case 0x35: tmpv = ptr2_read(op); OP_CMPA(tmpv); break;
1066 case 0x45: tmpv = ptr2_read(op); OP_ADDA(tmpv); break;
1067 case 0x55: tmpv = ptr2_read(op); OP_ANDA(tmpv); break;
1068 case 0x65: tmpv = ptr2_read(op); OP_ORA (tmpv); break;
1069 case 0x75: tmpv = ptr2_read(op); OP_EORA(tmpv); break;
1072 case 0x19: tmpv = rIJ[IJind]; OP_SUBA(tmpv); break;
1073 case 0x39: tmpv = rIJ[IJind]; OP_CMPA(tmpv); break;
1074 case 0x49: tmpv = rIJ[IJind]; OP_ADDA(tmpv); break;
1075 case 0x59: tmpv = rIJ[IJind]; OP_ANDA(tmpv); break;
1076 case 0x69: tmpv = rIJ[IJind]; OP_ORA (tmpv); break;
1077 case 0x79: tmpv = rIJ[IJind]; OP_EORA(tmpv); break;
1080 case 0x1c: OP_SUBA(op & 0xff); break;
1081 case 0x3c: OP_CMPA(op & 0xff); break;
1082 case 0x4c: OP_ADDA(op & 0xff); break;
1083 // MAME code only does LSB of top word, but this looks wrong to me.
1084 case 0x5c: OP_ANDA(op & 0xff); break;
1085 case 0x6c: OP_ORA (op & 0xff); break;
1086 case 0x7c: OP_EORA(op & 0xff); break;
1089 elprintf(EL_ANOMALY|EL_SVP, "ssp16: unhandled op %04x @ %04x", op, GET_PPC_OFFS());
1095 read_P(); // update P
1098 if (ssp->gr[SSP_GR0].v != 0xffff0000)
1099 elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: REG 0 corruption! %08x", ssp->gr[SSP_GR0].v);