1 // basic, incomplete SSP160x (SSP1601?) interpreter
5 * most names taken from MAME code
9 * desc: Constant register with all bits set (0xffff).
13 * desc: Generic register. When set, updates P (P = X * Y * 2) ??
17 * desc: Generic register. When set, updates P (P = X * Y * 2) ??
25 * desc: Status register. From MAME: bits 0-9 are CONTROL, other FLAG
27 * 210 - RPL (?) "Loop size". If non-zero, makes (rX+) and (rX-) respectively
28 * modulo-increment and modulo-decrement. The value shows which
29 * power of 2 to use, i.e. 4 means modulo by 16.
30 * (e: fir16_32.sc, IIR_4B.SC, DECIM.SC)
32 * 5 - GP0_0 (ST5?) Changed before acessing PM0 (affects banking?).
33 * 6 - GP0_1 (ST6?) Cleared before acessing PM0 (affects banking?). Set after.
34 * datasheet says these (5,6) bits correspond to hardware pins.
35 * 7 - IE (?) Not directly used by SVP code (never set, but preserved)?
36 * 8 - OP (?) Not used by SVP code (only cleared)? (MAME: saturated value
37 * (probably means clamping? i.e. 0x7ffc + 9 -> 0x7fff))
38 * 9 - MACS (?) Not used by SVP code (only cleared)? (e: "mac shift")
39 * a - GPI_0 Interrupt 0 enable/status?
40 * b - GPI_1 Interrupt 1 enable/status?
41 * c - L L flag. Carry?
43 * e - OV Overflow flag.
44 * f - N Negative flag.
45 * seen directly changing code sequences:
46 * ldi ST, 0 ld A, ST ld A, ST ld A, ST ldi st, 20h
47 * ldi ST, 60h ori A, 60h and A, E8h and A, E8h
48 * ld ST, A ld ST, A ori 3
53 * desc: hw stack of 6 levels (according to datasheet)
57 * desc: Program counter.
61 * desc: multiply result register. Updated after mp* instructions,
62 * or writes to X or Y (P = X * Y * 2) ??
63 * probably affected by MACS bit in ST.
65 * 8. "PM0" (PM from PMAR name from Tasco's docs)
67 * desc: Programmable Memory access register.
68 * On reset, or when one (both?) GP0 bits are clear,
69 * acts as status for XST, mapped at 015004 at 68k side:
70 * bit0: ssp has written something to XST (cleared when 015004 is read)
71 * bit1: 68k has written something through a1500{0|2} (cleared on PM0 read)
75 * desc: Programmable Memory access register.
76 * This reg. is only used as PMAR.
80 * desc: Programmable Memory access register.
81 * This reg. is only used as PMAR.
85 * desc: eXternal STate. Mapped to a15000 and a15002 at 68k side.
86 * Can be programmed as PMAR? (only seen in test mode code)
87 * Affects PM0 when written to?
91 * desc: Programmable Memory access register.
92 * This reg. is only used as PMAR. The most used PMAR by VR.
96 * 14. "PMC" (PMC from PMAC name from Tasco's docs)
98 * desc: Programmable Memory access Control. Set using 2 16bit writes,
99 * first address, then mode word. After setting PMAC, PMAR sould
100 * be blind accessed (ld -, PMx or ld PMx, -) to program it for
101 * reading and writing respectively.
102 * Reading the register also shifts it's state (from "waiting for
103 * address" to "waiting for mode" and back). Reads always return
104 * address related to last PMx register accressed.
105 * (note: addresses do not wrap).
109 * desc: Accumulator Low. 16 least significant bits of accumulator (not 100% sure)
110 * (normally reading acc (ld X, A) you get 16 most significant bits).
113 * There are 8 8-bit pointer registers rX. r0-r3 (ri) point to RAM0, r4-r7 (rj) point to RAM1.
114 * They can be accessed directly, or 2 indirection levels can be used [ (rX), ((rX)) ],
115 * which work similar to * and ** operators in C, only they use different memory banks and
116 * ((rX)) also does post-increment. First indirection level (rX) accesses RAMx, second accesses
117 * program memory at address read from (rX), and increments value in (rX).
119 * r0,r1,r2,r4,r5,r6 can be modified [ex: ldi r0, 5].
120 * 3 modifiers can be applied (optional):
121 * + : post-increment [ex: ld a, (r0+) ]. Can be made modulo-increment by setting RPL bits in ST.
122 * - : post-decrement. Can be made modulo-decrement by setting RPL bits in ST (not sure).
123 * +!: post-increment, unaffected by RPL (probably).
124 * These are only used on 1st indirection level, so things like [ld a, ((r0+))] and [ld X, r6-]
125 * ar probably invalid.
127 * r3 and r7 are special and can not be changed (at least Samsung samples and SVP code never do).
128 * They are fixed to the start of their RAM banks. (They are probably changeable for ssp1605+,
129 * Samsung's old DSP page claims that).
130 * 1 of these 4 modifiers must be used (short form direct addressing?):
131 * |00: RAMx[0] [ex: (r3|00), 0] (based on sample code)
133 * |10: RAMx[2] ? maybe 10h? accortding to Div_c_dp.sc, 2
139 * ld a, * doesn't affect flags! (e: A_LAW.SC, Div_c_dp.sc)
141 * mld (rj), (ri) [, b]
142 * operation: A = 0; P = (rj) * (ri)
143 * notes: based on IIR_4B.SC sample. flags? what is b???
145 * mpya (rj), (ri) [, b]
146 * name: multiply and add?
147 * operation: A += P; P = (rj) * (ri)
150 * name: multiply and subtract?
151 * notes: not used by VR code.
154 * mod cond, shr does arithmetic shift
156 * 'ld -, AL' and probably 'ld AL, -' are for dummy assigns
159 * 000000 - 1fffff ROM, accessable by both
160 * 200000 - 2fffff unused?
161 * 300000 - 31ffff DRAM, both
162 * 320000 - 38ffff unused?
163 * 390000 - 3907ff IRAM. can only be accessed by ssp?
164 * 390000 - 39ffff similar mapping to "cell arrange" in Sega CD, 68k only?
165 * 3a0000 - 3affff similar mapping to "cell arrange" in Sega CD, a bit different
167 * 30fe02 - 0 if SVP busy, 1 if done (set by SVP, checked and cleared by 68k)
168 * 30fe06 - also sync related.
169 * 30fe08 - job number [1-12] for SVP. 0 means no job. Set by 68k, read-cleared by SVP.
172 * + figure out if 'op A, P' is 32bit (nearly sure it is)
173 * * what exactly is AL?
174 * * does mld, mpya load their operands into X and Y?
178 * pressing all buttons while resetting game will kick into test mode
180 * Assumptions in this code
181 * P is not directly writeable
182 * flags correspond to full 32bit accumulator
183 * only Z and N status flags are emulated (others unused by SVP)
184 * modifiers for 'OP a, ri' are ignored (invalid?/not used by SVP)
185 * modifiers '+' and '+!' act the same (this is most likely wrong)
186 * 'ld d, (a)' loads from program ROM
189 #include "../../PicoInt.h"
191 #define u32 unsigned int
193 //#define USE_DEBUGGER
196 #define rX ssp->gr[SSP_X].h
197 #define rY ssp->gr[SSP_Y].h
198 #define rA ssp->gr[SSP_A].h
199 #define rST ssp->gr[SSP_ST].h // 4
200 #define rSTACK ssp->gr[SSP_STACK].h
201 #define rPC ssp->gr[SSP_PC].h
202 #define rP ssp->gr[SSP_P]
203 #define rPM0 ssp->gr[SSP_PM0].h // 8
204 #define rPM1 ssp->gr[SSP_PM1].h
205 #define rPM2 ssp->gr[SSP_PM2].h
206 #define rXST ssp->gr[SSP_XST].h
207 #define rPM4 ssp->gr[SSP_PM4].h // 12
209 #define rPMC ssp->gr[SSP_PMC] // will keep addr in .h, mode in .l
210 #define rAL ssp->gr[SSP_A].l
212 #define rA32 ssp->gr[SSP_A].v
215 #define IJind (((op>>6)&4)|(op&3))
217 #define GET_PC() (PC - (unsigned short *)svp->iram_rom)
218 #define GET_PPC_OFFS() ((unsigned int)PC - (unsigned int)svp->iram_rom - 2)
219 #define SET_PC(d) PC = (unsigned short *)svp->iram_rom + d
221 #define REG_READ(r) (((r) <= 4) ? ssp->gr[r].h : read_handlers[r]())
222 #define REG_WRITE(r,d) { \
224 if (r1 >= 4) write_handlers[r1](d); \
225 else if (r1 > 0) ssp->gr[r1].h = d; \
229 #define SSP_FLAG_L (1<<0xc)
230 #define SSP_FLAG_Z (1<<0xd)
231 #define SSP_FLAG_V (1<<0xe)
232 #define SSP_FLAG_N (1<<0xf)
234 // update ZN according to 32bit ACC.
236 rST &= ~(SSP_FLAG_Z|SSP_FLAG_N); \
237 if (!rA32) rST |= SSP_FLAG_Z; \
238 else rST |= (rA32>>16)&SSP_FLAG_N;
240 // it seems SVP code never checks for L and OV, so we leave them out.
241 // rST |= (t>>4)&SSP_FLAG_L;
243 rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
244 if (!rA32) rST |= SSP_FLAG_Z; \
245 else rST |= (rA32>>16)&SSP_FLAG_N;
247 // standard cond processing.
248 // again, only Z and N is checked, as SVP doesn't seem to use any other conds.
251 case 0x00: cond = 1; break; /* always true */ \
252 case 0x50: cond = !((rST ^ (op<<5)) & SSP_FLAG_Z); break; /* Z matches f(?) bit */ \
253 case 0x70: cond = !((rST ^ (op<<7)) & SSP_FLAG_N); break; /* N matches f(?) bit */ \
254 default:elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: unimplemented cond @ %04x", GET_PPC_OFFS()); break; \
257 // ops with accumulator.
258 // how is low word really affected by these?
259 // nearly sure 'ld A' doesn't affect flags
263 #define OP_LDA32(x) \
266 #define OP_SUBA(x) { \
271 #define OP_SUBA32(x) { \
276 #define OP_CMPA(x) { \
277 u32 t = rA32 - ((x) << 16); \
278 rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
279 if (!t) rST |= SSP_FLAG_Z; \
280 else rST |= (t>>16)&SSP_FLAG_N; \
283 #define OP_CMPA32(x) { \
284 u32 t = rA32 - (x); \
285 rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
286 if (!t) rST |= SSP_FLAG_Z; \
287 else rST |= (t>>16)&SSP_FLAG_N; \
290 #define OP_ADDA(x) { \
295 #define OP_ADDA32(x) { \
304 #define OP_ANDA32(x) \
312 #define OP_ORA32(x) \
320 #define OP_EORA32(x) \
325 #define OP_CHECK32(OP) \
326 if ((op & 0x0f) == SSP_P) { /* A <- P */ \
327 read_P(); /* update P */ \
328 OP(ssp->gr[SSP_P].v); \
333 static ssp1601_t *ssp = NULL;
334 static unsigned short *PC;
338 static int running = 0;
339 static int last_iram = 0;
342 // -----------------------------------------------------
343 // register i/o handlers
346 static u32 read_unknown(void)
348 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: unknown read @ %04x", GET_PPC_OFFS());
352 static void write_unknown(u32 d)
354 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: unknown write @ %04x", GET_PPC_OFFS());
358 static void write_ST(u32 d)
360 //if ((rST ^ d) & 0x0007) elprintf(EL_SVP, "ssp RPL %i -> %i @ %04x", rST&7, d&7, GET_PPC_OFFS());
361 if ((rST ^ d) & 0x0f98) elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME ST %04x -> %04x @ %04x", rST, d, GET_PPC_OFFS());
366 static u32 read_STACK(void)
369 if ((short)rSTACK < 0) {
371 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: stack underflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
373 return ssp->stack[rSTACK];
376 static void write_STACK(u32 d)
379 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: stack overflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
382 ssp->stack[rSTACK++] = d;
386 static u32 read_PC(void)
391 static void write_PC(u32 d)
398 static u32 read_P(void)
400 int m1 = (signed short)rX;
401 int m2 = (signed short)rY;
402 rP.v = (m1 * m2 * 2);
406 // -----------------------------------------------------
408 static int get_inc(int mode)
410 int inc = (mode >> 11) & 7;
413 inc = (1<<16) << inc; // 0 1 2 4 8 16 32 128
414 if (mode & 0x8000) inc = -inc; // decrement mode
419 #define overwite_write(dst, d) \
421 if (d & 0xf000) { dst &= ~0xf000; dst |= d & 0xf000; } \
422 if (d & 0x0f00) { dst &= ~0x0f00; dst |= d & 0x0f00; } \
423 if (d & 0x00f0) { dst &= ~0x00f0; dst |= d & 0x00f0; } \
424 if (d & 0x000f) { dst &= ~0x000f; dst |= d & 0x000f; } \
427 static u32 pm_io(int reg, int write, u32 d)
429 if (ssp->emu_status & SSP_PMC_SET)
431 // this MUST be blind r or w
432 if ((*(PC-1) & 0xff0f) && (*(PC-1) & 0xfff0)) {
433 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: tried to set PM%i (%c) with non-blind i/o %08x @ %04x",
434 reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
435 ssp->emu_status &= ~SSP_PMC_SET;
438 elprintf(EL_SVP, "PM%i (%c) set to %08x @ %04x", reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
439 ssp->pmac_read[write ? reg + 6 : reg] = rPMC.v;
440 ssp->emu_status &= ~SSP_PMC_SET;
441 if ((rPMC.v & 0x7f) == 0x1c && (rPMC.v & 0x7fff0000) == 0) {
442 elprintf(EL_SVP, "ssp IRAM copy from %06x", (ssp->RAM1[0]-1)<<1);
444 last_iram = (ssp->RAM1[0]-1)<<1;
451 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
452 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i (%c) with only addr set @ %04x",
453 reg, write ? 'w' : 'r', GET_PPC_OFFS());
454 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
457 if (reg == 4 || (rST & 0x60))
459 #define CADDR ((((mode<<16)&0x7f0000)|addr)<<1)
460 unsigned short *dram = (unsigned short *)svp->dram;
463 int mode = ssp->pmac_write[reg]&0xffff;
464 int addr = ssp->pmac_write[reg]>>16;
465 if ((mode & 0xb800) == 0xb800)
466 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: mode %04x", mode);
467 if ((mode & 0x43ff) == 0x0018) // DRAM
469 int inc = get_inc(mode);
470 elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (inc %i, ovrw %i)",
471 reg, CADDR, d, inc >> 16, (mode>>10)&1);
473 overwite_write(dram[addr], d);
474 } else dram[addr] = d;
475 ssp->pmac_write[reg] += inc;
477 else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
479 elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (cell inc, ovrw %i) @ %04x",
480 reg, CADDR, d, (mode>>10)&1, GET_PPC_OFFS());
482 overwite_write(dram[addr], d);
483 } else dram[addr] = d;
484 ssp->pmac_write[reg] += (addr&1) ? (31<<16) : (1<<16);
486 else if ((mode & 0x47ff) == 0x001c) // IRAM
488 int inc = get_inc(mode);
489 if ((addr&0xfc00) != 0x8000)
490 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid IRAM addr: %04x", addr<<1);
491 elprintf(EL_SVP, "ssp IRAM w [%06x] %04x (inc %i)", (addr<<1)&0x7ff, d, inc >> 16);
492 ((unsigned short *)svp->iram_rom)[addr&0x3ff] = d;
493 ssp->pmac_write[reg] += inc;
497 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i unhandled write mode %04x, [%06x] %04x @ %04x",
498 reg, mode, CADDR, d, GET_PPC_OFFS());
503 int mode = ssp->pmac_read[reg]&0xffff;
504 int addr = ssp->pmac_read[reg]>>16;
505 if ((mode & 0xfff0) == 0x0800) // ROM, inc 1, verified to be correct
507 elprintf(EL_SVP, "ssp ROM r [%06x] %04x", CADDR,
508 ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)]);
509 if ((signed int)ssp->pmac_read[reg] >> 16 == -1)
510 ssp->pmac_read[reg]++;
511 ssp->pmac_read[reg] += 1<<16;
512 d = ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)];
514 else if ((mode & 0x47ff) == 0x0018) // DRAM
516 int inc = get_inc(mode);
517 elprintf(EL_SVP, "ssp PM%i DRAM r [%06x] %04x (inc %i)", reg, CADDR, dram[addr], inc >> 16);
519 ssp->pmac_read[reg] += inc;
523 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i unhandled read mode %04x, [%06x] @ %04x",
524 reg, mode, CADDR, GET_PPC_OFFS());
529 // PMC value corresponds to last PMR accessed (not sure).
530 rPMC.v = ssp->pmac_read[write ? reg + 6 : reg];
539 static u32 read_PM0(void)
541 u32 d = pm_io(0, 0, 0);
542 if (d != (u32)-1) return d;
543 elprintf(EL_SVP, "PM0 raw r %04x @ %04x", rPM0, GET_PPC_OFFS());
545 if (!(d & 2) && (GET_PPC_OFFS() == 0x800 || GET_PPC_OFFS() == 0x1851E)) {
546 ssp->emu_status |= SSP_WAIT_PM0; elprintf(EL_SVP, "det TIGHT loop: PM0");
552 static void write_PM0(u32 d)
554 u32 r = pm_io(0, 1, d);
555 if (r != (u32)-1) return;
556 elprintf(EL_SVP, "PM0 raw w %04x @ %04x", d, GET_PPC_OFFS());
561 static u32 read_PM1(void)
563 u32 d = pm_io(1, 0, 0);
564 if (d != (u32)-1) return d;
566 elprintf(EL_SVP, "PM1 raw r %04x @ %04x", rPM1, GET_PPC_OFFS());
570 static void write_PM1(u32 d)
572 u32 r = pm_io(1, 1, d);
573 if (r != (u32)-1) return;
575 elprintf(EL_SVP, "PM1 raw w %04x @ %04x", d, GET_PPC_OFFS());
580 static u32 read_PM2(void)
582 u32 d = pm_io(2, 0, 0);
583 if (d != (u32)-1) return d;
585 elprintf(EL_SVP, "PM2 raw r %04x @ %04x", rPM2, GET_PPC_OFFS());
589 static void write_PM2(u32 d)
591 u32 r = pm_io(2, 1, d);
592 if (r != (u32)-1) return;
594 elprintf(EL_SVP, "PM2 raw w %04x @ %04x", d, GET_PPC_OFFS());
599 static u32 read_XST(void)
602 u32 d = pm_io(3, 0, 0);
603 if (d != (u32)-1) return d;
605 elprintf(EL_SVP, "XST raw r %04x @ %04x", rXST, GET_PPC_OFFS());
609 static void write_XST(u32 d)
612 u32 r = pm_io(3, 1, d);
613 if (r != (u32)-1) return;
615 elprintf(EL_SVP, "XST raw w %04x @ %04x", d, GET_PPC_OFFS());
621 static u32 read_PM4(void)
623 u32 d = pm_io(4, 0, 0);
625 switch (GET_PPC_OFFS()) {
626 case 0x0854: ssp->emu_status |= SSP_WAIT_30FE08; elprintf(EL_SVP, "det TIGHT loop: [30fe08]"); break;
627 case 0x4f12: ssp->emu_status |= SSP_WAIT_30FE06; elprintf(EL_SVP, "det TIGHT loop: [30fe06]"); break;
630 if (d != (u32)-1) return d;
632 elprintf(EL_SVP, "PM4 raw r %04x @ %04x", rPM4, GET_PPC_OFFS());
636 static void write_PM4(u32 d)
638 u32 r = pm_io(4, 1, d);
639 if (r != (u32)-1) return;
641 elprintf(EL_SVP, "PM4 raw w %04x @ %04x", d, GET_PPC_OFFS());
646 static u32 read_PMC(void)
648 elprintf(EL_SVP, "PMC r a %04x (st %c) @ %04x", rPMC.h,
649 (ssp->emu_status & SSP_PMC_HAVE_ADDR) ? 'm' : 'a', GET_PPC_OFFS());
650 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
651 //if (ssp->emu_status & SSP_PMC_SET)
652 // elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
653 ssp->emu_status |= SSP_PMC_SET;
654 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
656 ssp->emu_status |= SSP_PMC_HAVE_ADDR;
661 static void write_PMC(u32 d)
663 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
664 //if (ssp->emu_status & SSP_PMC_SET)
665 // elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
666 ssp->emu_status |= SSP_PMC_SET;
667 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
669 elprintf(EL_SVP, "PMC w m %04x @ %04x", rPMC.l, GET_PPC_OFFS());
671 ssp->emu_status |= SSP_PMC_HAVE_ADDR;
673 elprintf(EL_SVP, "PMC w a %04x @ %04x", rPMC.h, GET_PPC_OFFS());
678 static u32 read_AL(void)
680 if (*(PC-1) == 0x000f) {
681 elprintf(EL_SVP, "ssp dummy PM assign %08x @ %04x", rPMC.v, GET_PPC_OFFS());
682 ssp->emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR); // ?
687 static void write_AL(u32 d)
693 typedef u32 (*read_func_t)(void);
694 typedef void (*write_func_t)(u32 d);
696 static read_func_t read_handlers[16] =
698 read_unknown, read_unknown, read_unknown, read_unknown, // -, X, Y, A
699 read_unknown, // 4 ST
708 read_unknown, // 13 gr13
713 static write_func_t write_handlers[16] =
715 write_unknown, write_unknown, write_unknown, write_unknown, // -, X, Y, A
716 // write_unknown, // 4 ST
717 write_ST, // 4 ST (debug hook)
720 write_unknown, // 7 P
726 write_unknown, // 13 gr13
731 // -----------------------------------------------------
732 // pointer register handlers
735 #define ptr1_read(op) ptr1_read_(op&3,(op>>6)&4,(op<<1)&0x18)
737 static u32 ptr1_read_(int ri, int isj2, int modi3)
739 //int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
740 u32 mask, add = 0, t = ri | isj2 | modi3;
741 unsigned char *rp = NULL;
747 case 0x02: return ssp->RAM0[ssp->r0[t&3]];
748 case 0x03: return ssp->RAM0[0];
751 case 0x06: return ssp->RAM1[ssp->r1[t&3]];
752 case 0x07: return ssp->RAM1[0];
756 case 0x0a: return ssp->RAM0[ssp->r0[t&3]++];
757 case 0x0b: return ssp->RAM0[1];
760 case 0x0e: return ssp->RAM1[ssp->r1[t&3]++];
761 case 0x0f: return ssp->RAM1[1];
765 case 0x12: rp = &ssp->r0[t&3]; t = ssp->RAM0[*rp];
766 if (!(rST&7)) { (*rp)--; return t; }
767 add = -1; goto modulo;
768 case 0x13: return ssp->RAM0[2];
771 case 0x16: rp = &ssp->r1[t&3]; t = ssp->RAM1[*rp];
772 if (!(rST&7)) { (*rp)--; return t; }
773 add = -1; goto modulo;
774 case 0x17: return ssp->RAM1[2];
778 case 0x1a: rp = &ssp->r0[t&3]; t = ssp->RAM0[*rp];
779 if (!(rST&7)) { (*rp)++; return t; }
780 add = 1; goto modulo;
781 case 0x1b: return ssp->RAM0[3];
784 case 0x1e: rp = &ssp->r1[t&3]; t = ssp->RAM1[*rp];
785 if (!(rST&7)) { (*rp)++; return t; }
786 add = 1; goto modulo;
787 case 0x1f: return ssp->RAM1[3];
793 mask = (1 << (rST&7)) - 1;
794 *rp = (*rp & ~mask) | ((*rp + add) & mask);
798 static void ptr1_write(int op, u32 d)
800 int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
806 case 0x02: ssp->RAM0[ssp->r0[t&3]] = d; return;
807 case 0x03: ssp->RAM0[0] = d; return;
810 case 0x06: ssp->RAM1[ssp->r1[t&3]] = d; return;
811 case 0x07: ssp->RAM1[0] = d; return;
819 case 0x1a: ssp->RAM0[ssp->r0[t&3]++] = d; return;
820 case 0x0b: ssp->RAM0[1] = d; return;
826 case 0x1e: ssp->RAM1[ssp->r1[t&3]++] = d; return;
827 case 0x0f: ssp->RAM1[1] = d; return;
831 case 0x12: ssp->RAM0[ssp->r0[t&3]--] = d; return;
832 case 0x13: ssp->RAM0[2] = d; return;
835 case 0x16: ssp->RAM1[ssp->r1[t&3]--] = d; return;
836 case 0x17: ssp->RAM1[2] = d; return;
838 case 0x1b: ssp->RAM0[3] = d; return;
839 case 0x1f: ssp->RAM1[3] = d; return;
843 static u32 ptr2_read(int op)
845 int mv = 0, t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
851 case 0x02: mv = ssp->RAM0[ssp->r0[t&3]]++; break;
852 case 0x03: mv = ssp->RAM0[0]++; break;
855 case 0x06: mv = ssp->RAM1[ssp->r1[t&3]]++; break;
856 case 0x07: mv = ssp->RAM1[0]++; break;
858 case 0x0b: mv = ssp->RAM0[1]++; break;
859 case 0x0f: mv = ssp->RAM1[1]++; break;
861 case 0x13: mv = ssp->RAM0[2]++; break;
862 case 0x17: mv = ssp->RAM1[2]++; break;
864 case 0x1b: mv = ssp->RAM0[3]++; break;
865 case 0x1f: mv = ssp->RAM1[3]++; break;
866 default: elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid mod in ((rX))? @ %04x", GET_PPC_OFFS());
870 return ((unsigned short *)svp->iram_rom)[mv];
874 // -----------------------------------------------------
876 void ssp1601_reset(ssp1601_t *l_ssp)
880 ssp->gr[SSP_GR0].v = 0xffff0000;
882 rSTACK = 0; // ? using ascending stack
888 static void debug_dump(void)
890 printf("GR0: %04x X: %04x Y: %04x A: %08x\n", ssp->gr[SSP_GR0].h, rX, rY, ssp->gr[SSP_A].v);
891 printf("PC: %04x (%04x) P: %08x\n", GET_PC(), GET_PC() << 1, ssp->gr[SSP_P].v);
892 printf("PM0: %04x PM1: %04x PM2: %04x\n", rPM0, rPM1, rPM2);
893 printf("XST: %04x PM4: %04x PMC: %08x\n", rXST, rPM4, ssp->gr[SSP_PMC].v);
894 printf(" ST: %04x %c%c%c%c, GP0_0 %i, GP0_1 %i\n", rST, rST&SSP_FLAG_N?'N':'n', rST&SSP_FLAG_V?'V':'v',
895 rST&SSP_FLAG_Z?'Z':'z', rST&SSP_FLAG_L?'L':'l', (rST>>5)&1, (rST>>6)&1);
896 printf("STACK: %i %04x %04x %04x %04x %04x %04x\n", rSTACK, ssp->stack[0], ssp->stack[1],
897 ssp->stack[2], ssp->stack[3], ssp->stack[4], ssp->stack[5]);
898 printf("r0-r2: %02x %02x %02x r4-r6: %02x %02x %02x\n", rIJ[0], rIJ[1], rIJ[2], rIJ[4], rIJ[5], rIJ[6]);
899 elprintf(EL_SVP, "cycles: %i, emu_status: %x", g_cycles, ssp->emu_status);
902 static void debug_dump_mem(void)
906 for (h = 0; h < 32; h++)
908 if (h == 16) printf("RAM1\n");
909 printf("%03x:", h*16);
910 for (i = 0; i < 16; i++)
911 printf(" %04x", ssp->RAM[h*16+i]);
916 static void debug_dump2file(const char *fname, void *mem, int len)
918 FILE *f = fopen(fname, "wb");
919 unsigned short *p = mem;
922 for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
923 fwrite(mem, 1, len, f);
925 for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
926 printf("dumped to %s\n", fname);
929 printf("dump failed\n");
932 static int bpts[10] = { 0, };
934 static void debug(unsigned int pc, unsigned int op)
936 static char buffo[64] = {0,};
937 char buff[64] = {0,};
941 for (i = 0; i < 10; i++)
942 if (pc != 0 && bpts[i] == pc) {
943 printf("breakpoint %i\n", i);
950 printf("%04x (%02x) @ %04x\n", op, op >> 9, pc<<1);
956 fgets(buff, sizeof(buff), stdin);
957 if (buff[0] == '\n') strcpy(buff, buffo);
958 else strcpy(buffo, buff);
963 case 'r': running = 1; return;
966 case 'x': debug_dump(); break;
967 case 'm': debug_dump_mem(); break;
969 char *baddr = buff + 2;
971 if (buff[3] == ' ') { i = buff[2] - '0'; baddr = buff + 4; }
972 bpts[i] = strtol(baddr, NULL, 16) >> 1;
973 printf("breakpoint %i set @ %04x\n", i, bpts[i]<<1);
977 sprintf(buff, "iramrom_%04x.bin", last_iram);
978 debug_dump2file(buff, svp->iram_rom, sizeof(svp->iram_rom));
979 debug_dump2file("dram.bin", svp->dram, sizeof(svp->dram));
981 default: printf("unknown command\n"); break;
985 #endif // USE_DEBUGGER
988 void ssp1601_run(int cycles)
993 while (g_cycles > 0 && !(ssp->emu_status & SSP_WAIT_MASK))
1000 debug(GET_PC()-1, op);
1006 if (op == 0) break; // nop
1007 if (op == ((SSP_A<<4)|SSP_P)) { // A <- P
1008 // not sure. MAME claims that only hi word is transfered.
1009 read_P(); // update P
1010 rA32 = ssp->gr[SSP_P].v;
1014 tmpv = REG_READ(op & 0x0f);
1015 REG_WRITE((op & 0xf0) >> 4, tmpv);
1020 case 0x01: tmpv = ptr1_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1023 case 0x02: tmpv = REG_READ((op & 0xf0) >> 4); ptr1_write(op, tmpv); break;
1026 case 0x04: tmpv = *PC++; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1029 case 0x05: tmpv = ptr2_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1032 case 0x06: tmpv = *PC++; ptr1_write(op, tmpv); break;
1035 case 0x07: ssp->RAM[op & 0x1ff] = rA; break;
1038 case 0x09: tmpv = rIJ[(op&3)|((op>>6)&4)]; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1041 case 0x0a: rIJ[(op&3)|((op>>6)&4)] = REG_READ((op & 0xf0) >> 4); break;
1047 case 0x0f: rIJ[(op>>8)&7] = op; break;
1053 if (cond) { int new_PC = *PC++; write_STACK(GET_PC()); write_PC(new_PC); }
1059 case 0x25: tmpv = ((unsigned short *)svp->iram_rom)[rA]; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1065 if (cond) { int new_PC = *PC++; write_PC(new_PC); }
1076 case 2: rA32 = (signed int)rA32 >> 1; break; // shr (arithmetic)
1077 case 3: rA32 <<= 1; break; // shl
1078 case 6: rA32 = -(signed int)rA32; break; // neg
1079 case 7: if ((int)rA32 < 0) rA32 = -(signed int)rA32; break; // abs
1080 default: elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: unhandled mod %i @ %04x",
1081 op&7, GET_PPC_OFFS());
1090 if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: no b bit @ %04x", GET_PPC_OFFS());
1091 read_P(); // update P
1092 rA32 -= ssp->gr[SSP_P].v; // maybe only upper word?
1093 UPD_ACC_ZN // there checking flags after this
1094 rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
1095 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
1098 // mpya (rj), (ri), b
1100 if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: no b bit @ %04x", GET_PPC_OFFS());
1101 read_P(); // update P
1102 rA32 += ssp->gr[SSP_P].v; // confirmed to be 32bit
1104 rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
1105 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
1108 // mld (rj), (ri), b
1110 if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: no b bit @ %04x", GET_PPC_OFFS());
1113 rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
1114 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
1118 case 0x10: OP_CHECK32(OP_SUBA32); tmpv = REG_READ(op & 0x0f); OP_SUBA(tmpv); break;
1119 case 0x30: OP_CHECK32(OP_CMPA32); tmpv = REG_READ(op & 0x0f); OP_CMPA(tmpv); break;
1120 case 0x40: OP_CHECK32(OP_ADDA32); tmpv = REG_READ(op & 0x0f); OP_ADDA(tmpv); break;
1121 case 0x50: OP_CHECK32(OP_ANDA32); tmpv = REG_READ(op & 0x0f); OP_ANDA(tmpv); break;
1122 case 0x60: OP_CHECK32(OP_ORA32 ); tmpv = REG_READ(op & 0x0f); OP_ORA (tmpv); break;
1123 case 0x70: OP_CHECK32(OP_EORA32); tmpv = REG_READ(op & 0x0f); OP_EORA(tmpv); break;
1126 case 0x11: tmpv = ptr1_read(op); OP_SUBA(tmpv); break;
1127 case 0x31: tmpv = ptr1_read(op); OP_CMPA(tmpv); break;
1128 case 0x41: tmpv = ptr1_read(op); OP_ADDA(tmpv); break;
1129 case 0x51: tmpv = ptr1_read(op); OP_ANDA(tmpv); break;
1130 case 0x61: tmpv = ptr1_read(op); OP_ORA (tmpv); break;
1131 case 0x71: tmpv = ptr1_read(op); OP_EORA(tmpv); break;
1134 case 0x03: tmpv = ssp->RAM[op & 0x1ff]; OP_LDA (tmpv); break;
1135 case 0x13: tmpv = ssp->RAM[op & 0x1ff]; OP_SUBA(tmpv); break;
1136 case 0x33: tmpv = ssp->RAM[op & 0x1ff]; OP_CMPA(tmpv); break;
1137 case 0x43: tmpv = ssp->RAM[op & 0x1ff]; OP_ADDA(tmpv); break;
1138 case 0x53: tmpv = ssp->RAM[op & 0x1ff]; OP_ANDA(tmpv); break;
1139 case 0x63: tmpv = ssp->RAM[op & 0x1ff]; OP_ORA (tmpv); break;
1140 case 0x73: tmpv = ssp->RAM[op & 0x1ff]; OP_EORA(tmpv); break;
1143 case 0x14: tmpv = *PC++; OP_SUBA(tmpv); break;
1144 case 0x34: tmpv = *PC++; OP_CMPA(tmpv); break;
1145 case 0x44: tmpv = *PC++; OP_ADDA(tmpv); break;
1146 case 0x54: tmpv = *PC++; OP_ANDA(tmpv); break;
1147 case 0x64: tmpv = *PC++; OP_ORA (tmpv); break;
1148 case 0x74: tmpv = *PC++; OP_EORA(tmpv); break;
1151 case 0x15: tmpv = ptr2_read(op); OP_SUBA(tmpv); break;
1152 case 0x35: tmpv = ptr2_read(op); OP_CMPA(tmpv); break;
1153 case 0x45: tmpv = ptr2_read(op); OP_ADDA(tmpv); break;
1154 case 0x55: tmpv = ptr2_read(op); OP_ANDA(tmpv); break;
1155 case 0x65: tmpv = ptr2_read(op); OP_ORA (tmpv); break;
1156 case 0x75: tmpv = ptr2_read(op); OP_EORA(tmpv); break;
1159 case 0x19: tmpv = rIJ[IJind]; OP_SUBA(tmpv); break;
1160 case 0x39: tmpv = rIJ[IJind]; OP_CMPA(tmpv); break;
1161 case 0x49: tmpv = rIJ[IJind]; OP_ADDA(tmpv); break;
1162 case 0x59: tmpv = rIJ[IJind]; OP_ANDA(tmpv); break;
1163 case 0x69: tmpv = rIJ[IJind]; OP_ORA (tmpv); break;
1164 case 0x79: tmpv = rIJ[IJind]; OP_EORA(tmpv); break;
1167 case 0x1c: OP_SUBA(op & 0xff); if (op&0x100) elprintf(EL_SVP|EL_ANOMALY, "FIXME: simm with upper bit set"); break;
1168 case 0x3c: OP_CMPA(op & 0xff); if (op&0x100) elprintf(EL_SVP|EL_ANOMALY, "FIXME: simm with upper bit set"); break;
1169 case 0x4c: OP_ADDA(op & 0xff); if (op&0x100) elprintf(EL_SVP|EL_ANOMALY, "FIXME: simm with upper bit set"); break;
1170 // MAME code only does LSB of top word, but this looks wrong to me.
1171 case 0x5c: OP_ANDA(op & 0xff); if (op&0x100) elprintf(EL_SVP|EL_ANOMALY, "FIXME: simm with upper bit set"); break;
1172 case 0x6c: OP_ORA (op & 0xff); if (op&0x100) elprintf(EL_SVP|EL_ANOMALY, "FIXME: simm with upper bit set"); break;
1173 case 0x7c: OP_EORA(op & 0xff); if (op&0x100) elprintf(EL_SVP|EL_ANOMALY, "FIXME: simm with upper bit set"); break;
1176 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME unhandled op %04x @ %04x", op, GET_PPC_OFFS());
1182 read_P(); // update P
1185 if (ssp->gr[SSP_GR0].v != 0xffff0000)
1186 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: REG 0 corruption! %08x", ssp->gr[SSP_GR0].v);