9 .global flush_inval_caches
14 @ translation cache buffer
17 .size tcache, TCACHE_SIZE
27 mov r2, #0x0 @ must be 0
32 @ SSP_GR0, SSP_X, SSP_Y, SSP_A,
33 @ SSP_ST, SSP_STACK, SSP_PC, SSP_P,
34 @ SSP_PM0, SSP_PM1, SSP_PM2, SSP_XST,
35 @ SSP_PM4, SSP_gr13, SSP_PMC, SSP_AL
40 @ r6: STACK and emu flags: sss0 * .uu. .lll NZCV (NZCV is PSR bits from ARM)
54 ldmia r2, {r3,r4,r5,r6,r8}
57 orr r4, r3, r4, lsr #16 @ XXYY
60 mov r8, r8, lsl #13 @ sss0 *
65 orrne r8, r8, #0x4 @ sss0 * NZ..
66 orr r6, r8, r9, lsr #12 @ sss0 * .uu. .lll NZ..
68 ldr r8, [r7, #0x440] @ r0-r2
69 ldr r9, [r7, #0x444] @ r4-r6
70 ldr r10,[r7, #(0x400+7*4)] @ P
75 str r10,[r7, #(0x400+7*4)] @ P
76 str r8, [r7, #0x440] @ r0-r2
77 str r9, [r7, #0x444] @ r4-r6
80 and r9, r9, #(7<<16) @ STACK
82 msr cpsr_flg, r3 @ to to ARM PSR
85 orrmi r6, r6, #0x80000000 @ N
86 orreq r6, r6, #0x20000000 @ Z
88 mov r3, r4, lsl #16 @ Y
90 mov r2, r2, lsl #16 @ X
93 stmia r8, {r2,r3,r5,r6,r9}
97 #define SSP_OFFS_GR 0x400
98 #define SSP_OFFS_EMUST 0x484
101 #define SSP_WAIT_PM0 0x2000
108 stmfd sp!, {r4-r11, lr}
112 ldr r0, [r7, #(SSP_OFFS_GR+SSP_PM0*4)]
113 ldr r1, [r7, #SSP_OFFS_EMUST]
115 orreq r1, r1, #SSP_WAIT_PM0
117 streq r1, [r7, #SSP_OFFS_EMUST]
118 movne r0, #0x04000000
119 orrne r0, r0, #0x00040000
120 strne r0, [r7, #(SSP_OFFS_GR+SSP_PC*4)]
124 ldmfd sp!, {r4-r11, lr}