1 // Memory I/O handlers for Sega/Mega CD.
\r
2 // Loosely based on Gens code.
\r
3 // (c) Copyright 2007, Grazvydas "notaz" Ignotas
\r
6 #include "../PicoInt.h"
\r
8 #include "../sound/ym2612.h"
\r
9 #include "../sound/sn76496.h"
\r
14 #ifndef UTYPES_DEFINED
\r
15 typedef unsigned char u8;
\r
16 typedef unsigned short u16;
\r
17 typedef unsigned int u32;
\r
18 #define UTYPES_DEFINED
\r
21 //#define rdprintf dprintf
\r
22 #define rdprintf(...)
\r
23 //#define wrdprintf dprintf
\r
24 #define wrdprintf(...)
\r
26 #ifdef EMU_CORE_DEBUG
\r
27 extern u32 lastread_a, lastread_d[16], lastwrite_cyc_d[16];
\r
28 extern int lrp_cyc, lwp_cyc;
\r
29 #undef USE_POLL_DETECT
\r
32 // -----------------------------------------------------------------
\r
35 #define POLL_LIMIT 16
\r
36 #define POLL_CYCLES 124
\r
37 // int m68k_poll_addr, m68k_poll_cnt;
\r
38 unsigned int s68k_poll_adclk, s68k_poll_cnt;
\r
40 #ifndef _ASM_CD_MEMORY_C
\r
41 static u32 m68k_reg_read16(u32 a)
\r
45 // dprintf("m68k_regs r%2i: [%02x] @%06x", realsize&~1, a+(realsize&1), SekPc);
\r
49 d = ((Pico_mcd->s68k_regs[0x33]<<13)&0x8000) | Pico_mcd->m.busreq; // here IFL2 is always 0, just like in Gens
\r
52 d = (Pico_mcd->s68k_regs[a]<<8) | (Pico_mcd->s68k_regs[a+1]&0xc7);
\r
53 // the DMNA delay must only be visible on s68k side (Lunar2, Silpheed)
\r
54 if (Pico_mcd->m.state_flags&2) { d &= ~1; d |= 2; }
\r
55 //printf("m68k_regs r3: %02x @%06x\n", (u8)d, SekPc);
\r
58 d = Pico_mcd->s68k_regs[4]<<8;
\r
61 d = *(u16 *)(Pico_mcd->bios + 0x72);
\r
64 d = Read_CDC_Host(0);
\r
67 elprintf(EL_UIO, "m68k FIXME: reserved read");
\r
70 d = Pico_mcd->m.timer_stopwatch >> 16;
\r
71 dprintf("m68k stopwatch timer read (%04x)", d);
\r
76 // comm flag/cmd/status (0xE-0x2F)
\r
77 d = (Pico_mcd->s68k_regs[a]<<8) | Pico_mcd->s68k_regs[a+1];
\r
81 elprintf(EL_UIO, "m68k_regs FIXME invalid read @ %02x", a);
\r
89 #ifndef _ASM_CD_MEMORY_C
\r
92 void m68k_reg_write8(u32 a, u32 d)
\r
95 // dprintf("m68k_regs w%2i: [%02x] %02x @%06x", realsize, a, d, SekPc);
\r
100 if ((d&1) && (Pico_mcd->s68k_regs[0x33]&(1<<2))) { elprintf(EL_INTS, "m68k: s68k irq 2"); SekInterruptS68k(2); }
\r
104 if (!(d&1)) Pico_mcd->m.state_flags |= 1; // reset pending, needed to be sure we fetch the right vectors on reset
\r
105 if ( (Pico_mcd->m.busreq&1) != (d&1)) dprintf("m68k: s68k reset %i", !(d&1));
\r
106 if ( (Pico_mcd->m.busreq&2) != (d&2)) dprintf("m68k: s68k brq %i", (d&2)>>1);
\r
107 if ((Pico_mcd->m.state_flags&1) && (d&3)==1) {
\r
108 SekResetS68k(); // S68k comes out of RESET or BRQ state
\r
109 Pico_mcd->m.state_flags&=~1;
\r
110 dprintf("m68k: resetting s68k, cycles=%i", SekCyclesLeft);
\r
112 Pico_mcd->m.busreq = d;
\r
115 dprintf("m68k: prg wp=%02x", d);
\r
116 Pico_mcd->s68k_regs[2] = d; // really use s68k side register
\r
119 u32 dold = Pico_mcd->s68k_regs[3]&0x1f;
\r
120 //printf("m68k_regs w3: %02x @%06x\n", (u8)d, SekPc);
\r
122 if ((dold>>6) != ((d>>6)&3))
\r
123 dprintf("m68k: prg bank: %i -> %i", (Pico_mcd->s68k_regs[a]>>6), ((d>>6)&3));
\r
124 //if ((Pico_mcd->s68k_regs[3]&4) != (d&4)) dprintf("m68k: ram mode %i mbit", (d&4) ? 1 : 2);
\r
125 //if ((Pico_mcd->s68k_regs[3]&2) != (d&2)) dprintf("m68k: %s", (d&4) ? ((d&2) ? "word swap req" : "noop?") :
\r
126 // ((d&2) ? "word ram to s68k" : "word ram to m68k"));
\r
128 d ^= 2; // writing 0 to DMNA actually sets it, 1 does nothing
\r
130 //dold &= ~2; // ??
\r
132 if ((d & 2) && !(dold & 2)) {
\r
133 Pico_mcd->m.state_flags |= 2; // we must delay setting DMNA bit (needed for Silpheed)
\r
137 if (d & 2) dold &= ~1; // return word RAM to s68k in 2M mode
\r
140 Pico_mcd->s68k_regs[3] = d | dold; // really use s68k side register
\r
141 #ifdef USE_POLL_DETECT
\r
142 if ((s68k_poll_adclk&0xfe) == 2 && s68k_poll_cnt > POLL_LIMIT) {
\r
143 SekSetStopS68k(0); s68k_poll_adclk = 0;
\r
144 elprintf(EL_CDPOLL, "s68k poll release, a=%02x", a);
\r
150 Pico_mcd->bios[0x72 + 1] = d; // simple hint vector changer
\r
153 Pico_mcd->bios[0x72] = d;
\r
154 dprintf("hint vector set to %08x", PicoRead32(0x70));
\r
157 d = (d << 1) | ((d >> 7) & 1); // rol8 1 (special case)
\r
159 //dprintf("m68k: comm flag: %02x", d);
\r
160 Pico_mcd->s68k_regs[0xe] = d;
\r
161 #ifdef USE_POLL_DETECT
\r
162 if ((s68k_poll_adclk&0xfe) == 0xe && s68k_poll_cnt > POLL_LIMIT) {
\r
163 SekSetStopS68k(0); s68k_poll_adclk = 0;
\r
164 elprintf(EL_CDPOLL, "s68k poll release, a=%02x", a);
\r
170 if ((a&0xf0) == 0x10) {
\r
171 Pico_mcd->s68k_regs[a] = d;
\r
172 #ifdef USE_POLL_DETECT
\r
173 if ((a&0xfe) == (s68k_poll_adclk&0xfe) && s68k_poll_cnt > POLL_LIMIT) {
\r
174 SekSetStopS68k(0); s68k_poll_adclk = 0;
\r
175 elprintf(EL_CDPOLL, "s68k poll release, a=%02x", a);
\r
181 elprintf(EL_UIO, "m68k FIXME: invalid write? [%02x] %02x", a, d);
\r
184 #ifndef _ASM_CD_MEMORY_C
\r
187 u32 s68k_poll_detect(u32 a, u32 d)
\r
189 #ifdef USE_POLL_DETECT
\r
190 // needed mostly for Cyclone, which doesn't always check it's cycle counter
\r
191 if (SekIsStoppedS68k()) return d;
\r
192 // polling detection
\r
193 if (a == (s68k_poll_adclk&0xff)) {
\r
194 unsigned int clkdiff = SekCyclesDoneS68k() - (s68k_poll_adclk>>8);
\r
195 if (clkdiff <= POLL_CYCLES) {
\r
197 //printf("-- diff: %u, cnt = %i\n", clkdiff, s68k_poll_cnt);
\r
198 if (s68k_poll_cnt > POLL_LIMIT) {
\r
200 elprintf(EL_CDPOLL, "s68k poll detected @ %06x, a=%02x", SekPcS68k, a);
\r
202 s68k_poll_adclk = (SekCyclesDoneS68k() << 8) | a;
\r
206 s68k_poll_adclk = (SekCyclesDoneS68k() << 8) | a;
\r
212 #define READ_FONT_DATA(basemask) \
\r
214 unsigned int fnt = *(unsigned int *)(Pico_mcd->s68k_regs + 0x4c); \
\r
215 unsigned int col0 = (fnt >> 8) & 0x0f, col1 = (fnt >> 12) & 0x0f; \
\r
216 if (fnt & (basemask << 0)) d = col1 ; else d = col0; \
\r
217 if (fnt & (basemask << 1)) d |= col1 << 4; else d |= col0 << 4; \
\r
218 if (fnt & (basemask << 2)) d |= col1 << 8; else d |= col0 << 8; \
\r
219 if (fnt & (basemask << 3)) d |= col1 << 12; else d |= col0 << 12; \
\r
223 #ifndef _ASM_CD_MEMORY_C
\r
226 u32 s68k_reg_read16(u32 a)
\r
230 // dprintf("s68k_regs r%2i: [%02x] @ %06x", realsize&~1, a+(realsize&1), SekPcS68k);
\r
234 return ((Pico_mcd->s68k_regs[0]&3)<<8) | 1; // ver = 0, not in reset state
\r
236 d = (Pico_mcd->s68k_regs[2]<<8) | (Pico_mcd->s68k_regs[3]&0x1f);
\r
237 //printf("s68k_regs r3: %02x @%06x\n", (u8)d, SekPcS68k);
\r
238 return s68k_poll_detect(a, d);
\r
240 return CDC_Read_Reg();
\r
242 return Read_CDC_Host(1); // Gens returns 0 here on byte reads
\r
244 d = Pico_mcd->m.timer_stopwatch >> 16;
\r
245 dprintf("s68k stopwatch timer read (%04x)", d);
\r
248 dprintf("s68k int3 timer read (%02x)", Pico_mcd->s68k_regs[31]);
\r
249 return Pico_mcd->s68k_regs[31];
\r
250 case 0x34: // fader
\r
251 return 0; // no busy bit
\r
252 case 0x50: // font data (check: Lunar 2, Silpheed)
\r
253 READ_FONT_DATA(0x00100000);
\r
256 READ_FONT_DATA(0x00010000);
\r
259 READ_FONT_DATA(0x10000000);
\r
262 READ_FONT_DATA(0x01000000);
\r
266 d = (Pico_mcd->s68k_regs[a]<<8) | Pico_mcd->s68k_regs[a+1];
\r
268 if (a >= 0x0e && a < 0x30)
\r
269 return s68k_poll_detect(a, d);
\r
274 #ifndef _ASM_CD_MEMORY_C
\r
277 void s68k_reg_write8(u32 a, u32 d)
\r
279 //dprintf("s68k_regs w%2i: [%02x] %02x @ %06x", realsize, a, d, SekPcS68k);
\r
281 // Warning: d might have upper bits set
\r
284 return; // only m68k can change WP
\r
286 int dold = Pico_mcd->s68k_regs[3];
\r
287 //printf("s68k_regs w3: %02x @%06x\n", (u8)d, SekPcS68k);
\r
291 if ((d ^ dold) & 5) {
\r
292 d &= ~2; // in case of mode or bank change we clear DMNA (m68k req) bit
\r
295 #ifdef _ASM_CD_MEMORY_C
\r
296 if ((d ^ dold) & 0x1d)
\r
297 PicoMemResetCDdecode(d);
\r
300 dprintf("wram mode 2M->1M");
\r
301 wram_2M_to_1M(Pico_mcd->word_ram2M);
\r
305 dprintf("wram mode 1M->2M");
\r
306 if (!(d&1)) { // it didn't set the ret bit, which means it doesn't want to give WRAM to m68k
\r
308 d |= (dold&1) ? 2 : 1; // then give it to the one which had bank0 in 1M mode
\r
310 wram_1M_to_2M(Pico_mcd->word_ram2M);
\r
315 if (d&1) d &= ~2; // return word RAM to m68k in 2M mode
\r
320 dprintf("s68k CDC dest: %x", d&7);
\r
321 Pico_mcd->s68k_regs[4] = (Pico_mcd->s68k_regs[4]&0xC0) | (d&7); // CDC mode
\r
324 //dprintf("s68k CDC reg addr: %x", d&0xf);
\r
330 dprintf("s68k set CDC dma addr");
\r
334 dprintf("s68k set stopwatch timer");
\r
335 Pico_mcd->m.timer_stopwatch = 0;
\r
338 Pico_mcd->s68k_regs[0xf] = (d>>1) | (d<<7); // ror8 1, Gens note: Dragons lair
\r
341 dprintf("s68k set int3 timer: %02x", d);
\r
342 Pico_mcd->m.timer_int3 = (d & 0xff) << 16;
\r
344 case 0x33: // IRQ mask
\r
345 dprintf("s68k irq mask: %02x", d);
\r
346 if ((d&(1<<4)) && (Pico_mcd->s68k_regs[0x37]&4) && !(Pico_mcd->s68k_regs[0x33]&(1<<4))) {
\r
347 CDD_Export_Status();
\r
350 case 0x34: // fader
\r
351 Pico_mcd->s68k_regs[a] = (u8) d & 0x7f;
\r
354 return; // d/m bit is unsetable
\r
356 u32 d_old = Pico_mcd->s68k_regs[0x37];
\r
357 Pico_mcd->s68k_regs[0x37] = d&7;
\r
358 if ((d&4) && !(d_old&4)) {
\r
359 CDD_Export_Status();
\r
364 Pico_mcd->s68k_regs[a] = (u8) d;
\r
365 CDD_Import_Command();
\r
369 if ((a&0x1f0) == 0x10 || (a >= 0x38 && a < 0x42))
\r
371 elprintf(EL_UIO, "s68k FIXME: invalid write @ %02x?", a);
\r
375 Pico_mcd->s68k_regs[a] = (u8) d;
\r
379 static u32 OtherRead16End(u32 a, int realsize)
\r
383 #ifndef _ASM_CD_MEMORY_C
\r
384 if ((a&0xffffc0)==0xa12000) {
\r
385 d=m68k_reg_read16(a);
\r
390 if (SRam.data != NULL) d=3; // 64k cart
\r
394 if ((a&0xfe0000)==0x600000) {
\r
395 if (SRam.data != NULL) {
\r
396 d=SRam.data[((a>>1)&0xffff)+0x2000];
\r
397 if (realsize == 8) d|=d<<8;
\r
403 d=Pico_mcd->m.bcram_reg;
\r
408 elprintf(EL_UIO, "m68k FIXME: unusual r%i: %06x @%06x", realsize&~1, (a&0xfffffe)+(realsize&1), SekPc);
\r
410 #ifndef _ASM_CD_MEMORY_C
\r
417 static void OtherWrite8End(u32 a, u32 d, int realsize)
\r
419 #ifndef _ASM_CD_MEMORY_C
\r
420 if ((a&0xffffc0)==0xa12000) { m68k_reg_write8(a, d); return; }
\r
422 if ((a&0xfe0000)==0x600000) {
\r
423 if (SRam.data != NULL && (Pico_mcd->m.bcram_reg&1)) {
\r
424 SRam.data[((a>>1)&0xffff)+0x2000]=d;
\r
431 Pico_mcd->m.bcram_reg=d;
\r
436 elprintf(EL_UIO, "m68k FIXME: strange w%i: [%06x], %08x @%06x", realsize, a&0xffffff, d, SekPc);
\r
439 #ifndef _ASM_CD_MEMORY_C
\r
440 #define _CD_MEMORY_C
\r
441 #undef _ASM_MEMORY_C
\r
442 #include "../MemoryCmn.c"
\r
443 #include "cell_map.c"
\r
447 // -----------------------------------------------------------------
\r
448 // Read Rom and read Ram
\r
450 #ifdef _ASM_CD_MEMORY_C
\r
451 u32 PicoReadM68k8(u32 a);
\r
453 u32 PicoReadM68k8(u32 a)
\r
461 case 0x00>>1: // BIOS: 000000 - 020000
\r
462 d = *(u8 *)(Pico_mcd->bios+(a^1));
\r
464 case 0x02>>1: // prg RAM
\r
465 if ((Pico_mcd->m.busreq&3)!=1) {
\r
466 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
\r
467 d = *(prg_bank+((a^1)&0x1ffff));
\r
470 case 0x20>>1: // word RAM: 200000 - 220000
\r
471 wrdprintf("m68k_wram r8: [%06x] @%06x", a, SekPc);
\r
473 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
474 int bank = Pico_mcd->s68k_regs[3]&1;
\r
475 d = Pico_mcd->word_ram1M[bank][a^1];
\r
477 // allow access in any mode, like Gens does
\r
478 d = Pico_mcd->word_ram2M[a^1];
\r
480 wrdprintf("ret = %02x", (u8)d);
\r
482 case 0x22>>1: // word RAM: 220000 - 240000
\r
483 wrdprintf("m68k_wram r8: [%06x] @%06x", a, SekPc);
\r
484 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
485 int bank = Pico_mcd->s68k_regs[3]&1;
\r
486 a = (a&3) | (cell_map(a >> 2) << 2); // cell arranged
\r
487 d = Pico_mcd->word_ram1M[bank][a^1];
\r
489 // allow access in any mode, like Gens does
\r
490 d = Pico_mcd->word_ram2M[(a^1)&0x3ffff];
\r
492 wrdprintf("ret = %02x", (u8)d);
\r
494 case 0xc0>>1: case 0xc2>>1: case 0xc4>>1: case 0xc6>>1:
\r
495 case 0xc8>>1: case 0xca>>1: case 0xcc>>1: case 0xce>>1:
\r
496 case 0xd0>>1: case 0xd2>>1: case 0xd4>>1: case 0xd6>>1:
\r
497 case 0xd8>>1: case 0xda>>1: case 0xdc>>1: case 0xde>>1:
\r
499 if ((a&0xe700e0)==0xc00000) {
\r
500 d=PicoVideoRead(a);
\r
501 if ((a&1)==0) d>>=8;
\r
504 case 0xe0>>1: case 0xe2>>1: case 0xe4>>1: case 0xe6>>1:
\r
505 case 0xe8>>1: case 0xea>>1: case 0xec>>1: case 0xee>>1:
\r
506 case 0xf0>>1: case 0xf2>>1: case 0xf4>>1: case 0xf6>>1:
\r
507 case 0xf8>>1: case 0xfa>>1: case 0xfc>>1: case 0xfe>>1:
\r
509 d = *(u8 *)(Pico.ram+((a^1)&0xffff));
\r
512 if ((a&0xff4000)==0xa00000) { d=z80Read8(a); break; } // Z80 Ram
\r
513 if ((a&0xffffc0)==0xa12000)
\r
514 rdprintf("m68k_regs r8: [%02x] @%06x", a&0x3f, SekPc);
\r
516 d=OtherRead16(a&~1, 8|(a&1)); if ((a&1)==0) d>>=8;
\r
518 if ((a&0xffffc0)==0xa12000)
\r
519 rdprintf("ret = %02x", (u8)d);
\r
524 elprintf(EL_IO, "r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPc);
\r
525 #ifdef EMU_CORE_DEBUG
\r
526 if (a>=Pico.romsize) {
\r
528 lastread_d[lrp_cyc++&15] = d;
\r
536 #ifdef _ASM_CD_MEMORY_C
\r
537 u32 PicoReadM68k16(u32 a);
\r
539 static u32 PicoReadM68k16(u32 a)
\r
547 case 0x00>>1: // BIOS: 000000 - 020000
\r
548 d = *(u16 *)(Pico_mcd->bios+a);
\r
550 case 0x02>>1: // prg RAM
\r
551 if ((Pico_mcd->m.busreq&3)!=1) {
\r
552 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
\r
553 wrdprintf("m68k_prgram r16: [%i,%06x] @%06x", Pico_mcd->s68k_regs[3]>>6, a, SekPc);
\r
554 d = *(u16 *)(prg_bank+(a&0x1fffe));
\r
555 wrdprintf("ret = %04x", d);
\r
558 case 0x20>>1: // word RAM: 200000 - 220000
\r
559 wrdprintf("m68k_wram r16: [%06x] @%06x", a, SekPc);
\r
561 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
562 int bank = Pico_mcd->s68k_regs[3]&1;
\r
563 d = *(u16 *)(Pico_mcd->word_ram1M[bank]+a);
\r
565 // allow access in any mode, like Gens does
\r
566 d = *(u16 *)(Pico_mcd->word_ram2M+a);
\r
568 wrdprintf("ret = %04x", d);
\r
570 case 0x22>>1: // word RAM: 220000 - 240000
\r
571 wrdprintf("m68k_wram r16: [%06x] @%06x", a, SekPc);
\r
572 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
573 int bank = Pico_mcd->s68k_regs[3]&1;
\r
574 a = (a&2) | (cell_map(a >> 2) << 2); // cell arranged
\r
575 d = *(u16 *)(Pico_mcd->word_ram1M[bank]+a);
\r
577 // allow access in any mode, like Gens does
\r
578 d = *(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe));
\r
580 wrdprintf("ret = %04x", d);
\r
582 case 0xc0>>1: case 0xc2>>1: case 0xc4>>1: case 0xc6>>1:
\r
583 case 0xc8>>1: case 0xca>>1: case 0xcc>>1: case 0xce>>1:
\r
584 case 0xd0>>1: case 0xd2>>1: case 0xd4>>1: case 0xd6>>1:
\r
585 case 0xd8>>1: case 0xda>>1: case 0xdc>>1: case 0xde>>1:
\r
587 if ((a&0xe700e0)==0xc00000)
\r
588 d=PicoVideoRead(a);
\r
590 case 0xe0>>1: case 0xe2>>1: case 0xe4>>1: case 0xe6>>1:
\r
591 case 0xe8>>1: case 0xea>>1: case 0xec>>1: case 0xee>>1:
\r
592 case 0xf0>>1: case 0xf2>>1: case 0xf4>>1: case 0xf6>>1:
\r
593 case 0xf8>>1: case 0xfa>>1: case 0xfc>>1: case 0xfe>>1:
\r
595 d=*(u16 *)(Pico.ram+(a&0xfffe));
\r
598 if ((a&0xffffc0)==0xa12000)
\r
599 rdprintf("m68k_regs r16: [%02x] @%06x", a&0x3f, SekPc);
\r
601 d = OtherRead16(a, 16);
\r
603 if ((a&0xffffc0)==0xa12000)
\r
604 rdprintf("ret = %04x", d);
\r
609 elprintf(EL_IO, "r16: %06x, %04x @%06x", a&0xffffff, d, SekPc);
\r
610 #ifdef EMU_CORE_DEBUG
\r
611 if (a>=Pico.romsize) {
\r
613 lastread_d[lrp_cyc++&15] = d;
\r
621 #ifdef _ASM_CD_MEMORY_C
\r
622 u32 PicoReadM68k32(u32 a);
\r
624 static u32 PicoReadM68k32(u32 a)
\r
632 case 0x00>>1: { // BIOS: 000000 - 020000
\r
633 u16 *pm=(u16 *)(Pico_mcd->bios+a);
\r
634 d = (pm[0]<<16)|pm[1];
\r
637 case 0x02>>1: // prg RAM
\r
638 if ((Pico_mcd->m.busreq&3)!=1) {
\r
639 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
\r
640 u16 *pm=(u16 *)(prg_bank+(a&0x1fffe));
\r
641 d = (pm[0]<<16)|pm[1];
\r
644 case 0x20>>1: // word RAM: 200000 - 220000
\r
645 wrdprintf("m68k_wram r32: [%06x] @%06x", a, SekPc);
\r
647 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
648 int bank = Pico_mcd->s68k_regs[3]&1;
\r
649 u16 *pm=(u16 *)(Pico_mcd->word_ram1M[bank]+a);
\r
650 d = (pm[0]<<16)|pm[1];
\r
652 // allow access in any mode, like Gens does
\r
653 u16 *pm=(u16 *)(Pico_mcd->word_ram2M+a);
\r
654 d = (pm[0]<<16)|pm[1];
\r
656 wrdprintf("ret = %08x", d);
\r
658 case 0x22>>1: // word RAM: 220000 - 240000
\r
659 wrdprintf("m68k_wram r32: [%06x] @%06x", a, SekPc);
\r
660 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode, cell arranged?
\r
662 int bank = Pico_mcd->s68k_regs[3]&1;
\r
663 a1 = (a&2) | (cell_map(a >> 2) << 2);
\r
664 if (a&2) a2 = cell_map((a+2) >> 2) << 2;
\r
666 d = *(u16 *)(Pico_mcd->word_ram1M[bank]+a1) << 16;
\r
667 d |= *(u16 *)(Pico_mcd->word_ram1M[bank]+a2);
\r
669 // allow access in any mode, like Gens does
\r
670 u16 *pm=(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe));
\r
671 d = (pm[0]<<16)|pm[1];
\r
673 wrdprintf("ret = %08x", d);
\r
675 case 0xc0>>1: case 0xc2>>1: case 0xc4>>1: case 0xc6>>1:
\r
676 case 0xc8>>1: case 0xca>>1: case 0xcc>>1: case 0xce>>1:
\r
677 case 0xd0>>1: case 0xd2>>1: case 0xd4>>1: case 0xd6>>1:
\r
678 case 0xd8>>1: case 0xda>>1: case 0xdc>>1: case 0xde>>1:
\r
680 d = (PicoVideoRead(a)<<16)|PicoVideoRead(a+2);
\r
682 case 0xe0>>1: case 0xe2>>1: case 0xe4>>1: case 0xe6>>1:
\r
683 case 0xe8>>1: case 0xea>>1: case 0xec>>1: case 0xee>>1:
\r
684 case 0xf0>>1: case 0xf2>>1: case 0xf4>>1: case 0xf6>>1:
\r
685 case 0xf8>>1: case 0xfa>>1: case 0xfc>>1: case 0xfe>>1: {
\r
687 u16 *pm=(u16 *)(Pico.ram+(a&0xfffe));
\r
688 d = (pm[0]<<16)|pm[1];
\r
692 if ((a&0xffffc0)==0xa12000)
\r
693 rdprintf("m68k_regs r32: [%02x] @%06x", a&0x3f, SekPc);
\r
695 d = (OtherRead16(a, 32)<<16)|OtherRead16(a+2, 32);
\r
697 if ((a&0xffffc0)==0xa12000)
\r
698 rdprintf("ret = %08x", d);
\r
703 elprintf(EL_IO, "r32: %06x, %08x @%06x", a&0xffffff, d, SekPc);
\r
704 #ifdef EMU_CORE_DEBUG
\r
705 if (a>=Pico.romsize) {
\r
707 lastread_d[lrp_cyc++&15] = d;
\r
715 // -----------------------------------------------------------------
\r
717 #ifdef _ASM_CD_MEMORY_C
\r
718 void PicoWriteM68k8(u32 a,u8 d);
\r
720 void PicoWriteM68k8(u32 a,u8 d)
\r
722 elprintf(EL_IO, "w8 : %06x, %02x @%06x", a&0xffffff, d, SekPc);
\r
723 #ifdef EMU_CORE_DEBUG
\r
724 lastwrite_cyc_d[lwp_cyc++&15] = d;
\r
727 if ((a&0xe00000)==0xe00000) { // Ram
\r
728 *(u8 *)(Pico.ram+((a^1)&0xffff)) = d;
\r
733 if ((a&0xfe0000)==0x020000 && (Pico_mcd->m.busreq&3)!=1) {
\r
734 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
\r
735 *(u8 *)(prg_bank+((a^1)&0x1ffff))=d;
\r
742 if ((a&0xfc0000)==0x200000) {
\r
743 wrdprintf("m68k_wram w8: [%06x] %02x @%06x", a, d, SekPc);
\r
744 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
745 int bank = Pico_mcd->s68k_regs[3]&1;
\r
747 a = (a&3) | (cell_map(a >> 2) << 2); // cell arranged
\r
749 *(u8 *)(Pico_mcd->word_ram1M[bank]+(a^1))=d;
\r
751 // allow access in any mode, like Gens does
\r
752 *(u8 *)(Pico_mcd->word_ram2M+((a^1)&0x3ffff))=d;
\r
757 if ((a&0xffffc0)==0xa12000) {
\r
758 rdprintf("m68k_regs w8: [%02x] %02x @%06x", a&0x3f, d, SekPc);
\r
759 m68k_reg_write8(a, d);
\r
768 #ifdef _ASM_CD_MEMORY_C
\r
769 void PicoWriteM68k16(u32 a,u16 d);
\r
771 static void PicoWriteM68k16(u32 a,u16 d)
\r
773 elprintf(EL_IO, "w16: %06x, %04x", a&0xffffff, d);
\r
774 #ifdef EMU_CORE_DEBUG
\r
775 lastwrite_cyc_d[lwp_cyc++&15] = d;
\r
778 if ((a&0xe00000)==0xe00000) { // Ram
\r
779 *(u16 *)(Pico.ram+(a&0xfffe))=d;
\r
784 if ((a&0xfe0000)==0x020000 && (Pico_mcd->m.busreq&3)!=1) {
\r
785 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
\r
786 wrdprintf("m68k_prgram w16: [%i,%06x] %04x @%06x", Pico_mcd->s68k_regs[3]>>6, a, d, SekPc);
\r
787 *(u16 *)(prg_bank+(a&0x1fffe))=d;
\r
794 if ((a&0xfc0000)==0x200000) {
\r
795 wrdprintf("m68k_wram w16: [%06x] %04x @%06x", a, d, SekPc);
\r
796 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
797 int bank = Pico_mcd->s68k_regs[3]&1;
\r
799 a = (a&2) | (cell_map(a >> 2) << 2); // cell arranged
\r
801 *(u16 *)(Pico_mcd->word_ram1M[bank]+a)=d;
\r
803 // allow access in any mode, like Gens does
\r
804 *(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe))=d;
\r
810 if ((a&0xffffc0)==0xa12000) {
\r
811 rdprintf("m68k_regs w16: [%02x] %04x @%06x", a&0x3f, d, SekPc);
\r
812 if (a == 0xe) { // special case, 2 byte writes would be handled differently
\r
813 Pico_mcd->s68k_regs[0xe] = d >> 8;
\r
814 #ifdef USE_POLL_DETECT
\r
815 if ((s68k_poll_adclk&0xfe) == 0xe && s68k_poll_cnt > POLL_LIMIT) {
\r
816 SekSetStopS68k(0); s68k_poll_adclk = 0;
\r
817 elprintf(EL_CDPOLL, "s68k poll release, a=%02x", a);
\r
822 m68k_reg_write8(a, d>>8);
\r
823 m68k_reg_write8(a+1,d&0xff);
\r
828 if ((a&0xe700e0)==0xc00000) {
\r
829 PicoVideoWrite(a,(u16)d);
\r
838 #ifdef _ASM_CD_MEMORY_C
\r
839 void PicoWriteM68k32(u32 a,u32 d);
\r
841 static void PicoWriteM68k32(u32 a,u32 d)
\r
843 elprintf(EL_IO, "w32: %06x, %08x", a&0xffffff, d);
\r
844 #ifdef EMU_CORE_DEBUG
\r
845 lastwrite_cyc_d[lwp_cyc++&15] = d;
\r
848 if ((a&0xe00000)==0xe00000)
\r
851 u16 *pm=(u16 *)(Pico.ram+(a&0xfffe));
\r
852 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
857 if ((a&0xfe0000)==0x020000 && (Pico_mcd->m.busreq&3)!=1) {
\r
858 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
\r
859 u16 *pm=(u16 *)(prg_bank+(a&0x1fffe));
\r
860 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
867 if ((a&0xfc0000)==0x200000) {
\r
868 if (d != 0) // don't log clears
\r
869 wrdprintf("m68k_wram w32: [%06x] %08x @%06x", a, d, SekPc);
\r
870 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
871 int bank = Pico_mcd->s68k_regs[3]&1;
\r
872 if (a >= 0x220000) { // cell arranged
\r
874 a1 = (a&2) | (cell_map(a >> 2) << 2);
\r
875 if (a&2) a2 = cell_map((a+2) >> 2) << 2;
\r
877 *(u16 *)(Pico_mcd->word_ram1M[bank]+a1) = d >> 16;
\r
878 *(u16 *)(Pico_mcd->word_ram1M[bank]+a2) = d;
\r
880 u16 *pm=(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe));
\r
881 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
884 // allow access in any mode, like Gens does
\r
885 u16 *pm=(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe));
\r
886 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
891 if ((a&0xffffc0)==0xa12000) {
\r
892 rdprintf("m68k_regs w32: [%02x] %08x @%06x", a&0x3f, d, SekPc);
\r
893 if ((a&0x3e) == 0xe) dprintf("m68k FIXME: w32 [%02x]", a&0x3f);
\r
897 if ((a&0xe700e0)==0xc00000)
\r
899 PicoVideoWrite(a, (u16)(d>>16));
\r
900 PicoVideoWrite(a+2,(u16)d);
\r
904 OtherWrite16(a, (u16)(d>>16));
\r
905 OtherWrite16(a+2,(u16)d);
\r
910 // -----------------------------------------------------------------
\r
912 // -----------------------------------------------------------------
\r
914 #ifdef _ASM_CD_MEMORY_C
\r
915 u32 PicoReadS68k8(u32 a);
\r
917 static u32 PicoReadS68k8(u32 a)
\r
921 #ifdef EMU_CORE_DEBUG
\r
928 d = *(Pico_mcd->prg_ram+(a^1));
\r
933 if ((a&0xfffe00) == 0xff8000) {
\r
935 rdprintf("s68k_regs r8: [%02x] @ %06x", a, SekPcS68k);
\r
936 if (a >= 0x0e && a < 0x30) {
\r
937 d = Pico_mcd->s68k_regs[a];
\r
938 s68k_poll_detect(a, d);
\r
939 rdprintf("ret = %02x", (u8)d);
\r
942 else if (a >= 0x58 && a < 0x68)
\r
943 d = gfx_cd_read(a&~1);
\r
944 else d = s68k_reg_read16(a&~1);
\r
945 if ((a&1)==0) d>>=8;
\r
946 rdprintf("ret = %02x", (u8)d);
\r
950 // word RAM (2M area)
\r
951 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
952 // test: batman returns
\r
953 wrdprintf("s68k_wram2M r8: [%06x] @%06x", a, SekPcS68k);
\r
954 if (Pico_mcd->s68k_regs[3]&4) { // 1M decode mode?
\r
955 int bank = (Pico_mcd->s68k_regs[3]&1)^1;
\r
956 d = Pico_mcd->word_ram1M[bank][((a>>1)^1)&0x1ffff];
\r
957 if (a&1) d &= 0x0f;
\r
960 // allow access in any mode, like Gens does
\r
961 d = Pico_mcd->word_ram2M[(a^1)&0x3ffff];
\r
963 wrdprintf("ret = %02x", (u8)d);
\r
967 // word RAM (1M area)
\r
968 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
970 wrdprintf("s68k_wram1M r8: [%06x] @%06x", a, SekPcS68k);
\r
971 // if (!(Pico_mcd->s68k_regs[3]&4))
\r
972 // dprintf("s68k_wram1M FIXME: wrong mode");
\r
973 bank = (Pico_mcd->s68k_regs[3]&1)^1;
\r
974 d = Pico_mcd->word_ram1M[bank][(a^1)&0x1ffff];
\r
975 wrdprintf("ret = %02x", (u8)d);
\r
980 if ((a&0xff8000)==0xff0000) {
\r
981 elprintf(EL_IO, "s68k_pcm r8: [%06x] @%06x", a, SekPcS68k);
\r
984 d = Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a>>1)&0xfff];
\r
985 else if (a >= 0x20) {
\r
987 d = Pico_mcd->pcm.ch[a>>2].addr >> PCM_STEP_SHIFT;
\r
988 if (a & 2) d >>= 8;
\r
990 elprintf(EL_IO, "ret = %02x", (u8)d);
\r
995 if ((a&0xff0000)==0xfe0000) {
\r
996 d = Pico_mcd->bram[(a>>1)&0x1fff];
\r
1000 elprintf(EL_UIO, "s68k r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPcS68k);
\r
1004 elprintf(EL_IO, "s68k r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPcS68k);
\r
1005 #ifdef EMU_CORE_DEBUG
\r
1007 lastread_d[lrp_cyc++&15] = d;
\r
1014 #ifdef _ASM_CD_MEMORY_C
\r
1015 u32 PicoReadS68k16(u32 a);
\r
1017 static u32 PicoReadS68k16(u32 a)
\r
1021 #ifdef EMU_CORE_DEBUG
\r
1022 u32 ab=a&0xfffffe;
\r
1027 if (a < 0x80000) {
\r
1028 wrdprintf("s68k_prgram r16: [%06x] @%06x", a, SekPcS68k);
\r
1029 d = *(u16 *)(Pico_mcd->prg_ram+a);
\r
1030 wrdprintf("ret = %04x", d);
\r
1035 if ((a&0xfffe00) == 0xff8000) {
\r
1037 rdprintf("s68k_regs r16: [%02x] @ %06x", a, SekPcS68k);
\r
1038 if (a >= 0x58 && a < 0x68)
\r
1039 d = gfx_cd_read(a);
\r
1040 else d = s68k_reg_read16(a);
\r
1041 rdprintf("ret = %04x", d);
\r
1045 // word RAM (2M area)
\r
1046 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
1047 wrdprintf("s68k_wram2M r16: [%06x] @%06x", a, SekPcS68k);
\r
1048 if (Pico_mcd->s68k_regs[3]&4) { // 1M decode mode?
\r
1049 int bank = (Pico_mcd->s68k_regs[3]&1)^1;
\r
1050 d = Pico_mcd->word_ram1M[bank][((a>>1)^1)&0x1ffff];
\r
1051 d |= d << 4; d &= ~0xf0;
\r
1053 // allow access in any mode, like Gens does
\r
1054 d = *(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe));
\r
1056 wrdprintf("ret = %04x", d);
\r
1060 // word RAM (1M area)
\r
1061 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
1063 wrdprintf("s68k_wram1M r16: [%06x] @%06x", a, SekPcS68k);
\r
1064 // if (!(Pico_mcd->s68k_regs[3]&4))
\r
1065 // dprintf("s68k_wram1M FIXME: wrong mode");
\r
1066 bank = (Pico_mcd->s68k_regs[3]&1)^1;
\r
1067 d = *(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe));
\r
1068 wrdprintf("ret = %04x", d);
\r
1073 if ((a&0xff0000)==0xfe0000) {
\r
1074 dprintf("FIXME: s68k_bram r16: [%06x] @%06x", a, SekPcS68k);
\r
1075 a = (a>>1)&0x1fff;
\r
1076 d = Pico_mcd->bram[a++]; // Gens does little endian here, and so do we..
\r
1077 d|= Pico_mcd->bram[a++] << 8; // This is most likely wrong
\r
1078 dprintf("ret = %04x", d);
\r
1083 if ((a&0xff8000)==0xff0000) {
\r
1084 dprintf("FIXME: s68k_pcm r16: [%06x] @%06x", a, SekPcS68k);
\r
1087 d = Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a>>1)&0xfff];
\r
1088 else if (a >= 0x20) {
\r
1090 d = Pico_mcd->pcm.ch[a>>2].addr >> PCM_STEP_SHIFT;
\r
1091 if (a & 2) d >>= 8;
\r
1093 dprintf("ret = %04x", d);
\r
1097 elprintf(EL_UIO, "s68k r16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);
\r
1101 elprintf(EL_IO, "s68k r16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);
\r
1102 #ifdef EMU_CORE_DEBUG
\r
1104 lastread_d[lrp_cyc++&15] = d;
\r
1111 #ifdef _ASM_CD_MEMORY_C
\r
1112 u32 PicoReadS68k32(u32 a);
\r
1114 static u32 PicoReadS68k32(u32 a)
\r
1118 #ifdef EMU_CORE_DEBUG
\r
1119 u32 ab=a&0xfffffe;
\r
1124 if (a < 0x80000) {
\r
1125 u16 *pm=(u16 *)(Pico_mcd->prg_ram+a);
\r
1126 d = (pm[0]<<16)|pm[1];
\r
1131 if ((a&0xfffe00) == 0xff8000) {
\r
1133 rdprintf("s68k_regs r32: [%02x] @ %06x", a, SekPcS68k);
\r
1134 if (a >= 0x58 && a < 0x68)
\r
1135 d = (gfx_cd_read(a)<<16)|gfx_cd_read(a+2);
\r
1136 else d = (s68k_reg_read16(a)<<16)|s68k_reg_read16(a+2);
\r
1137 rdprintf("ret = %08x", d);
\r
1141 // word RAM (2M area)
\r
1142 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
1143 wrdprintf("s68k_wram2M r32: [%06x] @%06x", a, SekPcS68k);
\r
1144 if (Pico_mcd->s68k_regs[3]&4) { // 1M decode mode?
\r
1145 int bank = (Pico_mcd->s68k_regs[3]&1)^1;
\r
1147 d = Pico_mcd->word_ram1M[bank][((a+0)^1)&0x1ffff] << 16;
\r
1148 d |= Pico_mcd->word_ram1M[bank][((a+1)^1)&0x1ffff];
\r
1149 d |= d << 4; d &= 0x0f0f0f0f;
\r
1151 // allow access in any mode, like Gens does
\r
1152 u16 *pm=(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe)); d = (pm[0]<<16)|pm[1];
\r
1154 wrdprintf("ret = %08x", d);
\r
1158 // word RAM (1M area)
\r
1159 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
1161 wrdprintf("s68k_wram1M r32: [%06x] @%06x", a, SekPcS68k);
\r
1162 // if (!(Pico_mcd->s68k_regs[3]&4))
\r
1163 // dprintf("s68k_wram1M FIXME: wrong mode");
\r
1164 bank = (Pico_mcd->s68k_regs[3]&1)^1;
\r
1165 u16 *pm=(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe)); d = (pm[0]<<16)|pm[1];
\r
1166 wrdprintf("ret = %08x", d);
\r
1171 if ((a&0xff8000)==0xff0000) {
\r
1172 dprintf("s68k_pcm r32: [%06x] @%06x", a, SekPcS68k);
\r
1174 if (a >= 0x2000) {
\r
1176 d = Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][a&0xfff] << 16;
\r
1177 d |= Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a+1)&0xfff];
\r
1178 } else if (a >= 0x20) {
\r
1182 d = (Pico_mcd->pcm.ch[a].addr >> (PCM_STEP_SHIFT-8)) & 0xff0000;
\r
1183 d |= (Pico_mcd->pcm.ch[(a+1)&7].addr >> PCM_STEP_SHIFT) & 0xff;
\r
1185 d = Pico_mcd->pcm.ch[a>>2].addr >> PCM_STEP_SHIFT;
\r
1186 d = ((d<<16)&0xff0000) | ((d>>8)&0xff); // PCM chip is LE
\r
1189 dprintf("ret = %08x", d);
\r
1194 if ((a&0xff0000)==0xfe0000) {
\r
1195 dprintf("FIXME: s68k_bram r32: [%06x] @%06x", a, SekPcS68k);
\r
1196 a = (a>>1)&0x1fff;
\r
1197 d = Pico_mcd->bram[a++] << 16; // middle endian? TODO: verify against Fusion..
\r
1198 d|= Pico_mcd->bram[a++] << 24;
\r
1199 d|= Pico_mcd->bram[a++];
\r
1200 d|= Pico_mcd->bram[a++] << 8;
\r
1201 dprintf("ret = %08x", d);
\r
1205 elprintf(EL_UIO, "s68k r32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);
\r
1209 elprintf(EL_IO, "s68k r32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);
\r
1210 #ifdef EMU_CORE_DEBUG
\r
1211 if (ab > 0x78) { // not vectors and stuff
\r
1213 lastread_d[lrp_cyc++&15] = d;
\r
1221 #ifndef _ASM_CD_MEMORY_C
\r
1222 /* check: jaguar xj 220 (draws entire world using decode) */
\r
1223 static void decode_write8(u32 a, u8 d, int r3)
\r
1225 u8 *pd = Pico_mcd->word_ram1M[(r3 & 1)^1] + (((a>>1)^1)&0x1ffff);
\r
1226 u8 oldmask = (a&1) ? 0xf0 : 0x0f;
\r
1230 if (!(a&1)) d <<= 4;
\r
1233 if ((!(*pd & (~oldmask))) && d) goto do_it;
\r
1234 } else if (r3 > 8) {
\r
1235 if (d) goto do_it;
\r
1242 *pd = d | (*pd & oldmask);
\r
1246 static void decode_write16(u32 a, u16 d, int r3)
\r
1248 u8 *pd = Pico_mcd->word_ram1M[(r3 & 1)^1] + (((a>>1)^1)&0x1ffff);
\r
1250 //if ((a & 0x3ffff) < 0x28000) return;
\r
1258 if (!(dold & 0xf0)) dold |= d & 0xf0;
\r
1259 if (!(dold & 0x0f)) dold |= d & 0x0f;
\r
1261 } else if (r3 > 8) {
\r
1263 if (!(d & 0xf0)) d |= dold & 0xf0;
\r
1264 if (!(d & 0x0f)) d |= dold & 0x0f;
\r
1272 // -----------------------------------------------------------------
\r
1274 #ifdef _ASM_CD_MEMORY_C
\r
1275 void PicoWriteS68k8(u32 a,u8 d);
\r
1277 static void PicoWriteS68k8(u32 a,u8 d)
\r
1279 elprintf(EL_IO, "s68k w8 : %06x, %02x @%06x", a&0xffffff, d, SekPcS68k);
\r
1283 #ifdef EMU_CORE_DEBUG
\r
1284 lastwrite_cyc_d[lwp_cyc++&15] = d;
\r
1288 if (a < 0x80000) {
\r
1289 u8 *pm=(u8 *)(Pico_mcd->prg_ram+(a^1));
\r
1290 if (a >= (Pico_mcd->s68k_regs[2]<<8)) *pm=d;
\r
1295 if ((a&0xfffe00) == 0xff8000) {
\r
1297 rdprintf("s68k_regs w8: [%02x] %02x @ %06x", a, d, SekPcS68k);
\r
1298 if (a >= 0x58 && a < 0x68)
\r
1299 gfx_cd_write16(a&~1, (d<<8)|d);
\r
1300 else s68k_reg_write8(a,d);
\r
1304 // word RAM (2M area)
\r
1305 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
1306 int r3 = Pico_mcd->s68k_regs[3];
\r
1307 wrdprintf("s68k_wram2M w8: [%06x] %02x @%06x", a, d, SekPcS68k);
\r
1308 if (r3 & 4) { // 1M decode mode?
\r
1309 decode_write8(a, d, r3);
\r
1311 // allow access in any mode, like Gens does
\r
1312 *(u8 *)(Pico_mcd->word_ram2M+((a^1)&0x3ffff))=d;
\r
1317 // word RAM (1M area)
\r
1318 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
1319 // Wing Commander tries to write here in wrong mode
\r
1322 wrdprintf("s68k_wram1M w8: [%06x] %02x @%06x", a, d, SekPcS68k);
\r
1323 // if (!(Pico_mcd->s68k_regs[3]&4))
\r
1324 // dprintf("s68k_wram1M FIXME: wrong mode");
\r
1325 bank = (Pico_mcd->s68k_regs[3]&1)^1;
\r
1326 *(u8 *)(Pico_mcd->word_ram1M[bank]+((a^1)&0x1ffff))=d;
\r
1331 if ((a&0xff8000)==0xff0000) {
\r
1334 Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a>>1)&0xfff] = d;
\r
1335 else if (a < 0x12)
\r
1336 pcm_write(a>>1, d);
\r
1341 if ((a&0xff0000)==0xfe0000) {
\r
1342 Pico_mcd->bram[(a>>1)&0x1fff] = d;
\r
1347 elprintf(EL_UIO, "s68k w8 : %06x, %02x @%06x", a&0xffffff, d, SekPcS68k);
\r
1352 #ifdef _ASM_CD_MEMORY_C
\r
1353 void PicoWriteS68k16(u32 a,u16 d);
\r
1355 static void PicoWriteS68k16(u32 a,u16 d)
\r
1357 elprintf(EL_IO, "s68k w16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);
\r
1361 #ifdef EMU_CORE_DEBUG
\r
1362 lastwrite_cyc_d[lwp_cyc++&15] = d;
\r
1366 if (a < 0x80000) {
\r
1367 wrdprintf("s68k_prgram w16: [%06x] %04x @%06x", a, d, SekPcS68k);
\r
1368 if (a >= (Pico_mcd->s68k_regs[2]<<8)) // needed for Dungeon Explorer
\r
1369 *(u16 *)(Pico_mcd->prg_ram+a)=d;
\r
1374 if ((a&0xfffe00) == 0xff8000) {
\r
1376 rdprintf("s68k_regs w16: [%02x] %04x @ %06x", a, d, SekPcS68k);
\r
1377 if (a >= 0x58 && a < 0x68)
\r
1378 gfx_cd_write16(a, d);
\r
1380 if (a == 0xe) { // special case, 2 byte writes would be handled differently
\r
1381 Pico_mcd->s68k_regs[0xf] = d;
\r
1384 s68k_reg_write8(a, d>>8);
\r
1385 s68k_reg_write8(a+1,d&0xff);
\r
1390 // word RAM (2M area)
\r
1391 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
1392 int r3 = Pico_mcd->s68k_regs[3];
\r
1393 wrdprintf("s68k_wram2M w16: [%06x] %04x @%06x", a, d, SekPcS68k);
\r
1394 if (r3 & 4) { // 1M decode mode?
\r
1395 decode_write16(a, d, r3);
\r
1397 // allow access in any mode, like Gens does
\r
1398 *(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe))=d;
\r
1403 // word RAM (1M area)
\r
1404 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
1407 wrdprintf("s68k_wram1M w16: [%06x] %04x @%06x", a, d, SekPcS68k);
\r
1408 // if (!(Pico_mcd->s68k_regs[3]&4))
\r
1409 // dprintf("s68k_wram1M FIXME: wrong mode");
\r
1410 bank = (Pico_mcd->s68k_regs[3]&1)^1;
\r
1411 *(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe))=d;
\r
1416 if ((a&0xff8000)==0xff0000) {
\r
1419 Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a>>1)&0xfff] = d;
\r
1420 else if (a < 0x12)
\r
1421 pcm_write(a>>1, d & 0xff);
\r
1426 if ((a&0xff0000)==0xfe0000) {
\r
1427 dprintf("s68k_bram w16: [%06x] %04x @%06x", a, d, SekPcS68k);
\r
1428 a = (a>>1)&0x1fff;
\r
1429 Pico_mcd->bram[a++] = d; // Gens does little endian here, an so do we..
\r
1430 Pico_mcd->bram[a++] = d >> 8;
\r
1435 elprintf(EL_UIO, "s68k w16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);
\r
1440 #ifdef _ASM_CD_MEMORY_C
\r
1441 void PicoWriteS68k32(u32 a,u32 d);
\r
1443 static void PicoWriteS68k32(u32 a,u32 d)
\r
1445 elprintf(EL_IO, "s68k w32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);
\r
1449 #ifdef EMU_CORE_DEBUG
\r
1450 lastwrite_cyc_d[lwp_cyc++&15] = d;
\r
1454 if (a < 0x80000) {
\r
1455 if (a >= (Pico_mcd->s68k_regs[2]<<8)) {
\r
1456 u16 *pm=(u16 *)(Pico_mcd->prg_ram+a);
\r
1457 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
1463 if ((a&0xfffe00) == 0xff8000) {
\r
1465 rdprintf("s68k_regs w32: [%02x] %08x @ %06x", a, d, SekPcS68k);
\r
1466 if (a >= 0x58 && a < 0x68) {
\r
1467 gfx_cd_write16(a, d>>16);
\r
1468 gfx_cd_write16(a+2, d&0xffff);
\r
1470 if ((a&0x1fe) == 0xe) dprintf("s68k FIXME: w32 [%02x]", a&0x3f);
\r
1471 s68k_reg_write8(a, d>>24);
\r
1472 s68k_reg_write8(a+1,(d>>16)&0xff);
\r
1473 s68k_reg_write8(a+2,(d>>8) &0xff);
\r
1474 s68k_reg_write8(a+3, d &0xff);
\r
1479 // word RAM (2M area)
\r
1480 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
1481 int r3 = Pico_mcd->s68k_regs[3];
\r
1482 wrdprintf("s68k_wram2M w32: [%06x] %08x @%06x", a, d, SekPcS68k);
\r
1483 if (r3 & 4) { // 1M decode mode?
\r
1484 decode_write16(a , d >> 16, r3);
\r
1485 decode_write16(a+2, d , r3);
\r
1487 // allow access in any mode, like Gens does
\r
1488 u16 *pm=(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe));
\r
1489 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
1494 // word RAM (1M area)
\r
1495 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
1499 wrdprintf("s68k_wram1M w32: [%06x] %08x @%06x", a, d, SekPcS68k);
\r
1500 // if (!(Pico_mcd->s68k_regs[3]&4))
\r
1501 // dprintf("s68k_wram1M FIXME: wrong mode");
\r
1502 bank = (Pico_mcd->s68k_regs[3]&1)^1;
\r
1503 pm=(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe));
\r
1504 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
1509 if ((a&0xff8000)==0xff0000) {
\r
1511 if (a >= 0x2000) {
\r
1513 Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][a&0xfff] = (d >> 16);
\r
1514 Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a+1)&0xfff] = d;
\r
1515 } else if (a < 0x12) {
\r
1517 pcm_write(a, (d>>16) & 0xff);
\r
1518 pcm_write(a+1, d & 0xff);
\r
1524 if ((a&0xff0000)==0xfe0000) {
\r
1525 dprintf("s68k_bram w32: [%06x] %08x @%06x", a, d, SekPcS68k);
\r
1526 a = (a>>1)&0x1fff;
\r
1527 Pico_mcd->bram[a++] = d >> 16; // middle endian? verify?
\r
1528 Pico_mcd->bram[a++] = d >> 24;
\r
1529 Pico_mcd->bram[a++] = d;
\r
1530 Pico_mcd->bram[a++] = d >> 8;
\r
1535 elprintf(EL_UIO, "s68k w32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);
\r
1540 // -----------------------------------------------------------------
\r
1544 static __inline int PicoMemBaseM68k(u32 pc)
\r
1546 if ((pc&0xe00000)==0xe00000)
\r
1547 return (int)Pico.ram-(pc&0xff0000); // Program Counter in Ram
\r
1550 return (int)Pico_mcd->bios; // Program Counter in BIOS
\r
1552 if ((pc&0xfc0000)==0x200000)
\r
1554 if (!(Pico_mcd->s68k_regs[3]&4))
\r
1555 return (int)Pico_mcd->word_ram2M - 0x200000; // Program Counter in Word Ram
\r
1556 if (pc < 0x220000) {
\r
1557 int bank = Pico_mcd->s68k_regs[3]&1;
\r
1558 return (int)Pico_mcd->word_ram1M[bank] - 0x200000;
\r
1562 // Error - Program Counter is invalid
\r
1563 elprintf(EL_ANOMALY, "m68k FIXME: unhandled jump to %06x", pc);
\r
1565 return (int)Pico_mcd->bios;
\r
1569 static u32 PicoCheckPcM68k(u32 pc)
\r
1571 pc-=PicoCpuCM68k.membase; // Get real pc
\r
1574 PicoCpuCM68k.membase=PicoMemBaseM68k(pc);
\r
1576 return PicoCpuCM68k.membase+pc;
\r
1580 static __inline int PicoMemBaseS68k(u32 pc)
\r
1582 if (pc < 0x80000) // PRG RAM
\r
1583 return (int)Pico_mcd->prg_ram;
\r
1585 if ((pc&0xfc0000)==0x080000) // WORD RAM 2M area (assume we are in the right mode..)
\r
1586 return (int)Pico_mcd->word_ram2M - 0x080000;
\r
1588 if ((pc&0xfe0000)==0x0c0000) { // word RAM 1M area
\r
1589 int bank = (Pico_mcd->s68k_regs[3]&1)^1;
\r
1590 return (int)Pico_mcd->word_ram1M[bank] - 0x0c0000;
\r
1593 // Error - Program Counter is invalid
\r
1594 elprintf(EL_ANOMALY, "s68k FIXME: unhandled jump to %06x", pc);
\r
1596 return (int)Pico_mcd->prg_ram;
\r
1600 static u32 PicoCheckPcS68k(u32 pc)
\r
1602 pc-=PicoCpuCS68k.membase; // Get real pc
\r
1605 PicoCpuCS68k.membase=PicoMemBaseS68k(pc);
\r
1607 return PicoCpuCS68k.membase+pc;
\r
1611 #ifndef _ASM_CD_MEMORY_C
\r
1612 void PicoMemResetCD(int r3)
\r
1615 // update fetchmap..
\r
1619 for (i = M68K_FETCHBANK1*2/16; (i<<(24-FAMEC_FETCHBITS)) < 0x240000; i++)
\r
1620 PicoCpuFM68k.Fetch[i] = (unsigned int)Pico_mcd->word_ram2M - 0x200000;
\r
1624 for (i = M68K_FETCHBANK1*2/16; (i<<(24-FAMEC_FETCHBITS)) < 0x220000; i++)
\r
1625 PicoCpuFM68k.Fetch[i] = (unsigned int)Pico_mcd->word_ram1M[r3 & 1] - 0x200000;
\r
1626 for (i = M68K_FETCHBANK1*0x0c/0x100; (i<<(24-FAMEC_FETCHBITS)) < 0x0e0000; i++)
\r
1627 PicoCpuFS68k.Fetch[i] = (unsigned int)Pico_mcd->word_ram1M[(r3&1)^1] - 0x0c0000;
\r
1633 PICO_INTERNAL void PicoMemSetupCD(void)
\r
1635 // additional handlers for common code
\r
1636 PicoRead16Hook = OtherRead16End;
\r
1637 PicoWrite8Hook = OtherWrite8End;
\r
1640 // Setup m68k memory callbacks:
\r
1641 PicoCpuCM68k.checkpc=PicoCheckPcM68k;
\r
1642 PicoCpuCM68k.fetch8 =PicoCpuCM68k.read8 =PicoReadM68k8;
\r
1643 PicoCpuCM68k.fetch16=PicoCpuCM68k.read16=PicoReadM68k16;
\r
1644 PicoCpuCM68k.fetch32=PicoCpuCM68k.read32=PicoReadM68k32;
\r
1645 PicoCpuCM68k.write8 =PicoWriteM68k8;
\r
1646 PicoCpuCM68k.write16=PicoWriteM68k16;
\r
1647 PicoCpuCM68k.write32=PicoWriteM68k32;
\r
1649 PicoCpuCS68k.checkpc=PicoCheckPcS68k;
\r
1650 PicoCpuCS68k.fetch8 =PicoCpuCS68k.read8 =PicoReadS68k8;
\r
1651 PicoCpuCS68k.fetch16=PicoCpuCS68k.read16=PicoReadS68k16;
\r
1652 PicoCpuCS68k.fetch32=PicoCpuCS68k.read32=PicoReadS68k32;
\r
1653 PicoCpuCS68k.write8 =PicoWriteS68k8;
\r
1654 PicoCpuCS68k.write16=PicoWriteS68k16;
\r
1655 PicoCpuCS68k.write32=PicoWriteS68k32;
\r
1659 PicoCpuFM68k.read_byte =PicoReadM68k8;
\r
1660 PicoCpuFM68k.read_word =PicoReadM68k16;
\r
1661 PicoCpuFM68k.read_long =PicoReadM68k32;
\r
1662 PicoCpuFM68k.write_byte=PicoWriteM68k8;
\r
1663 PicoCpuFM68k.write_word=PicoWriteM68k16;
\r
1664 PicoCpuFM68k.write_long=PicoWriteM68k32;
\r
1666 PicoCpuFS68k.read_byte =PicoReadS68k8;
\r
1667 PicoCpuFS68k.read_word =PicoReadS68k16;
\r
1668 PicoCpuFS68k.read_long =PicoReadS68k32;
\r
1669 PicoCpuFS68k.write_byte=PicoWriteS68k8;
\r
1670 PicoCpuFS68k.write_word=PicoWriteS68k16;
\r
1671 PicoCpuFS68k.write_long=PicoWriteS68k32;
\r
1673 // setup FAME fetchmap
\r
1677 // by default, point everything to fitst 64k of ROM (BIOS)
\r
1678 for (i = 0; i < M68K_FETCHBANK1; i++)
\r
1679 PicoCpuFM68k.Fetch[i] = (unsigned int)Pico.rom - (i<<(24-FAMEC_FETCHBITS));
\r
1680 // now real ROM (BIOS)
\r
1681 for (i = 0; i < M68K_FETCHBANK1 && (i<<(24-FAMEC_FETCHBITS)) < Pico.romsize; i++)
\r
1682 PicoCpuFM68k.Fetch[i] = (unsigned int)Pico.rom;
\r
1684 for (i = M68K_FETCHBANK1*14/16; i < M68K_FETCHBANK1; i++)
\r
1685 PicoCpuFM68k.Fetch[i] = (unsigned int)Pico.ram - (i<<(24-FAMEC_FETCHBITS));
\r
1687 // PRG RAM is default
\r
1688 for (i = 0; i < M68K_FETCHBANK1; i++)
\r
1689 PicoCpuFS68k.Fetch[i] = (unsigned int)Pico_mcd->prg_ram - (i<<(24-FAMEC_FETCHBITS));
\r
1691 for (i = 0; i < M68K_FETCHBANK1 && (i<<(24-FAMEC_FETCHBITS)) < 0x80000; i++)
\r
1692 PicoCpuFS68k.Fetch[i] = (unsigned int)Pico_mcd->prg_ram;
\r
1693 // WORD RAM 2M area
\r
1694 for (i = M68K_FETCHBANK1*0x08/0x100; i < M68K_FETCHBANK1 && (i<<(24-FAMEC_FETCHBITS)) < 0xc0000; i++)
\r
1695 PicoCpuFS68k.Fetch[i] = (unsigned int)Pico_mcd->word_ram2M - 0x80000;
\r
1696 // PicoMemResetCD() will setup word ram for both
\r
1700 // m68k_poll_addr = m68k_poll_cnt = 0;
\r
1701 s68k_poll_adclk = s68k_poll_cnt = 0;
\r
1706 unsigned char PicoReadCD8w (unsigned int a) {
\r
1707 return m68ki_cpu_p == &PicoCpuMS68k ? PicoReadS68k8(a) : PicoReadM68k8(a);
\r
1709 unsigned short PicoReadCD16w(unsigned int a) {
\r
1710 return m68ki_cpu_p == &PicoCpuMS68k ? PicoReadS68k16(a) : PicoReadM68k16(a);
\r
1712 unsigned int PicoReadCD32w(unsigned int a) {
\r
1713 return m68ki_cpu_p == &PicoCpuMS68k ? PicoReadS68k32(a) : PicoReadM68k32(a);
\r
1715 void PicoWriteCD8w (unsigned int a, unsigned char d) {
\r
1716 if (m68ki_cpu_p == &PicoCpuMS68k) PicoWriteS68k8(a, d); else PicoWriteM68k8(a, d);
\r
1718 void PicoWriteCD16w(unsigned int a, unsigned short d) {
\r
1719 if (m68ki_cpu_p == &PicoCpuMS68k) PicoWriteS68k16(a, d); else PicoWriteM68k16(a, d);
\r
1721 void PicoWriteCD32w(unsigned int a, unsigned int d) {
\r
1722 if (m68ki_cpu_p == &PicoCpuMS68k) PicoWriteS68k32(a, d); else PicoWriteM68k32(a, d);
\r
1725 // these are allowed to access RAM
\r
1726 unsigned int m68k_read_pcrelative_CD8 (unsigned int a)
\r
1729 if(m68ki_cpu_p == &PicoCpuMS68k) {
\r
1730 if (a < 0x80000) return *(u8 *)(Pico_mcd->prg_ram+(a^1)); // PRG Ram
\r
1731 if ((a&0xfc0000)==0x080000 && !(Pico_mcd->s68k_regs[3]&4)) // word RAM (2M area: 080000-0bffff)
\r
1732 return *(u8 *)(Pico_mcd->word_ram2M+((a^1)&0x3ffff));
\r
1733 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // word RAM (1M area: 0c0000-0dffff)
\r
1734 int bank = (Pico_mcd->s68k_regs[3]&1)^1;
\r
1735 return *(u8 *)(Pico_mcd->word_ram1M[bank]+((a^1)&0x1ffff));
\r
1737 elprintf(EL_ANOMALY, "s68k_read_pcrelative_CD8 FIXME: can't handle %06x", a);
\r
1739 if((a&0xe00000)==0xe00000) return *(u8 *)(Pico.ram+((a^1)&0xffff)); // Ram
\r
1740 if(a<0x20000) return *(u8 *)(Pico.rom+(a^1)); // Bios
\r
1741 if((a&0xfc0000)==0x200000) { // word RAM
\r
1742 if(!(Pico_mcd->s68k_regs[3]&4)) // 2M?
\r
1743 return *(u8 *)(Pico_mcd->word_ram2M+((a^1)&0x3ffff));
\r
1744 else if (a < 0x220000) {
\r
1745 int bank = Pico_mcd->s68k_regs[3]&1;
\r
1746 return *(u8 *)(Pico_mcd->word_ram1M[bank]+((a^1)&0x1ffff));
\r
1749 elprintf(EL_ANOMALY, "m68k_read_pcrelative_CD8 FIXME: can't handle %06x", a);
\r
1751 return 0;//(u8) lastread_d;
\r
1753 unsigned int m68k_read_pcrelative_CD16(unsigned int a)
\r
1756 if(m68ki_cpu_p == &PicoCpuMS68k) {
\r
1757 if (a < 0x80000) return *(u16 *)(Pico_mcd->prg_ram+(a&~1)); // PRG Ram
\r
1758 if ((a&0xfc0000)==0x080000 && !(Pico_mcd->s68k_regs[3]&4)) // word RAM (2M area: 080000-0bffff)
\r
1759 return *(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe));
\r
1760 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // word RAM (1M area: 0c0000-0dffff)
\r
1761 int bank = (Pico_mcd->s68k_regs[3]&1)^1;
\r
1762 return *(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe));
\r
1764 elprintf(EL_ANOMALY, "s68k_read_pcrelative_CD16 FIXME: can't handle %06x", a);
\r
1766 if((a&0xe00000)==0xe00000) return *(u16 *)(Pico.ram+(a&0xfffe)); // Ram
\r
1767 if(a<0x20000) return *(u16 *)(Pico.rom+(a&~1)); // Bios
\r
1768 if((a&0xfc0000)==0x200000) { // word RAM
\r
1769 if(!(Pico_mcd->s68k_regs[3]&4)) // 2M?
\r
1770 return *(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe));
\r
1771 else if (a < 0x220000) {
\r
1772 int bank = Pico_mcd->s68k_regs[3]&1;
\r
1773 return *(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe));
\r
1776 elprintf(EL_ANOMALY, "m68k_read_pcrelative_CD16 FIXME: can't handle %06x", a);
\r
1780 unsigned int m68k_read_pcrelative_CD32(unsigned int a)
\r
1784 if(m68ki_cpu_p == &PicoCpuMS68k) {
\r
1785 if (a < 0x80000) { u16 *pm=(u16 *)(Pico_mcd->prg_ram+(a&~1)); return (pm[0]<<16)|pm[1]; } // PRG Ram
\r
1786 if ((a&0xfc0000)==0x080000 && !(Pico_mcd->s68k_regs[3]&4)) // word RAM (2M area: 080000-0bffff)
\r
1787 { pm=(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe)); return (pm[0]<<16)|pm[1]; }
\r
1788 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // word RAM (1M area: 0c0000-0dffff)
\r
1789 int bank = (Pico_mcd->s68k_regs[3]&1)^1;
\r
1790 pm=(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe));
\r
1791 return (pm[0]<<16)|pm[1];
\r
1793 elprintf(EL_ANOMALY, "s68k_read_pcrelative_CD32 FIXME: can't handle %06x", a);
\r
1795 if((a&0xe00000)==0xe00000) { u16 *pm=(u16 *)(Pico.ram+(a&0xfffe)); return (pm[0]<<16)|pm[1]; } // Ram
\r
1796 if(a<0x20000) { u16 *pm=(u16 *)(Pico.rom+(a&~1)); return (pm[0]<<16)|pm[1]; }
\r
1797 if((a&0xfc0000)==0x200000) { // word RAM
\r
1798 if(!(Pico_mcd->s68k_regs[3]&4)) // 2M?
\r
1799 { pm=(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe)); return (pm[0]<<16)|pm[1]; }
\r
1800 else if (a < 0x220000) {
\r
1801 int bank = Pico_mcd->s68k_regs[3]&1;
\r
1802 pm=(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe));
\r
1803 return (pm[0]<<16)|pm[1];
\r
1806 elprintf(EL_ANOMALY, "m68k_read_pcrelative_CD32 FIXME: can't handle %06x", a);
\r
1810 #endif // EMU_M68K
\r