1 // Memory I/O handlers for Sega/Mega CD.
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2 // Loosely based on Gens code.
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3 // (c) Copyright 2007, Grazvydas "notaz" Ignotas
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8 #include "../PicoInt.h"
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10 #include "../sound/ym2612.h"
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11 #include "../sound/sn76496.h"
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16 #ifndef UTYPES_DEFINED
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17 typedef unsigned char u8;
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18 typedef unsigned short u16;
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19 typedef unsigned int u32;
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20 #define UTYPES_DEFINED
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23 //#define __debug_io
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24 //#define __debug_io2
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26 //#define rdprintf dprintf
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27 #define rdprintf(...)
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28 //#define wrdprintf dprintf
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29 #define wrdprintf(...)
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30 #define plprintf dprintf
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31 //#define plprintf(...)
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33 #ifdef EMU_CORE_DEBUG
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34 extern u32 lastread_a, lastread_d[16], lastwrite_cyc_d[16];
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35 extern int lrp_cyc, lwp_cyc;
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36 #undef USE_POLL_DETECT
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39 // -----------------------------------------------------------------
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42 #define POLL_LIMIT 16
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43 #define POLL_CYCLES 124
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44 // int m68k_poll_addr, m68k_poll_cnt;
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45 unsigned int s68k_poll_adclk, s68k_poll_cnt;
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47 #ifndef _ASM_CD_MEMORY_C
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48 static u32 m68k_reg_read16(u32 a)
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52 // dprintf("m68k_regs r%2i: [%02x] @%06x", realsize&~1, a+(realsize&1), SekPc);
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56 d = ((Pico_mcd->s68k_regs[0x33]<<13)&0x8000) | Pico_mcd->m.busreq; // here IFL2 is always 0, just like in Gens
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59 d = (Pico_mcd->s68k_regs[a]<<8) | (Pico_mcd->s68k_regs[a+1]&0xc7);
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60 // the DMNA delay must only be visible on s68k side (Lunar2, Silpheed)
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61 if (Pico_mcd->m.state_flags&2) { d &= ~1; d |= 2; }
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62 //printf("m68k_regs r3: %02x @%06x\n", (u8)d, SekPc);
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65 d = Pico_mcd->s68k_regs[4]<<8;
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68 d = *(u16 *)(Pico_mcd->bios + 0x72);
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71 d = Read_CDC_Host(0);
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74 dprintf("m68k FIXME: reserved read");
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77 d = Pico_mcd->m.timer_stopwatch >> 16;
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78 dprintf("m68k stopwatch timer read (%04x)", d);
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83 // comm flag/cmd/status (0xE-0x2F)
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84 d = (Pico_mcd->s68k_regs[a]<<8) | Pico_mcd->s68k_regs[a+1];
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88 dprintf("m68k_regs FIXME invalid read @ %02x", a);
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92 // dprintf("ret = %04x", d);
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97 #ifndef _ASM_CD_MEMORY_C
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100 void m68k_reg_write8(u32 a, u32 d)
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103 // dprintf("m68k_regs w%2i: [%02x] %02x @%06x", realsize, a, d, SekPc);
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108 if ((d&1) && (Pico_mcd->s68k_regs[0x33]&(1<<2))) { dprintf("m68k: s68k irq 2"); SekInterruptS68k(2); }
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112 if (!(d&1)) Pico_mcd->m.state_flags |= 1; // reset pending, needed to be sure we fetch the right vectors on reset
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113 if ( (Pico_mcd->m.busreq&1) != (d&1)) dprintf("m68k: s68k reset %i", !(d&1));
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114 if ( (Pico_mcd->m.busreq&2) != (d&2)) dprintf("m68k: s68k brq %i", (d&2)>>1);
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115 if ((Pico_mcd->m.state_flags&1) && (d&3)==1) {
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116 SekResetS68k(); // S68k comes out of RESET or BRQ state
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117 Pico_mcd->m.state_flags&=~1;
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118 dprintf("m68k: resetting s68k, cycles=%i", SekCyclesLeft);
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120 Pico_mcd->m.busreq = d;
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123 dprintf("m68k: prg wp=%02x", d);
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124 Pico_mcd->s68k_regs[2] = d; // really use s68k side register
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127 u32 dold = Pico_mcd->s68k_regs[3]&0x1f;
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128 //printf("m68k_regs w3: %02x @%06x\n", (u8)d, SekPc);
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130 if ((dold>>6) != ((d>>6)&3))
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131 dprintf("m68k: prg bank: %i -> %i", (Pico_mcd->s68k_regs[a]>>6), ((d>>6)&3));
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132 //if ((Pico_mcd->s68k_regs[3]&4) != (d&4)) dprintf("m68k: ram mode %i mbit", (d&4) ? 1 : 2);
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133 //if ((Pico_mcd->s68k_regs[3]&2) != (d&2)) dprintf("m68k: %s", (d&4) ? ((d&2) ? "word swap req" : "noop?") :
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134 // ((d&2) ? "word ram to s68k" : "word ram to m68k"));
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136 d ^= 2; // writing 0 to DMNA actually sets it, 1 does nothing
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138 //dold &= ~2; // ??
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140 if ((d & 2) && !(dold & 2)) {
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141 Pico_mcd->m.state_flags |= 2; // we must delay setting DMNA bit (needed for Silpheed)
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145 if (d & 2) dold &= ~1; // return word RAM to s68k in 2M mode
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148 Pico_mcd->s68k_regs[3] = d | dold; // really use s68k side register
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149 #ifdef USE_POLL_DETECT
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150 if ((s68k_poll_adclk&0xfe) == 2 && s68k_poll_cnt > POLL_LIMIT) {
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151 SekSetStopS68k(0); s68k_poll_adclk = 0;
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152 plprintf("s68k poll release, a=%02x\n", a);
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158 Pico_mcd->bios[0x72 + 1] = d; // simple hint vector changer
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161 Pico_mcd->bios[0x72] = d;
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162 dprintf("hint vector set to %08x", PicoRead32(0x70));
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165 d = (d << 1) | ((d >> 7) & 1); // rol8 1 (special case)
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167 //dprintf("m68k: comm flag: %02x", d);
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168 Pico_mcd->s68k_regs[0xe] = d;
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169 #ifdef USE_POLL_DETECT
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170 if ((s68k_poll_adclk&0xfe) == 0xe && s68k_poll_cnt > POLL_LIMIT) {
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171 SekSetStopS68k(0); s68k_poll_adclk = 0;
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172 plprintf("s68k poll release, a=%02x\n", a);
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178 if ((a&0xf0) == 0x10) {
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179 Pico_mcd->s68k_regs[a] = d;
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180 #ifdef USE_POLL_DETECT
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181 if ((a&0xfe) == (s68k_poll_adclk&0xfe) && s68k_poll_cnt > POLL_LIMIT) {
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182 SekSetStopS68k(0); s68k_poll_adclk = 0;
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183 plprintf("s68k poll release, a=%02x\n", a);
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189 dprintf("m68k FIXME: invalid write? [%02x] %02x", a, d);
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192 #ifndef _ASM_CD_MEMORY_C
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195 u32 s68k_poll_detect(u32 a, u32 d)
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197 #ifdef USE_POLL_DETECT
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198 // polling detection
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199 if (a == (s68k_poll_adclk&0xff)) {
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200 unsigned int clkdiff = SekCyclesDoneS68k() - (s68k_poll_adclk>>8);
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201 if (clkdiff <= POLL_CYCLES) {
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203 //printf("-- diff: %u, cnt = %i\n", clkdiff, s68k_poll_cnt);
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204 if (s68k_poll_cnt > POLL_LIMIT) {
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206 plprintf("s68k poll detected @ %06x, a=%02x\n", SekPcS68k, a);
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208 s68k_poll_adclk = (SekCyclesDoneS68k() << 8) | a;
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212 s68k_poll_adclk = (SekCyclesDoneS68k() << 8) | a;
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218 #define READ_FONT_DATA(basemask) \
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220 unsigned int fnt = *(unsigned int *)(Pico_mcd->s68k_regs + 0x4c); \
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221 unsigned int col0 = (fnt >> 8) & 0x0f, col1 = (fnt >> 12) & 0x0f; \
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222 if (fnt & (basemask << 0)) d = col1 ; else d = col0; \
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223 if (fnt & (basemask << 1)) d |= col1 << 4; else d |= col0 << 4; \
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224 if (fnt & (basemask << 2)) d |= col1 << 8; else d |= col0 << 8; \
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225 if (fnt & (basemask << 3)) d |= col1 << 12; else d |= col0 << 12; \
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229 #ifndef _ASM_CD_MEMORY_C
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232 u32 s68k_reg_read16(u32 a)
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236 // dprintf("s68k_regs r%2i: [%02x] @ %06x", realsize&~1, a+(realsize&1), SekPcS68k);
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240 return ((Pico_mcd->s68k_regs[0]&3)<<8) | 1; // ver = 0, not in reset state
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242 d = (Pico_mcd->s68k_regs[2]<<8) | (Pico_mcd->s68k_regs[3]&0x1f);
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243 //printf("s68k_regs r3: %02x @%06x\n", (u8)d, SekPcS68k);
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244 return s68k_poll_detect(a, d);
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246 return CDC_Read_Reg();
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248 return Read_CDC_Host(1); // Gens returns 0 here on byte reads
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250 d = Pico_mcd->m.timer_stopwatch >> 16;
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251 dprintf("s68k stopwatch timer read (%04x)", d);
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254 dprintf("s68k int3 timer read (%02x)", Pico_mcd->s68k_regs[31]);
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255 return Pico_mcd->s68k_regs[31];
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256 case 0x34: // fader
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257 return 0; // no busy bit
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258 case 0x50: // font data (check: Lunar 2, Silpheed)
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259 READ_FONT_DATA(0x00100000);
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262 READ_FONT_DATA(0x00010000);
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265 READ_FONT_DATA(0x10000000);
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268 READ_FONT_DATA(0x01000000);
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272 d = (Pico_mcd->s68k_regs[a]<<8) | Pico_mcd->s68k_regs[a+1];
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274 if (a >= 0x0e && a < 0x30)
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275 return s68k_poll_detect(a, d);
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280 #ifndef _ASM_CD_MEMORY_C
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283 void s68k_reg_write8(u32 a, u32 d)
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285 //dprintf("s68k_regs w%2i: [%02x] %02x @ %06x", realsize, a, d, SekPcS68k);
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287 // Warning: d might have upper bits set
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290 return; // only m68k can change WP
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292 int dold = Pico_mcd->s68k_regs[3];
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293 //printf("s68k_regs w3: %02x @%06x\n", (u8)d, SekPcS68k);
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297 if ((d ^ dold) & 5) {
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298 d &= ~2; // in case of mode or bank change we clear DMNA (m68k req) bit
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301 #ifdef _ASM_CD_MEMORY_C
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302 if ((d ^ dold) & 0x1d)
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303 PicoMemResetCDdecode(d);
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306 dprintf("wram mode 2M->1M");
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307 wram_2M_to_1M(Pico_mcd->word_ram2M);
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311 dprintf("wram mode 1M->2M");
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312 if (!(d&1)) { // it didn't set the ret bit, which means it doesn't want to give WRAM to m68k
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314 d |= (dold&1) ? 2 : 1; // then give it to the one which had bank0 in 1M mode
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316 wram_1M_to_2M(Pico_mcd->word_ram2M);
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321 if (d&1) d &= ~2; // return word RAM to m68k in 2M mode
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326 dprintf("s68k CDC dest: %x", d&7);
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327 Pico_mcd->s68k_regs[4] = (Pico_mcd->s68k_regs[4]&0xC0) | (d&7); // CDC mode
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330 //dprintf("s68k CDC reg addr: %x", d&0xf);
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336 dprintf("s68k set CDC dma addr");
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340 dprintf("s68k set stopwatch timer");
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341 Pico_mcd->m.timer_stopwatch = 0;
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344 Pico_mcd->s68k_regs[0xf] = (d>>1) | (d<<7); // ror8 1, Gens note: Dragons lair
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347 dprintf("s68k set int3 timer: %02x", d);
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348 Pico_mcd->m.timer_int3 = (d & 0xff) << 16;
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350 case 0x33: // IRQ mask
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351 dprintf("s68k irq mask: %02x", d);
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352 if ((d&(1<<4)) && (Pico_mcd->s68k_regs[0x37]&4) && !(Pico_mcd->s68k_regs[0x33]&(1<<4))) {
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353 CDD_Export_Status();
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356 case 0x34: // fader
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357 Pico_mcd->s68k_regs[a] = (u8) d & 0x7f;
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360 return; // d/m bit is unsetable
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362 u32 d_old = Pico_mcd->s68k_regs[0x37];
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363 Pico_mcd->s68k_regs[0x37] = d&7;
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364 if ((d&4) && !(d_old&4)) {
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365 CDD_Export_Status();
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370 Pico_mcd->s68k_regs[a] = (u8) d;
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371 CDD_Import_Command();
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375 if ((a&0x1f0) == 0x10 || (a >= 0x38 && a < 0x42))
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377 dprintf("s68k FIXME: invalid write @ %02x?", a);
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381 Pico_mcd->s68k_regs[a] = (u8) d;
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385 #ifndef _ASM_CD_MEMORY_C
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386 static u32 OtherRead16End(u32 a, int realsize)
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390 if ((a&0xffffc0)==0xa12000) {
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391 d=m68k_reg_read16(a);
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396 if (SRam.data != NULL) d=3; // 64k cart
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400 if ((a&0xfe0000)==0x600000) {
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401 if (SRam.data != NULL) {
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402 d=SRam.data[((a>>1)&0xffff)+0x2000];
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403 if (realsize == 8) d|=d<<8;
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409 d=Pico_mcd->m.bcram_reg;
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413 dprintf("m68k FIXME: unusual r%i: %06x @%06x", realsize&~1, (a&0xfffffe)+(realsize&1), SekPc);
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420 static void OtherWrite8End(u32 a, u32 d, int realsize)
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422 if ((a&0xffffc0)==0xa12000) { m68k_reg_write8(a, d); return; }
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424 if ((a&0xfe0000)==0x600000) {
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425 if (SRam.data != NULL && (Pico_mcd->m.bcram_reg&1)) {
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426 SRam.data[((a>>1)&0xffff)+0x2000]=d;
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433 Pico_mcd->m.bcram_reg=d;
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437 dprintf("m68k FIXME: strange w%i: [%06x], %08x @%06x", realsize, a&0xffffff, d, SekPc);
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440 #define _CD_MEMORY_C
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441 #undef _ASM_MEMORY_C
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442 #include "../MemoryCmn.c"
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443 #include "cell_map.c"
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444 #endif // !def _ASM_CD_MEMORY_C
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447 // -----------------------------------------------------------------
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448 // Read Rom and read Ram
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450 #ifdef _ASM_CD_MEMORY_C
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451 u32 PicoReadM68k8(u32 a);
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453 static u32 PicoReadM68k8(u32 a)
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457 if ((a&0xe00000)==0xe00000) { d = *(u8 *)(Pico.ram+((a^1)&0xffff)); goto end; } // Ram
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461 if (a < 0x20000) { d = *(u8 *)(Pico_mcd->bios+(a^1)); goto end; } // bios
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464 if ((a&0xfe0000)==0x020000 && (Pico_mcd->m.busreq&3)!=1) {
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465 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
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466 d = *(prg_bank+((a^1)&0x1ffff));
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471 if ((a&0xfc0000)==0x200000) {
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472 wrdprintf("m68k_wram r8: [%06x] @%06x", a, SekPc);
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473 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
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474 int bank = Pico_mcd->s68k_regs[3]&1;
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476 a = (a&3) | (cell_map(a >> 2) << 2); // cell arranged
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478 d = Pico_mcd->word_ram1M[bank][a^1];
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480 // allow access in any mode, like Gens does
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481 d = Pico_mcd->word_ram2M[(a^1)&0x3ffff];
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483 wrdprintf("ret = %02x", (u8)d);
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487 if ((a&0xff4000)==0xa00000) { d=z80Read8(a); goto end; } // Z80 Ram
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489 if ((a&0xffffc0)==0xa12000)
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490 rdprintf("m68k_regs r8: [%02x] @%06x", a&0x3f, SekPc);
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492 d=OtherRead16(a&~1, 8|(a&1)); if ((a&1)==0) d>>=8;
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494 if ((a&0xffffc0)==0xa12000)
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495 rdprintf("ret = %02x", (u8)d);
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500 dprintf("r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPc);
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502 #ifdef EMU_CORE_DEBUG
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503 if (a>=Pico.romsize) {
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505 lastread_d[lrp_cyc++&15] = d;
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513 #ifdef _ASM_CD_MEMORY_C
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514 u32 PicoReadM68k16(u32 a);
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516 static u32 PicoReadM68k16(u32 a)
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520 if ((a&0xe00000)==0xe00000) { d=*(u16 *)(Pico.ram+(a&0xfffe)); goto end; } // Ram
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524 if (a < 0x20000) { d = *(u16 *)(Pico_mcd->bios+a); goto end; } // bios
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527 if ((a&0xfe0000)==0x020000 && (Pico_mcd->m.busreq&3)!=1) {
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528 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
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529 wrdprintf("m68k_prgram r16: [%i,%06x] @%06x", Pico_mcd->s68k_regs[3]>>6, a, SekPc);
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530 d = *(u16 *)(prg_bank+(a&0x1fffe));
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531 wrdprintf("ret = %04x", d);
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536 if ((a&0xfc0000)==0x200000) {
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537 wrdprintf("m68k_wram r16: [%06x] @%06x", a, SekPc);
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538 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
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539 int bank = Pico_mcd->s68k_regs[3]&1;
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541 a = (a&2) | (cell_map(a >> 2) << 2); // cell arranged
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543 d = *(u16 *)(Pico_mcd->word_ram1M[bank]+a);
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545 // allow access in any mode, like Gens does
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546 d = *(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe));
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548 wrdprintf("ret = %04x", d);
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552 if ((a&0xffffc0)==0xa12000)
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553 rdprintf("m68k_regs r16: [%02x] @%06x", a&0x3f, SekPc);
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555 d = OtherRead16(a, 16);
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557 if ((a&0xffffc0)==0xa12000)
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558 rdprintf("ret = %04x", d);
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563 dprintf("r16: %06x, %04x @%06x", a&0xffffff, d, SekPc);
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565 #ifdef EMU_CORE_DEBUG
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566 if (a>=Pico.romsize) {
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568 lastread_d[lrp_cyc++&15] = d;
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576 #ifdef _ASM_CD_MEMORY_C
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577 u32 PicoReadM68k32(u32 a);
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579 static u32 PicoReadM68k32(u32 a)
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583 if ((a&0xe00000)==0xe00000) { u16 *pm=(u16 *)(Pico.ram+(a&0xfffe)); d = (pm[0]<<16)|pm[1]; goto end; } // Ram
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587 if (a < 0x20000) { u16 *pm=(u16 *)(Pico_mcd->bios+a); d = (pm[0]<<16)|pm[1]; goto end; } // bios
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590 if ((a&0xfe0000)==0x020000 && (Pico_mcd->m.busreq&3)!=1) {
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591 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
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592 u16 *pm=(u16 *)(prg_bank+(a&0x1fffe));
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593 d = (pm[0]<<16)|pm[1];
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598 if ((a&0xfc0000)==0x200000) {
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599 wrdprintf("m68k_wram r32: [%06x] @%06x", a, SekPc);
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600 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
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601 int bank = Pico_mcd->s68k_regs[3]&1;
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602 if (a >= 0x220000) { // cell arranged
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604 a1 = (a&2) | (cell_map(a >> 2) << 2);
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605 if (a&2) a2 = cell_map((a+2) >> 2) << 2;
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607 d = *(u16 *)(Pico_mcd->word_ram1M[bank]+a1) << 16;
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608 d |= *(u16 *)(Pico_mcd->word_ram1M[bank]+a2);
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610 u16 *pm=(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe)); d = (pm[0]<<16)|pm[1];
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613 // allow access in any mode, like Gens does
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614 u16 *pm=(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe)); d = (pm[0]<<16)|pm[1];
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616 wrdprintf("ret = %08x", d);
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620 if ((a&0xffffc0)==0xa12000)
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621 rdprintf("m68k_regs r32: [%02x] @%06x", a&0x3f, SekPc);
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623 d = (OtherRead16(a, 32)<<16)|OtherRead16(a+2, 32);
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625 if ((a&0xffffc0)==0xa12000)
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626 rdprintf("ret = %08x", d);
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630 dprintf("r32: %06x, %08x @%06x", a&0xffffff, d, SekPc);
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632 #ifdef EMU_CORE_DEBUG
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633 if (a>=Pico.romsize) {
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635 lastread_d[lrp_cyc++&15] = d;
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643 // -----------------------------------------------------------------
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645 #ifdef _ASM_CD_MEMORY_C
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646 void PicoWriteM68k8(u32 a,u8 d);
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648 static void PicoWriteM68k8(u32 a,u8 d)
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651 dprintf("w8 : %06x, %02x @%06x", a&0xffffff, d, SekPc);
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653 #ifdef EMU_CORE_DEBUG
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654 lastwrite_cyc_d[lwp_cyc++&15] = d;
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657 if ((a&0xe00000)==0xe00000) { // Ram
\r
658 *(u8 *)(Pico.ram+((a^1)&0xffff)) = d;
\r
665 if ((a&0xfe0000)==0x020000 && (Pico_mcd->m.busreq&3)!=1) {
\r
666 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
\r
667 *(u8 *)(prg_bank+((a^1)&0x1ffff))=d;
\r
672 if ((a&0xfc0000)==0x200000) {
\r
673 wrdprintf("m68k_wram w8: [%06x] %02x @%06x", a, d, SekPc);
\r
674 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
675 int bank = Pico_mcd->s68k_regs[3]&1;
\r
677 a = (a&3) | (cell_map(a >> 2) << 2); // cell arranged
\r
679 *(u8 *)(Pico_mcd->word_ram1M[bank]+(a^1))=d;
\r
681 // allow access in any mode, like Gens does
\r
682 *(u8 *)(Pico_mcd->word_ram2M+((a^1)&0x3ffff))=d;
\r
687 if ((a&0xffffc0)==0xa12000) {
\r
688 rdprintf("m68k_regs w8: [%02x] %02x @%06x", a&0x3f, d, SekPc);
\r
689 m68k_reg_write8(a, d);
\r
698 #ifdef _ASM_CD_MEMORY_C
\r
699 void PicoWriteM68k16(u32 a,u16 d);
\r
701 static void PicoWriteM68k16(u32 a,u16 d)
\r
704 dprintf("w16: %06x, %04x", a&0xffffff, d);
\r
706 #ifdef EMU_CORE_DEBUG
\r
707 lastwrite_cyc_d[lwp_cyc++&15] = d;
\r
710 if ((a&0xe00000)==0xe00000) { // Ram
\r
711 *(u16 *)(Pico.ram+(a&0xfffe))=d;
\r
718 if ((a&0xfe0000)==0x020000 && (Pico_mcd->m.busreq&3)!=1) {
\r
719 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
\r
720 wrdprintf("m68k_prgram w16: [%i,%06x] %04x @%06x", Pico_mcd->s68k_regs[3]>>6, a, d, SekPc);
\r
721 *(u16 *)(prg_bank+(a&0x1fffe))=d;
\r
726 if ((a&0xfc0000)==0x200000) {
\r
727 wrdprintf("m68k_wram w16: [%06x] %04x @%06x", a, d, SekPc);
\r
728 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
729 int bank = Pico_mcd->s68k_regs[3]&1;
\r
731 a = (a&2) | (cell_map(a >> 2) << 2); // cell arranged
\r
733 *(u16 *)(Pico_mcd->word_ram1M[bank]+a)=d;
\r
735 // allow access in any mode, like Gens does
\r
736 *(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe))=d;
\r
742 if ((a&0xffffc0)==0xa12000) {
\r
743 rdprintf("m68k_regs w16: [%02x] %04x @%06x", a&0x3f, d, SekPc);
\r
744 if (a == 0xe) { // special case, 2 byte writes would be handled differently
\r
745 Pico_mcd->s68k_regs[0xe] = d >> 8;
\r
746 #ifdef USE_POLL_DETECT
\r
747 if ((s68k_poll_adclk&0xfe) == 0xe && s68k_poll_cnt > POLL_LIMIT) {
\r
748 SekSetStopS68k(0); s68k_poll_adclk = 0;
\r
749 plprintf("s68k poll release, a=%02x\n", a);
\r
754 m68k_reg_write8(a, d>>8);
\r
755 m68k_reg_write8(a+1,d&0xff);
\r
764 #ifdef _ASM_CD_MEMORY_C
\r
765 void PicoWriteM68k32(u32 a,u32 d);
\r
767 static void PicoWriteM68k32(u32 a,u32 d)
\r
770 dprintf("w32: %06x, %08x", a&0xffffff, d);
\r
772 #ifdef EMU_CORE_DEBUG
\r
773 lastwrite_cyc_d[lwp_cyc++&15] = d;
\r
776 if ((a&0xe00000)==0xe00000)
\r
779 u16 *pm=(u16 *)(Pico.ram+(a&0xfffe));
\r
780 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
787 if ((a&0xfe0000)==0x020000 && (Pico_mcd->m.busreq&3)!=1) {
\r
788 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
\r
789 u16 *pm=(u16 *)(prg_bank+(a&0x1fffe));
\r
790 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
795 if ((a&0xfc0000)==0x200000) {
\r
796 if (d != 0) // don't log clears
\r
797 wrdprintf("m68k_wram w32: [%06x] %08x @%06x", a, d, SekPc);
\r
798 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
799 int bank = Pico_mcd->s68k_regs[3]&1;
\r
800 if (a >= 0x220000) { // cell arranged
\r
802 a1 = (a&2) | (cell_map(a >> 2) << 2);
\r
803 if (a&2) a2 = cell_map((a+2) >> 2) << 2;
\r
805 *(u16 *)(Pico_mcd->word_ram1M[bank]+a1) = d >> 16;
\r
806 *(u16 *)(Pico_mcd->word_ram1M[bank]+a2) = d;
\r
808 u16 *pm=(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe));
\r
809 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
812 // allow access in any mode, like Gens does
\r
813 u16 *pm=(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe));
\r
814 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
819 if ((a&0xffffc0)==0xa12000) {
\r
820 rdprintf("m68k_regs w32: [%02x] %08x @%06x", a&0x3f, d, SekPc);
\r
821 if ((a&0x3e) == 0xe) dprintf("m68k FIXME: w32 [%02x]", a&0x3f);
\r
824 OtherWrite16(a, (u16)(d>>16));
\r
825 OtherWrite16(a+2,(u16)d);
\r
830 // -----------------------------------------------------------------
\r
832 // -----------------------------------------------------------------
\r
834 #ifdef _ASM_CD_MEMORY_C
\r
835 u32 PicoReadS68k8(u32 a);
\r
837 static u32 PicoReadS68k8(u32 a)
\r
841 #ifdef EMU_CORE_DEBUG
\r
848 d = *(Pico_mcd->prg_ram+(a^1));
\r
853 if ((a&0xfffe00) == 0xff8000) {
\r
855 rdprintf("s68k_regs r8: [%02x] @ %06x", a, SekPcS68k);
\r
856 if (a >= 0x0e && a < 0x30) {
\r
857 d = Pico_mcd->s68k_regs[a];
\r
858 s68k_poll_detect(a, d);
\r
859 rdprintf("ret = %02x", (u8)d);
\r
862 else if (a >= 0x58 && a < 0x68)
\r
863 d = gfx_cd_read(a&~1);
\r
864 else d = s68k_reg_read16(a&~1);
\r
865 if ((a&1)==0) d>>=8;
\r
866 rdprintf("ret = %02x", (u8)d);
\r
870 // word RAM (2M area)
\r
871 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
872 // test: batman returns
\r
873 wrdprintf("s68k_wram2M r8: [%06x] @%06x", a, SekPcS68k);
\r
874 if (Pico_mcd->s68k_regs[3]&4) { // 1M decode mode?
\r
875 int bank = (Pico_mcd->s68k_regs[3]&1)^1;
\r
876 d = Pico_mcd->word_ram1M[bank][((a>>1)^1)&0x1ffff];
\r
877 if (a&1) d &= 0x0f;
\r
879 dprintf("FIXME: decode");
\r
881 // allow access in any mode, like Gens does
\r
882 d = Pico_mcd->word_ram2M[(a^1)&0x3ffff];
\r
884 wrdprintf("ret = %02x", (u8)d);
\r
888 // word RAM (1M area)
\r
889 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
891 wrdprintf("s68k_wram1M r8: [%06x] @%06x", a, SekPcS68k);
\r
892 // if (!(Pico_mcd->s68k_regs[3]&4))
\r
893 // dprintf("s68k_wram1M FIXME: wrong mode");
\r
894 bank = (Pico_mcd->s68k_regs[3]&1)^1;
\r
895 d = Pico_mcd->word_ram1M[bank][(a^1)&0x1ffff];
\r
896 wrdprintf("ret = %02x", (u8)d);
\r
901 if ((a&0xff8000)==0xff0000) {
\r
902 dprintf("s68k_pcm r8: [%06x] @%06x", a, SekPcS68k);
\r
905 d = Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a>>1)&0xfff];
\r
906 else if (a >= 0x20) {
\r
908 d = Pico_mcd->pcm.ch[a>>2].addr >> PCM_STEP_SHIFT;
\r
909 if (a & 2) d >>= 8;
\r
911 dprintf("ret = %02x", (u8)d);
\r
916 if ((a&0xff0000)==0xfe0000) {
\r
917 d = Pico_mcd->bram[(a>>1)&0x1fff];
\r
921 dprintf("s68k r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPcS68k);
\r
926 dprintf("s68k r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPcS68k);
\r
928 #ifdef EMU_CORE_DEBUG
\r
930 lastread_d[lrp_cyc++&15] = d;
\r
937 #ifdef _ASM_CD_MEMORY_C
\r
938 u32 PicoReadS68k16(u32 a);
\r
940 static u32 PicoReadS68k16(u32 a)
\r
944 #ifdef EMU_CORE_DEBUG
\r
951 wrdprintf("s68k_prgram r16: [%06x] @%06x", a, SekPcS68k);
\r
952 d = *(u16 *)(Pico_mcd->prg_ram+a);
\r
953 wrdprintf("ret = %04x", d);
\r
958 if ((a&0xfffe00) == 0xff8000) {
\r
960 rdprintf("s68k_regs r16: [%02x] @ %06x", a, SekPcS68k);
\r
961 if (a >= 0x58 && a < 0x68)
\r
962 d = gfx_cd_read(a);
\r
963 else d = s68k_reg_read16(a);
\r
964 rdprintf("ret = %04x", d);
\r
968 // word RAM (2M area)
\r
969 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
970 wrdprintf("s68k_wram2M r16: [%06x] @%06x", a, SekPcS68k);
\r
971 if (Pico_mcd->s68k_regs[3]&4) { // 1M decode mode?
\r
972 int bank = (Pico_mcd->s68k_regs[3]&1)^1;
\r
973 d = Pico_mcd->word_ram1M[bank][((a>>1)^1)&0x1ffff];
\r
974 d |= d << 4; d &= ~0xf0;
\r
975 dprintf("FIXME: decode");
\r
977 // allow access in any mode, like Gens does
\r
978 d = *(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe));
\r
980 wrdprintf("ret = %04x", d);
\r
984 // word RAM (1M area)
\r
985 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
987 wrdprintf("s68k_wram1M r16: [%06x] @%06x", a, SekPcS68k);
\r
988 // if (!(Pico_mcd->s68k_regs[3]&4))
\r
989 // dprintf("s68k_wram1M FIXME: wrong mode");
\r
990 bank = (Pico_mcd->s68k_regs[3]&1)^1;
\r
991 d = *(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe));
\r
992 wrdprintf("ret = %04x", d);
\r
997 if ((a&0xff0000)==0xfe0000) {
\r
998 dprintf("FIXME: s68k_bram r16: [%06x] @%06x", a, SekPcS68k);
\r
1000 d = Pico_mcd->bram[a++]; // Gens does little endian here, and so do we..
\r
1001 d|= Pico_mcd->bram[a++] << 8; // This is most likely wrong
\r
1002 dprintf("ret = %04x", d);
\r
1007 if ((a&0xff8000)==0xff0000) {
\r
1008 dprintf("FIXME: s68k_pcm r16: [%06x] @%06x", a, SekPcS68k);
\r
1011 d = Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a>>1)&0xfff];
\r
1012 else if (a >= 0x20) {
\r
1014 d = Pico_mcd->pcm.ch[a>>2].addr >> PCM_STEP_SHIFT;
\r
1015 if (a & 2) d >>= 8;
\r
1017 dprintf("ret = %04x", d);
\r
1021 dprintf("s68k r16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);
\r
1025 #ifdef __debug_io2
\r
1026 dprintf("s68k r16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);
\r
1028 #ifdef EMU_CORE_DEBUG
\r
1030 lastread_d[lrp_cyc++&15] = d;
\r
1037 #ifdef _ASM_CD_MEMORY_C
\r
1038 u32 PicoReadS68k32(u32 a);
\r
1040 static u32 PicoReadS68k32(u32 a)
\r
1044 #ifdef EMU_CORE_DEBUG
\r
1045 u32 ab=a&0xfffffe;
\r
1050 if (a < 0x80000) {
\r
1051 u16 *pm=(u16 *)(Pico_mcd->prg_ram+a);
\r
1052 d = (pm[0]<<16)|pm[1];
\r
1057 if ((a&0xfffe00) == 0xff8000) {
\r
1059 rdprintf("s68k_regs r32: [%02x] @ %06x", a, SekPcS68k);
\r
1060 if (a >= 0x58 && a < 0x68)
\r
1061 d = (gfx_cd_read(a)<<16)|gfx_cd_read(a+2);
\r
1062 else d = (s68k_reg_read16(a)<<16)|s68k_reg_read16(a+2);
\r
1063 rdprintf("ret = %08x", d);
\r
1067 // word RAM (2M area)
\r
1068 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
1069 wrdprintf("s68k_wram2M r32: [%06x] @%06x", a, SekPcS68k);
\r
1070 if (Pico_mcd->s68k_regs[3]&4) { // 1M decode mode?
\r
1071 int bank = (Pico_mcd->s68k_regs[3]&1)^1;
\r
1073 d = Pico_mcd->word_ram1M[bank][((a+0)^1)&0x1ffff] << 16;
\r
1074 d |= Pico_mcd->word_ram1M[bank][((a+1)^1)&0x1ffff];
\r
1075 d |= d << 4; d &= 0x0f0f0f0f;
\r
1077 // allow access in any mode, like Gens does
\r
1078 u16 *pm=(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe)); d = (pm[0]<<16)|pm[1];
\r
1080 wrdprintf("ret = %08x", d);
\r
1084 // word RAM (1M area)
\r
1085 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
1087 wrdprintf("s68k_wram1M r32: [%06x] @%06x", a, SekPcS68k);
\r
1088 // if (!(Pico_mcd->s68k_regs[3]&4))
\r
1089 // dprintf("s68k_wram1M FIXME: wrong mode");
\r
1090 bank = (Pico_mcd->s68k_regs[3]&1)^1;
\r
1091 u16 *pm=(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe)); d = (pm[0]<<16)|pm[1];
\r
1092 wrdprintf("ret = %08x", d);
\r
1097 if ((a&0xff8000)==0xff0000) {
\r
1098 dprintf("s68k_pcm r32: [%06x] @%06x", a, SekPcS68k);
\r
1100 if (a >= 0x2000) {
\r
1102 d = Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][a&0xfff] << 16;
\r
1103 d |= Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a+1)&0xfff];
\r
1104 } else if (a >= 0x20) {
\r
1108 d = (Pico_mcd->pcm.ch[a].addr >> (PCM_STEP_SHIFT-8)) & 0xff0000;
\r
1109 d |= (Pico_mcd->pcm.ch[(a+1)&7].addr >> PCM_STEP_SHIFT) & 0xff;
\r
1111 d = Pico_mcd->pcm.ch[a>>2].addr >> PCM_STEP_SHIFT;
\r
1112 d = ((d<<16)&0xff0000) | ((d>>8)&0xff); // PCM chip is LE
\r
1115 dprintf("ret = %08x", d);
\r
1120 if ((a&0xff0000)==0xfe0000) {
\r
1121 dprintf("FIXME: s68k_bram r32: [%06x] @%06x", a, SekPcS68k);
\r
1122 a = (a>>1)&0x1fff;
\r
1123 d = Pico_mcd->bram[a++] << 16; // middle endian? TODO: verify against Fusion..
\r
1124 d|= Pico_mcd->bram[a++] << 24;
\r
1125 d|= Pico_mcd->bram[a++];
\r
1126 d|= Pico_mcd->bram[a++] << 8;
\r
1127 dprintf("ret = %08x", d);
\r
1131 dprintf("s68k r32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);
\r
1135 #ifdef __debug_io2
\r
1136 dprintf("s68k r32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);
\r
1138 #ifdef EMU_CORE_DEBUG
\r
1139 if (ab > 0x78) { // not vectors and stuff
\r
1141 lastread_d[lrp_cyc++&15] = d;
\r
1149 #ifndef _ASM_CD_MEMORY_C
\r
1150 /* check: jaguar xj 220 (draws entire world using decode) */
\r
1151 static void decode_write8(u32 a, u8 d, int r3)
\r
1153 u8 *pd = Pico_mcd->word_ram1M[(r3 & 1)^1] + (((a>>1)^1)&0x1ffff);
\r
1154 u8 oldmask = (a&1) ? 0xf0 : 0x0f;
\r
1158 if (!(a&1)) d <<= 4;
\r
1161 if ((!(*pd & (~oldmask))) && d) goto do_it;
\r
1162 } else if (r3 > 8) {
\r
1163 if (d) goto do_it;
\r
1170 *pd = d | (*pd & oldmask);
\r
1174 static void decode_write16(u32 a, u16 d, int r3)
\r
1176 u8 *pd = Pico_mcd->word_ram1M[(r3 & 1)^1] + (((a>>1)^1)&0x1ffff);
\r
1178 //if ((a & 0x3ffff) < 0x28000) return;
\r
1186 if (!(dold & 0xf0)) dold |= d & 0xf0;
\r
1187 if (!(dold & 0x0f)) dold |= d & 0x0f;
\r
1189 } else if (r3 > 8) {
\r
1191 if (!(d & 0xf0)) d |= dold & 0xf0;
\r
1192 if (!(d & 0x0f)) d |= dold & 0x0f;
\r
1200 // -----------------------------------------------------------------
\r
1202 #ifdef _ASM_CD_MEMORY_C
\r
1203 void PicoWriteS68k8(u32 a,u8 d);
\r
1205 static void PicoWriteS68k8(u32 a,u8 d)
\r
1207 #ifdef __debug_io2
\r
1208 dprintf("s68k w8 : %06x, %02x @%06x", a&0xffffff, d, SekPcS68k);
\r
1213 #ifdef EMU_CORE_DEBUG
\r
1214 lastwrite_cyc_d[lwp_cyc++&15] = d;
\r
1218 if (a < 0x80000) {
\r
1219 u8 *pm=(u8 *)(Pico_mcd->prg_ram+(a^1));
\r
1220 if (a >= (Pico_mcd->s68k_regs[2]<<8)) *pm=d;
\r
1225 if ((a&0xfffe00) == 0xff8000) {
\r
1227 rdprintf("s68k_regs w8: [%02x] %02x @ %06x", a, d, SekPcS68k);
\r
1228 if (a >= 0x58 && a < 0x68)
\r
1229 gfx_cd_write16(a&~1, (d<<8)|d);
\r
1230 else s68k_reg_write8(a,d);
\r
1234 // word RAM (2M area)
\r
1235 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
1236 int r3 = Pico_mcd->s68k_regs[3];
\r
1237 wrdprintf("s68k_wram2M w8: [%06x] %02x @%06x", a, d, SekPcS68k);
\r
1238 if (r3 & 4) { // 1M decode mode?
\r
1239 decode_write8(a, d, r3);
\r
1241 // allow access in any mode, like Gens does
\r
1242 *(u8 *)(Pico_mcd->word_ram2M+((a^1)&0x3ffff))=d;
\r
1247 // word RAM (1M area)
\r
1248 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
1249 // Wing Commander tries to write here in wrong mode
\r
1252 wrdprintf("s68k_wram1M w8: [%06x] %02x @%06x", a, d, SekPcS68k);
\r
1253 // if (!(Pico_mcd->s68k_regs[3]&4))
\r
1254 // dprintf("s68k_wram1M FIXME: wrong mode");
\r
1255 bank = (Pico_mcd->s68k_regs[3]&1)^1;
\r
1256 *(u8 *)(Pico_mcd->word_ram1M[bank]+((a^1)&0x1ffff))=d;
\r
1261 if ((a&0xff8000)==0xff0000) {
\r
1264 Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a>>1)&0xfff] = d;
\r
1265 else if (a < 0x12)
\r
1266 pcm_write(a>>1, d);
\r
1271 if ((a&0xff0000)==0xfe0000) {
\r
1272 Pico_mcd->bram[(a>>1)&0x1fff] = d;
\r
1277 dprintf("s68k w8 : %06x, %02x @%06x", a&0xffffff, d, SekPcS68k);
\r
1282 #ifdef _ASM_CD_MEMORY_C
\r
1283 void PicoWriteS68k16(u32 a,u16 d);
\r
1285 static void PicoWriteS68k16(u32 a,u16 d)
\r
1287 #ifdef __debug_io2
\r
1288 dprintf("s68k w16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);
\r
1293 #ifdef EMU_CORE_DEBUG
\r
1294 lastwrite_cyc_d[lwp_cyc++&15] = d;
\r
1298 if (a < 0x80000) {
\r
1299 wrdprintf("s68k_prgram w16: [%06x] %04x @%06x", a, d, SekPcS68k);
\r
1300 if (a >= (Pico_mcd->s68k_regs[2]<<8)) // needed for Dungeon Explorer
\r
1301 *(u16 *)(Pico_mcd->prg_ram+a)=d;
\r
1306 if ((a&0xfffe00) == 0xff8000) {
\r
1308 rdprintf("s68k_regs w16: [%02x] %04x @ %06x", a, d, SekPcS68k);
\r
1309 if (a >= 0x58 && a < 0x68)
\r
1310 gfx_cd_write16(a, d);
\r
1312 if (a == 0xe) { // special case, 2 byte writes would be handled differently
\r
1313 Pico_mcd->s68k_regs[0xf] = d;
\r
1316 s68k_reg_write8(a, d>>8);
\r
1317 s68k_reg_write8(a+1,d&0xff);
\r
1322 // word RAM (2M area)
\r
1323 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
1324 int r3 = Pico_mcd->s68k_regs[3];
\r
1325 wrdprintf("s68k_wram2M w16: [%06x] %04x @%06x", a, d, SekPcS68k);
\r
1326 if (r3 & 4) { // 1M decode mode?
\r
1327 decode_write16(a, d, r3);
\r
1329 // allow access in any mode, like Gens does
\r
1330 *(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe))=d;
\r
1335 // word RAM (1M area)
\r
1336 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
1339 wrdprintf("s68k_wram1M w16: [%06x] %04x @%06x", a, d, SekPcS68k);
\r
1340 // if (!(Pico_mcd->s68k_regs[3]&4))
\r
1341 // dprintf("s68k_wram1M FIXME: wrong mode");
\r
1342 bank = (Pico_mcd->s68k_regs[3]&1)^1;
\r
1343 *(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe))=d;
\r
1348 if ((a&0xff8000)==0xff0000) {
\r
1351 Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a>>1)&0xfff] = d;
\r
1352 else if (a < 0x12)
\r
1353 pcm_write(a>>1, d & 0xff);
\r
1358 if ((a&0xff0000)==0xfe0000) {
\r
1359 dprintf("s68k_bram w16: [%06x] %04x @%06x", a, d, SekPcS68k);
\r
1360 a = (a>>1)&0x1fff;
\r
1361 Pico_mcd->bram[a++] = d; // Gens does little endian here, an so do we..
\r
1362 Pico_mcd->bram[a++] = d >> 8;
\r
1367 dprintf("s68k w16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);
\r
1372 #ifdef _ASM_CD_MEMORY_C
\r
1373 void PicoWriteS68k32(u32 a,u32 d);
\r
1375 static void PicoWriteS68k32(u32 a,u32 d)
\r
1377 #ifdef __debug_io2
\r
1378 dprintf("s68k w32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);
\r
1383 #ifdef EMU_CORE_DEBUG
\r
1384 lastwrite_cyc_d[lwp_cyc++&15] = d;
\r
1388 if (a < 0x80000) {
\r
1389 if (a >= (Pico_mcd->s68k_regs[2]<<8)) {
\r
1390 u16 *pm=(u16 *)(Pico_mcd->prg_ram+a);
\r
1391 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
1397 if ((a&0xfffe00) == 0xff8000) {
\r
1399 rdprintf("s68k_regs w32: [%02x] %08x @ %06x", a, d, SekPcS68k);
\r
1400 if (a >= 0x58 && a < 0x68) {
\r
1401 gfx_cd_write16(a, d>>16);
\r
1402 gfx_cd_write16(a+2, d&0xffff);
\r
1404 if ((a&0x1fe) == 0xe) dprintf("s68k FIXME: w32 [%02x]", a&0x3f);
\r
1405 s68k_reg_write8(a, d>>24);
\r
1406 s68k_reg_write8(a+1,(d>>16)&0xff);
\r
1407 s68k_reg_write8(a+2,(d>>8) &0xff);
\r
1408 s68k_reg_write8(a+3, d &0xff);
\r
1413 // word RAM (2M area)
\r
1414 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
1415 int r3 = Pico_mcd->s68k_regs[3];
\r
1416 wrdprintf("s68k_wram2M w32: [%06x] %08x @%06x", a, d, SekPcS68k);
\r
1417 if (r3 & 4) { // 1M decode mode?
\r
1418 decode_write16(a , d >> 16, r3);
\r
1419 decode_write16(a+2, d , r3);
\r
1421 // allow access in any mode, like Gens does
\r
1422 u16 *pm=(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe));
\r
1423 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
1428 // word RAM (1M area)
\r
1429 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
1433 wrdprintf("s68k_wram1M w32: [%06x] %08x @%06x", a, d, SekPcS68k);
\r
1434 // if (!(Pico_mcd->s68k_regs[3]&4))
\r
1435 // dprintf("s68k_wram1M FIXME: wrong mode");
\r
1436 bank = (Pico_mcd->s68k_regs[3]&1)^1;
\r
1437 pm=(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe));
\r
1438 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
1443 if ((a&0xff8000)==0xff0000) {
\r
1445 if (a >= 0x2000) {
\r
1447 Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][a&0xfff] = (d >> 16);
\r
1448 Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a+1)&0xfff] = d;
\r
1449 } else if (a < 0x12) {
\r
1451 pcm_write(a, (d>>16) & 0xff);
\r
1452 pcm_write(a+1, d & 0xff);
\r
1458 if ((a&0xff0000)==0xfe0000) {
\r
1459 dprintf("s68k_bram w32: [%06x] %08x @%06x", a, d, SekPcS68k);
\r
1460 a = (a>>1)&0x1fff;
\r
1461 Pico_mcd->bram[a++] = d >> 16; // middle endian? verify?
\r
1462 Pico_mcd->bram[a++] = d >> 24;
\r
1463 Pico_mcd->bram[a++] = d;
\r
1464 Pico_mcd->bram[a++] = d >> 8;
\r
1469 dprintf("s68k w32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);
\r
1474 // -----------------------------------------------------------------
\r
1478 static __inline int PicoMemBaseM68k(u32 pc)
\r
1480 if ((pc&0xe00000)==0xe00000)
\r
1481 return (int)Pico.ram-(pc&0xff0000); // Program Counter in Ram
\r
1484 return (int)Pico_mcd->bios; // Program Counter in BIOS
\r
1486 if ((pc&0xfc0000)==0x200000)
\r
1488 if (!(Pico_mcd->s68k_regs[3]&4))
\r
1489 return (int)Pico_mcd->word_ram2M - 0x200000; // Program Counter in Word Ram
\r
1490 if (pc < 0x220000) {
\r
1491 int bank = Pico_mcd->s68k_regs[3]&1;
\r
1492 return (int)Pico_mcd->word_ram1M[bank] - 0x200000;
\r
1496 // Error - Program Counter is invalid
\r
1497 dprintf("m68k FIXME: unhandled jump to %06x", pc);
\r
1499 return (int)Pico_mcd->bios;
\r
1503 static u32 PicoCheckPcM68k(u32 pc)
\r
1505 pc-=PicoCpuCM68k.membase; // Get real pc
\r
1508 PicoCpuCM68k.membase=PicoMemBaseM68k(pc);
\r
1510 return PicoCpuCM68k.membase+pc;
\r
1514 static __inline int PicoMemBaseS68k(u32 pc)
\r
1516 if (pc < 0x80000) // PRG RAM
\r
1517 return (int)Pico_mcd->prg_ram;
\r
1519 if ((pc&0xfc0000)==0x080000) // WORD RAM 2M area (assume we are in the right mode..)
\r
1520 return (int)Pico_mcd->word_ram2M - 0x080000;
\r
1522 if ((pc&0xfe0000)==0x0c0000) { // word RAM 1M area
\r
1523 int bank = (Pico_mcd->s68k_regs[3]&1)^1;
\r
1524 return (int)Pico_mcd->word_ram1M[bank] - 0x0c0000;
\r
1527 // Error - Program Counter is invalid
\r
1528 dprintf("s68k FIXME: unhandled jump to %06x", pc);
\r
1530 return (int)Pico_mcd->prg_ram;
\r
1534 static u32 PicoCheckPcS68k(u32 pc)
\r
1536 pc-=PicoCpuCS68k.membase; // Get real pc
\r
1539 PicoCpuCS68k.membase=PicoMemBaseS68k(pc);
\r
1541 return PicoCpuCS68k.membase+pc;
\r
1545 #ifndef _ASM_CD_MEMORY_C
\r
1546 void PicoMemResetCD(int r3)
\r
1549 // update fetchmap..
\r
1553 for (i = M68K_FETCHBANK1*2/16; (i<<(24-FAMEC_FETCHBITS)) < 0x240000; i++)
\r
1554 PicoCpuFM68k.Fetch[i] = (unsigned int)Pico_mcd->word_ram2M - 0x200000;
\r
1558 for (i = M68K_FETCHBANK1*2/16; (i<<(24-FAMEC_FETCHBITS)) < 0x220000; i++)
\r
1559 PicoCpuFM68k.Fetch[i] = (unsigned int)Pico_mcd->word_ram1M[r3 & 1] - 0x200000;
\r
1560 for (i = M68K_FETCHBANK1*0x0c/0x100; (i<<(24-FAMEC_FETCHBITS)) < 0x0e0000; i++)
\r
1561 PicoCpuFS68k.Fetch[i] = (unsigned int)Pico_mcd->word_ram1M[(r3&1)^1] - 0x0c0000;
\r
1567 PICO_INTERNAL void PicoMemSetupCD(void)
\r
1569 dprintf("PicoMemSetupCD()");
\r
1571 // Setup m68k memory callbacks:
\r
1572 PicoCpuCM68k.checkpc=PicoCheckPcM68k;
\r
1573 PicoCpuCM68k.fetch8 =PicoCpuCM68k.read8 =PicoReadM68k8;
\r
1574 PicoCpuCM68k.fetch16=PicoCpuCM68k.read16=PicoReadM68k16;
\r
1575 PicoCpuCM68k.fetch32=PicoCpuCM68k.read32=PicoReadM68k32;
\r
1576 PicoCpuCM68k.write8 =PicoWriteM68k8;
\r
1577 PicoCpuCM68k.write16=PicoWriteM68k16;
\r
1578 PicoCpuCM68k.write32=PicoWriteM68k32;
\r
1580 PicoCpuCS68k.checkpc=PicoCheckPcS68k;
\r
1581 PicoCpuCS68k.fetch8 =PicoCpuCS68k.read8 =PicoReadS68k8;
\r
1582 PicoCpuCS68k.fetch16=PicoCpuCS68k.read16=PicoReadS68k16;
\r
1583 PicoCpuCS68k.fetch32=PicoCpuCS68k.read32=PicoReadS68k32;
\r
1584 PicoCpuCS68k.write8 =PicoWriteS68k8;
\r
1585 PicoCpuCS68k.write16=PicoWriteS68k16;
\r
1586 PicoCpuCS68k.write32=PicoWriteS68k32;
\r
1590 PicoCpuFM68k.read_byte =PicoReadM68k8;
\r
1591 PicoCpuFM68k.read_word =PicoReadM68k16;
\r
1592 PicoCpuFM68k.read_long =PicoReadM68k32;
\r
1593 PicoCpuFM68k.write_byte=PicoWriteM68k8;
\r
1594 PicoCpuFM68k.write_word=PicoWriteM68k16;
\r
1595 PicoCpuFM68k.write_long=PicoWriteM68k32;
\r
1597 PicoCpuFS68k.read_byte =PicoReadS68k8;
\r
1598 PicoCpuFS68k.read_word =PicoReadS68k16;
\r
1599 PicoCpuFS68k.read_long =PicoReadS68k32;
\r
1600 PicoCpuFS68k.write_byte=PicoWriteS68k8;
\r
1601 PicoCpuFS68k.write_word=PicoWriteS68k16;
\r
1602 PicoCpuFS68k.write_long=PicoWriteS68k32;
\r
1604 // setup FAME fetchmap
\r
1608 // by default, point everything to fitst 64k of ROM (BIOS)
\r
1609 for (i = 0; i < M68K_FETCHBANK1; i++)
\r
1610 PicoCpuFM68k.Fetch[i] = (unsigned int)Pico.rom - (i<<(24-FAMEC_FETCHBITS));
\r
1611 // now real ROM (BIOS)
\r
1612 for (i = 0; i < M68K_FETCHBANK1 && (i<<(24-FAMEC_FETCHBITS)) < Pico.romsize; i++)
\r
1613 PicoCpuFM68k.Fetch[i] = (unsigned int)Pico.rom;
\r
1615 for (i = M68K_FETCHBANK1*14/16; i < M68K_FETCHBANK1; i++)
\r
1616 PicoCpuFM68k.Fetch[i] = (unsigned int)Pico.ram - (i<<(24-FAMEC_FETCHBITS));
\r
1618 // PRG RAM is default
\r
1619 for (i = 0; i < M68K_FETCHBANK1; i++)
\r
1620 PicoCpuFS68k.Fetch[i] = (unsigned int)Pico_mcd->prg_ram - (i<<(24-FAMEC_FETCHBITS));
\r
1622 for (i = 0; i < M68K_FETCHBANK1 && (i<<(24-FAMEC_FETCHBITS)) < 0x80000; i++)
\r
1623 PicoCpuFS68k.Fetch[i] = (unsigned int)Pico_mcd->prg_ram;
\r
1624 // WORD RAM 2M area
\r
1625 for (i = M68K_FETCHBANK1*0x08/0x100; i < M68K_FETCHBANK1 && (i<<(24-FAMEC_FETCHBITS)) < 0xc0000; i++)
\r
1626 PicoCpuFS68k.Fetch[i] = (unsigned int)Pico_mcd->word_ram2M - 0x80000;
\r
1627 // PicoMemResetCD() will setup word ram for both
\r
1631 // m68k_poll_addr = m68k_poll_cnt = 0;
\r
1632 s68k_poll_adclk = s68k_poll_cnt = 0;
\r
1637 unsigned char PicoReadCD8w (unsigned int a) {
\r
1638 return m68ki_cpu_p == &PicoCpuMS68k ? PicoReadS68k8(a) : PicoReadM68k8(a);
\r
1640 unsigned short PicoReadCD16w(unsigned int a) {
\r
1641 return m68ki_cpu_p == &PicoCpuMS68k ? PicoReadS68k16(a) : PicoReadM68k16(a);
\r
1643 unsigned int PicoReadCD32w(unsigned int a) {
\r
1644 return m68ki_cpu_p == &PicoCpuMS68k ? PicoReadS68k32(a) : PicoReadM68k32(a);
\r
1646 void PicoWriteCD8w (unsigned int a, unsigned char d) {
\r
1647 if (m68ki_cpu_p == &PicoCpuMS68k) PicoWriteS68k8(a, d); else PicoWriteM68k8(a, d);
\r
1649 void PicoWriteCD16w(unsigned int a, unsigned short d) {
\r
1650 if (m68ki_cpu_p == &PicoCpuMS68k) PicoWriteS68k16(a, d); else PicoWriteM68k16(a, d);
\r
1652 void PicoWriteCD32w(unsigned int a, unsigned int d) {
\r
1653 if (m68ki_cpu_p == &PicoCpuMS68k) PicoWriteS68k32(a, d); else PicoWriteM68k32(a, d);
\r
1656 // these are allowed to access RAM
\r
1657 unsigned int m68k_read_pcrelative_CD8 (unsigned int a)
\r
1660 if(m68ki_cpu_p == &PicoCpuMS68k) {
\r
1661 if (a < 0x80000) return *(u8 *)(Pico_mcd->prg_ram+(a^1)); // PRG Ram
\r
1662 if ((a&0xfc0000)==0x080000 && !(Pico_mcd->s68k_regs[3]&4)) // word RAM (2M area: 080000-0bffff)
\r
1663 return *(u8 *)(Pico_mcd->word_ram2M+((a^1)&0x3ffff));
\r
1664 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // word RAM (1M area: 0c0000-0dffff)
\r
1665 int bank = (Pico_mcd->s68k_regs[3]&1)^1;
\r
1666 return *(u8 *)(Pico_mcd->word_ram1M[bank]+((a^1)&0x1ffff));
\r
1668 dprintf("s68k_read_pcrelative_CD8 FIXME: can't handle %06x", a);
\r
1670 if((a&0xe00000)==0xe00000) return *(u8 *)(Pico.ram+((a^1)&0xffff)); // Ram
\r
1671 if(a<0x20000) return *(u8 *)(Pico.rom+(a^1)); // Bios
\r
1672 if((a&0xfc0000)==0x200000) { // word RAM
\r
1673 if(!(Pico_mcd->s68k_regs[3]&4)) // 2M?
\r
1674 return *(u8 *)(Pico_mcd->word_ram2M+((a^1)&0x3ffff));
\r
1675 else if (a < 0x220000) {
\r
1676 int bank = Pico_mcd->s68k_regs[3]&1;
\r
1677 return *(u8 *)(Pico_mcd->word_ram1M[bank]+((a^1)&0x1ffff));
\r
1680 dprintf("m68k_read_pcrelative_CD8 FIXME: can't handle %06x", a);
\r
1682 return 0;//(u8) lastread_d;
\r
1684 unsigned int m68k_read_pcrelative_CD16(unsigned int a)
\r
1687 if(m68ki_cpu_p == &PicoCpuMS68k) {
\r
1688 if (a < 0x80000) return *(u16 *)(Pico_mcd->prg_ram+(a&~1)); // PRG Ram
\r
1689 if ((a&0xfc0000)==0x080000 && !(Pico_mcd->s68k_regs[3]&4)) // word RAM (2M area: 080000-0bffff)
\r
1690 return *(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe));
\r
1691 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // word RAM (1M area: 0c0000-0dffff)
\r
1692 int bank = (Pico_mcd->s68k_regs[3]&1)^1;
\r
1693 return *(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe));
\r
1695 dprintf("s68k_read_pcrelative_CD16 FIXME: can't handle %06x", a);
\r
1697 if((a&0xe00000)==0xe00000) return *(u16 *)(Pico.ram+(a&0xfffe)); // Ram
\r
1698 if(a<0x20000) return *(u16 *)(Pico.rom+(a&~1)); // Bios
\r
1699 if((a&0xfc0000)==0x200000) { // word RAM
\r
1700 if(!(Pico_mcd->s68k_regs[3]&4)) // 2M?
\r
1701 return *(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe));
\r
1702 else if (a < 0x220000) {
\r
1703 int bank = Pico_mcd->s68k_regs[3]&1;
\r
1704 return *(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe));
\r
1707 dprintf("m68k_read_pcrelative_CD16 FIXME: can't handle %06x", a);
\r
1711 unsigned int m68k_read_pcrelative_CD32(unsigned int a)
\r
1715 if(m68ki_cpu_p == &PicoCpuMS68k) {
\r
1716 if (a < 0x80000) { u16 *pm=(u16 *)(Pico_mcd->prg_ram+(a&~1)); return (pm[0]<<16)|pm[1]; } // PRG Ram
\r
1717 if ((a&0xfc0000)==0x080000 && !(Pico_mcd->s68k_regs[3]&4)) // word RAM (2M area: 080000-0bffff)
\r
1718 { pm=(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe)); return (pm[0]<<16)|pm[1]; }
\r
1719 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // word RAM (1M area: 0c0000-0dffff)
\r
1720 int bank = (Pico_mcd->s68k_regs[3]&1)^1;
\r
1721 pm=(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe));
\r
1722 return (pm[0]<<16)|pm[1];
\r
1724 dprintf("s68k_read_pcrelative_CD32 FIXME: can't handle %06x", a);
\r
1726 if((a&0xe00000)==0xe00000) { u16 *pm=(u16 *)(Pico.ram+(a&0xfffe)); return (pm[0]<<16)|pm[1]; } // Ram
\r
1727 if(a<0x20000) { u16 *pm=(u16 *)(Pico.rom+(a&~1)); return (pm[0]<<16)|pm[1]; }
\r
1728 if((a&0xfc0000)==0x200000) { // word RAM
\r
1729 if(!(Pico_mcd->s68k_regs[3]&4)) // 2M?
\r
1730 { pm=(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe)); return (pm[0]<<16)|pm[1]; }
\r
1731 else if (a < 0x220000) {
\r
1732 int bank = Pico_mcd->s68k_regs[3]&1;
\r
1733 pm=(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe));
\r
1734 return (pm[0]<<16)|pm[1];
\r
1737 dprintf("m68k_read_pcrelative_CD32 FIXME: can't handle %06x", a);
\r
1741 #endif // EMU_M68K
\r