1 // This is part of Pico Library
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3 // (c) Copyright 2004 Dave, All rights reserved.
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4 // (c) Copyright 2007 notaz, All rights reserved.
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5 // Free for non-commercial use.
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7 // For commercial use, separate licencing terms must be obtained.
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9 // A68K no longer supported here
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11 //#define __debug_io
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13 #include "../PicoInt.h"
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15 #include "../sound/sound.h"
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16 #include "../sound/ym2612.h"
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17 #include "../sound/sn76496.h"
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22 typedef unsigned char u8;
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23 typedef unsigned short u16;
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24 typedef unsigned int u32;
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26 //#define __debug_io
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27 //#define __debug_io2
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28 //#define rdprintf dprintf
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29 #define rdprintf(...)
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31 // -----------------------------------------------------------------
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34 static u32 m68k_reg_read16(u32 a)
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38 // dprintf("m68k_regs r%2i: [%02x] @%06x", realsize&~1, a+(realsize&1), SekPc);
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42 d = ((Pico_mcd->s68k_regs[0x33]<<13)&0x8000) | Pico_mcd->m.busreq; // here IFL2 is always 0, just like in Gens
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45 d = (Pico_mcd->s68k_regs[a]<<8) | (Pico_mcd->s68k_regs[a+1]&0xc7);
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46 dprintf("m68k_regs r3: %02x @%06x", (u8)d, SekPc);
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49 d = Pico_mcd->s68k_regs[4]<<8;
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52 d = Pico_mcd->m.hint_vector;
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55 d = Read_CDC_Host(0);
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58 dprintf("m68k reserved read");
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61 dprintf("m68k stopwatch timer read");
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66 // comm flag/cmd/status (0xE-0x2F)
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67 d = (Pico_mcd->s68k_regs[a]<<8) | Pico_mcd->s68k_regs[a+1];
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71 dprintf("m68k_regs invalid read @ %02x", a);
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75 // dprintf("ret = %04x", d);
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79 static void m68k_reg_write8(u32 a, u32 d)
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82 // dprintf("m68k_regs w%2i: [%02x] %02x @%06x", realsize, a, d, SekPc);
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87 if ((d&1) && (Pico_mcd->s68k_regs[0x33]&(1<<2))) { dprintf("m68k: s68k irq 2"); SekInterruptS68k(2); }
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91 if (!(d&1)) Pico_mcd->m.state_flags |= 1; // reset pending, needed to be sure we fetch the right vectors on reset
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92 if ( (Pico_mcd->m.busreq&1) != (d&1)) dprintf("m68k: s68k reset %i", !(d&1));
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93 if ( (Pico_mcd->m.busreq&2) != (d&2)) dprintf("m68k: s68k brq %i", (d&2)>>1);
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94 if ((Pico_mcd->m.state_flags&1) && (d&3)==1) {
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95 SekResetS68k(); // S68k comes out of RESET or BRQ state
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96 Pico_mcd->m.state_flags&=~1;
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97 dprintf("m68k: resetting s68k, cycles=%i", SekCyclesLeft);
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99 Pico_mcd->m.busreq = d;
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102 Pico_mcd->s68k_regs[2] = d; // really use s68k side register
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105 dprintf("m68k_regs w3: %02x @%06x", (u8)d, SekPc);
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107 if ((Pico_mcd->s68k_regs[3]>>6) != ((d>>6)&3))
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108 dprintf("m68k: prg bank: %i -> %i", (Pico_mcd->s68k_regs[a]>>6), ((d>>6)&3));
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109 //if ((Pico_mcd->s68k_regs[3]&4) != (d&4)) dprintf("m68k: ram mode %i mbit", (d&4) ? 1 : 2);
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110 //if ((Pico_mcd->s68k_regs[3]&2) != (d&2)) dprintf("m68k: %s", (d&4) ? ((d&2) ? "word swap req" : "noop?") :
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111 // ((d&2) ? "word ram to s68k" : "word ram to m68k"));
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112 d |= Pico_mcd->s68k_regs[3]&0x1d;
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113 if (!(d & 4) && (d & 2)) d &= ~1; // return word RAM to s68k in 2M mode
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114 Pico_mcd->s68k_regs[3] = d; // really use s68k side register
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117 *((char *)&Pico_mcd->m.hint_vector+1) = d;
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118 Pico_mcd->bios[0x72 + 1] = d; // simple hint vector changer
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121 *(char *)&Pico_mcd->m.hint_vector = d;
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122 Pico_mcd->bios[0x72] = d;
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125 //dprintf("m68k: comm flag: %02x", d);
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127 //dprintf("s68k @ %06x", SekPcS68k);
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129 Pico_mcd->s68k_regs[0xe] = d;
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133 if ((a&0xf0) == 0x10) {
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134 Pico_mcd->s68k_regs[a] = d;
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138 dprintf("m68k: invalid write? [%02x] %02x", a, d);
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143 static u32 s68k_reg_read16(u32 a)
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147 // dprintf("s68k_regs r%2i: [%02x] @ %06x", realsize&~1, a+(realsize&1), SekPcS68k);
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151 d = ((Pico_mcd->s68k_regs[0]&3)<<8) | 1; // ver = 0, not in reset state
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154 d = (Pico_mcd->s68k_regs[a]<<8) | (Pico_mcd->s68k_regs[a+1]&0x1f);
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155 dprintf("s68k_regs r3: %02x @%06x", (u8)d, SekPc);
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158 d = CDC_Read_Reg();
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161 d = Read_CDC_Host(1); // Gens returns 0 here on byte reads
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164 dprintf("s68k stopwatch timer read");
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165 d = Pico_mcd->m.timer_stopwatch >> 16;
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168 dprintf("s68k int3 timer read");
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170 case 0x34: // fader
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171 d = 0; // no busy bit
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175 d = (Pico_mcd->s68k_regs[a]<<8) | Pico_mcd->s68k_regs[a+1];
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179 // dprintf("ret = %04x", d);
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184 static void s68k_reg_write8(u32 a, u32 d)
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186 //dprintf("s68k_regs w%2i: [%02x] %02x @ %06x", realsize, a, d, SekPcS68k);
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188 // TODO: review against Gens
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191 return; // only m68k can change WP
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193 dprintf("s68k_regs w3: %02x @%06x", (u8)d, SekPc);
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196 d |= Pico_mcd->s68k_regs[3]&0xc2;
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197 if ((d ^ Pico_mcd->s68k_regs[3]) & 5) d &= ~2; // in case of mode or bank change we clear DMNA (m68k req) bit
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199 d |= Pico_mcd->s68k_regs[3]&0xc3;
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200 if (d&1) d &= ~2; // return word RAM to m68k in 2M mode
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204 dprintf("s68k CDC dest: %x", d&7);
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205 Pico_mcd->s68k_regs[4] = (Pico_mcd->s68k_regs[4]&0xC0) | (d&7); // CDC mode
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208 //dprintf("s68k CDC reg addr: %x", d&0xf);
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214 dprintf("s68k set CDC dma addr");
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218 dprintf("s68k set stopwatch timer");
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219 Pico_mcd->m.timer_stopwatch = 0;
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222 dprintf("s68k set int3 timer: %02x", d);
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223 Pico_mcd->m.timer_int3 = d << 16;
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225 case 0x33: // IRQ mask
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226 dprintf("s68k irq mask: %02x", d);
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227 if ((d&(1<<4)) && (Pico_mcd->s68k_regs[0x37]&4) && !(Pico_mcd->s68k_regs[0x33]&(1<<4))) {
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228 CDD_Export_Status();
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231 case 0x34: // fader
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232 Pico_mcd->s68k_regs[a] = (u8) d & 0x7f;
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235 return; // d/m bit is unsetable
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237 u32 d_old = Pico_mcd->s68k_regs[0x37];
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238 Pico_mcd->s68k_regs[0x37] = d&7;
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239 if ((d&4) && !(d_old&4)) {
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240 CDD_Export_Status();
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245 Pico_mcd->s68k_regs[a] = (u8) d;
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246 CDD_Import_Command();
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250 if ((a&0x1f0) == 0x10 || a == 0x0e || (a >= 0x38 && a < 0x42))
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252 dprintf("m68k: invalid write @ %02x?", a);
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256 Pico_mcd->s68k_regs[a] = (u8) d;
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263 static int PadRead(int i)
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265 int pad=0,value=0,TH;
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266 pad=~PicoPad[i]; // Get inverse of pad MXYZ SACB RLDU
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267 TH=Pico.ioports[i+1]&0x40;
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269 if(PicoOpt & 0x20) { // 6 button gamepad enabled
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270 int phase = Pico.m.padTHPhase[i];
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272 if(phase == 2 && !TH) {
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273 value=(pad&0xc0)>>2; // ?0SA 0000
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275 } else if(phase == 3 && TH) {
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276 value=(pad&0x30)|((pad>>8)&0xf); // ?1CB MXYZ
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278 } else if(phase == 3 && !TH) {
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279 value=((pad&0xc0)>>2)|0x0f; // ?0SA 1111
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284 if(TH) value=(pad&0x3f); // ?1CB RLDU
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285 else value=((pad&0xc0)>>2)|(pad&3); // ?0SA 00DU
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289 // orr the bits, which are set as output
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290 value |= Pico.ioports[i+1]&Pico.ioports[i+4];
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292 return value; // will mirror later
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295 static u8 z80Read8(u32 a)
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297 if(Pico.m.z80Run&1) return 0;
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302 // Z80 disabled, do some faking
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303 static u8 zerosent = 0;
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304 if(a == Pico.m.z80_lastaddr) { // probably polling something
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305 u8 d = Pico.m.z80_fakeval;
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306 if((d & 0xf) == 0xf && !zerosent) {
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307 d = 0; zerosent = 1;
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309 Pico.m.z80_fakeval++;
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314 Pico.m.z80_fakeval = 0;
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318 Pico.m.z80_lastaddr = (u16) a;
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319 return Pico.zram[a];
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323 // for nonstandard reads
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324 static u32 UnusualRead16(u32 a, int realsize)
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328 dprintf("unusual r%i: %06x @%06x", realsize&~1, (a&0xfffffe)+(realsize&1), SekPc);
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331 dprintf("ret = %04x", d);
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335 static u32 OtherRead16(u32 a, int realsize)
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339 if ((a&0xff0000)==0xa00000) {
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340 if ((a&0x4000)==0x0000) { d=z80Read8(a); d|=d<<8; goto end; } // Z80 ram (not byteswaped)
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341 if ((a&0x6000)==0x4000) { if(PicoOpt&1) d=YM2612Read(); else d=Pico.m.rotate++&3; goto end; } // 0x4000-0x5fff, Fudge if disabled
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342 d=0xffff; goto end;
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344 if ((a&0xffffe0)==0xa10000) { // I/O ports
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347 case 0: d=Pico.m.hardware; break; // Hardware value (Version register)
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348 case 1: d=PadRead(0); d|=Pico.ioports[1]&0x80; break;
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349 case 2: d=PadRead(1); d|=Pico.ioports[2]&0x80; break;
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350 default: d=Pico.ioports[a]; break; // IO ports can be used as RAM
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355 // |=0x80 for Shadow of the Beast & Super Offroad; rotate fakes next fetched instruction for Time Killers
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356 if (a==0xa11100) { d=((Pico.m.z80Run&1)<<8)|0x8000|Pico.m.rotate++; goto end; }
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358 if ((a&0xe700e0)==0xc00000) { d=PicoVideoRead(a); goto end; }
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360 if ((a&0xffffc0)==0xa12000) {
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361 d=m68k_reg_read16(a);
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365 d = UnusualRead16(a, realsize);
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371 //extern UINT32 mz80GetRegisterValue(void *, UINT32);
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373 static void OtherWrite8(u32 a,u32 d,int realsize)
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375 if ((a&0xe700f9)==0xc00011||(a&0xff7ff9)==0xa07f11) { if(PicoOpt&2) SN76496Write(d); return; } // PSG Sound
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376 if ((a&0xff4000)==0xa00000) { if(!(Pico.m.z80Run&1)) Pico.zram[a&0x1fff]=(u8)d; return; } // Z80 ram
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377 if ((a&0xff6000)==0xa04000) { if(PicoOpt&1) emustatus|=YM2612Write(a&3, d); return; } // FM Sound
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378 if ((a&0xffffe0)==0xa10000) { // I/O ports
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380 // 6 button gamepad: if TH went from 0 to 1, gamepad changes state
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383 Pico.m.padDelay[0] = 0;
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384 if(!(Pico.ioports[1]&0x40) && (d&0x40)) Pico.m.padTHPhase[0]++;
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387 Pico.m.padDelay[1] = 0;
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388 if(!(Pico.ioports[2]&0x40) && (d&0x40)) Pico.m.padTHPhase[1]++;
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391 Pico.ioports[a]=(u8)d; // IO ports can be used as RAM
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395 extern int z80startCycle, z80stopCycle;
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396 //int lineCycles=(488-SekCyclesLeft)&0x1ff;
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399 // hack: detect a nasty situation where Z80 was enabled and disabled in the same 68k timeslice (Golden Axe III)
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400 if((PicoOpt&4) && Pico.m.z80Run==1) z80_run(20);
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401 z80stopCycle = SekCyclesDone();
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402 //z80ExtraCycles += (lineCycles>>1)-(lineCycles>>5); // only meaningful in PicoFrameHints()
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404 z80startCycle = SekCyclesDone();
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405 //if(Pico.m.scanline != -1)
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406 //z80ExtraCycles -= (lineCycles>>1)-(lineCycles>>5)+16;
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408 //dprintf("set_zrun: %i [%i|%i] zPC=%04x @%06x", d, Pico.m.scanline, SekCyclesDone(), mz80GetRegisterValue(NULL, 0), SekPc);
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409 Pico.m.z80Run=(u8)d; return;
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411 if (a==0xa11200) { if(!(d&1)) z80_reset(); return; }
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413 if ((a&0xff7f00)==0xa06000) // Z80 BANK register
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415 Pico.m.z80_bank68k>>=1;
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416 Pico.m.z80_bank68k|=(d&1)<<8;
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417 Pico.m.z80_bank68k&=0x1ff; // 9 bits and filled in the new top one
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421 if ((a&0xe700e0)==0xc00000) { PicoVideoWrite(a,(u16)(d|(d<<8))); return; } // Byte access gets mirrored
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423 if ((a&0xffffc0)==0xa12000) { m68k_reg_write8(a, d); return; }
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425 dprintf("strange w%i: %06x, %08x @%06x", realsize, a&0xffffff, d, SekPc);
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428 static void OtherWrite16(u32 a,u32 d)
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430 if ((a&0xe700e0)==0xc00000) { PicoVideoWrite(a,(u16)d); return; }
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431 if ((a&0xff4000)==0xa00000) { if(!(Pico.m.z80Run&1)) Pico.zram[a&0x1fff]=(u8)(d>>8); return; } // Z80 ram (MSB only)
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433 if ((a&0xffffe0)==0xa10000) { // I/O ports
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435 // 6 button gamepad: if TH went from 0 to 1, gamepad changes state
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438 Pico.m.padDelay[0] = 0;
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439 if(!(Pico.ioports[1]&0x40) && (d&0x40)) Pico.m.padTHPhase[0]++;
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442 Pico.m.padDelay[1] = 0;
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443 if(!(Pico.ioports[2]&0x40) && (d&0x40)) Pico.m.padTHPhase[1]++;
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446 Pico.ioports[a]=(u8)d; // IO ports can be used as RAM
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449 if (a==0xa11100) { OtherWrite8(a, d>>8, 16); return; }
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450 if (a==0xa11200) { if(!(d&0x100)) z80_reset(); return; }
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452 OtherWrite8(a, d>>8, 16);
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453 OtherWrite8(a+1,d&0xff, 16);
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456 // -----------------------------------------------------------------
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457 // Read Rom and read Ram
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459 u8 PicoReadM68k8(u32 a)
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463 if ((a&0xe00000)==0xe00000) { d = *(u8 *)(Pico.ram+((a^1)&0xffff)); goto end; } // Ram
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467 if (a < 0x20000) { d = *(u8 *)(Pico_mcd->bios+(a^1)); goto end; } // bios
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470 if ((a&0xfe0000)==0x020000) {
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471 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
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472 d = *(prg_bank+((a^1)&0x1ffff));
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477 if (a == 0x200000 && SekPc == 0xff0b66 && Pico.m.frame_count > 1000)
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481 unsigned short *ram = (unsigned short *) Pico.ram;
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482 // unswap and dump RAM
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483 for (i = 0; i < 0x10000/2; i++)
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484 ram[i] = (ram[i]>>8) | (ram[i]<<8);
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485 ff = fopen("ram.bin", "wb");
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486 fwrite(ram, 1, 0x10000, ff);
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493 if ((a&0xfc0000)==0x200000) {
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494 dprintf("m68k_wram r8: [%06x] @%06x", a, SekPc);
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495 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
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496 if (a >= 0x220000) {
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499 a=((a&0x1fffe)<<1)|(a&1);
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500 if (Pico_mcd->s68k_regs[3]&1) a+=2;
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501 d = Pico_mcd->word_ram[a^1];
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504 // allow access in any mode, like Gens does
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505 d = Pico_mcd->word_ram[(a^1)&0x3ffff];
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507 dprintf("ret = %02x", (u8)d);
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511 if ((a&0xff4000)==0xa00000) { d=z80Read8(a); goto end; } // Z80 Ram
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513 if ((a&0xffffc0)==0xa12000)
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514 rdprintf("m68k_regs r8: [%02x] @%06x", a&0x3f, SekPc);
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516 d=OtherRead16(a&~1, 8|(a&1)); if ((a&1)==0) d>>=8;
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518 if ((a&0xffffc0)==0xa12000)
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519 rdprintf("ret = %02x", (u8)d);
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524 dprintf("r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPc);
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530 u16 PicoReadM68k16(u32 a)
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534 if ((a&0xe00000)==0xe00000) { d=*(u16 *)(Pico.ram+(a&0xfffe)); goto end; } // Ram
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538 if (a < 0x20000) { d = *(u16 *)(Pico_mcd->bios+a); goto end; } // bios
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541 if ((a&0xfe0000)==0x020000) {
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542 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
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543 d = *(u16 *)(prg_bank+(a&0x1fffe));
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548 if ((a&0xfc0000)==0x200000) {
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549 dprintf("m68k_wram r16: [%06x] @%06x", a, SekPc);
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550 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
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551 if (a >= 0x220000) {
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554 a=((a&0x1fffe)<<1);
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555 if (Pico_mcd->s68k_regs[3]&1) a+=2;
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556 d = *(u16 *)(Pico_mcd->word_ram+a);
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559 // allow access in any mode, like Gens does
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560 d = *(u16 *)(Pico_mcd->word_ram+(a&0x3fffe));
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562 dprintf("ret = %04x", d);
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566 if ((a&0xffffc0)==0xa12000)
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567 rdprintf("m68k_regs r16: [%02x] @%06x", a&0x3f, SekPc);
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569 d = (u16)OtherRead16(a, 16);
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571 if ((a&0xffffc0)==0xa12000)
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572 rdprintf("ret = %04x", d);
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577 dprintf("r16: %06x, %04x @%06x", a&0xffffff, d, SekPc);
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583 u32 PicoReadM68k32(u32 a)
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587 if ((a&0xe00000)==0xe00000) { u16 *pm=(u16 *)(Pico.ram+(a&0xfffe)); d = (pm[0]<<16)|pm[1]; goto end; } // Ram
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591 if (a < 0x20000) { u16 *pm=(u16 *)(Pico_mcd->bios+a); d = (pm[0]<<16)|pm[1]; goto end; } // bios
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594 if ((a&0xfe0000)==0x020000) {
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595 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
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596 u16 *pm=(u16 *)(prg_bank+(a&0x1fffe));
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597 d = (pm[0]<<16)|pm[1];
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602 if ((a&0xfc0000)==0x200000) {
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603 dprintf("m68k_wram r32: [%06x] @%06x", a, SekPc);
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604 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
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605 if (a >= 0x220000) {
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608 a=((a&0x1fffe)<<1);
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609 if (Pico_mcd->s68k_regs[3]&1) a+=2;
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610 d = *(u16 *)(Pico_mcd->word_ram+a) << 16;
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611 d |= *(u16 *)(Pico_mcd->word_ram+a+4);
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614 // allow access in any mode, like Gens does
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615 u16 *pm=(u16 *)(Pico_mcd->word_ram+(a&0x3fffe)); d = (pm[0]<<16)|pm[1];
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617 dprintf("ret = %08x", d);
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621 if ((a&0xffffc0)==0xa12000)
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622 rdprintf("m68k_regs r32: [%02x] @%06x", a&0x3f, SekPc);
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624 d = (OtherRead16(a, 32)<<16)|OtherRead16(a+2, 32);
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626 if ((a&0xffffc0)==0xa12000)
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627 rdprintf("ret = %08x", d);
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631 dprintf("r32: %06x, %08x @%06x", a&0xffffff, d, SekPc);
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637 // -----------------------------------------------------------------
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640 void PicoWriteM68k8(u32 a,u8 d)
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643 dprintf("w8 : %06x, %02x @%06x", a&0xffffff, d, SekPc);
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645 //if ((a&0xe0ffff)==0xe0a9ba+0x69c)
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646 // dprintf("w8 : %06x, %02x @%06x", a&0xffffff, d, SekPc);
\r
649 if ((a&0xe00000)==0xe00000) { // Ram
\r
650 *(u8 *)(Pico.ram+((a^1)&0xffff)) = d;
\r
657 if ((a&0xfe0000)==0x020000) {
\r
658 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
\r
659 *(u8 *)(prg_bank+((a^1)&0x1ffff))=d;
\r
664 if ((a&0xfc0000)==0x200000) {
\r
665 dprintf("m68k_wram w8: [%06x] %02x @%06x", a, d, SekPc);
\r
666 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
667 if (a >= 0x220000) {
\r
670 a=((a&0x1fffe)<<1)|(a&1);
\r
671 if (Pico_mcd->s68k_regs[3]&1) a+=2;
\r
672 *(u8 *)(Pico_mcd->word_ram+(a^1))=d;
\r
675 // allow access in any mode, like Gens does
\r
676 *(u8 *)(Pico_mcd->word_ram+((a^1)&0x3ffff))=d;
\r
681 if ((a&0xffffc0)==0xa12000)
\r
682 rdprintf("m68k_regs w8: [%02x] %02x @%06x", a&0x3f, d, SekPc);
\r
684 OtherWrite8(a,d,8);
\r
688 void PicoWriteM68k16(u32 a,u16 d)
\r
691 dprintf("w16: %06x, %04x", a&0xffffff, d);
\r
693 // dprintf("w16: %06x, %04x @%06x", a&0xffffff, d, SekPc);
\r
695 if ((a&0xe00000)==0xe00000) { // Ram
\r
696 *(u16 *)(Pico.ram+(a&0xfffe))=d;
\r
703 if ((a&0xfe0000)==0x020000) {
\r
704 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
\r
705 *(u16 *)(prg_bank+(a&0x1fffe))=d;
\r
710 if ((a&0xfc0000)==0x200000) {
\r
711 dprintf("m68k_wram w16: [%06x] %04x @%06x", a, d, SekPc);
\r
712 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
713 if (a >= 0x220000) {
\r
716 a=((a&0x1fffe)<<1);
\r
717 if (Pico_mcd->s68k_regs[3]&1) a+=2;
\r
718 *(u16 *)(Pico_mcd->word_ram+a)=d;
\r
721 // allow access in any mode, like Gens does
\r
722 *(u16 *)(Pico_mcd->word_ram+(a&0x3fffe))=d;
\r
727 if ((a&0xffffc0)==0xa12000)
\r
728 rdprintf("m68k_regs w16: [%02x] %04x @%06x", a&0x3f, d, SekPc);
\r
734 void PicoWriteM68k32(u32 a,u32 d)
\r
737 dprintf("w32: %06x, %08x", a&0xffffff, d);
\r
740 if ((a&0xe00000)==0xe00000)
\r
743 u16 *pm=(u16 *)(Pico.ram+(a&0xfffe));
\r
744 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
751 if ((a&0xfe0000)==0x020000) {
\r
752 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
\r
753 u16 *pm=(u16 *)(prg_bank+(a&0x1fffe));
\r
754 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
759 if ((a&0xfc0000)==0x200000) {
\r
760 if (d != 0) // don't log clears
\r
761 dprintf("m68k_wram w32: [%06x] %08x @%06x", a, d, SekPc);
\r
762 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
763 if (a >= 0x220000) {
\r
766 a=((a&0x1fffe)<<1);
\r
767 if (Pico_mcd->s68k_regs[3]&1) a+=2;
\r
768 *(u16 *)(Pico_mcd->word_ram+a) = d>>16;
\r
769 *(u16 *)(Pico_mcd->word_ram+a+4) = d;
\r
772 // allow access in any mode, like Gens does
\r
773 u16 *pm=(u16 *)(Pico_mcd->word_ram+(a&0x3fffe));
\r
774 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
779 if ((a&0xffffc0)==0xa12000)
\r
780 rdprintf("m68k_regs w32: [%02x] %08x @%06x", a&0x3f, d, SekPc);
\r
782 OtherWrite16(a, (u16)(d>>16));
\r
783 OtherWrite16(a+2,(u16)d);
\r
787 // -----------------------------------------------------------------
\r
790 u8 PicoReadS68k8(u32 a)
\r
798 d = *(Pico_mcd->prg_ram+(a^1));
\r
803 if ((a&0xfffe00) == 0xff8000) {
\r
805 rdprintf("s68k_regs r8: [%02x] @ %06x", a, SekPcS68k);
\r
806 if (a >= 0x50 && a < 0x68)
\r
807 d = gfx_cd_read(a&~1);
\r
808 else d = s68k_reg_read16(a&~1);
\r
809 if ((a&1)==0) d>>=8;
\r
810 rdprintf("ret = %02x", (u8)d);
\r
814 // word RAM (2M area)
\r
815 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
816 dprintf("s68k_wram2M r8: [%06x] @%06x", a, SekPc);
\r
817 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
819 dprintf("(decode)");
\r
821 // allow access in any mode, like Gens does
\r
822 d = Pico_mcd->word_ram[(a^1)&0x3ffff];
\r
824 dprintf("ret = %02x", (u8)d);
\r
828 // word RAM (1M area)
\r
829 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
830 dprintf("s68k_wram1M r8: [%06x] @%06x", a, SekPc);
\r
831 a=((a&0x1fffe)<<1)|(a&1);
\r
832 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;
\r
833 d = Pico_mcd->word_ram[a^1];
\r
834 dprintf("ret = %02x", (u8)d);
\r
839 if ((a&0xff8000)==0xff0000) {
\r
840 dprintf("s68k_pcm r8: [%06x] @%06x", a, SekPc);
\r
843 d = Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a>>1)&0xfff];
\r
844 else if (a >= 0x20) {
\r
846 d = Pico_mcd->pcm.ch[a>>2].addr >> PCM_STEP_SHIFT;
\r
847 if (a & 2) d >>= 8;
\r
849 dprintf("ret = %02x", (u8)d);
\r
854 if ((a&0xff0000)==0xfe0000) {
\r
855 d = Pico_mcd->bram[(a>>1)&0x1fff];
\r
859 dprintf("s68k r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPcS68k);
\r
864 dprintf("s68k r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPcS68k);
\r
870 u16 PicoReadS68k16(u32 a)
\r
878 d = *(u16 *)(Pico_mcd->prg_ram+a);
\r
883 if ((a&0xfffe00) == 0xff8000) {
\r
885 rdprintf("s68k_regs r16: [%02x] @ %06x", a, SekPcS68k);
\r
886 if (a >= 0x50 && a < 0x68)
\r
887 d = gfx_cd_read(a);
\r
888 else d = s68k_reg_read16(a);
\r
889 rdprintf("ret = %04x", d);
\r
893 // word RAM (2M area)
\r
894 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
895 dprintf("s68k_wram2M r16: [%06x] @%06x", a, SekPc);
\r
896 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
898 dprintf("(decode)");
\r
900 // allow access in any mode, like Gens does
\r
901 d = *(u16 *)(Pico_mcd->word_ram+(a&0x3fffe));
\r
903 dprintf("ret = %04x", d);
\r
907 // word RAM (1M area)
\r
908 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
909 dprintf("s68k_wram1M r16: [%06x] @%06x", a, SekPc);
\r
910 a=((a&0x1fffe)<<1);
\r
911 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;
\r
912 d = *(u16 *)(Pico_mcd->word_ram+a);
\r
913 dprintf("ret = %04x", d);
\r
918 if ((a&0xff0000)==0xfe0000) {
\r
919 dprintf("s68k_bram r16: [%06x] @%06x", a, SekPc);
\r
921 d = Pico_mcd->bram[a++]; // Gens does little endian here, and so do we..
\r
922 d|= Pico_mcd->bram[a++] << 8;
\r
923 dprintf("ret = %04x", d);
\r
928 if ((a&0xff8000)==0xff0000) {
\r
929 dprintf("s68k_pcm r16: [%06x] @%06x", a, SekPc);
\r
932 d = Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a>>1)&0xfff];
\r
933 else if (a >= 0x20) {
\r
935 d = Pico_mcd->pcm.ch[a>>2].addr >> PCM_STEP_SHIFT;
\r
936 if (a & 2) d >>= 8;
\r
938 dprintf("ret = %04x", d);
\r
942 dprintf("s68k r16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);
\r
947 dprintf("s68k r16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);
\r
953 u32 PicoReadS68k32(u32 a)
\r
961 u16 *pm=(u16 *)(Pico_mcd->prg_ram+a);
\r
962 d = (pm[0]<<16)|pm[1];
\r
967 if ((a&0xfffe00) == 0xff8000) {
\r
969 rdprintf("s68k_regs r32: [%02x] @ %06x", a, SekPcS68k);
\r
970 if (a >= 0x50 && a < 0x68)
\r
971 d = (gfx_cd_read(a)<<16)|gfx_cd_read(a+2);
\r
972 else d = (s68k_reg_read16(a)<<16)|s68k_reg_read16(a+2);
\r
973 rdprintf("ret = %08x", d);
\r
977 // word RAM (2M area)
\r
978 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
979 dprintf("s68k_wram2M r32: [%06x] @%06x", a, SekPc);
\r
980 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
982 dprintf("(decode)");
\r
984 // allow access in any mode, like Gens does
\r
985 u16 *pm=(u16 *)(Pico_mcd->word_ram+(a&0x3fffe)); d = (pm[0]<<16)|pm[1];
\r
987 dprintf("ret = %08x", d);
\r
991 // word RAM (1M area)
\r
992 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
993 dprintf("s68k_wram1M r32: [%06x] @%06x", a, SekPc);
\r
994 a=((a&0x1fffe)<<1);
\r
995 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;
\r
996 d = *(u16 *)(Pico_mcd->word_ram+a) << 16;
\r
997 d |= *(u16 *)(Pico_mcd->word_ram+a+4);
\r
998 dprintf("ret = %08x", d);
\r
1003 if ((a&0xff8000)==0xff0000) {
\r
1004 dprintf("s68k_pcm r32: [%06x] @%06x", a, SekPc);
\r
1006 if (a >= 0x2000) {
\r
1008 d = Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][a&0xfff] << 16;
\r
1009 d |= Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a+1)&0xfff];
\r
1010 } else if (a >= 0x20) {
\r
1014 d = (Pico_mcd->pcm.ch[a].addr >> (PCM_STEP_SHIFT-8)) & 0xff0000;
\r
1015 d |= (Pico_mcd->pcm.ch[(a+1)&7].addr >> PCM_STEP_SHIFT) & 0xff;
\r
1017 d = Pico_mcd->pcm.ch[a>>2].addr >> PCM_STEP_SHIFT;
\r
1018 d = ((d<<16)&0xff0000) | ((d>>8)&0xff); // PCM chip is LE
\r
1021 dprintf("ret = %08x", d);
\r
1026 if ((a&0xff0000)==0xfe0000) {
\r
1027 dprintf("s68k_bram r32: [%06x] @%06x", a, SekPc);
\r
1028 a = (a>>1)&0x1fff;
\r
1029 d = Pico_mcd->bram[a++] << 16; // middle endian? TODO: verify against Fusion..
\r
1030 d|= Pico_mcd->bram[a++] << 24;
\r
1031 d|= Pico_mcd->bram[a++];
\r
1032 d|= Pico_mcd->bram[a++] << 8;
\r
1033 dprintf("ret = %08x", d);
\r
1037 dprintf("s68k r32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);
\r
1041 #ifdef __debug_io2
\r
1042 dprintf("s68k r32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);
\r
1048 // -----------------------------------------------------------------
\r
1050 void PicoWriteS68k8(u32 a,u8 d)
\r
1052 #ifdef __debug_io2
\r
1053 dprintf("s68k w8 : %06x, %02x @%06x", a&0xffffff, d, SekPcS68k);
\r
1059 if (a < 0x80000) {
\r
1060 u8 *pm=(u8 *)(Pico_mcd->prg_ram+(a^1));
\r
1066 if ((a&0xfffe00) == 0xff8000) {
\r
1068 rdprintf("s68k_regs w8: [%02x] %02x @ %06x", a, d, SekPcS68k);
\r
1069 if (a >= 0x50 && a < 0x68)
\r
1070 gfx_cd_write(a&~1, (d<<8)|d);
\r
1071 else s68k_reg_write8(a,d);
\r
1075 // word RAM (2M area)
\r
1076 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
1077 dprintf("s68k_wram2M w8: [%06x] %02x @%06x", a, d, SekPc);
\r
1078 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
1080 dprintf("(decode)");
\r
1082 // allow access in any mode, like Gens does
\r
1083 *(u8 *)(Pico_mcd->word_ram+((a^1)&0x3ffff))=d;
\r
1088 // word RAM (1M area)
\r
1089 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
1091 dprintf("s68k_wram1M w8: [%06x] %02x @%06x", a, d, SekPc);
\r
1092 a=((a&0x1fffe)<<1)|(a&1);
\r
1093 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;
\r
1094 *(u8 *)(Pico_mcd->word_ram+(a^1))=d;
\r
1099 if ((a&0xff8000)==0xff0000) {
\r
1102 Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a>>1)&0xfff] = d;
\r
1103 else if (a < 0x12)
\r
1104 pcm_write(a>>1, d);
\r
1109 if ((a&0xff0000)==0xfe0000) {
\r
1110 Pico_mcd->bram[(a>>1)&0x1fff] = d;
\r
1115 dprintf("s68k w8 : %06x, %02x @%06x", a&0xffffff, d, SekPcS68k);
\r
1119 void PicoWriteS68k16(u32 a,u16 d)
\r
1121 #ifdef __debug_io2
\r
1122 dprintf("s68k w16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);
\r
1128 if (a < 0x80000) {
\r
1129 *(u16 *)(Pico_mcd->prg_ram+a)=d;
\r
1134 if ((a&0xfffe00) == 0xff8000) {
\r
1136 rdprintf("s68k_regs w16: [%02x] %04x @ %06x", a, d, SekPcS68k);
\r
1137 if (a >= 0x50 && a < 0x68)
\r
1138 gfx_cd_write(a, d);
\r
1140 s68k_reg_write8(a, d>>8);
\r
1141 s68k_reg_write8(a+1,d&0xff);
\r
1146 // word RAM (2M area)
\r
1147 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
1148 dprintf("s68k_wram2M w16: [%06x] %04x @%06x", a, d, SekPc);
\r
1149 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
1151 dprintf("(decode)");
\r
1153 // allow access in any mode, like Gens does
\r
1154 *(u16 *)(Pico_mcd->word_ram+(a&0x3fffe))=d;
\r
1159 // word RAM (1M area)
\r
1160 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
1162 dprintf("s68k_wram1M w16: [%06x] %04x @%06x", a, d, SekPc);
\r
1163 a=((a&0x1fffe)<<1);
\r
1164 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;
\r
1165 *(u16 *)(Pico_mcd->word_ram+a)=d;
\r
1170 if ((a&0xff8000)==0xff0000) {
\r
1173 Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a>>1)&0xfff] = d;
\r
1174 else if (a < 0x12)
\r
1175 pcm_write(a>>1, d & 0xff);
\r
1180 if ((a&0xff0000)==0xfe0000) {
\r
1181 dprintf("s68k_bram w16: [%06x] %04x @%06x", a, d, SekPc);
\r
1182 a = (a>>1)&0x1fff;
\r
1183 Pico_mcd->bram[a++] = d; // Gens does little endian here, an so do we..
\r
1184 Pico_mcd->bram[a++] = d >> 8;
\r
1189 dprintf("s68k w16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);
\r
1193 void PicoWriteS68k32(u32 a,u32 d)
\r
1195 #ifdef __debug_io2
\r
1196 dprintf("s68k w32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);
\r
1202 if (a < 0x80000) {
\r
1203 u16 *pm=(u16 *)(Pico_mcd->prg_ram+a);
\r
1204 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
1209 if ((a&0xfffe00) == 0xff8000) {
\r
1211 rdprintf("s68k_regs w32: [%02x] %08x @ %06x", a, d, SekPcS68k);
\r
1212 if (a >= 0x50 && a < 0x68) {
\r
1213 gfx_cd_write(a, d>>16);
\r
1214 gfx_cd_write(a+2, d&0xffff);
\r
1216 s68k_reg_write8(a, d>>24);
\r
1217 s68k_reg_write8(a+1,(d>>16)&0xff);
\r
1218 s68k_reg_write8(a+2,(d>>8) &0xff);
\r
1219 s68k_reg_write8(a+3, d &0xff);
\r
1224 // word RAM (2M area)
\r
1225 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
1226 dprintf("s68k_wram2M w32: [%06x] %08x @%06x", a, d, SekPc);
\r
1227 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
1229 dprintf("(decode)");
\r
1231 // allow access in any mode, like Gens does
\r
1232 u16 *pm=(u16 *)(Pico_mcd->word_ram+(a&0x3fffe));
\r
1233 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
1238 // word RAM (1M area)
\r
1239 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
1241 dprintf("s68k_wram1M w32: [%06x] %08x @%06x", a, d, SekPc);
\r
1242 a=((a&0x1fffe)<<1);
\r
1243 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;
\r
1244 *(u16 *)(Pico_mcd->word_ram+a) = d>>16;
\r
1245 *(u16 *)(Pico_mcd->word_ram+a+4) = d;
\r
1250 if ((a&0xff8000)==0xff0000) {
\r
1252 if (a >= 0x2000) {
\r
1254 Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][a&0xfff] = (d >> 16);
\r
1255 Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a+1)&0xfff] = d;
\r
1256 } else if (a < 0x12) {
\r
1258 pcm_write(a, (d>>16) & 0xff);
\r
1259 pcm_write(a+1, d & 0xff);
\r
1265 if ((a&0xff0000)==0xfe0000) {
\r
1266 dprintf("s68k_bram w32: [%06x] %08x @%06x", a, d, SekPc);
\r
1267 a = (a>>1)&0x1fff;
\r
1268 Pico_mcd->bram[a++] = d >> 16; // middle endian? verify?
\r
1269 Pico_mcd->bram[a++] = d >> 24;
\r
1270 Pico_mcd->bram[a++] = d;
\r
1271 Pico_mcd->bram[a++] = d >> 8;
\r
1276 dprintf("s68k w32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);
\r
1281 // -----------------------------------------------------------------
\r
1284 #if defined(EMU_C68K)
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1285 static __inline int PicoMemBaseM68k(u32 pc)
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1291 membase=(int)Pico_mcd->bios; // Program Counter in BIOS
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1293 else if ((pc&0xe00000)==0xe00000)
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1295 membase=(int)Pico.ram-(pc&0xff0000); // Program Counter in Ram
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1297 else if ((pc&0xfc0000)==0x200000 && !(Pico_mcd->s68k_regs[3]&4))
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1299 membase=(int)Pico_mcd->word_ram-0x200000; // Program Counter in Word Ram
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1303 // Error - Program Counter is invalid
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1304 dprintf("m68k: unhandled jump to %06x", pc);
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1305 membase=(int)Pico.rom;
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1312 static u32 PicoCheckPcM68k(u32 pc)
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1314 pc-=PicoCpu.membase; // Get real pc
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1317 PicoCpu.membase=PicoMemBaseM68k(pc);
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1319 return PicoCpu.membase+pc;
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1323 static __inline int PicoMemBaseS68k(u32 pc)
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1327 membase=(int)Pico_mcd->prg_ram; // Program Counter in Prg RAM
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1328 if (pc >= 0x80000)
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1330 // Error - Program Counter is invalid
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1331 dprintf("s68k: unhandled jump to %06x", pc);
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1338 static u32 PicoCheckPcS68k(u32 pc)
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1340 pc-=PicoCpuS68k.membase; // Get real pc
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1343 PicoCpuS68k.membase=PicoMemBaseS68k(pc);
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1345 return PicoCpuS68k.membase+pc;
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1350 void PicoMemSetupCD()
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1352 dprintf("PicoMemSetupCD()");
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1354 // Setup m68k memory callbacks:
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1355 PicoCpu.checkpc=PicoCheckPcM68k;
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1356 PicoCpu.fetch8 =PicoCpu.read8 =PicoReadM68k8;
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1357 PicoCpu.fetch16=PicoCpu.read16=PicoReadM68k16;
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1358 PicoCpu.fetch32=PicoCpu.read32=PicoReadM68k32;
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1359 PicoCpu.write8 =PicoWriteM68k8;
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1360 PicoCpu.write16=PicoWriteM68k16;
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1361 PicoCpu.write32=PicoWriteM68k32;
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1363 PicoCpuS68k.checkpc=PicoCheckPcS68k;
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1364 PicoCpuS68k.fetch8 =PicoCpuS68k.read8 =PicoReadS68k8;
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1365 PicoCpuS68k.fetch16=PicoCpuS68k.read16=PicoReadS68k16;
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1366 PicoCpuS68k.fetch32=PicoCpuS68k.read32=PicoReadS68k32;
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1367 PicoCpuS68k.write8 =PicoWriteS68k8;
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1368 PicoCpuS68k.write16=PicoWriteS68k16;
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1369 PicoCpuS68k.write32=PicoWriteS68k32;
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1375 unsigned char PicoReadCD8w (unsigned int a) {
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1376 return m68ki_cpu_p == &PicoS68kCPU ? PicoReadS68k8(a) : PicoReadM68k8(a);
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1378 unsigned short PicoReadCD16w(unsigned int a) {
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1379 return m68ki_cpu_p == &PicoS68kCPU ? PicoReadS68k16(a) : PicoReadM68k16(a);
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1381 unsigned int PicoReadCD32w(unsigned int a) {
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1382 return m68ki_cpu_p == &PicoS68kCPU ? PicoReadS68k32(a) : PicoReadM68k32(a);
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1384 void PicoWriteCD8w (unsigned int a, unsigned char d) {
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1385 if (m68ki_cpu_p == &PicoS68kCPU) PicoWriteS68k8(a, d); else PicoWriteM68k8(a, d);
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1387 void PicoWriteCD16w(unsigned int a, unsigned short d) {
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1388 if (m68ki_cpu_p == &PicoS68kCPU) PicoWriteS68k16(a, d); else PicoWriteM68k16(a, d);
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1390 void PicoWriteCD32w(unsigned int a, unsigned int d) {
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1391 if (m68ki_cpu_p == &PicoS68kCPU) PicoWriteS68k32(a, d); else PicoWriteM68k32(a, d);
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1394 // these are allowed to access RAM
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1395 unsigned int m68k_read_pcrelative_CD8 (unsigned int a) {
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1397 if(m68ki_cpu_p == &PicoS68kCPU) {
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1398 if (a < 0x80000) return *(u8 *)(Pico_mcd->prg_ram+(a^1)); // PRG Ram
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1399 dprintf("s68k_read_pcrelative_CD8: can't handle %06x", a);
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1401 if(a<0x20000) return *(u8 *)(Pico.rom+(a^1)); // Bios
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1402 if((a&0xe00000)==0xe00000) return *(u8 *)(Pico.ram+((a^1)&0xffff)); // Ram
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1403 if(!(Pico_mcd->s68k_regs[3]&4) && (a&0xfc0000)==0x200000)
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1404 return Pico_mcd->word_ram[(a^1)&0x3fffe];
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1405 dprintf("m68k_read_pcrelative_CD8: can't handle %06x", a);
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1407 return 0;//(u8) lastread_d;
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1409 unsigned int m68k_read_pcrelative_CD16(unsigned int a) {
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1411 if(m68ki_cpu_p == &PicoS68kCPU) {
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1412 if (a < 0x80000) return *(u16 *)(Pico_mcd->prg_ram+(a&~1)); // PRG Ram
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1413 dprintf("s68k_read_pcrelative_CD16: can't handle %06x", a);
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1415 if(a<0x20000) return *(u16 *)(Pico.rom+(a&~1)); // Bios
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1416 if((a&0xe00000)==0xe00000) return *(u16 *)(Pico.ram+(a&0xfffe)); // Ram
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1417 if(!(Pico_mcd->s68k_regs[3]&4) && (a&0xfc0000)==0x200000)
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1418 return *(u16 *)(Pico_mcd->word_ram+(a&0x3fffe));
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1419 dprintf("m68k_read_pcrelative_CD16: can't handle %06x", a);
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1423 unsigned int m68k_read_pcrelative_CD32(unsigned int a) {
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1425 if(m68ki_cpu_p == &PicoS68kCPU) {
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1426 if (a < 0x80000) { u16 *pm=(u16 *)(Pico_mcd->prg_ram+(a&~1)); return (pm[0]<<16)|pm[1]; } // PRG Ram
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1427 dprintf("s68k_read_pcrelative_CD32: can't handle %06x", a);
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1429 if(a<0x20000) { u16 *pm=(u16 *)(Pico.rom+(a&~1)); return (pm[0]<<16)|pm[1]; }
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1430 if((a&0xe00000)==0xe00000) { u16 *pm=(u16 *)(Pico.ram+(a&0xfffe)); return (pm[0]<<16)|pm[1]; } // Ram
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1431 if(!(Pico_mcd->s68k_regs[3]&4) && (a&0xfc0000)==0x200000)
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1432 { u16 *pm=(u16 *)(Pico_mcd->word_ram+(a&0x3fffe)); return (pm[0]<<16)|pm[1]; }
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1433 dprintf("m68k_read_pcrelative_CD32: can't handle %06x", a);
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1437 #endif // EMU_M68K
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