3 @ Memory i/o handlers for Sega/Mega CD emulation
4 @ (c) Copyright 2007, Grazvydas "notaz" Ignotas
9 .equiv PCM_STEP_SHIFT, 11
17 .macro mk_m68k_jump_table on sz @ operation name, size
18 .long m_m68k_&\on&\sz&_bios @ 0x000000 - 0x01ffff
19 .long m_m68k_&\on&\sz&_prgbank @ 0x020000 - 0x03ffff
20 .long m_&\on&_null, m_&\on&_null @ 0x040000 - 0x07ffff
21 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x080000 - 0x0fffff
22 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x100000 - 0x17ffff
23 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x180000 - 0x1fffff
24 .long m_m68k_&\on&\sz&_wordram0_2M @ 0x200000 - 0x21ffff
25 .long m_m68k_&\on&\sz&_wordram1_2M @ 0x220000 - 0x23ffff
26 .long m_&\on&_null, m_&\on&_null @ 0x240000 - 0x27ffff
27 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x280000 - 0x2fffff
28 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x300000
29 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0x3fffff
30 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x400000
31 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0x4fffff
32 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x500000
33 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0x5fffff
34 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x600000
35 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0x6fffff
36 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x700000
37 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0x7fffff
38 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x800000
39 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0x8fffff
40 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x900000
41 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0x9fffff
42 .long m_m68k_&\on&\sz&_system_io @ 0xa00000 - 0xa1ffff
43 .long m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0xa20000 - 0xa7ffff
44 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0xa80000 - 0xafffff
45 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0xb00000
46 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0xbfffff
47 .long m_m68k_&\on&\sz&_vdp, m_m68k_&\on&\sz&_vdp, m_m68k_&\on&\sz&_vdp, m_m68k_&\on&\sz&_vdp @ 0xc00000
48 .long m_m68k_&\on&\sz&_vdp, m_m68k_&\on&\sz&_vdp, m_m68k_&\on&\sz&_vdp, m_m68k_&\on&\sz&_vdp @ - 0xcfffff
49 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0xd00000
50 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0xdfffff
51 .long m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram @ 0xe00000
52 .long m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram @ - 0xefffff
53 .long m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram @ 0xf00000
54 .long m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram @ - 0xffffff
57 .macro mk_s68k_jump_table on sz @ operation name, size
58 .long m_s68k_&\on&\sz&_prg, m_s68k_&\on&\sz&_prg, m_s68k_&\on&\sz&_prg, m_s68k_&\on&\sz&_prg @ 0x000000 - 0x07ffff
59 .long m_s68k_&\on&\sz&_wordram_2M @ 0x080000 - 0x09ffff
60 .long m_s68k_&\on&\sz&_wordram_2M @ 0x0a0000 - 0x0bffff
61 .long m_&\on&_null @ 0x0c0000 - 0x0dffff, 1M area
62 .long m_&\on&_null @ 0x0e0000 - 0x0fffff
66 @ the jumptables themselves.
67 m_m68k_read8_table: mk_m68k_jump_table read 8
68 m_m68k_read16_table: mk_m68k_jump_table read 16
69 m_m68k_read32_table: mk_m68k_jump_table read 32
70 m_m68k_write8_table: mk_m68k_jump_table write 8
71 m_m68k_write16_table: mk_m68k_jump_table write 16
72 m_m68k_write32_table: mk_m68k_jump_table write 32
74 m_s68k_read8_table: mk_s68k_jump_table read 8
75 m_s68k_read16_table: mk_s68k_jump_table read 16
76 m_s68k_read32_table: mk_s68k_jump_table read 32
77 m_s68k_write8_table: mk_s68k_jump_table write 8
78 m_s68k_write16_table: mk_s68k_jump_table write 16
79 m_s68k_write32_table: mk_s68k_jump_table write 32
81 m_s68k_decode_write_table:
82 .long m_s68k_write8_2M_decode_b0_m0
83 .long m_s68k_write16_2M_decode_b0_m0
84 .long m_s68k_write32_2M_decode_b0_m0
85 .long m_s68k_write8_2M_decode_b0_m1
86 .long m_s68k_write16_2M_decode_b0_m1
87 .long m_s68k_write32_2M_decode_b0_m1
88 .long m_s68k_write8_2M_decode_b0_m2
89 .long m_s68k_write16_2M_decode_b0_m2
90 .long m_s68k_write32_2M_decode_b0_m2
91 .long m_s68k_write8_2M_decode_b1_m0
92 .long m_s68k_write16_2M_decode_b1_m0
93 .long m_s68k_write32_2M_decode_b1_m0
94 .long m_s68k_write8_2M_decode_b1_m1
95 .long m_s68k_write16_2M_decode_b1_m1
96 .long m_s68k_write32_2M_decode_b1_m1
97 .long m_s68k_write8_2M_decode_b1_m2
98 .long m_s68k_write16_2M_decode_b1_m2
99 .long m_s68k_write32_2M_decode_b1_m2
102 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
107 .global PicoMemResetCD
108 .global PicoMemResetCDdecode
109 .global PicoReadM68k8
110 .global PicoReadM68k16
111 .global PicoReadM68k32
112 .global PicoWriteM68k8
113 .global PicoWriteM68k16
114 .global PicoWriteM68k32
115 .global PicoReadS68k8
116 .global PicoReadS68k16
117 .global PicoReadS68k32
118 .global PicoWriteS68k8
119 .global PicoWriteS68k16
120 .global PicoWriteS68k32
122 @ externs, just for reference
126 .extern PicoVideoRead
127 .extern Read_CDC_Host
128 .extern m68k_reg_write8
132 .extern s68k_reg_read16
134 .extern gfx_cd_write16
135 .extern s68k_reg_write8
136 .extern s68k_poll_adclk
138 .extern s68k_poll_detect
142 @ r0=reg3, r1-r3=temp
143 .macro mk_update_table on sz @ operation name, size
144 @ we only set word-ram handlers
145 ldr r1, =m_m68k_&\on&\sz&_table
146 ldr r12,=m_s68k_&\on&\sz&_table
151 ldr r2, =m_m68k_&\on&\sz&_wordram0_2M
152 ldr r3, =m_s68k_&\on&\sz&_wordram_2M
155 ldr r2, =m_&\on&_null
166 ldr r2, =m_m68k_&\on&\sz&_wordram0_1M_b0
167 ldr r3, =m_m68k_&\on&\sz&_wordram1_1M_b0
170 ldr r3, =m_s68k_&\on&\sz&_wordram_1M_b1
172 ldr r2, =m_s68k_&\on&\sz&_wordram_2M_decode_b1
180 ldr r2, =m_m68k_&\on&\sz&_wordram0_1M_b1
181 ldr r3, =m_m68k_&\on&\sz&_wordram1_1M_b1
184 ldr r3, =m_s68k_&\on&\sz&_wordram_1M_b0
186 ldr r2, =m_s68k_&\on&\sz&_wordram_2M_decode_b0
197 mk_update_table read 8
198 mk_update_table read 16
199 mk_update_table read 32
200 mk_update_table write 8
201 mk_update_table write 16
202 mk_update_table write 32
206 PicoMemResetCDdecode: @reg3
208 bxeq lr @ we should not be called in 2M mode
209 ldr r1, =m_s68k_write8_table
210 ldr r3, =m_s68k_decode_write_table
214 moveq r2, #2 @ mode3 is same as mode2?
216 addeq r2, r2, #3 @ bank1 (r2=0..5)
217 add r2, r2, r2, lsl #1 @ *= 3
218 add r2, r3, r2, lsl #2
219 ldmia r2, {r0,r3,r12}
222 str r3, [r1, #4*4+8*4]
223 str r3, [r1, #5*4+8*4]
224 str r12,[r1, #4*4+8*4*2]
225 str r12,[r1, #5*4+8*4*2]
231 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
233 .macro mk_entry_m68k table
235 bic r0, r0, #0xff000000
236 and r3, r0, #0x00fe0000
237 ldr pc, [r2, r3, lsr #15]
240 PicoReadM68k8: @ u32 a
241 mk_entry_m68k m_m68k_read8_table
243 PicoReadM68k16: @ u32 a
244 mk_entry_m68k m_m68k_read16_table
246 PicoReadM68k32: @ u32 a
247 mk_entry_m68k m_m68k_read32_table
249 PicoWriteM68k8: @ u32 a, u8 d
250 mk_entry_m68k m_m68k_write8_table
252 PicoWriteM68k16: @ u32 a, u16 d
253 mk_entry_m68k m_m68k_write16_table
255 PicoWriteM68k32: @ u32 a, u32 d
256 mk_entry_m68k m_m68k_write32_table
259 .macro mk_entry_s68k on sz
260 bic r0, r0, #0xff000000
262 blt m_s68k_&\on&\sz&_prg
264 ldrlt r2, =m_s68k_&\on&\sz&_table
265 andlt r3, r0, #0x000e0000
266 ldrlt pc, [r2, r3, lsr #15]
268 orr r3, r3, #0x00008000
270 bge m_s68k_&\on&\sz&_regs
272 bge m_s68k_&\on&\sz&_pcm
274 bge m_s68k_&\on&\sz&_backup
279 PicoReadS68k8: @ u32 a
282 PicoReadS68k16: @ u32 a
283 mk_entry_s68k read 16
285 PicoReadS68k32: @ u32 a
286 mk_entry_s68k read 32
288 PicoWriteS68k8: @ u32 a, u8 d
289 mk_entry_s68k write 8
291 PicoWriteS68k16: @ u32 a, u16 d
292 mk_entry_s68k write 16
294 PicoWriteS68k32: @ u32 a, u32 d
295 mk_entry_s68k write 32
300 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
304 @ r0=addr[in,out], r1,r2=tmp
306 ands r1, r0, #0x01c000
307 ldrne pc, [pc, r1, lsr #12]
308 beq 0f @ most common?
318 and r1, r0, #0x7e00 @ col
319 and r2, r0, #0x01fc @ row
321 orr r1, r2, r1, ror #13
324 and r1, r0, #0x3f00 @ col
325 and r2, r0, #0x00fc @ row
327 orr r1, r2, r1, ror #12
330 and r1, r0, #0x1f80 @ col
331 and r2, r0, #0x007c @ row
332 orr r1, r2, r1, ror #11
334 orr r1, r1, r2, lsr #6
337 and r1, r0, #0xfc00 @ col
338 and r2, r0, #0x03fc @ row
339 orr r1, r2, r1, ror #14
342 orr r0, r0, r1, ror #26 @ rol 4+2
346 @ r0=prt1, r1=ptr2; unaligned ptr MUST be r0
352 moveq r0, r0, ror #16
353 orrne r0, r1, r0, lsl #16
357 @ r0=prt1, r1=data, r2=ptr2; unaligned ptr MUST be r0
362 movne r1, r1, lsr #16
368 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
377 ldr r1, =(Pico+0x22200)
378 bic r0, r0, #0xfe0000
385 m_m68k_read8_prgbank:
386 ldr r1, =(Pico+0x22200)
390 orr r3, r2, #0x002200
393 and r3, r3, #0x00030000
394 cmp r3, #0x00010000 @ have bus or in reset state?
397 and r2, r2, #0xc0000000 @ r3 & 0xC0
398 add r1, r1, r2, lsr #12
403 m_m68k_read8_wordram0_2M: @ 0x200000 - 0x21ffff
404 m_m68k_read8_wordram1_2M: @ 0x220000 - 0x23ffff
405 ldr r1, =(Pico+0x22200)
406 sub r0, r0, #0x160000 @ map to our offset, which is 0x0a0000
413 m_m68k_read8_wordram0_1M_b0: @ 0x200000 - 0x21ffff
414 ldr r1, =(Pico+0x22200)
415 sub r0, r0, #0x140000 @ map to our offset, which is 0x0c0000
422 m_m68k_read8_wordram0_1M_b1: @ 0x200000 - 0x21ffff
423 ldr r1, =(Pico+0x22200)
424 sub r0, r0, #0x120000 @ map to our offset, which is 0x0e0000
431 m_m68k_read8_wordram1_1M_b0: @ 0x220000 - 0x23ffff, cell arranged
433 ldr r1, =(Pico+0x22200)
434 add r0, r0, #0x0c0000
441 m_m68k_read8_wordram1_1M_b1: @ 0x220000 - 0x23ffff, cell arranged
443 ldr r1, =(Pico+0x22200)
444 add r0, r0, #0x0e0000
451 m_m68k_read8_system_io:
452 bic r2, r0, #0xfe0000
455 bne m_m68k_read8_misc
457 ldr r1, =(Pico+0x22200)
459 ldr r1, [r1] @ Pico.mcd (used everywhere)
461 ldrlt pc, [pc, r0, lsl #2]
463 .long m_m68k_read8_r00
464 .long m_m68k_read8_r01
465 .long m_m68k_read8_r02
466 .long m_m68k_read8_r03
467 .long m_m68k_read8_r04
468 .long m_read_null @ unused bits
469 .long m_m68k_read8_r06
470 .long m_m68k_read8_r07
471 .long m_m68k_read8_r08
472 .long m_m68k_read8_r09
473 .long m_read_null @ reserved
475 .long m_m68k_read8_r0c
476 .long m_m68k_read8_r0d
478 add r1, r1, #0x110000
480 and r0, r0, #0x04000000 @ we need irq2 mask state
484 add r1, r1, #0x110000
485 add r1, r1, #0x002200
486 ldrb r0, [r1, #2] @ Pico_mcd->m.busreq
489 add r1, r1, #0x110000
493 add r1, r1, #0x110000
495 add r1, r1, #0x002200
498 tst r1, #2 @ DMNA pending?
504 add r1, r1, #0x110000
508 ldrb r0, [r1, #0x73] @ IRQ vector
515 bl Read_CDC_Host @ TODO: make it local
522 add r1, r1, #0x110000
523 add r1, r1, #0x002200
524 ldr r0, [r1, #0x14] @ Pico_mcd->m.timer_stopwatch
528 add r1, r1, #0x110000
529 add r1, r1, #0x002200
537 add r1, r1, #0x110000
545 cmp r2, #0xa00000 @ Z80 RAM?
547 @ ldreq r2, =z80Read8
552 bl OtherRead16 @ non-MCD version should be ok too
562 bxne lr @ invalid read
565 bl PicoVideoRead @ TODO: implement it in asm
574 bic r0, r0, #0xff0000
580 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
584 ldr r1, =(Pico+0x22200)
585 bic r0, r0, #0xfe0000
592 m_m68k_read16_prgbank:
593 ldr r1, =(Pico+0x22200)
597 orr r3, r2, #0x002200
600 and r3, r3, #0x00030000
601 cmp r3, #0x00010000 @ have bus or in reset state?
604 and r2, r2, #0xc0000000 @ r3 & 0xC0
605 add r1, r1, r2, lsr #12
610 m_m68k_read16_wordram0_2M: @ 0x200000 - 0x21ffff
611 m_m68k_read16_wordram1_2M: @ 0x220000 - 0x23ffff
612 ldr r1, =(Pico+0x22200)
613 sub r0, r0, #0x160000 @ map to our offset, which is 0x0a0000
620 m_m68k_read16_wordram0_1M_b0: @ 0x200000 - 0x21ffff
621 ldr r1, =(Pico+0x22200)
622 sub r0, r0, #0x140000 @ map to our offset, which is 0x0c0000
629 m_m68k_read16_wordram0_1M_b1: @ 0x200000 - 0x21ffff
630 ldr r1, =(Pico+0x22200)
631 sub r0, r0, #0x120000 @ map to our offset, which is 0x0e0000
638 m_m68k_read16_wordram1_1M_b0: @ 0x220000 - 0x23ffff, cell arranged
639 @ Warning: read32 relies on NOT using r3 and r12 here
641 ldr r1, =(Pico+0x22200)
642 add r0, r0, #0x0c0000
649 m_m68k_read16_wordram1_1M_b1: @ 0x220000 - 0x23ffff, cell arranged
651 ldr r1, =(Pico+0x22200)
652 add r0, r0, #0x0e0000
659 m_m68k_read16_system_io:
660 bic r1, r0, #0xfe0000
663 bne m_m68k_read16_misc
665 m_m68k_read16_m68k_regs:
666 ldr r1, =(Pico+0x22200)
668 ldr r1, [r1] @ Pico.mcd (used everywhere)
670 ldrlt pc, [pc, r0, lsl #1]
672 .long m_m68k_read16_r00
673 .long m_m68k_read16_r02
674 .long m_m68k_read16_r04
675 .long m_m68k_read16_r06
676 .long m_m68k_read16_r08
677 .long m_read_null @ reserved
678 .long m_m68k_read16_r0c
680 add r1, r1, #0x110000
682 add r1, r1, #0x002200
683 ldrb r1, [r1, #2] @ Pico_mcd->m.busreq
684 and r0, r0, #0x04000000 @ we need irq2 mask state
685 orr r0, r1, r0, lsr #11
688 add r1, r1, #0x110000
691 add r1, r1, #0x002200
694 orr r0, r2, r0, lsl #8
695 tst r1, #2 @ DMNA pending?
701 add r1, r1, #0x110000
706 ldrh r0, [r1, #0x72] @ IRQ vector
712 add r1, r1, #0x110000
713 add r1, r1, #0x002200
719 addlt r1, r1, #0x110000
725 orr r0, r0, r1, lsl #8
738 bxne lr @ invalid read
745 bic r0, r0, #0xff0000
751 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
755 ldr r1, =(Pico+0x22200)
756 bic r0, r0, #0xfe0000
763 m_m68k_read32_prgbank:
764 ldr r1, =(Pico+0x22200)
768 orr r3, r2, #0x002200
771 and r3, r3, #0x00030000
772 cmp r3, #0x00010000 @ have bus or in reset state?
775 and r2, r2, #0xc0000000 @ r3 & 0xC0
776 add r1, r1, r2, lsr #12
781 m_m68k_read32_wordram0_2M: @ 0x200000 - 0x21ffff
782 m_m68k_read32_wordram1_2M: @ 0x220000 - 0x23ffff
783 ldr r1, =(Pico+0x22200)
784 sub r0, r0, #0x160000 @ map to our offset, which is 0x0a0000
791 m_m68k_read32_wordram0_1M_b0: @ 0x200000 - 0x21ffff
792 ldr r1, =(Pico+0x22200)
793 sub r0, r0, #0x140000 @ map to our offset, which is 0x0c0000
800 m_m68k_read32_wordram0_1M_b1: @ 0x200000 - 0x21ffff
801 ldr r1, =(Pico+0x22200)
802 sub r0, r0, #0x120000 @ map to our offset, which is 0x0e0000
809 m_m68k_read32_wordram1_1M_b0: @ 0x220000 - 0x23ffff, cell arranged
811 bne m_m68k_read32_wordram1_1M_b0_unal
813 ldr r1, =(Pico+0x22200)
814 add r0, r0, #0x0c0000
819 m_m68k_read32_wordram1_1M_b0_unal:
820 @ hopefully this doesn't happen too often
823 bl m_m68k_read16_wordram1_1M_b0 @ must not trash r12 and r3
827 bl m_m68k_read16_wordram1_1M_b0
828 orr r0, r0, r3, lsl #16
832 m_m68k_read32_wordram1_1M_b1: @ 0x220000 - 0x23ffff, cell arranged
834 bne m_m68k_read32_wordram1_1M_b1_unal
836 ldr r1, =(Pico+0x22200)
837 add r0, r0, #0x0e0000
842 m_m68k_read32_wordram1_1M_b1_unal:
845 bl m_m68k_read16_wordram1_1M_b1 @ must not trash r12 and r3
849 bl m_m68k_read16_wordram1_1M_b1
850 orr r0, r0, r3, lsl #16
854 @ it is not very practical to use long access on hw registers, so I assume it is not used too much.
855 m_m68k_read32_system_io:
856 bic r1, r0, #0xfe0000
859 bne m_m68k_read32_misc
862 blt m_m68k_read32_misc
866 @ I have seen the range 0x0e-0x2f accessed quite frequently with long i/o, so here is some code for that
868 ldr r1, =(Pico+0x22200)
871 orr r2, r2, r2, lsl #16
872 add r1, r1, #0x110000
874 and r1, r2, r0 @ data is big-endian read as little, have to byteswap
875 and r0, r2, r0, lsr #8
876 orr r0, r0, r1, lsl #8
882 bl m_m68k_read16_system_io
884 bl m_m68k_read16_system_io
886 orr r0, r0, r1, lsl #16
893 bxne lr @ invalid read
901 orr r0, r0, r1, lsl #16
907 bic r0, r0, #0xff0000
914 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
922 m_m68k_write8_prgbank:
923 ldr r2, =(Pico+0x22200)
927 orr r3, r12, #0x002200
930 and r3, r3, #0x00030000
931 cmp r3, #0x00010000 @ have bus or in reset state?
933 and r12,r12,#0xc0000000 @ r3 & 0xC0
934 add r2, r2, r12, lsr #12
939 m_m68k_write8_wordram0_2M: @ 0x200000 - 0x21ffff
940 m_m68k_write8_wordram1_2M: @ 0x220000 - 0x23ffff
941 ldr r2, =(Pico+0x22200)
942 sub r0, r0, #0x160000 @ map to our offset, which is 0x0a0000
949 m_m68k_write8_wordram0_1M_b0: @ 0x200000 - 0x21ffff
950 ldr r2, =(Pico+0x22200)
951 sub r0, r0, #0x140000 @ map to our offset, which is 0x0c0000
958 m_m68k_write8_wordram0_1M_b1: @ 0x200000 - 0x21ffff
959 ldr r2, =(Pico+0x22200)
960 sub r0, r0, #0x120000 @ map to our offset, which is 0x0e0000
967 m_m68k_write8_wordram1_1M_b0: @ 0x220000 - 0x23ffff, cell arranged
970 ldr r2, =(Pico+0x22200)
971 add r0, r0, #0x0c0000
978 m_m68k_write8_wordram1_1M_b1: @ 0x220000 - 0x23ffff, cell arranged
981 ldr r2, =(Pico+0x22200)
982 add r0, r0, #0x0e0000
989 m_m68k_write8_system_io:
990 bic r2, r0, #0xfe0000
1007 orr r1, r1, r1, lsl #8 @ byte access gets mirrored
1013 bic r0, r0, #0xff0000
1019 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1022 m_m68k_write16_bios:
1026 m_m68k_write16_prgbank:
1027 ldr r2, =(Pico+0x22200)
1031 orr r3, r12, #0x002200
1034 and r3, r3, #0x00030000
1035 cmp r3, #0x00010000 @ have bus or in reset state?
1037 and r12,r12,#0xc0000000 @ r3 & 0xC0
1038 add r2, r2, r12, lsr #12
1043 m_m68k_write16_wordram0_2M: @ 0x200000 - 0x21ffff
1044 m_m68k_write16_wordram1_2M: @ 0x220000 - 0x23ffff
1045 ldr r2, =(Pico+0x22200)
1046 sub r0, r0, #0x160000 @ map to our offset, which is 0x0a0000
1053 m_m68k_write16_wordram0_1M_b0: @ 0x200000 - 0x21ffff
1054 ldr r2, =(Pico+0x22200)
1055 sub r0, r0, #0x140000 @ map to our offset, which is 0x0c0000
1062 m_m68k_write16_wordram0_1M_b1: @ 0x200000 - 0x21ffff
1063 ldr r2, =(Pico+0x22200)
1064 sub r0, r0, #0x120000 @ map to our offset, which is 0x0e0000
1071 m_m68k_write16_wordram1_1M_b0: @ 0x220000 - 0x23ffff, cell arranged
1072 @ Warning: write32 relies on NOT using r12 and and keeping data in r3
1075 ldr r1, =(Pico+0x22200)
1076 add r0, r0, #0x0c0000
1083 m_m68k_write16_wordram1_1M_b1: @ 0x220000 - 0x23ffff, cell arranged
1086 ldr r1, =(Pico+0x22200)
1087 add r0, r0, #0x0e0000
1094 m_m68k_write16_system_io:
1096 bic r2, r0, #0xfe0000
1101 m_m68k_write16_m68k_regs:
1104 beq m_m68k_write16_regs_spec
1107 stmfd sp!,{r2,r3,lr}
1110 ldmfd sp!,{r0,r1,lr}
1113 m_m68k_write16_regs_spec: @ special case
1114 ldr r2, =(Pico+0x22200)
1115 ldr r3, =s68k_poll_adclk
1118 add r0, r0, #0x00000e
1120 strb r1, [r2, r0] @ if (a == 0xe) s68k_regs[0x0e] = d >> 8;
1126 ldr r0, =PicoCpuS68k
1127 str r1, [r0, #0x58] @ push s68k out of stopped state
1141 b SN76496Write @ lsb goes to 0x11
1146 bic r0, r0, #0xff0000
1152 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1155 m_m68k_write32_bios:
1159 m_m68k_write32_prgbank:
1160 ldr r2, =(Pico+0x22200)
1164 orr r3, r12, #0x002200
1167 and r3, r3, #0x00030000
1168 cmp r3, #0x00010000 @ have bus or in reset state?
1170 and r12,r12,#0xc0000000 @ r3 & 0xC0
1171 add r2, r2, r12, lsr #12
1176 m_m68k_write32_wordram0_2M: @ 0x200000 - 0x21ffff
1177 m_m68k_write32_wordram1_2M: @ 0x220000 - 0x23ffff
1178 ldr r2, =(Pico+0x22200)
1179 sub r0, r0, #0x160000 @ map to our offset, which is 0x0a0000
1186 m_m68k_write32_wordram0_1M_b0: @ 0x200000 - 0x21ffff
1187 ldr r2, =(Pico+0x22200)
1188 sub r0, r0, #0x140000 @ map to our offset, which is 0x0c0000
1195 m_m68k_write32_wordram0_1M_b1: @ 0x200000 - 0x21ffff
1196 ldr r2, =(Pico+0x22200)
1197 sub r0, r0, #0x120000 @ map to our offset, which is 0x0e0000
1204 m_m68k_write32_wordram1_1M_b0: @ 0x220000 - 0x23ffff, cell arranged
1206 bne m_m68k_write32_wordram1_1M_b0_unal
1209 ldr r2, =(Pico+0x22200)
1210 add r0, r0, #0x0c0000
1216 m_m68k_write32_wordram1_1M_b0_unal:
1217 @ hopefully this doesn't happen too often
1221 bl m_m68k_write16_wordram1_1M_b0 @ must not trash r12 and keep data in r3
1225 b m_m68k_write16_wordram1_1M_b0
1228 m_m68k_write32_wordram1_1M_b1: @ 0x220000 - 0x23ffff, cell arranged
1230 bne m_m68k_write32_wordram1_1M_b1_unal
1233 ldr r2, =(Pico+0x22200)
1234 add r0, r0, #0x0e0000
1240 m_m68k_write32_wordram1_1M_b1_unal:
1244 bl m_m68k_write16_wordram1_1M_b1 @ same as above
1248 b m_m68k_write16_wordram1_1M_b1
1251 @ it is not very practical to use long access on hw registers, so I assume it is not used too much.
1252 m_m68k_write32_system_io:
1253 bic r2, r0, #0xfe0000
1256 bne m_m68k_write32_misc
1259 blt m_m68k_write32_regs
1262 @ Handle the 0x10-0x1f range
1263 ldr r0, =(Pico+0x22200)
1266 orr r3, r3, r3, lsl #16
1267 add r0, r0, #0x110000
1268 and r12,r3, r1, ror #16 @ data is big-endian to be written as little, have to byteswap
1269 and r1, r3, r1, ror #24
1270 orr r1, r1, r12,lsl #8 @ end of byteswap
1273 movne r1, r1, lsr #16
1277 m_m68k_write32_regs:
1279 stmfd sp!,{r0,r1,lr}
1292 ldmfd sp!,{r0,r1,lr}
1296 m_m68k_write32_misc:
1298 stmfd sp!,{r0,r1,lr}
1301 ldmfd sp!,{r0,r1,lr}
1312 moveq r0, r1, lsr #16
1313 beq SN76496Write @ which game is crazy enough to do that?
1314 stmfd sp!,{r0,r1,lr}
1317 ldmfd sp!,{r0,r1,lr}
1324 bic r0, r0, #0xff0000
1332 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1334 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1337 .macro m_s68k_read8_ram map_addr
1338 ldr r1, =(Pico+0x22200)
1342 add r0, r0, #\map_addr @ map to our address
1348 .macro m_s68k_read8_wordram_2M_decode map_addr
1349 ldr r2, =(Pico+0x22200)
1352 movs r0, r0, lsr #1 @ +4-6 <<16
1353 add r2, r2, #\map_addr @ map to our address
1355 movcc r0, r0, lsr #4
1361 m_s68k_read8_prg: @ 0x000000 - 0x07ffff
1362 m_s68k_read8_wordram_2M: @ 0x080000 - 0x0bffff
1363 m_s68k_read8_wordram_1M_b1: @ 0x0c0000 - 0x0dffff, maps to 0x0e0000
1364 m_s68k_read8_ram 0x020000
1367 m_s68k_read8_wordram_2M_decode_b0: @ 0x080000 - 0x0bffff
1368 m_s68k_read8_wordram_2M_decode 0x080000 @ + ^ / 2
1371 m_s68k_read8_wordram_2M_decode_b1: @ 0x080000 - 0x0bffff
1372 m_s68k_read8_wordram_2M_decode 0x0a0000 @ + ^ / 2
1375 m_s68k_read8_wordram_1M_b0: @ 0x0c0000 - 0x0dffff (same as our offset :)
1379 m_s68k_read8_backup: @ 0xfe0000 - 0xfe3fff (repeated?)
1380 @ must not trash r3 and r12
1381 ldr r1, =(Pico+0x22200)
1384 bic r0, r0, #0xff0000
1385 bic r0, r0, #0x00e000
1386 add r1, r1, #0x110000
1387 add r1, r1, #0x000200
1393 @ must not trash r3 and r12
1394 ldr r1, =(Pico+0x22200)
1395 bic r0, r0, #0xff0000
1396 @ bic r0, r0, #0x008000
1399 orr r2, r2, #0x002200
1401 bge m_s68k_read8_pcm_ram
1405 orr r2, r2, #(0x48+8) @ pcm.ch + addr_offset
1408 ldr r1, [r1, r2, lsl #2]
1410 moveq r0, r1, lsr #PCM_STEP_SHIFT
1411 movne r0, r1, lsr #(PCM_STEP_SHIFT+8)
1415 m_s68k_read8_pcm_ram:
1418 add r1, r1, #0x100000 @ pcm_ram
1419 and r2, r2, #0x0f000000 @ bank
1420 add r1, r1, r2, lsr #12
1421 bic r0, r0, #0x00e000
1428 bic r0, r0, #0xff0000
1429 bic r0, r0, #0x008000
1434 cmp r2, #(0x30-0x0e)
1435 blo m_s68k_read8_comm
1438 ldrlo r2, =gfx_cd_read
1439 ldrhs r2, =s68k_reg_read16
1446 moveq r0, r0, lsr #8
1451 ldr r1, =(Pico+0x22200)
1453 add r1, r1, #0x110000
1458 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1461 .macro m_s68k_read16_ram map_addr
1462 ldr r1, =(Pico+0x22200)
1466 add r0, r0, #\map_addr @ map to our address
1472 .macro m_s68k_read16_wordram_2M_decode map_addr
1473 ldr r2, =(Pico+0x22200)
1476 mov r0, r0, lsr #1 @ +4-6 <<16
1477 add r2, r2, #\map_addr @ map to our address
1479 orr r0, r0, r0, lsl #4
1485 m_s68k_read16_prg: @ 0x000000 - 0x07ffff
1486 m_s68k_read16_wordram_2M: @ 0x080000 - 0x0bffff
1487 m_s68k_read16_wordram_1M_b1: @ 0x0c0000 - 0x0dffff, maps to 0x0e0000
1488 m_s68k_read16_ram 0x020000
1491 m_s68k_read16_wordram_2M_decode_b0: @ 0x080000 - 0x0bffff
1492 m_s68k_read16_wordram_2M_decode 0x080000
1495 m_s68k_read16_wordram_2M_decode_b1: @ 0x080000 - 0x0bffff
1496 m_s68k_read16_wordram_2M_decode 0x0a0000
1499 m_s68k_read16_wordram_1M_b0: @ 0x0c0000 - 0x0dffff (same as our offset :)
1503 @ m_s68k_read16_backup: @ 0xfe0000 - 0xfe3fff (repeated?)
1504 @ bram is not meant to be accessed by words, does any game do this?
1505 .equiv m_s68k_read16_backup, m_s68k_read8_backup
1508 @ m_s68k_read16_pcm:
1509 @ pcm is on 8-bit bus, would this be same as byte access?
1510 .equiv m_s68k_read16_pcm, m_s68k_read8_pcm
1514 bic r0, r0, #0xff0000
1515 bic r0, r0, #0x008000
1516 bic r0, r0, #0x000001
1529 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1532 .macro m_s68k_read32_ram map_addr
1533 ldr r1, =(Pico+0x22200)
1537 add r0, r0, #\map_addr @ map to our address
1543 .macro m_s68k_read32_wordram_2M_decode map_addr
1544 ldr r2, =(Pico+0x22200)
1547 mov r0, r0, lsr #1 @ +4-6 <<16
1548 add r2, r2, #\map_addr @ map to our address
1551 ldrneb r0, [r2, #-1]
1553 orr r1, r1, r1, lsl #4
1555 orr r0, r0, r0, lsl #4
1557 orr r0, r0, r1, lsl #16
1562 m_s68k_read32_prg: @ 0x000000 - 0x07ffff
1563 m_s68k_read32_wordram_2M: @ 0x080000 - 0x0bffff
1564 m_s68k_read32_wordram_1M_b1: @ 0x0c0000 - 0x0dffff, maps to 0x0e0000
1565 m_s68k_read32_ram 0x020000
1568 m_s68k_read32_wordram_2M_decode_b0: @ 0x080000 - 0x0bffff
1569 m_s68k_read32_wordram_2M_decode 0x080000
1572 m_s68k_read32_wordram_2M_decode_b1: @ 0x080000 - 0x0bffff
1573 m_s68k_read32_wordram_2M_decode 0x0a0000
1576 m_s68k_read32_wordram_1M_b0: @ 0x0c0000 - 0x0dffff (same as our offset :)
1580 m_s68k_read32_backup: @ 0xfe0000 - 0xfe3fff (repeated?)
1581 @ bram is not meant to be accessed by words, does any game do this?
1584 bl m_s68k_read8_backup @ must preserve r3 and r12
1588 bl m_s68k_read8_backup
1589 orr r0, r0, r3, lsl #16
1596 bl m_s68k_read8_pcm @ must preserve r3 and r12
1601 orr r0, r0, r3, lsl #16
1606 bic r0, r0, #0xff0000
1607 bic r0, r0, #0x008000
1608 bic r0, r0, #0x000001
1615 blo m_s68k_read32_regs_gfx
1621 orr r0, r0, r1, lsl #16
1625 m_s68k_read32_regs_gfx:
1631 orr r0, r0, r1, lsl #16
1636 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1639 .macro m_s68k_write8_ram map_addr
1640 ldr r2, =(Pico+0x22200)
1644 add r0, r0, #\map_addr @ map to our address
1650 .macro m_s68k_write8_2M_decode map_addr
1651 ldr r2, =(Pico+0x22200)
1654 movs r0, r0, lsr #1 @ +4-6 <<16
1655 add r2, r2, #\map_addr @ map to our address
1658 .macro m_s68k_write8_2M_decode_m0 map_addr @ mode off
1659 m_s68k_write8_2M_decode \map_addr
1662 movcc r1, r1, lsl #4
1666 cmp r0, r3 @ avoid writing if result is same
1671 .macro m_s68k_write8_2M_decode_m1 map_addr @ mode underwrite
1674 m_s68k_write8_2M_decode \map_addr
1676 movcc r1, r1, lsl #4
1687 .macro m_s68k_write8_2M_decode_m2 map_addr @ mode overwrite
1690 m_s68k_write8_2M_decode_m0 \map_addr @ same as in off mode
1695 m_s68k_write8_prg: @ 0x000000 - 0x07ffff
1696 ldr r2, =(Pico+0x22200)
1699 add r3, r0, #0x020000 @ map to our address
1700 add r12,r2, #0x110000
1702 and r12,r12,#0x00ff0000 @ wp
1708 m_s68k_write8_wordram_2M: @ 0x080000 - 0x0bffff
1709 m_s68k_write8_wordram_1M_b1: @ 0x0c0000 - 0x0dffff, maps to 0x0e0000
1710 m_s68k_write8_ram 0x020000
1713 m_s68k_write8_2M_decode_b0_m0: @ 0x080000 - 0x0bffff
1714 m_s68k_write8_2M_decode_m0 0x080000
1716 m_s68k_write8_2M_decode_b0_m1:
1717 m_s68k_write8_2M_decode_m1 0x080000
1719 m_s68k_write8_2M_decode_b0_m2:
1720 m_s68k_write8_2M_decode_m2 0x080000
1722 m_s68k_write8_2M_decode_b1_m0:
1723 m_s68k_write8_2M_decode_m0 0x0a0000
1725 m_s68k_write8_2M_decode_b1_m1:
1726 m_s68k_write8_2M_decode_m1 0x0a0000
1728 m_s68k_write8_2M_decode_b1_m2:
1729 m_s68k_write8_2M_decode_m2 0x0a0000
1732 m_s68k_write8_wordram_1M_b0: @ 0x0c0000 - 0x0dffff (same as our offset :)
1736 m_s68k_write8_backup: @ 0xfe0000 - 0xfe3fff (repeated?)
1737 @ must not trash r3 and r12
1738 ldr r2, =(Pico+0x22200)
1741 bic r0, r0, #0xff0000
1742 bic r0, r0, #0x00e000
1743 add r2, r2, #0x110000
1744 add r2, r2, #0x000200
1748 strb r0, [r1, #0x0e] @ SRam.changed = 1
1753 bic r0, r0, #0xff0000
1755 movlt r0, r0, lsr #1
1761 m_s68k_write8_pcm_ram:
1762 ldr r3, =(Pico+0x22200)
1763 bic r0, r0, #0x00e000
1766 add r2, r3, #0x110000
1767 add r2, r2, #0x002200
1768 add r2, r2, #0x000040
1770 add r3, r3, #0x100000 @ pcm_ram
1771 and r2, r2, #0x0f000000 @ bank
1772 add r3, r3, r2, lsr #12
1778 bic r0, r0, #0xff0000
1779 bic r0, r0, #0x008000
1787 orr r1, r1, r1, lsl #8
1791 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1794 .macro m_s68k_write16_ram map_addr
1795 ldr r2, =(Pico+0x22200)
1799 add r0, r0, #\map_addr @ map to our address
1805 .macro m_s68k_write16_2M_decode map_addr
1806 ldr r2, =(Pico+0x22200)
1809 mov r0, r0, lsr #1 @ +4-6 <<16
1810 add r2, r2, #\map_addr @ map to our address
1813 .macro m_s68k_write16_2M_decode_m0 map_addr @ mode off
1814 m_s68k_write16_2M_decode \map_addr
1816 orr r1, r1, r1, lsr #4
1821 .macro m_s68k_write16_2M_decode_m1 map_addr @ mode underwrite
1822 bics r1, r1, #0xf000
1823 bicnes r1, r1, #0x00f0
1825 orr r1, r1, r1, lsr #4
1826 m_s68k_write16_2M_decode \map_addr
1838 .macro m_s68k_write16_2M_decode_m2 map_addr @ mode overwrite
1839 bics r1, r1, #0xf000
1840 bicnes r1, r1, #0x00f0
1842 orr r1, r1, r1, lsr #4
1843 m_s68k_write16_2M_decode \map_addr
1857 m_s68k_write16_prg: @ 0x000000 - 0x07ffff
1858 ldr r2, =(Pico+0x22200)
1861 add r3, r0, #0x020000 @ map to our address
1862 add r12,r2, #0x110000
1864 and r12,r12,#0x00ff0000 @ wp
1870 m_s68k_write16_wordram_2M: @ 0x080000 - 0x0bffff
1871 m_s68k_write16_wordram_1M_b1: @ 0x0c0000 - 0x0dffff, maps to 0x0e0000
1872 m_s68k_write16_ram 0x020000
1875 m_s68k_write16_2M_decode_b0_m0: @ 0x080000 - 0x0bffff
1876 m_s68k_write16_2M_decode_m0 0x080000
1878 m_s68k_write16_2M_decode_b0_m1:
1879 m_s68k_write16_2M_decode_m1 0x080000
1881 m_s68k_write16_2M_decode_b0_m2:
1882 m_s68k_write16_2M_decode_m2 0x080000
1884 m_s68k_write16_2M_decode_b1_m0:
1885 m_s68k_write16_2M_decode_m0 0x0a0000
1887 m_s68k_write16_2M_decode_b1_m1:
1888 m_s68k_write16_2M_decode_m1 0x0a0000
1890 m_s68k_write16_2M_decode_b1_m2:
1891 m_s68k_write16_2M_decode_m2 0x0a0000
1894 m_s68k_write16_wordram_1M_b0: @ 0x0c0000 - 0x0dffff (same as our offset :)
1895 m_s68k_write16_ram 0
1898 @ m_s68k_write16_backup:
1899 .equiv m_s68k_write16_backup, m_s68k_write8_backup
1902 @ m_s68k_write16_pcm:
1903 .equiv m_s68k_write16_pcm, m_s68k_write8_pcm
1906 m_s68k_write16_regs:
1907 bic r0, r0, #0xff0000
1908 bic r0, r0, #0x008000
1914 beq m_s68k_write16_regs_spec
1920 stmfd sp!,{r2,r3,lr}
1923 ldmfd sp!,{r0,r1,lr}
1926 m_s68k_write16_regs_spec: @ special case
1927 ldr r2, =(Pico+0x22200)
1930 add r0, r0, #0x00000f
1931 strb r1, [r2, r0] @ if (a == 0xe) s68k_regs[0xf] = d;
1935 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1938 .macro m_s68k_write32_ram map_addr
1939 ldr r2, =(Pico+0x22200)
1943 add r0, r0, #\map_addr @ map to our address
1949 .macro m_s68k_write32_2M_decode map_addr
1950 ldr r2, =(Pico+0x22200)
1953 mov r0, r0, lsr #1 @ +4-6 <<16
1954 add r2, r2, #\map_addr @ map to our address
1957 .macro m_s68k_write32_2M_decode_m0 map_addr @ mode off
1958 m_s68k_write32_2M_decode \map_addr
1959 bic r1, r1, #0x000000f0
1960 bic r1, r1, #0x00f00000
1961 orr r1, r1, r1, lsr #4
1965 strneb r1, [r2, #-1]
1970 .macro m_s68k_write32_2M_decode_m1 map_addr @ mode underwrite
1971 bics r1, r1, #0x000000f0
1972 bicnes r1, r1, #0x0000f000
1973 bicnes r1, r1, #0x00f00000
1974 bicnes r1, r1, #0xf0000000
1976 orr r1, r1, r1, lsr #4
1977 m_s68k_write32_2M_decode \map_addr
1980 ldrneb r0, [r2, #-1]
1982 and r12,r1, #0x0000000f
1983 orr r0, r0, r3, lsl #16
1984 orrne r0, r0, #0x80000000 @ remember addr lsb bit
1988 andeq r12,r1, #0x000000f0
1991 andeq r12,r1, #0x000f0000
1994 andeq r12,r1, #0x00f00000
1997 strneb r0, [r2, #-1]
2004 .macro m_s68k_write32_2M_decode_m2 map_addr @ mode overwrite
2005 bics r1, r1, #0x000000f0
2006 bicnes r1, r1, #0x0000f000
2007 bicnes r1, r1, #0x00f00000
2008 bicnes r1, r1, #0xf0000000
2010 orr r1, r1, r1, lsr #4
2011 m_s68k_write32_2M_decode \map_addr
2014 ldrneb r0, [r2, #-1]
2016 orrne r1, r1, #0x80000000 @ remember addr lsb bit
2017 orr r0, r0, r3, lsl #16
2019 andeq r12,r0, #0x0000000f
2022 andeq r12,r0, #0x000000f0
2025 andeq r12,r0, #0x000f0000
2028 andeq r12,r0, #0x00f00000
2033 strneb r1, [r2, #-1]
2042 m_s68k_write32_prg: @ 0x000000 - 0x07ffff
2043 ldr r2, =(Pico+0x22200)
2046 add r3, r0, #0x020000 @ map to our address
2047 add r12,r2, #0x110000
2049 and r12,r12,#0x00ff0000 @ wp
2058 m_s68k_write32_wordram_2M: @ 0x080000 - 0x0bffff
2059 m_s68k_write32_wordram_1M_b1: @ 0x0c0000 - 0x0dffff, maps to 0x0e0000
2060 m_s68k_write32_ram 0x020000
2063 m_s68k_write32_2M_decode_b0_m0: @ 0x080000 - 0x0bffff
2064 m_s68k_write32_2M_decode_m0 0x080000
2066 m_s68k_write32_2M_decode_b0_m1:
2067 m_s68k_write32_2M_decode_m1 0x080000
2069 m_s68k_write32_2M_decode_b0_m2:
2070 m_s68k_write32_2M_decode_m2 0x080000
2072 m_s68k_write32_2M_decode_b1_m0:
2073 m_s68k_write32_2M_decode_m0 0x0a0000
2075 m_s68k_write32_2M_decode_b1_m1:
2076 m_s68k_write32_2M_decode_m1 0x0a0000
2078 m_s68k_write32_2M_decode_b1_m2:
2079 m_s68k_write32_2M_decode_m2 0x0a0000
2082 m_s68k_write32_wordram_1M_b0: @ 0x0c0000 - 0x0dffff (same as our offset :)
2083 m_s68k_write32_ram 0
2086 m_s68k_write32_backup:
2091 bl m_s68k_write8_backup @ must preserve r3 and r12
2095 b m_s68k_write8_backup
2099 bic r0, r0, #0xff0000
2101 blt m_s68k_write32_pcm_reg
2106 m_s68k_write32_pcm_ram:
2107 ldr r3, =(Pico+0x22200)
2108 bic r0, r0, #0x00e000
2111 add r2, r3, #0x110000
2112 add r2, r2, #0x002200
2113 add r2, r2, #0x000040
2115 add r3, r3, #0x100000 @ pcm_ram
2116 and r2, r2, #0x0f000000 @ bank
2117 add r3, r3, r2, lsr #12
2124 m_s68k_write32_pcm_reg:
2128 stmfd sp!,{r2,r3,lr}
2131 ldmfd sp!,{r0,r1,lr}
2135 m_s68k_write32_regs:
2136 bic r0, r0, #0xff0000
2137 bic r0, r0, #0x008000
2144 blo m_s68k_write32_regs_gfx
2146 stmfd sp!,{r0,r1,lr}
2159 ldmfd sp!,{r0,r1,lr}
2163 m_s68k_write32_regs_gfx:
2166 stmfd sp!,{r2,r3,lr}
2169 ldmfd sp!,{r0,r1,lr}