3 * Copyright (C) 2006 Exophase <exophase@gmail.com>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
23 #include "arm_codegen.h"
25 u32 arm_update_gba_arm(u32 pc);
26 u32 arm_update_gba_thumb(u32 pc);
27 u32 arm_update_gba_idle_arm(u32 pc);
28 u32 arm_update_gba_idle_thumb(u32 pc);
30 // Although these are defined as a function, don't call them as
31 // such (jump to it instead)
32 void arm_indirect_branch_arm(u32 address);
33 void arm_indirect_branch_thumb(u32 address);
34 void arm_indirect_branch_dual_arm(u32 address);
35 void arm_indirect_branch_dual_thumb(u32 address);
37 void execute_store_cpsr(u32 new_cpsr, u32 store_mask, u32 address);
38 u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address);
39 void execute_store_spsr(u32 new_cpsr, u32 store_mask);
40 u32 execute_read_spsr();
41 u32 execute_spsr_restore(u32 address);
43 void execute_swi_arm(u32 pc);
44 void execute_swi_thumb(u32 pc);
46 void function_cc execute_store_u32_safe(u32 address, u32 source);
48 void step_debug_arm(u32 pc);
51 #define write32(value) \
52 *((u32 *)translation_ptr) = value; \
53 translation_ptr += 4 \
55 #define arm_relative_offset(source, offset) \
56 (((((u32)offset - (u32)source) - 8) >> 2) & 0xFFFFFF) \
59 // reg_base_offset is the amount of bytes after reg_base where the registers
62 #define reg_base_offset 1024
65 #define reg_a0 ARMREG_R0
66 #define reg_a1 ARMREG_R1
67 #define reg_a2 ARMREG_R2
69 #define reg_s0 ARMREG_R9
70 #define reg_base ARMREG_SP
71 #define reg_flags ARMREG_R11
73 #define reg_cycles ARMREG_R12
75 #define reg_rv ARMREG_R0
77 #define reg_rm ARMREG_R0
78 #define reg_rn ARMREG_R1
79 #define reg_rs ARMREG_R14
80 #define reg_rd ARMREG_R0
83 // Register allocation layout for ARM and Thumb:
84 // Map from a GBA register to a host ARM register. -1 means load it
85 // from memory into one of the temp registers.
87 // The following registers are chosen based on statistical analysis
88 // of a few games (see below), but might not be the best ones. Results
89 // vary tremendously between ARM and Thumb (for obvious reasons), so
90 // two sets are used. Take care to not call any function which can
91 // overwrite any of these registers from the dynarec - only call
92 // trusted functions in arm_stub.S which know how to save/restore
93 // them and know how to transfer them to the C functions it calls
96 // The following define the actual registers available for allocation.
97 // As registers are freed up add them to this list.
99 // Note that r15 is linked to the a0 temp reg - this register will
100 // be preloaded with a constant upon read, and used to link to
101 // indirect branch functions upon write.
103 #define reg_x0 ARMREG_R3
104 #define reg_x1 ARMREG_R4
105 #define reg_x2 ARMREG_R5
106 #define reg_x3 ARMREG_R6
107 #define reg_x4 ARMREG_R7
108 #define reg_x5 ARMREG_R8
114 ARM register usage (38.775138% ARM instructions):
115 r00: 18.263814% (-- 18.263814%)
116 r12: 11.531477% (-- 29.795291%)
117 r09: 11.500162% (-- 41.295453%)
118 r14: 9.063440% (-- 50.358893%)
119 r06: 7.837682% (-- 58.196574%)
120 r01: 7.401049% (-- 65.597623%)
121 r07: 6.778340% (-- 72.375963%)
122 r05: 5.445009% (-- 77.820973%)
123 r02: 5.427288% (-- 83.248260%)
124 r03: 5.293743% (-- 88.542003%)
125 r04: 3.601103% (-- 92.143106%)
126 r11: 3.207311% (-- 95.350417%)
127 r10: 2.334864% (-- 97.685281%)
128 r08: 1.708207% (-- 99.393488%)
129 r15: 0.311270% (-- 99.704757%)
130 r13: 0.295243% (-- 100.000000%)
132 Thumb register usage (61.224862% Thumb instructions):
133 r00: 34.788858% (-- 34.788858%)
134 r01: 26.564083% (-- 61.352941%)
135 r03: 10.983500% (-- 72.336441%)
136 r02: 8.303127% (-- 80.639567%)
137 r04: 4.900381% (-- 85.539948%)
138 r05: 3.941292% (-- 89.481240%)
139 r06: 3.257582% (-- 92.738822%)
140 r07: 2.644851% (-- 95.383673%)
141 r13: 1.408824% (-- 96.792497%)
142 r08: 0.906433% (-- 97.698930%)
143 r09: 0.679693% (-- 98.378623%)
144 r10: 0.656446% (-- 99.035069%)
145 r12: 0.453668% (-- 99.488737%)
146 r14: 0.248909% (-- 99.737646%)
147 r11: 0.171066% (-- 99.908713%)
148 r15: 0.091287% (-- 100.000000%)
152 s32 arm_register_allocation[] =
189 s32 thumb_register_allocation[] =
228 #define arm_imm_lsl_to_rot(value) \
232 u32 arm_disect_imm_32bit(u32 imm, u32 *stores, u32 *rotations)
238 // Otherwise it'll return 0 things to store because it'll never
247 // Find chunks of non-zero data at 2 bit alignments.
250 for(; left_shift < 32; left_shift += 2)
252 if((imm >> left_shift) & 0x03)
258 // We've hit the end of the useful data.
262 // Hit the end, it might wrap back around to the beginning.
265 // Make a mask for the residual bits. IE, if we have
266 // 5 bits of data at the end we can wrap around to 3
267 // bits of data in the beginning. Thus the first
268 // thing, after being shifted left, has to be less
269 // than 111b, 0x7, or (1 << 3) - 1.
270 u32 top_bits = 32 - left_shift;
271 u32 residual_bits = 8 - top_bits;
272 u32 residual_mask = (1 << residual_bits) - 1;
274 if((store_count > 1) && (left_shift > 24) &&
275 ((stores[0] << ((32 - rotations[0]) & 0x1F)) < residual_mask))
277 // Then we can throw out the last bit and tack it on
279 u32 initial_bits = rotations[0];
281 (stores[0] << ((top_bits + (32 - rotations[0])) & 0x1F)) |
282 ((imm >> left_shift) & 0xFF);
283 rotations[0] = top_bits;
289 // There's nothing to wrap over to in the beginning
290 stores[store_count] = (imm >> left_shift) & 0xFF;
291 rotations[store_count] = (32 - left_shift) & 0x1F;
292 return store_count + 1;
297 stores[store_count] = (imm >> left_shift) & 0xFF;
298 rotations[store_count] = (32 - left_shift) & 0x1F;
305 #define arm_load_imm_32bit(ireg, imm) \
309 u32 store_count = arm_disect_imm_32bit(imm, stores, rotations); \
312 ARM_MOV_REG_IMM(0, ireg, stores[0], rotations[0]); \
314 for(i = 1; i < store_count; i++) \
316 ARM_ORR_REG_IMM(0, ireg, ireg, stores[i], rotations[i]); \
321 #define generate_load_pc(ireg, new_pc) \
322 arm_load_imm_32bit(ireg, new_pc) \
324 #define generate_load_imm(ireg, imm, imm_ror) \
325 ARM_MOV_REG_IMM(0, ireg, imm, imm_ror) \
329 #define generate_shift_left(ireg, imm) \
330 ARM_MOV_REG_IMMSHIFT(0, ireg, ireg, ARMSHIFT_LSL, imm) \
332 #define generate_shift_right(ireg, imm) \
333 ARM_MOV_REG_IMMSHIFT(0, ireg, ireg, ARMSHIFT_LSR, imm) \
335 #define generate_shift_right_arithmetic(ireg, imm) \
336 ARM_MOV_REG_IMMSHIFT(0, ireg, ireg, ARMSHIFT_ASR, imm) \
338 #define generate_rotate_right(ireg, imm) \
339 ARM_MOV_REG_IMMSHIFT(0, ireg, ireg, ARMSHIFT_ROR, imm) \
341 #define generate_add(ireg_dest, ireg_src) \
342 ARM_ADD_REG_REG(0, ireg_dest, ireg_dest, ireg_src) \
344 #define generate_sub(ireg_dest, ireg_src) \
345 ARM_SUB_REG_REG(0, ireg_dest, ireg_dest, ireg_src) \
347 #define generate_or(ireg_dest, ireg_src) \
348 ARM_ORR_REG_REG(0, ireg_dest, ireg_dest, ireg_src) \
350 #define generate_xor(ireg_dest, ireg_src) \
351 ARM_EOR_REG_REG(0, ireg_dest, ireg_dest, ireg_src) \
353 #define generate_add_imm(ireg, imm, imm_ror) \
354 ARM_ADD_REG_IMM(0, ireg, ireg, imm, imm_ror) \
356 #define generate_sub_imm(ireg, imm, imm_ror) \
357 ARM_SUB_REG_IMM(0, ireg, ireg, imm, imm_ror) \
359 #define generate_xor_imm(ireg, imm, imm_ror) \
360 ARM_EOR_REG_IMM(0, ireg, ireg, imm, imm_ror) \
362 #define generate_add_reg_reg_imm(ireg_dest, ireg_src, imm, imm_ror) \
363 ARM_ADD_REG_IMM(0, ireg_dest, ireg_src, imm, imm_ror) \
365 #define generate_and_imm(ireg, imm, imm_ror) \
366 ARM_AND_REG_IMM(0, ireg, ireg, imm, imm_ror) \
368 #define generate_mov(ireg_dest, ireg_src) \
369 if(ireg_dest != ireg_src) \
371 ARM_MOV_REG_REG(0, ireg_dest, ireg_src); \
374 #define generate_function_call(function_location) \
375 ARM_BL(0, arm_relative_offset(translation_ptr, function_location)) \
377 #define generate_exit_block() \
378 ARM_BX(0, ARMREG_LR) \
380 // The branch target is to be filled in later (thus a 0 for now)
382 #define generate_branch_filler(condition_code, writeback_location) \
383 (writeback_location) = translation_ptr; \
384 ARM_B_COND(0, condition_code, 0) \
386 #define generate_update_pc(new_pc) \
387 generate_load_pc(reg_a0, new_pc) \
389 #define generate_cycle_update() \
392 if(cycle_count >> 8) \
394 ARM_ADD_REG_IMM(0, reg_cycles, reg_cycles, (cycle_count >> 8) & 0xFF, \
395 arm_imm_lsl_to_rot(8)); \
397 ARM_ADD_REG_IMM(0, reg_cycles, reg_cycles, (cycle_count & 0xFF), 0); \
401 #define generate_cycle_update_flag_set() \
402 if(cycle_count >> 8) \
404 ARM_ADD_REG_IMM(0, reg_cycles, reg_cycles, (cycle_count >> 8) & 0xFF, \
405 arm_imm_lsl_to_rot(8)); \
407 generate_save_flags(); \
408 ARM_ADDS_REG_IMM(0, reg_cycles, reg_cycles, (cycle_count & 0xFF), 0); \
411 #define generate_branch_patch_conditional(dest, offset) \
412 *((u32 *)(dest)) = (*((u32 *)dest) & 0xFF000000) | \
413 arm_relative_offset(dest, offset) \
415 #define generate_branch_patch_unconditional(dest, offset) \
416 *((u32 *)(dest)) = (*((u32 *)dest) & 0xFF000000) | \
417 arm_relative_offset(dest, offset) \
419 // A different function is called for idle updates because of the relative
420 // location of the embedded PC. The idle version could be optimized to put
421 // the CPU into halt mode too, however.
423 #define generate_branch_idle_eliminate(writeback_location, new_pc, mode) \
424 generate_function_call(arm_update_gba_idle_##mode); \
426 generate_branch_filler(ARMCOND_AL, writeback_location) \
428 #define generate_branch_update(writeback_location, new_pc, mode) \
429 ARM_MOV_REG_IMMSHIFT(0, reg_a0, reg_cycles, ARMSHIFT_LSR, 31); \
430 ARM_ADD_REG_IMMSHIFT(0, ARMREG_PC, ARMREG_PC, reg_a0, ARMSHIFT_LSL, 2); \
432 generate_function_call(arm_update_gba_##mode); \
433 generate_branch_filler(ARMCOND_AL, writeback_location) \
436 #define generate_branch_no_cycle_update(writeback_location, new_pc, mode) \
437 if(pc == idle_loop_target_pc) \
439 generate_branch_idle_eliminate(writeback_location, new_pc, mode); \
443 generate_branch_update(writeback_location, new_pc, mode); \
446 #define generate_branch_cycle_update(writeback_location, new_pc, mode) \
447 generate_cycle_update(); \
448 generate_branch_no_cycle_update(writeback_location, new_pc, mode) \
450 // a0 holds the destination
452 #define generate_indirect_branch_no_cycle_update(type) \
453 ARM_B(0, arm_relative_offset(translation_ptr, arm_indirect_branch_##type)) \
455 #define generate_indirect_branch_cycle_update(type) \
456 generate_cycle_update(); \
457 generate_indirect_branch_no_cycle_update(type) \
459 #define generate_block_prologue() \
461 #define generate_block_extra_vars_arm() \
462 void generate_indirect_branch_arm() \
464 if(condition == 0x0E) \
466 generate_cycle_update(); \
468 generate_indirect_branch_no_cycle_update(arm); \
471 void generate_indirect_branch_dual() \
473 if(condition == 0x0E) \
475 generate_cycle_update(); \
477 generate_indirect_branch_no_cycle_update(dual_arm); \
480 u32 prepare_load_reg(u32 scratch_reg, u32 reg_index) \
482 u32 reg_use = arm_register_allocation[reg_index]; \
483 if(reg_use == mem_reg) \
485 ARM_LDR_IMM(0, scratch_reg, reg_base, \
486 (reg_base_offset + (reg_index * 4))); \
487 return scratch_reg; \
493 u32 prepare_load_reg_pc(u32 scratch_reg, u32 reg_index, u32 pc_offset) \
495 if(reg_index == 15) \
497 generate_load_pc(scratch_reg, pc + pc_offset); \
498 return scratch_reg; \
500 return prepare_load_reg(scratch_reg, reg_index); \
503 u32 prepare_store_reg(u32 scratch_reg, u32 reg_index) \
505 u32 reg_use = arm_register_allocation[reg_index]; \
506 if(reg_use == mem_reg) \
507 return scratch_reg; \
512 void complete_store_reg(u32 scratch_reg, u32 reg_index) \
514 if(arm_register_allocation[reg_index] == mem_reg) \
516 ARM_STR_IMM(0, scratch_reg, reg_base, \
517 (reg_base_offset + (reg_index * 4))); \
521 void complete_store_reg_pc_no_flags(u32 scratch_reg, u32 reg_index) \
523 if(reg_index == 15) \
525 generate_indirect_branch_arm(); \
529 complete_store_reg(scratch_reg, reg_index); \
533 void complete_store_reg_pc_flags(u32 scratch_reg, u32 reg_index) \
535 if(reg_index == 15) \
537 if(condition == 0x0E) \
539 generate_cycle_update(); \
541 generate_function_call(execute_spsr_restore); \
545 complete_store_reg(scratch_reg, reg_index); \
549 void generate_load_reg(u32 ireg, u32 reg_index) \
551 s32 load_src = arm_register_allocation[reg_index]; \
552 if(load_src != mem_reg) \
554 ARM_MOV_REG_REG(0, ireg, load_src); \
558 ARM_LDR_IMM(0, ireg, reg_base, (reg_base_offset + (reg_index * 4))); \
562 void generate_store_reg(u32 ireg, u32 reg_index) \
564 s32 store_dest = arm_register_allocation[reg_index]; \
565 if(store_dest != mem_reg) \
567 ARM_MOV_REG_REG(0, store_dest, ireg); \
571 ARM_STR_IMM(0, ireg, reg_base, (reg_base_offset + (reg_index * 4))); \
576 #define generate_block_extra_vars_thumb() \
577 u32 prepare_load_reg(u32 scratch_reg, u32 reg_index) \
579 u32 reg_use = thumb_register_allocation[reg_index]; \
580 if(reg_use == mem_reg) \
582 ARM_LDR_IMM(0, scratch_reg, reg_base, \
583 (reg_base_offset + (reg_index * 4))); \
584 return scratch_reg; \
590 u32 prepare_load_reg_pc(u32 scratch_reg, u32 reg_index, u32 pc_offset) \
592 if(reg_index == 15) \
594 generate_load_pc(scratch_reg, pc + pc_offset); \
595 return scratch_reg; \
597 return prepare_load_reg(scratch_reg, reg_index); \
600 u32 prepare_store_reg(u32 scratch_reg, u32 reg_index) \
602 u32 reg_use = thumb_register_allocation[reg_index]; \
603 if(reg_use == mem_reg) \
604 return scratch_reg; \
609 void complete_store_reg(u32 scratch_reg, u32 reg_index) \
611 if(thumb_register_allocation[reg_index] == mem_reg) \
613 ARM_STR_IMM(0, scratch_reg, reg_base, \
614 (reg_base_offset + (reg_index * 4))); \
618 void generate_load_reg(u32 ireg, u32 reg_index) \
620 s32 load_src = thumb_register_allocation[reg_index]; \
621 if(load_src != mem_reg) \
623 ARM_MOV_REG_REG(0, ireg, load_src); \
627 ARM_LDR_IMM(0, ireg, reg_base, (reg_base_offset + (reg_index * 4))); \
631 void generate_store_reg(u32 ireg, u32 reg_index) \
633 s32 store_dest = thumb_register_allocation[reg_index]; \
634 if(store_dest != mem_reg) \
636 ARM_MOV_REG_REG(0, store_dest, ireg); \
640 ARM_STR_IMM(0, ireg, reg_base, (reg_base_offset + (reg_index * 4))); \
644 #define translate_invalidate_dcache() \
646 invalidate_cache_region(rom_translation_cache, \
647 rom_translation_cache + ROM_TRANSLATION_CACHE_SIZE); \
648 invalidate_cache_region(ram_translation_cache, \
649 ram_translation_cache + RAM_TRANSLATION_CACHE_SIZE); \
650 invalidate_cache_region(bios_translation_cache, \
651 bios_translation_cache + BIOS_TRANSLATION_CACHE_SIZE); \
654 #define block_prologue_size 0
657 // It should be okay to still generate result flags, spsr will overwrite them.
658 // This is pretty infrequent (returning from interrupt handlers, et al) so
659 // probably not worth optimizing for.
661 #define check_for_interrupts() \
662 if((io_registers[REG_IE] & io_registers[REG_IF]) && \
663 io_registers[REG_IME] && ((reg[REG_CPSR] & 0x80) == 0)) \
665 reg_mode[MODE_IRQ][6] = pc + 4; \
666 spsr[MODE_IRQ] = reg[REG_CPSR]; \
667 reg[REG_CPSR] = 0xD2; \
669 set_cpu_mode(MODE_IRQ); \
672 #define generate_load_reg_pc(ireg, reg_index, pc_offset) \
673 if(reg_index == 15) \
675 generate_load_pc(ireg, pc + pc_offset); \
679 generate_load_reg(ireg, reg_index); \
682 #define generate_store_reg_pc_no_flags(ireg, reg_index) \
683 generate_store_reg(ireg, reg_index); \
684 if(reg_index == 15) \
686 generate_indirect_branch_arm(); \
690 u32 function_cc execute_spsr_restore_body(u32 pc)
692 set_cpu_mode(cpu_modes[reg[REG_CPSR] & 0x1F]);
693 check_for_interrupts();
699 #define generate_store_reg_pc_flags(ireg, reg_index) \
700 generate_store_reg(ireg, reg_index); \
701 if(reg_index == 15) \
703 if(condition == 0x0E) \
705 generate_cycle_update(); \
707 generate_function_call(execute_spsr_restore); \
711 #define generate_load_flags() \
712 /* ARM_MSR_REG(0, ARM_PSR_F, reg_flags, ARM_CPSR) */ \
714 #define generate_store_flags() \
715 /* ARM_MRS_CPSR(0, reg_flags) */ \
717 #define generate_save_flags() \
718 ARM_MRS_CPSR(0, reg_flags) \
720 #define generate_restore_flags() \
721 ARM_MSR_REG(0, ARM_PSR_F, reg_flags, ARM_CPSR) \
724 #define condition_opposite_eq ARMCOND_NE
725 #define condition_opposite_ne ARMCOND_EQ
726 #define condition_opposite_cs ARMCOND_CC
727 #define condition_opposite_cc ARMCOND_CS
728 #define condition_opposite_mi ARMCOND_PL
729 #define condition_opposite_pl ARMCOND_MI
730 #define condition_opposite_vs ARMCOND_VC
731 #define condition_opposite_vc ARMCOND_VS
732 #define condition_opposite_hi ARMCOND_LS
733 #define condition_opposite_ls ARMCOND_HI
734 #define condition_opposite_ge ARMCOND_LT
735 #define condition_opposite_lt ARMCOND_GE
736 #define condition_opposite_gt ARMCOND_LE
737 #define condition_opposite_le ARMCOND_GT
738 #define condition_opposite_al ARMCOND_NV
739 #define condition_opposite_nv ARMCOND_AL
741 #define generate_branch(mode) \
743 generate_branch_cycle_update( \
744 block_exits[block_exit_position].branch_source, \
745 block_exits[block_exit_position].branch_target, mode); \
746 block_exit_position++; \
750 #define generate_op_and_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
751 ARM_AND_REG_IMMSHIFT(0, _rd, _rn, _rm, shift_type, shift) \
753 #define generate_op_orr_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
754 ARM_ORR_REG_IMMSHIFT(0, _rd, _rn, _rm, shift_type, shift) \
756 #define generate_op_eor_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
757 ARM_EOR_REG_IMMSHIFT(0, _rd, _rn, _rm, shift_type, shift) \
759 #define generate_op_bic_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
760 ARM_BIC_REG_IMMSHIFT(0, _rd, _rn, _rm, shift_type, shift) \
762 #define generate_op_sub_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
763 ARM_SUB_REG_IMMSHIFT(0, _rd, _rn, _rm, shift_type, shift) \
765 #define generate_op_rsb_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
766 ARM_RSB_REG_IMMSHIFT(0, _rd, _rn, _rm, shift_type, shift) \
768 #define generate_op_sbc_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
769 ARM_SBC_REG_IMMSHIFT(0, _rd, _rn, _rm, shift_type, shift) \
771 #define generate_op_rsc_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
772 ARM_RSC_REG_IMMSHIFT(0, _rd, _rn, _rm, shift_type, shift) \
774 #define generate_op_add_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
775 ARM_ADD_REG_IMMSHIFT(0, _rd, _rn, _rm, shift_type, shift) \
777 #define generate_op_adc_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
778 ARM_ADC_REG_IMMSHIFT(0, _rd, _rn, _rm, shift_type, shift) \
780 #define generate_op_mov_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
781 ARM_MOV_REG_IMMSHIFT(0, _rd, _rm, shift_type, shift) \
783 #define generate_op_mvn_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
784 ARM_MVN_REG_IMMSHIFT(0, _rd, _rm, shift_type, shift) \
787 #define generate_op_and_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
788 ARM_AND_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs) \
790 #define generate_op_orr_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
791 ARM_ORR_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs) \
793 #define generate_op_eor_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
794 ARM_EOR_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs) \
796 #define generate_op_bic_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
797 ARM_BIC_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs) \
799 #define generate_op_sub_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
800 ARM_SUB_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs) \
802 #define generate_op_rsb_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
803 ARM_RSB_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs) \
805 #define generate_op_sbc_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
806 ARM_SBC_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs) \
808 #define generate_op_rsc_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
809 ARM_RSC_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs) \
811 #define generate_op_add_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
812 ARM_ADD_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs) \
814 #define generate_op_adc_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
815 ARM_ADC_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs) \
817 #define generate_op_mov_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
818 ARM_MOV_REG_REGSHIFT(0, _rd, _rm, shift_type, _rs) \
820 #define generate_op_mvn_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
821 ARM_MVN_REG_REGSHIFT(0, _rd, _rm, shift_type, _rs) \
824 #define generate_op_and_imm(_rd, _rn) \
825 ARM_AND_REG_IMM(0, _rd, _rn, imm, imm_ror) \
827 #define generate_op_orr_imm(_rd, _rn) \
828 ARM_ORR_REG_IMM(0, _rd, _rn, imm, imm_ror) \
830 #define generate_op_eor_imm(_rd, _rn) \
831 ARM_EOR_REG_IMM(0, _rd, _rn, imm, imm_ror) \
833 #define generate_op_bic_imm(_rd, _rn) \
834 ARM_BIC_REG_IMM(0, _rd, _rn, imm, imm_ror) \
836 #define generate_op_sub_imm(_rd, _rn) \
837 ARM_SUB_REG_IMM(0, _rd, _rn, imm, imm_ror) \
839 #define generate_op_rsb_imm(_rd, _rn) \
840 ARM_RSB_REG_IMM(0, _rd, _rn, imm, imm_ror) \
842 #define generate_op_sbc_imm(_rd, _rn) \
843 ARM_SBC_REG_IMM(0, _rd, _rn, imm, imm_ror) \
845 #define generate_op_rsc_imm(_rd, _rn) \
846 ARM_RSC_REG_IMM(0, _rd, _rn, imm, imm_ror) \
848 #define generate_op_add_imm(_rd, _rn) \
849 ARM_ADD_REG_IMM(0, _rd, _rn, imm, imm_ror) \
851 #define generate_op_adc_imm(_rd, _rn) \
852 ARM_ADC_REG_IMM(0, _rd, _rn, imm, imm_ror) \
854 #define generate_op_mov_imm(_rd, _rn) \
855 ARM_MOV_REG_IMM(0, _rd, imm, imm_ror) \
857 #define generate_op_mvn_imm(_rd, _rn) \
858 ARM_MVN_REG_IMM(0, _rd, imm, imm_ror) \
861 #define generate_op_reg_immshift_lflags(name, _rd, _rn, _rm, st, shift) \
862 ARM_##name##_REG_IMMSHIFT(0, _rd, _rn, _rm, st, shift) \
864 #define generate_op_reg_immshift_aflags(name, _rd, _rn, _rm, st, shift) \
865 ARM_##name##_REG_IMMSHIFT(0, _rd, _rn, _rm, st, shift) \
867 #define generate_op_reg_immshift_aflags_load_c(name, _rd, _rn, _rm, st, sh) \
868 ARM_##name##_REG_IMMSHIFT(0, _rd, _rn, _rm, st, sh) \
870 #define generate_op_reg_immshift_uflags(name, _rd, _rm, shift_type, shift) \
871 ARM_##name##_REG_IMMSHIFT(0, _rd, _rm, shift_type, shift) \
873 #define generate_op_reg_immshift_tflags(name, _rn, _rm, shift_type, shift) \
874 ARM_##name##_REG_IMMSHIFT(0, _rn, _rm, shift_type, shift) \
877 #define generate_op_reg_regshift_lflags(name, _rd, _rn, _rm, shift_type, _rs) \
878 ARM_##name##_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs) \
880 #define generate_op_reg_regshift_aflags(name, _rd, _rn, _rm, st, _rs) \
881 ARM_##name##_REG_REGSHIFT(0, _rd, _rn, _rm, st, _rs) \
883 #define generate_op_reg_regshift_aflags_load_c(name, _rd, _rn, _rm, st, _rs) \
884 ARM_##name##_REG_REGSHIFT(0, _rd, _rn, _rm, st, _rs) \
886 #define generate_op_reg_regshift_uflags(name, _rd, _rm, shift_type, _rs) \
887 ARM_##name##_REG_REGSHIFT(0, _rd, _rm, shift_type, _rs) \
889 #define generate_op_reg_regshift_tflags(name, _rn, _rm, shift_type, _rs) \
890 ARM_##name##_REG_REGSHIFT(0, _rn, _rm, shift_type, _rs) \
893 #define generate_op_imm_lflags(name, _rd, _rn) \
894 ARM_##name##_REG_IMM(0, _rd, _rn, imm, imm_ror) \
896 #define generate_op_imm_aflags(name, _rd, _rn) \
897 ARM_##name##_REG_IMM(0, _rd, _rn, imm, imm_ror) \
899 #define generate_op_imm_aflags_load_c(name, _rd, _rn) \
900 ARM_##name##_REG_IMM(0, _rd, _rn, imm, imm_ror) \
902 #define generate_op_imm_uflags(name, _rd) \
903 ARM_##name##_REG_IMM(0, _rd, imm, imm_ror) \
905 #define generate_op_imm_tflags(name, _rn) \
906 ARM_##name##_REG_IMM(0, _rn, imm, imm_ror) \
909 #define generate_op_ands_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
910 generate_op_reg_immshift_lflags(ANDS, _rd, _rn, _rm, shift_type, shift) \
912 #define generate_op_orrs_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
913 generate_op_reg_immshift_lflags(ORRS, _rd, _rn, _rm, shift_type, shift) \
915 #define generate_op_eors_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
916 generate_op_reg_immshift_lflags(EORS, _rd, _rn, _rm, shift_type, shift) \
918 #define generate_op_bics_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
919 generate_op_reg_immshift_lflags(BICS, _rd, _rn, _rm, shift_type, shift) \
921 #define generate_op_subs_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
922 generate_op_reg_immshift_aflags(SUBS, _rd, _rn, _rm, shift_type, shift) \
924 #define generate_op_rsbs_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
925 generate_op_reg_immshift_aflags(RSBS, _rd, _rn, _rm, shift_type, shift) \
927 #define generate_op_sbcs_reg_immshift(_rd, _rn, _rm, st, shift) \
928 generate_op_reg_immshift_aflags_load_c(SBCS, _rd, _rn, _rm, st, shift) \
930 #define generate_op_rscs_reg_immshift(_rd, _rn, _rm, st, shift) \
931 generate_op_reg_immshift_aflags_load_c(RSCS, _rd, _rn, _rm, st, shift) \
933 #define generate_op_adds_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
934 generate_op_reg_immshift_aflags(ADDS, _rd, _rn, _rm, shift_type, shift) \
936 #define generate_op_adcs_reg_immshift(_rd, _rn, _rm, st, shift) \
937 generate_op_reg_immshift_aflags_load_c(ADCS, _rd, _rn, _rm, st, shift) \
939 #define generate_op_movs_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
940 generate_op_reg_immshift_uflags(MOVS, _rd, _rm, shift_type, shift) \
942 #define generate_op_mvns_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
943 generate_op_reg_immshift_uflags(MVNS, _rd, _rm, shift_type, shift) \
945 // The reg operand is in reg_rm, not reg_rn like expected, so rsbs isn't
946 // being used here. When rsbs is fully inlined it can be used with the
947 // apropriate operands.
949 #define generate_op_neg_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
951 generate_load_imm(reg_rn, 0, 0); \
952 generate_op_subs_reg_immshift(_rd, reg_rn, _rm, ARMSHIFT_LSL, 0); \
955 #define generate_op_muls_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
956 generate_load_flags(); \
957 ARM_MULS(0, _rd, _rn, _rm); \
958 generate_store_flags() \
960 #define generate_op_cmp_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
961 generate_op_reg_immshift_tflags(CMP, _rn, _rm, shift_type, shift) \
963 #define generate_op_cmn_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
964 generate_op_reg_immshift_tflags(CMN, _rn, _rm, shift_type, shift) \
966 #define generate_op_tst_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
967 generate_op_reg_immshift_tflags(TST, _rn, _rm, shift_type, shift) \
969 #define generate_op_teq_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
970 generate_op_reg_immshift_tflags(TEQ, _rn, _rm, shift_type, shift) \
973 #define generate_op_ands_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
974 generate_op_reg_regshift_lflags(ANDS, _rd, _rn, _rm, shift_type, _rs) \
976 #define generate_op_orrs_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
977 generate_op_reg_regshift_lflags(ORRS, _rd, _rn, _rm, shift_type, _rs) \
979 #define generate_op_eors_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
980 generate_op_reg_regshift_lflags(EORS, _rd, _rn, _rm, shift_type, _rs) \
982 #define generate_op_bics_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
983 generate_op_reg_regshift_lflags(BICS, _rd, _rn, _rm, shift_type, _rs) \
985 #define generate_op_subs_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
986 generate_op_reg_regshift_aflags(SUBS, _rd, _rn, _rm, shift_type, _rs) \
988 #define generate_op_rsbs_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
989 generate_op_reg_regshift_aflags(RSBS, _rd, _rn, _rm, shift_type, _rs) \
991 #define generate_op_sbcs_reg_regshift(_rd, _rn, _rm, st, _rs) \
992 generate_op_reg_regshift_aflags_load_c(SBCS, _rd, _rn, _rm, st, _rs) \
994 #define generate_op_rscs_reg_regshift(_rd, _rn, _rm, st, _rs) \
995 generate_op_reg_regshift_aflags_load_c(RSCS, _rd, _rn, _rm, st, _rs) \
997 #define generate_op_adds_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
998 generate_op_reg_regshift_aflags(ADDS, _rd, _rn, _rm, shift_type, _rs) \
1000 #define generate_op_adcs_reg_regshift(_rd, _rn, _rm, st, _rs) \
1001 generate_op_reg_regshift_aflags_load_c(ADCS, _rd, _rn, _rm, st, _rs) \
1003 #define generate_op_movs_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
1004 generate_op_reg_regshift_uflags(MOVS, _rd, _rm, shift_type, _rs) \
1006 #define generate_op_mvns_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
1007 generate_op_reg_regshift_uflags(MVNS, _rd, _rm, shift_type, _rs) \
1009 #define generate_op_cmp_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
1010 generate_op_reg_regshift_tflags(CMP, _rn, _rm, shift_type, _rs) \
1012 #define generate_op_cmn_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
1013 generate_op_reg_regshift_tflags(CMN, _rn, _rm, shift_type, _rs) \
1015 #define generate_op_tst_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
1016 generate_op_reg_regshift_tflags(TST, _rn, _rm, shift_type, _rs) \
1018 #define generate_op_teq_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
1019 generate_op_reg_regshift_tflags(TEQ, _rn, _rm, shift_type, _rs) \
1022 #define generate_op_ands_imm(_rd, _rn) \
1023 generate_op_imm_lflags(ANDS, _rd, _rn) \
1025 #define generate_op_orrs_imm(_rd, _rn) \
1026 generate_op_imm_lflags(ORRS, _rd, _rn) \
1028 #define generate_op_eors_imm(_rd, _rn) \
1029 generate_op_imm_lflags(EORS, _rd, _rn) \
1031 #define generate_op_bics_imm(_rd, _rn) \
1032 generate_op_imm_lflags(BICS, _rd, _rn) \
1034 #define generate_op_subs_imm(_rd, _rn) \
1035 generate_op_imm_aflags(SUBS, _rd, _rn) \
1037 #define generate_op_rsbs_imm(_rd, _rn) \
1038 generate_op_imm_aflags(RSBS, _rd, _rn) \
1040 #define generate_op_sbcs_imm(_rd, _rn) \
1041 generate_op_imm_aflags_load_c(SBCS, _rd, _rn) \
1043 #define generate_op_rscs_imm(_rd, _rn) \
1044 generate_op_imm_aflags_load_c(RSCS, _rd, _rn) \
1046 #define generate_op_adds_imm(_rd, _rn) \
1047 generate_op_imm_aflags(ADDS, _rd, _rn) \
1049 #define generate_op_adcs_imm(_rd, _rn) \
1050 generate_op_imm_aflags_load_c(ADCS, _rd, _rn) \
1052 #define generate_op_movs_imm(_rd, _rn) \
1053 generate_op_imm_uflags(MOVS, _rd) \
1055 #define generate_op_mvns_imm(_rd, _rn) \
1056 generate_op_imm_uflags(MVNS, _rd) \
1058 #define generate_op_cmp_imm(_rd, _rn) \
1059 generate_op_imm_tflags(CMP, _rn) \
1061 #define generate_op_cmn_imm(_rd, _rn) \
1062 generate_op_imm_tflags(CMN, _rn) \
1064 #define generate_op_tst_imm(_rd, _rn) \
1065 generate_op_imm_tflags(TST, _rn) \
1067 #define generate_op_teq_imm(_rd, _rn) \
1068 generate_op_imm_tflags(TEQ, _rn) \
1071 #define prepare_load_rn_yes() \
1072 u32 _rn = prepare_load_reg_pc(reg_rn, rn, 8) \
1074 #define prepare_load_rn_no() \
1076 #define prepare_store_rd_yes() \
1077 u32 _rd = prepare_store_reg(reg_rd, rd) \
1079 #define prepare_store_rd_no() \
1081 #define complete_store_rd_yes(flags_op) \
1082 complete_store_reg_pc_##flags_op(_rd, rd) \
1084 #define complete_store_rd_no(flags_op) \
1086 #define arm_generate_op_reg(name, load_op, store_op, flags_op) \
1087 u32 shift_type = (opcode >> 5) & 0x03; \
1088 arm_decode_data_proc_reg(); \
1089 prepare_load_rn_##load_op(); \
1090 prepare_store_rd_##store_op(); \
1092 if((opcode >> 4) & 0x01) \
1094 u32 rs = ((opcode >> 8) & 0x0F); \
1095 u32 _rs = prepare_load_reg(reg_rs, rs); \
1096 u32 _rm = prepare_load_reg_pc(reg_rm, rm, 12); \
1097 generate_op_##name##_reg_regshift(_rd, _rn, _rm, shift_type, _rs); \
1101 u32 shift_imm = ((opcode >> 7) & 0x1F); \
1102 u32 _rm = prepare_load_reg_pc(reg_rm, rm, 8); \
1103 generate_op_##name##_reg_immshift(_rd, _rn, _rm, shift_type, shift_imm); \
1105 complete_store_rd_##store_op(flags_op) \
1107 #define arm_generate_op_reg_flags(name, load_op, store_op, flags_op) \
1108 arm_generate_op_reg(name, load_op, store_op, flags_op) \
1110 // imm will be loaded by the called function if necessary.
1112 #define arm_generate_op_imm(name, load_op, store_op, flags_op) \
1113 arm_decode_data_proc_imm(); \
1114 prepare_load_rn_##load_op(); \
1115 prepare_store_rd_##store_op(); \
1116 generate_op_##name##_imm(_rd, _rn); \
1117 complete_store_rd_##store_op(flags_op) \
1119 #define arm_generate_op_imm_flags(name, load_op, store_op, flags_op) \
1120 arm_generate_op_imm(name, load_op, store_op, flags_op) \
1122 #define arm_data_proc(name, type, flags_op) \
1124 arm_generate_op_##type(name, yes, yes, flags_op); \
1127 #define arm_data_proc_test(name, type) \
1129 arm_generate_op_##type(name, yes, no, no); \
1132 #define arm_data_proc_unary(name, type, flags_op) \
1134 arm_generate_op_##type(name, no, yes, flags_op); \
1138 #define arm_multiply_add_no_flags_no() \
1139 ARM_MUL(0, _rd, _rm, _rs) \
1141 #define arm_multiply_add_yes_flags_no() \
1142 u32 _rn = prepare_load_reg(reg_a2, rn); \
1143 ARM_MLA(0, _rd, _rm, _rs, _rn) \
1145 #define arm_multiply_add_no_flags_yes() \
1146 generate_load_flags(); \
1147 ARM_MULS(0, reg_a0, reg_a0, reg_a1) \
1148 generate_store_flags() \
1150 #define arm_multiply_add_yes_flags_yes() \
1151 u32 _rn = prepare_load_reg(reg_a2, rn); \
1152 generate_load_flags(); \
1153 ARM_MLAS(0, _rd, _rm, _rs, _rn); \
1154 generate_store_flags()
1157 #define arm_multiply(add_op, flags) \
1159 arm_decode_multiply(); \
1160 u32 _rm = prepare_load_reg(reg_a0, rm); \
1161 u32 _rs = prepare_load_reg(reg_a1, rs); \
1162 u32 _rd = prepare_store_reg(reg_a0, rd); \
1163 arm_multiply_add_##add_op##_flags_##flags(); \
1164 complete_store_reg(_rd, rd); \
1168 #define arm_multiply_long_name_s64 SMULL
1169 #define arm_multiply_long_name_u64 UMULL
1170 #define arm_multiply_long_name_s64_add SMLAL
1171 #define arm_multiply_long_name_u64_add UMLAL
1174 #define arm_multiply_long_flags_no(name) \
1175 ARM_##name(0, _rdlo, _rdhi, _rm, _rs) \
1177 #define arm_multiply_long_flags_yes(name) \
1178 generate_load_flags(); \
1179 ARM_##name##S(0, _rdlo, _rdhi, _rm, _rs); \
1180 generate_store_flags() \
1183 #define arm_multiply_long_add_no(name) \
1185 #define arm_multiply_long_add_yes(name) \
1186 prepare_load_reg(reg_a0, rdlo); \
1187 prepare_load_reg(reg_a1, rdhi) \
1190 #define arm_multiply_long_op(flags, name) \
1191 arm_multiply_long_flags_##flags(name) \
1193 #define arm_multiply_long(name, add_op, flags) \
1195 arm_decode_multiply_long(); \
1196 u32 _rm = prepare_load_reg(reg_a2, rm); \
1197 u32 _rs = prepare_load_reg(reg_rs, rs); \
1198 u32 _rdlo = prepare_store_reg(reg_a0, rdlo); \
1199 u32 _rdhi = prepare_store_reg(reg_a1, rdhi); \
1200 arm_multiply_long_add_##add_op(name); \
1201 arm_multiply_long_op(flags, arm_multiply_long_name_##name); \
1202 complete_store_reg(_rdlo, rdlo); \
1203 complete_store_reg(_rdhi, rdhi); \
1206 #define arm_psr_read_cpsr() \
1207 u32 _rd = prepare_store_reg(reg_a0, rd); \
1208 generate_load_reg(_rd, REG_CPSR); \
1209 ARM_BIC_REG_IMM(0, _rd, _rd, 0xF0, arm_imm_lsl_to_rot(24)); \
1210 ARM_AND_REG_IMM(0, reg_flags, reg_flags, 0xF0, arm_imm_lsl_to_rot(24)); \
1211 ARM_ORR_REG_REG(0, _rd, _rd, reg_flags); \
1212 complete_store_reg(_rd, rd) \
1214 #define arm_psr_read_spsr() \
1215 generate_function_call(execute_read_spsr) \
1216 generate_store_reg(reg_a0, rd) \
1218 #define arm_psr_read(op_type, psr_reg) \
1219 arm_psr_read_##psr_reg() \
1221 // This function's okay because it's called from an ASM function that can
1222 // wrap it correctly.
1224 u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address)
1226 reg[REG_CPSR] = _cpsr;
1227 if(store_mask & 0xFF)
1229 set_cpu_mode(cpu_modes[_cpsr & 0x1F]);
1230 if((io_registers[REG_IE] & io_registers[REG_IF]) &&
1231 io_registers[REG_IME] && ((_cpsr & 0x80) == 0))
1233 reg_mode[MODE_IRQ][6] = address + 4;
1234 spsr[MODE_IRQ] = _cpsr;
1235 reg[REG_CPSR] = 0xD2;
1236 set_cpu_mode(MODE_IRQ);
1244 #define arm_psr_load_new_reg() \
1245 generate_load_reg(reg_a0, rm) \
1247 #define arm_psr_load_new_imm() \
1248 generate_load_imm(reg_a0, imm, imm_ror) \
1250 #define arm_psr_store_cpsr() \
1251 arm_load_imm_32bit(reg_a1, psr_masks[psr_field]); \
1252 generate_function_call(execute_store_cpsr); \
1255 #define arm_psr_store_spsr() \
1256 generate_function_call(execute_store_spsr) \
1258 #define arm_psr_store(op_type, psr_reg) \
1259 arm_psr_load_new_##op_type(); \
1260 arm_psr_store_##psr_reg() \
1263 #define arm_psr(op_type, transfer_type, psr_reg) \
1265 arm_decode_psr_##op_type(); \
1266 arm_psr_##transfer_type(op_type, psr_reg); \
1269 // TODO: loads will need the PC passed as well for open address, however can
1270 // eventually be rectified with a hash table on the memory accesses
1271 // (same with the stores)
1273 #define arm_access_memory_load(mem_type) \
1275 generate_function_call(execute_load_##mem_type); \
1276 write32((pc + 8)); \
1277 generate_store_reg_pc_no_flags(reg_rv, rd) \
1279 #define arm_access_memory_store(mem_type) \
1281 generate_load_reg_pc(reg_a1, rd, 12); \
1282 generate_function_call(execute_store_##mem_type); \
1285 // Calculate the address into a0 from _rn, _rm
1287 #define arm_access_memory_adjust_reg_sh_up(ireg) \
1288 ARM_ADD_REG_IMMSHIFT(0, ireg, _rn, _rm, ((opcode >> 5) & 0x03), \
1289 ((opcode >> 7) & 0x1F)) \
1291 #define arm_access_memory_adjust_reg_sh_down(ireg) \
1292 ARM_SUB_REG_IMMSHIFT(0, ireg, _rn, _rm, ((opcode >> 5) & 0x03), \
1293 ((opcode >> 7) & 0x1F)) \
1295 #define arm_access_memory_adjust_reg_up(ireg) \
1296 ARM_ADD_REG_REG(0, ireg, _rn, _rm) \
1298 #define arm_access_memory_adjust_reg_down(ireg) \
1299 ARM_SUB_REG_REG(0, ireg, _rn, _rm) \
1301 #define arm_access_memory_adjust_imm(op, ireg) \
1305 u32 store_count = arm_disect_imm_32bit(offset, stores, rotations); \
1307 if(store_count > 1) \
1309 ARM_##op##_REG_IMM(0, ireg, _rn, stores[0], rotations[0]); \
1310 ARM_##op##_REG_IMM(0, ireg, ireg, stores[1], rotations[1]); \
1314 ARM_##op##_REG_IMM(0, ireg, _rn, stores[0], rotations[0]); \
1318 #define arm_access_memory_adjust_imm_up(ireg) \
1319 arm_access_memory_adjust_imm(ADD, ireg) \
1321 #define arm_access_memory_adjust_imm_down(ireg) \
1322 arm_access_memory_adjust_imm(SUB, ireg) \
1325 #define arm_access_memory_pre(type, direction) \
1326 arm_access_memory_adjust_##type##_##direction(reg_a0) \
1328 #define arm_access_memory_pre_wb(type, direction) \
1329 arm_access_memory_adjust_##type##_##direction(reg_a0); \
1330 generate_store_reg(reg_a0, rn) \
1332 #define arm_access_memory_post(type, direction) \
1333 u32 _rn_dest = prepare_store_reg(reg_a1, rn); \
1336 generate_load_reg(reg_a0, rn); \
1338 arm_access_memory_adjust_##type##_##direction(_rn_dest); \
1339 complete_store_reg(_rn_dest, rn) \
1342 #define arm_data_trans_reg(adjust_op, direction) \
1343 arm_decode_data_trans_reg(); \
1344 u32 _rn = prepare_load_reg_pc(reg_a0, rn, 8); \
1345 u32 _rm = prepare_load_reg(reg_a1, rm); \
1346 arm_access_memory_##adjust_op(reg_sh, direction) \
1348 #define arm_data_trans_imm(adjust_op, direction) \
1349 arm_decode_data_trans_imm(); \
1350 u32 _rn = prepare_load_reg_pc(reg_a0, rn, 8); \
1351 arm_access_memory_##adjust_op(imm, direction) \
1354 #define arm_data_trans_half_reg(adjust_op, direction) \
1355 arm_decode_half_trans_r(); \
1356 u32 _rn = prepare_load_reg_pc(reg_a0, rn, 8); \
1357 u32 _rm = prepare_load_reg(reg_a1, rm); \
1358 arm_access_memory_##adjust_op(reg, direction) \
1360 #define arm_data_trans_half_imm(adjust_op, direction) \
1361 arm_decode_half_trans_of(); \
1362 u32 _rn = prepare_load_reg_pc(reg_a0, rn, 8); \
1363 arm_access_memory_##adjust_op(imm, direction) \
1366 #define arm_access_memory(access_type, direction, adjust_op, mem_type, \
1369 arm_data_trans_##offset_type(adjust_op, direction); \
1370 arm_access_memory_##access_type(mem_type); \
1374 #define word_bit_count(word) \
1375 (bit_count[word >> 8] + bit_count[word & 0xFF]) \
1377 #define sprint_no(access_type, pre_op, post_op, wb) \
1379 #define sprint_yes(access_type, pre_op, post_op, wb) \
1380 printf("sbit on %s %s %s %s\n", #access_type, #pre_op, #post_op, #wb) \
1383 // TODO: Make these use cached registers. Implement iwram_stack_optimize.
1385 #define arm_block_memory_load() \
1386 generate_function_call(execute_load_u32); \
1387 write32((pc + 8)); \
1388 generate_store_reg(reg_rv, i) \
1390 #define arm_block_memory_store() \
1391 generate_load_reg_pc(reg_a1, i, 8); \
1392 generate_function_call(execute_store_u32_safe) \
1394 #define arm_block_memory_final_load() \
1395 arm_block_memory_load() \
1397 #define arm_block_memory_final_store() \
1398 generate_load_reg_pc(reg_a1, i, 12); \
1399 generate_function_call(execute_store_u32); \
1402 #define arm_block_memory_adjust_pc_store() \
1404 #define arm_block_memory_adjust_pc_load() \
1405 if(reg_list & 0x8000) \
1407 generate_mov(reg_a0, reg_rv); \
1408 generate_indirect_branch_arm(); \
1411 #define arm_block_memory_offset_down_a() \
1412 generate_sub_imm(reg_s0, ((word_bit_count(reg_list) * 4) - 4), 0) \
1414 #define arm_block_memory_offset_down_b() \
1415 generate_sub_imm(reg_s0, (word_bit_count(reg_list) * 4), 0) \
1417 #define arm_block_memory_offset_no() \
1419 #define arm_block_memory_offset_up() \
1420 generate_add_imm(reg_s0, 4, 0) \
1422 #define arm_block_memory_writeback_down() \
1423 generate_load_reg(reg_a0, rn); \
1424 generate_sub_imm(reg_a0, (word_bit_count(reg_list) * 4), 0); \
1425 generate_store_reg(reg_a0, rn) \
1427 #define arm_block_memory_writeback_up() \
1428 generate_load_reg(reg_a0, rn); \
1429 generate_add_imm(reg_a0, (word_bit_count(reg_list) * 4), 0); \
1430 generate_store_reg(reg_a0, rn) \
1432 #define arm_block_memory_writeback_no()
1434 // Only emit writeback if the register is not in the list
1436 #define arm_block_memory_writeback_load(writeback_type) \
1437 if(!((reg_list >> rn) & 0x01)) \
1439 arm_block_memory_writeback_##writeback_type(); \
1442 #define arm_block_memory_writeback_store(writeback_type) \
1443 arm_block_memory_writeback_##writeback_type() \
1445 #define arm_block_memory(access_type, offset_type, writeback_type, s_bit) \
1447 arm_decode_block_trans(); \
1451 generate_load_reg(reg_s0, rn); \
1452 arm_block_memory_offset_##offset_type(); \
1453 arm_block_memory_writeback_##access_type(writeback_type); \
1454 ARM_BIC_REG_IMM(0, reg_s0, reg_s0, 0x03, 0); \
1456 for(i = 0; i < 16; i++) \
1458 if((reg_list >> i) & 0x01) \
1461 generate_add_reg_reg_imm(reg_a0, reg_s0, offset, 0); \
1462 if(reg_list & ~((2 << i) - 1)) \
1464 arm_block_memory_##access_type(); \
1469 arm_block_memory_final_##access_type(); \
1475 arm_block_memory_adjust_pc_##access_type(); \
1478 #define arm_swap(type) \
1480 arm_decode_swap(); \
1482 generate_load_reg(reg_a0, rn); \
1483 generate_function_call(execute_load_##type); \
1484 write32((pc + 8)); \
1485 generate_mov(reg_s0, reg_rv); \
1486 generate_load_reg(reg_a0, rn); \
1487 generate_load_reg(reg_a1, rm); \
1488 generate_function_call(execute_store_##type); \
1489 write32((pc + 4)); \
1490 generate_store_reg(reg_s0, rd); \
1494 #define thumb_generate_op_reg(name, _rd, _rs, _rn) \
1495 u32 __rm = prepare_load_reg(reg_rm, _rn); \
1496 generate_op_##name##_reg_immshift(__rd, __rn, __rm, ARMSHIFT_LSL, 0) \
1498 #define thumb_generate_op_imm(name, _rd, _rs, imm_) \
1501 generate_op_##name##_imm(__rd, __rn); \
1505 #define thumb_data_proc(type, name, op_type, _rd, _rs, _rn) \
1507 thumb_decode_##type(); \
1508 u32 __rn = prepare_load_reg(reg_rn, _rs); \
1509 u32 __rd = prepare_store_reg(reg_rd, _rd); \
1510 generate_load_reg(reg_rn, _rs); \
1511 thumb_generate_op_##op_type(name, _rd, _rs, _rn); \
1512 complete_store_reg(__rd, _rd); \
1515 #define thumb_data_proc_test(type, name, op_type, _rd, _rs) \
1517 thumb_decode_##type(); \
1518 u32 __rn = prepare_load_reg(reg_rn, _rd); \
1519 thumb_generate_op_##op_type(name, 0, _rd, _rs); \
1522 #define thumb_data_proc_unary(type, name, op_type, _rd, _rs) \
1524 thumb_decode_##type(); \
1525 u32 __rd = prepare_store_reg(reg_rd, _rd); \
1526 thumb_generate_op_##op_type(name, _rd, 0, _rs); \
1527 complete_store_reg(__rd, _rd); \
1531 #define complete_store_reg_pc_thumb() \
1534 generate_indirect_branch_cycle_update(thumb); \
1538 complete_store_reg(_rd, rd); \
1541 #define thumb_data_proc_hi(name) \
1543 thumb_decode_hireg_op(); \
1544 u32 _rd = prepare_load_reg_pc(reg_rd, rd, 4); \
1545 u32 _rs = prepare_load_reg_pc(reg_rn, rs, 4); \
1546 generate_op_##name##_reg_immshift(_rd, _rd, _rs, ARMSHIFT_LSL, 0); \
1547 complete_store_reg_pc_thumb(); \
1550 #define thumb_data_proc_test_hi(name) \
1552 thumb_decode_hireg_op(); \
1553 u32 _rd = prepare_load_reg_pc(reg_rd, rd, 4); \
1554 u32 _rs = prepare_load_reg_pc(reg_rn, rs, 4); \
1555 generate_op_##name##_reg_immshift(0, _rd, _rs, ARMSHIFT_LSL, 0); \
1558 #define thumb_data_proc_mov_hi() \
1560 thumb_decode_hireg_op(); \
1561 u32 _rs = prepare_load_reg_pc(reg_rn, rs, 4); \
1562 u32 _rd = prepare_store_reg(reg_rd, rd); \
1563 ARM_MOV_REG_REG(0, _rd, _rs); \
1564 complete_store_reg_pc_thumb(); \
1569 #define thumb_load_pc(_rd) \
1571 thumb_decode_imm(); \
1572 u32 __rd = prepare_store_reg(reg_rd, _rd); \
1573 generate_load_pc(__rd, (((pc & ~2) + 4) + (imm * 4))); \
1574 complete_store_reg(__rd, _rd); \
1577 #define thumb_load_sp(_rd) \
1579 thumb_decode_imm(); \
1580 u32 __sp = prepare_load_reg(reg_a0, REG_SP); \
1581 u32 __rd = prepare_store_reg(reg_a0, _rd); \
1582 ARM_ADD_REG_IMM(0, __rd, __sp, imm, arm_imm_lsl_to_rot(2)); \
1583 complete_store_reg(__rd, _rd); \
1586 #define thumb_adjust_sp_up() \
1587 ARM_ADD_REG_IMM(0, _sp, _sp, imm, arm_imm_lsl_to_rot(2)) \
1589 #define thumb_adjust_sp_down() \
1590 ARM_SUB_REG_IMM(0, _sp, _sp, imm, arm_imm_lsl_to_rot(2)) \
1592 #define thumb_adjust_sp(direction) \
1594 thumb_decode_add_sp(); \
1595 u32 _sp = prepare_load_reg(reg_a0, REG_SP); \
1596 thumb_adjust_sp_##direction(); \
1597 complete_store_reg(_sp, REG_SP); \
1600 #define generate_op_lsl_reg(_rd, _rm, _rs) \
1601 generate_op_movs_reg_regshift(_rd, 0, _rm, ARMSHIFT_LSL, _rs) \
1603 #define generate_op_lsr_reg(_rd, _rm, _rs) \
1604 generate_op_movs_reg_regshift(_rd, 0, _rm, ARMSHIFT_LSR, _rs) \
1606 #define generate_op_asr_reg(_rd, _rm, _rs) \
1607 generate_op_movs_reg_regshift(_rd, 0, _rm, ARMSHIFT_ASR, _rs) \
1609 #define generate_op_ror_reg(_rd, _rm, _rs) \
1610 generate_op_movs_reg_regshift(_rd, 0, _rm, ARMSHIFT_ROR, _rs) \
1613 #define generate_op_lsl_imm(_rd, _rm) \
1614 generate_op_movs_reg_immshift(_rd, 0, _rm, ARMSHIFT_LSL, imm) \
1616 #define generate_op_lsr_imm(_rd, _rm) \
1617 generate_op_movs_reg_immshift(_rd, 0, _rm, ARMSHIFT_LSR, imm) \
1619 #define generate_op_asr_imm(_rd, _rm) \
1620 generate_op_movs_reg_immshift(_rd, 0, _rm, ARMSHIFT_ASR, imm) \
1622 #define generate_op_ror_imm(_rd, _rm) \
1623 generate_op_movs_reg_immshift(_rd, 0, _rm, ARMSHIFT_ROR, imm) \
1626 #define generate_shift_reg(op_type) \
1627 u32 __rm = prepare_load_reg(reg_rd, rd); \
1628 u32 __rs = prepare_load_reg(reg_rs, rs); \
1629 generate_op_##op_type##_reg(__rd, __rm, __rs) \
1631 #define generate_shift_imm(op_type) \
1632 u32 __rs = prepare_load_reg(reg_rs, rs); \
1633 generate_op_##op_type##_imm(__rd, __rs) \
1636 #define thumb_shift(decode_type, op_type, value_type) \
1638 thumb_decode_##decode_type(); \
1639 u32 __rd = prepare_store_reg(reg_rd, rd); \
1640 generate_shift_##value_type(op_type); \
1641 complete_store_reg(__rd, rd); \
1644 // Operation types: imm, mem_reg, mem_imm
1646 #define thumb_access_memory_load(mem_type, _rd) \
1648 generate_function_call(execute_load_##mem_type); \
1649 write32((pc + 4)); \
1650 generate_store_reg(reg_rv, _rd) \
1652 #define thumb_access_memory_store(mem_type, _rd) \
1654 generate_load_reg(reg_a1, _rd); \
1655 generate_function_call(execute_store_##mem_type); \
1658 #define thumb_access_memory_generate_address_pc_relative(offset, _rb, _ro) \
1659 generate_load_pc(reg_a0, (offset)) \
1661 #define thumb_access_memory_generate_address_reg_imm(offset, _rb, _ro) \
1662 u32 __rb = prepare_load_reg(reg_a0, _rb); \
1663 ARM_ADD_REG_IMM(0, reg_a0, __rb, offset, 0) \
1665 #define thumb_access_memory_generate_address_reg_imm_sp(offset, _rb, _ro) \
1666 u32 __rb = prepare_load_reg(reg_a0, _rb); \
1667 ARM_ADD_REG_IMM(0, reg_a0, __rb, offset, arm_imm_lsl_to_rot(2)) \
1669 #define thumb_access_memory_generate_address_reg_reg(offset, _rb, _ro) \
1670 u32 __rb = prepare_load_reg(reg_a0, _rb); \
1671 u32 __ro = prepare_load_reg(reg_a1, _ro); \
1672 ARM_ADD_REG_REG(0, reg_a0, __rb, __ro) \
1674 #define thumb_access_memory(access_type, op_type, _rd, _rb, _ro, \
1675 address_type, offset, mem_type) \
1677 thumb_decode_##op_type(); \
1678 thumb_access_memory_generate_address_##address_type(offset, _rb, _ro); \
1679 thumb_access_memory_##access_type(mem_type, _rd); \
1682 // TODO: Make these use cached registers. Implement iwram_stack_optimize.
1684 #define thumb_block_address_preadjust_up() \
1685 generate_add_imm(reg_s0, (bit_count[reg_list] * 4), 0) \
1687 #define thumb_block_address_preadjust_down() \
1688 generate_sub_imm(reg_s0, (bit_count[reg_list] * 4), 0) \
1690 #define thumb_block_address_preadjust_push_lr() \
1691 generate_sub_imm(reg_s0, ((bit_count[reg_list] + 1) * 4), 0) \
1693 #define thumb_block_address_preadjust_no() \
1695 #define thumb_block_address_postadjust_no(base_reg) \
1696 generate_store_reg(reg_s0, base_reg) \
1698 #define thumb_block_address_postadjust_up(base_reg) \
1699 generate_add_reg_reg_imm(reg_a0, reg_s0, (bit_count[reg_list] * 4), 0); \
1700 generate_store_reg(reg_a0, base_reg) \
1702 #define thumb_block_address_postadjust_down(base_reg) \
1703 generate_mov(reg_a0, reg_s0); \
1704 generate_sub_imm(reg_a0, (bit_count[reg_list] * 4), 0); \
1705 generate_store_reg(reg_a0, base_reg) \
1707 #define thumb_block_address_postadjust_pop_pc(base_reg) \
1708 generate_add_reg_reg_imm(reg_a0, reg_s0, \
1709 ((bit_count[reg_list] + 1) * 4), 0); \
1710 generate_store_reg(reg_a0, base_reg) \
1712 #define thumb_block_address_postadjust_push_lr(base_reg) \
1713 generate_store_reg(reg_s0, base_reg) \
1715 #define thumb_block_memory_extra_no() \
1717 #define thumb_block_memory_extra_up() \
1719 #define thumb_block_memory_extra_down() \
1721 #define thumb_block_memory_extra_pop_pc() \
1722 generate_add_reg_reg_imm(reg_a0, reg_s0, (bit_count[reg_list] * 4), 0); \
1723 generate_function_call(execute_load_u32); \
1724 write32((pc + 4)); \
1725 generate_mov(reg_a0, reg_rv); \
1726 generate_indirect_branch_cycle_update(thumb) \
1728 #define thumb_block_memory_extra_push_lr(base_reg) \
1729 generate_add_reg_reg_imm(reg_a0, reg_s0, (bit_count[reg_list] * 4), 0); \
1730 generate_load_reg(reg_a1, REG_LR); \
1731 generate_function_call(execute_store_u32_safe) \
1733 #define thumb_block_memory_load() \
1734 generate_function_call(execute_load_u32); \
1735 write32((pc + 4)); \
1736 generate_store_reg(reg_rv, i) \
1738 #define thumb_block_memory_store() \
1739 generate_load_reg(reg_a1, i); \
1740 generate_function_call(execute_store_u32_safe) \
1742 #define thumb_block_memory_final_load() \
1743 thumb_block_memory_load() \
1745 #define thumb_block_memory_final_store() \
1746 generate_load_reg(reg_a1, i); \
1747 generate_function_call(execute_store_u32); \
1750 #define thumb_block_memory_final_no(access_type) \
1751 thumb_block_memory_final_##access_type() \
1753 #define thumb_block_memory_final_up(access_type) \
1754 thumb_block_memory_final_##access_type() \
1756 #define thumb_block_memory_final_down(access_type) \
1757 thumb_block_memory_final_##access_type() \
1759 #define thumb_block_memory_final_push_lr(access_type) \
1760 thumb_block_memory_##access_type() \
1762 #define thumb_block_memory_final_pop_pc(access_type) \
1763 thumb_block_memory_##access_type() \
1765 #define thumb_block_memory(access_type, pre_op, post_op, base_reg) \
1767 thumb_decode_rlist(); \
1771 generate_load_reg(reg_s0, base_reg); \
1772 ARM_BIC_REG_IMM(0, reg_s0, reg_s0, 0x03, 0); \
1773 thumb_block_address_preadjust_##pre_op(); \
1774 thumb_block_address_postadjust_##post_op(base_reg); \
1776 for(i = 0; i < 8; i++) \
1778 if((reg_list >> i) & 0x01) \
1781 generate_add_reg_reg_imm(reg_a0, reg_s0, offset, 0); \
1782 if(reg_list & ~((2 << i) - 1)) \
1784 thumb_block_memory_##access_type(); \
1789 thumb_block_memory_final_##post_op(access_type); \
1795 thumb_block_memory_extra_##post_op(); \
1798 #define thumb_conditional_branch(condition) \
1800 generate_cycle_update(); \
1801 generate_load_flags(); \
1802 generate_branch_filler(condition_opposite_##condition, backpatch_address); \
1803 generate_branch_no_cycle_update( \
1804 block_exits[block_exit_position].branch_source, \
1805 block_exits[block_exit_position].branch_target, thumb); \
1806 generate_branch_patch_conditional(backpatch_address, translation_ptr); \
1807 block_exit_position++; \
1811 #define arm_conditional_block_header() \
1812 generate_cycle_update(); \
1813 generate_load_flags(); \
1814 /* This will choose the opposite condition */ \
1815 condition ^= 0x01; \
1816 generate_branch_filler(condition, backpatch_address) \
1819 generate_branch(arm) \
1822 generate_update_pc((pc + 4)); \
1823 generate_store_reg(reg_a0, REG_LR); \
1824 generate_branch(arm) \
1827 arm_decode_branchx(); \
1828 generate_load_reg(reg_a0, rn); \
1829 generate_indirect_branch_dual(); \
1832 generate_swi_hle_handler((opcode >> 16) & 0xFF, arm); \
1833 generate_function_call(execute_swi_arm); \
1834 write32((pc + 4)); \
1835 generate_branch(arm) \
1838 generate_branch(thumb) \
1840 #define thumb_bl() \
1841 generate_update_pc(((pc + 2) | 0x01)); \
1842 generate_store_reg(reg_a0, REG_LR); \
1843 generate_branch(thumb) \
1845 #define thumb_blh() \
1847 thumb_decode_branch(); \
1848 generate_update_pc(((pc + 2) | 0x01)); \
1849 generate_load_reg(reg_a1, REG_LR); \
1850 generate_store_reg(reg_a0, REG_LR); \
1851 generate_mov(reg_a0, reg_a1); \
1852 generate_add_imm(reg_a0, (offset * 2), 0); \
1853 generate_indirect_branch_cycle_update(thumb); \
1856 #define thumb_bx() \
1858 thumb_decode_hireg_op(); \
1859 generate_load_reg_pc(reg_a0, rs, 4); \
1860 generate_indirect_branch_cycle_update(dual_thumb); \
1863 #define thumb_swi() \
1864 generate_swi_hle_handler(opcode & 0xFF, thumb); \
1865 generate_function_call(execute_swi_thumb); \
1866 write32((pc + 2)); \
1867 /* We're in ARM mode now */ \
1868 generate_branch(arm) \
1870 u8 swi_hle_handle[256] =
1872 0x0, // SWI 0: SoftReset
1873 0x0, // SWI 1: RegisterRAMReset
1875 0x0, // SWI 3: Stop/Sleep
1876 0x0, // SWI 4: IntrWait
1877 0x0, // SWI 5: VBlankIntrWait
1879 0x0, // SWI 7: DivArm
1881 0x0, // SWI 9: ArcTan
1882 0x0, // SWI A: ArcTan2
1883 0x0, // SWI B: CpuSet
1884 0x0, // SWI C: CpuFastSet
1885 0x0, // SWI D: GetBIOSCheckSum
1886 0x0, // SWI E: BgAffineSet
1887 0x0, // SWI F: ObjAffineSet
1888 0x0, // SWI 10: BitUnpack
1889 0x0, // SWI 11: LZ77UnCompWram
1890 0x0, // SWI 12: LZ77UnCompVram
1891 0x0, // SWI 13: HuffUnComp
1892 0x0, // SWI 14: RLUnCompWram
1893 0x0, // SWI 15: RLUnCompVram
1894 0x0, // SWI 16: Diff8bitUnFilterWram
1895 0x0, // SWI 17: Diff8bitUnFilterVram
1896 0x0, // SWI 18: Diff16bitUnFilter
1897 0x0, // SWI 19: SoundBias
1898 0x0, // SWI 1A: SoundDriverInit
1899 0x0, // SWI 1B: SoundDriverMode
1900 0x0, // SWI 1C: SoundDriverMain
1901 0x0, // SWI 1D: SoundDriverVSync
1902 0x0, // SWI 1E: SoundChannelClear
1903 0x0, // SWI 1F: MidiKey2Freq
1904 0x0, // SWI 20: SoundWhatever0
1905 0x0, // SWI 21: SoundWhatever1
1906 0x0, // SWI 22: SoundWhatever2
1907 0x0, // SWI 23: SoundWhatever3
1908 0x0, // SWI 24: SoundWhatever4
1909 0x0, // SWI 25: MultiBoot
1910 0x0, // SWI 26: HardReset
1911 0x0, // SWI 27: CustomHalt
1912 0x0, // SWI 28: SoundDriverVSyncOff
1913 0x0, // SWI 29: SoundDriverVSyncOn
1914 0x0 // SWI 2A: SoundGetJumpList
1917 void execute_swi_hle_div_arm();
1918 void execute_swi_hle_div_thumb();
1920 void execute_swi_hle_div_c()
1922 s32 result = (s32)reg[0] / (s32)reg[1];
1923 reg[1] = (s32)reg[0] % (s32)reg[1];
1926 reg[3] = (result ^ (result >> 31)) - (result >> 31);
1929 #define generate_swi_hle_handler(_swi_number, mode) \
1931 u32 swi_number = _swi_number; \
1932 if(swi_hle_handle[swi_number]) \
1935 if(swi_number == 0x06) \
1937 generate_function_call(execute_swi_hle_div_##mode); \
1943 #define generate_translation_gate(type) \
1944 generate_update_pc(pc); \
1945 generate_indirect_branch_no_cycle_update(type) \
1947 #define generate_step_debug() \
1948 generate_function_call(step_debug_arm); \