2 # --register-prefix-optional --bitwise-or
3 # reminder: d2-d7/a2-a6 are callee-save
5 .macro ldarg arg, stacksz, reg
6 move.l (4 + \arg * 4 + \stacksz)(%sp), \reg
9 .macro ldargw arg, stacksz, reg
10 move.w (4 + \arg * 4 + 2 + \stacksz)(%sp), \reg
13 .global burn10 /* u16 val */
21 .global write16_x16 /* u32 a, u16 count, u16 d */
42 # read single phase from controller
47 move.b #0x40,(0xa10003)
52 move.b #0x00,(0xa10003)
53 andi.w #0x3f,d1 /* 00CB RLDU */
57 andi.w #0xc0,d0 /* SA00 0000 */
63 eor.w d0,d1 /* changed btns */
64 move.w d0,d7 /* old val */
66 and.w d0,d1 /* what changed now */
70 .global write_and_read1 /* u32 a, u16 d, void *dst */
77 /* different timing due to extra fetch of offset, */
78 /* less troulesome to emulate */
91 .global move_sr /* u16 sr */
97 .global move_sr_and_read /* u16 sr, u32 a */
110 .global memcpy_ /* void *dst, const void *src, u16 size */
117 move.b (a1)+, (a0)+ /* not in a hurry */
121 .global memset_ /* void *dst, int d, u16 size */
128 move.b d1, (a0)+ /* not in a hurry */
136 movem.l d2-d7/a2, -(sp)
137 movea.l #0xc00007, a0
138 movea.l #0xc00008, a1
139 movea.l #0xff0000, a2
140 moveq.l #0, d4 /* d4 = count */
141 moveq.l #0, d5 /* d5 = vcnt_expect */
143 move.l #1<<(3+16), d7 /* d7 = SR_VB */
146 beq 0b /* not blanking */
149 bne 0b /* blanking */
154 bne 0b /* not line 0 */
158 move.l d6, (a2)+ /* d0 = old */
161 move.b (a1), d2 /* 8 d2 = vcnt */
162 cmp.b (a1), d2 /* 8 reread for corruption */
163 bne 0b /* 10 on changing vcounter? */
164 cmp.b d2, d5 /* 4 vcnt == vcnt_expect? */
166 move.l (a0), d0 /* 12 */
170 addq.l #1, d4 /* count++ */
173 bne 2f /* vcnt == vcnt_expect + 1 */
176 and.l d7, d1 /* (old ^ val) & vb */
178 move.l d0, d6 /* old = val */
181 2: /* vcnt jump or vb change */
182 move.l d6, (a2)+ /* *ram++ = old */
183 move.l d0, (a2)+ /* *ram++ = val */
184 move.b d2, d5 /* vcnt_expect = vcnt */
185 move.l d0, d6 /* old = val */
191 bne 1b /* still in VB */
193 move.l d0, (a2)+ /* *ram++ = val */
194 move.l d4, (a2)+ /* *ram++ = count */
196 movem.l (sp)+, d2-d7/a2
199 .global test_vcnt_loops
202 movea.l #0xc00007, a0
203 movea.l #0xfff000, a1
204 move.b #0xff, d0 /* d0 = current_vcnt */
205 moveq.l #0, d1 /* d1 = loop counter */
206 move.w #315-1, d2 /* d2 = line limit */
209 beq 0b /* not blanking */
212 bne 0b /* blanking */
216 addq.w #1, d1 /* 4 */
217 cmp.b (a0), d0 /* 8 vcnt changed? */
220 move.w d0, (a1)+ /* 8 save */
222 move.b (a0), d0 /* 8 new vcnt */
231 move.w d0, -(sp) /* 8 */
232 move.w (0xc00008).l, d0 /* 16 */
233 addq.w #1, (0xf000).w /* 16 */
234 tst.w (0xf002).w /* 12 */
236 move.w d0, (0xf002).w /* 12 */
238 move.w d0, (0xf004).w /* 12 */
239 move.w (sp)+, d0 /* 8 */
241 .global test_hint_end
246 move.w d0, -(sp) /* 8 */
247 move.w (0xc00008).l, d0 /* 16 */
248 addq.w #1, (0xf008).w /* 16 */
249 tst.w (0xf00a).w /* 12 */
251 move.w d0, (0xf00a).w /* 12 */
253 move.w d0, (0xf00c).w /* 12 */
254 move.w (sp)+, d0 /* 8 */
256 .global test_vint_end
261 movea.l #0xa15100, a0
262 movea.l #0xa15122, a1
263 move.w #1, (a0) /* ADEN */
264 # wait for min(20_sh2_cycles, pll_setup_time)
265 # pll time is unclear, icd_mars.prg mentions 10ms which sounds
266 # way too much. Hope 40 68k cycles is enough
270 move.w #3, (a0) /* ADEN, nRES */
272 move.w #0xffff, d0 /* waste some cycles */
274 beq 0b /* master BIOS busy */
276 0: /* for slave, use a limit, as it */
277 tst.w 4(a1) /* won't respond on master error. */
278 dbne d0, 0b /* slave BIOS busy */
280 or.w #1, 6(a0) /* RV */
282 .global x32x_enable_end
287 movea.l #0xa15100, a0
288 move.w #1, (a0) /* ADEN (reset sh2) */
289 move.w #0, (a0) /* adapter disable, reset sh2 */
293 move.w #2, (a0) /* nRES - sh2s should see no ADEN and sleep */
295 .global x32x_disable_end
298 .global test_32x_b_c0
302 jsr (0xc0).l /* move.b d0, (a1); RV=0 */
303 bset #0, (0xa15107).l /* RV=1 */
305 .global test_32x_b_c0_end
308 # some nastyness from Fatal Rewind
312 move.w #0x8014, (0xFFC00004).l
313 move.w #0x8164, (0xFFC00004).l
323 movea.l #0xc00004, a0
326 move.w #480/2/10-1, d0
329 move.w #0x8164, (0xFFC00004).l
330 move.w #0x8014, (0xFFC00004).l
338 .global test_f_vint_end
343 movea.l #0xc00005, a0
344 movea.l #0xc00004, a1
352 movem.l d2-d7/a2, -(sp)
360 movea.l #0xff0000, a0
363 .macro test_lb_s sr, dr
374 movem.l (sp)+, d2-d7/a2
380 movea.l #0xc00004, a0
381 movea.l #0xc00008, a1
392 movea.l #0xff0000, a1
393 movea.l #0xff0000, a1
412 .macro ymwrite areg, dreg addr dat
413 move.b \addr, (\areg) /* 12 addr */
414 nbcd d0 /* 6 delay to reach 17 ym cycles (M/7) */
415 move.b \dat, (\dreg) /* 12 data */
418 .global test_ym_stopped_tick
419 test_ym_stopped_tick:
421 movea.l #0xa04000, a0
422 movea.l #0xa04001, a1
423 movea.l #0xc00007, a2
424 movea.l #0xfff000, a3
426 ymwrite a0, a1, #0x27, #0x30 /* 30 disable, clear */
427 ymwrite a0, a1, #0x26, #0xff /* 30 timer b shortest interval */
428 move.b #0x27, (a0) /* 12 addr prep */
431 beq 0b /* not blanking */
434 bne 0b /* blanking */
439 bne 0b /* not line 0 - waiting for sequential vcnt */
441 move.b #0x0a, (a1) /* 12 start timer b */
449 # move.w (a2), (a3)+ /* 12 save hvcnt */
454 move.b #0x30, (a1) /* 12 stop b, clear */
456 move.w #(1900/10-1), d0 /* waste cycles */
461 move.w (a0), (a3)+ /* 12 save status */
462 move.b #0x0a, (a1) /* 12 start b */
469 # move.w (a2), (a3)+ /* 12 save hvcnt */
474 move.w d0, (a3)+ /* 12 save status */
479 .global test_ym_ab_sync
481 movea.l #0xa04000, a0
482 movea.l #0xa04001, a1
484 ymwrite a0, a1, #0x27, #0x30 /* 30 disable, clear */
485 ymwrite a0, a1, #0x24, #0xfc /* 30 timer a */
486 ymwrite a0, a1, #0x25, #0x01 /* 30 =15 - why 15? expected 16 */
487 ymwrite a0, a1, #0x26, #0xff /* 30 timer b shortest interval */
488 move.b #0x27, (a0) /* 12 addr prep */
492 move.b #0x0a, (a1) /* 12 start timer b */
496 move.b (a0), d0 /* 8 */
500 move.b #0x3f, (a1) /* 12 start a, clear */
501 move.w #(1800/10-1), d0 /* waste cycles */
505 ymwrite a0, a1, #0x24, #0x00 /* 30 show that rewriting count */
506 ymwrite a0, a1, #0x25, #0x00 /* 30 does nothing */
507 ymwrite a0, a1, #0x26, #0x00 /* 30 */
508 ymwrite a0, a1, #0x27, #0x0f /* 30 setting already set bits too */
515 move.b (a0), d0 /* re-read, else very occasionally get 1 */
518 # vim:filetype=asmM68k:ts=4:sw=4:expandtab