2 # --register-prefix-optional --bitwise-or
4 .macro ldarg arg, stacksz, reg
5 move.l (4 + \arg * 4 + \stacksz)(%sp), \reg
8 .macro ldargw arg, stacksz, reg
9 move.w (4 + \arg * 4 + 2 + \stacksz)(%sp), \reg
12 .global burn10 /* u16 val */
20 .global write16_x16 /* u32 a, u16 count, u16 d */
41 # read single phase from controller
46 move.b #0x40,(0xa10003)
51 move.b #0x00,(0xa10003)
52 andi.w #0x3f,d1 /* 00CB RLDU */
56 andi.w #0xc0,d0 /* SA00 0000 */
62 eor.w d0,d1 /* changed btns */
63 move.w d0,d7 /* old val */
65 and.w d0,d1 /* what changed now */
69 .global write_and_read1 /* u32 a, u16 d, void *dst */
88 .global move_sr /* u16 sr */
94 .global move_sr_and_read /* u16 sr, u32 a */
102 .global memcpy_ /* void *dst, const void *src, u16 size */
109 move.b (a1)+, (a0)+ /* not in a hurry */
113 .global memset_ /* void *dst, int d, u16 size */
120 move.b d1, (a0)+ /* not in a hurry */
128 movem.l d2-d7/a2, -(sp)
129 movea.l #0xc00007, a0
130 movea.l #0xc00008, a1
131 movea.l #0xff0000, a2
132 moveq.l #0, d4 /* d4 = count */
133 moveq.l #0, d5 /* d5 = vcnt_expect */
135 move.l #1<<(3+16), d7 /* d7 = SR_VB */
138 beq 0b /* not blanking */
141 bne 0b /* blanking */
146 bne 0b /* not line 0 */
150 move.l d6, (a2)+ /* d0 = old */
153 move.b (a1), d2 /* 8 d2 = vcnt */
154 cmp.b (a1), d2 /* 8 reread for corruption */
155 bne 0b /* 10 on changing vcounter? */
156 cmp.b d2, d5 /* 4 vcnt == vcnt_expect? */
158 move.l (a0), d0 /* 12 */
162 addq.l #1, d4 /* count++ */
165 bne 2f /* vcnt == vcnt_expect + 1 */
168 and.l d7, d1 /* (old ^ val) & vb */
170 move.l d0, d6 /* old = val */
173 2: /* vcnt jump or vb change */
174 move.l d6, (a2)+ /* *ram++ = old */
175 move.l d0, (a2)+ /* *ram++ = val */
176 move.b d2, d5 /* vcnt_expect = vcnt */
177 move.l d0, d6 /* old = val */
183 bne 1b /* still in VB */
185 move.l d0, (a2)+ /* *ram++ = val */
186 move.l d4, (a2)+ /* *ram++ = count */
188 movem.l (sp)+, d2-d7/a2
193 move.w d0, -(sp) /* 8 */
194 move.w (0xc00008).l, d0 /* 16 */
195 addq.w #1, (0xf000).w /* 16 */
196 tst.w (0xf002).w /* 12 */
198 move.w d0, (0xf002).w /* 12 */
200 move.w d0, (0xf004).w /* 12 */
201 move.w (sp)+, d0 /* 8 */
203 .global test_hint_end
208 move.w d0, -(sp) /* 8 */
209 move.w (0xc00008).l, d0 /* 16 */
210 addq.w #1, (0xf008).w /* 16 */
211 tst.w (0xf00a).w /* 12 */
213 move.w d0, (0xf00a).w /* 12 */
215 move.w d0, (0xf00c).w /* 12 */
216 move.w (sp)+, d0 /* 8 */
218 .global test_vint_end
223 movea.l #0xa15100, a0
224 movea.l #0xa15122, a1
225 move.w #1, (a0) /* ADEN */
226 # wait for min(20_sh2_cycles, pll_setup_time)
227 # pll time is unclear, icd_mars.prg mentions 10ms which sounds
228 # way too much. Hope 40 68k cycles is enough
232 move.w #3, (a0) /* ADEN, nRES */
234 move.w #0xffff, d0 /* waste some cycles */
236 beq 0b /* master BIOS busy */
238 0: /* for slave, use a limit, as it */
239 tst.w 4(a1) /* won't respond on master error. */
240 dbne d0, 0b /* slave BIOS busy */
242 or.w #1, 6(a0) /* RV */
244 .global x32x_enable_end
247 # some nastyness from Fatal Rewind
251 move.w #0x8014, (0xFFC00004).l
252 move.w #0x8164, (0xFFC00004).l
262 movea.l #0xc00004, a0
265 move.w #480/2/10-1, d0
268 move.w #0x8164, (0xFFC00004).l
269 move.w #0x8014, (0xFFC00004).l
277 .global test_f_vint_end
282 movea.l #0xc00005, a0
283 movea.l #0xc00004, a1
291 movem.l d2-d7/a2, -(sp)
299 movea.l #0xff0000, a0
302 .macro test_lb_s sr, dr
313 movem.l (sp)+, d2-d7/a2
319 movea.l #0xc00004, a0
320 movea.l #0xc00008, a1
331 movea.l #0xff0000, a1
332 movea.l #0xff0000, a1
351 # vim:filetype=asmM68k:ts=4:sw=4:expandtab