2 # --register-prefix-optional --bitwise-or
3 # reminder: d2-d7/a2-a6 are callee-save
5 .macro ldarg arg, stacksz, reg
6 move.l (4 + \arg * 4 + \stacksz)(%sp), \reg
9 .macro ldargw arg, stacksz, reg
10 move.w (4 + \arg * 4 + 2 + \stacksz)(%sp), \reg
13 .global burn10 /* u16 val */
18 dbra d0, 0b /* 10|14 */
21 .global write16_x16 /* u32 a, u16 count, u16 d */
42 # read single phase from controller
47 move.b #0x40,(0xa10003)
52 move.b #0x00,(0xa10003)
53 andi.w #0x3f,d1 /* 00CB RLDU */
57 andi.w #0xc0,d0 /* SA00 0000 */
63 eor.w d0,d1 /* changed btns */
64 move.w d0,d7 /* old val */
66 and.w d0,d1 /* what changed now */
75 move.b (a0), d0 /* 8 d2 = vcnt */
76 cmp.b (a0), d0 /* 8 reread for super-rare corruption (torn read) */
80 .global write_and_read1 /* u32 a, u16 d, void *dst */
87 /* different timing due to extra fetch of offset, */
88 /* less troulesome to emulate */
101 .global move_sr /* u16 sr */
107 .global move_sr_and_read /* u16 sr, u32 a */
120 .global memcpy_ /* void *dst, const void *src, u16 size */
127 move.b (a1)+, (a0)+ /* not in a hurry */
131 .global memset_ /* void *dst, int d, u16 size */
138 move.b d1, (a0)+ /* not in a hurry */
146 movem.l d2-d7/a2, -(sp)
147 movea.l #0xc00007, a0
148 movea.l #0xc00008, a1
149 movea.l #0xff0000, a2
150 moveq.l #0, d4 /* d4 = count */
151 moveq.l #0, d5 /* d5 = vcnt_expect */
153 move.l #1<<(3+16), d7 /* d7 = SR_VB */
156 beq 0b /* not blanking */
159 bne 0b /* blanking */
164 bne 0b /* not line 0 */
168 move.l d6, (a2)+ /* d0 = old */
171 move.b (a1), d2 /* 8 d2 = vcnt */
172 cmp.b (a1), d2 /* 8 reread for corruption */
173 bne 0b /* 10 on changing vcounter? */
174 cmp.b d2, d5 /* 4 vcnt == vcnt_expect? */
176 move.l (a0), d0 /* 12 */
180 addq.l #1, d4 /* count++ */
183 bne 2f /* vcnt == vcnt_expect + 1 */
186 and.l d7, d1 /* (old ^ val) & vb */
188 move.l d0, d6 /* old = val */
191 2: /* vcnt jump or vb change */
192 move.l d6, (a2)+ /* *ram++ = old */
193 move.l d0, (a2)+ /* *ram++ = val */
194 move.b d2, d5 /* vcnt_expect = vcnt */
195 move.l d0, d6 /* old = val */
201 bne 1b /* still in VB */
203 move.l d0, (a2)+ /* *ram++ = val */
204 move.l d4, (a2)+ /* *ram++ = count */
206 movem.l (sp)+, d2-d7/a2
209 .global test_vcnt_loops
212 movea.l #0xc00007, a0
213 movea.l #0xfff000, a1
214 move.b #0xff, d0 /* d0 = current_vcnt */
215 moveq.l #0, d1 /* d1 = loop counter */
216 move.w #315-1, d2 /* d2 = line limit */
219 beq 0b /* not blanking */
222 bne 0b /* blanking */
226 addq.w #1, d1 /* 4 */
227 cmp.b (a0), d0 /* 8 vcnt changed? */
230 move.w d0, (a1)+ /* 8 save */
232 move.b (a0), d0 /* 8 new vcnt */
241 move.w d0, -(sp) /* 8 */
242 move.w (0xc00008).l, d0 /* 16 */
243 addq.w #1, (0xf000).w /* 16 */
244 tst.w (0xf002).w /* 12 */
246 move.w d0, (0xf002).w /* 12 */
248 move.w d0, (0xf004).w /* 12 */
249 move.w (sp)+, d0 /* 8 */
251 .global test_hint_end
256 move.w d0, -(sp) /* 8 */
257 move.w (0xc00008).l, d0 /* 16 */
258 addq.w #1, (0xf008).w /* 16 */
259 tst.w (0xf00a).w /* 12 */
261 move.w d0, (0xf00a).w /* 12 */
263 move.w d0, (0xf00c).w /* 12 */
264 move.w (sp)+, d0 /* 8 */
266 .global test_vint_end
271 movea.l #0xa15100, a0
272 movea.l #0xa15122, a1
273 move.w #1, (a0) /* ADEN */
274 # wait for min(20_sh2_cycles, pll_setup_time)
275 # pll time is unclear, icd_mars.prg mentions 10ms which sounds
276 # way too much. Hope 40 68k cycles is enough
280 move.w #3, (a0) /* ADEN, nRES */
282 move.w #0xffff, d0 /* waste some cycles */
284 beq 0b /* master BIOS busy */
286 0: /* for slave, use a limit, as it */
287 tst.w 4(a1) /* won't respond on master error. */
288 dbne d0, 0b /* slave BIOS busy */
290 or.w #1, 6(a0) /* RV */
292 .global x32x_enable_end
297 movea.l #0xa15100, a0
298 move.w #1, (a0) /* ADEN (reset sh2) */
299 move.w #0, (a0) /* adapter disable, reset sh2 */
303 move.w #2, (a0) /* nRES - sh2s should see no ADEN and sleep */
305 .global x32x_disable_end
308 .global test_32x_b_c0
312 jsr (0xc0).l /* move.b d0, (a1); RV=0 */
313 bset #0, (0xa15107).l /* RV=1 */
315 .global test_32x_b_c0_end
318 # some nastyness from Fatal Rewind
322 move.w #0x8014, (0xFFC00004).l
323 move.w #0x8164, (0xFFC00004).l
333 movea.l #0xc00004, a0
336 move.w #480/2/10-1, d0
339 move.w #0x8164, (0xFFC00004).l
340 move.w #0x8014, (0xFFC00004).l
348 .global test_f_vint_end
353 movea.l #0xc00005, a0
354 movea.l #0xc00004, a1
362 movem.l d2-d7/a2, -(sp)
370 movea.l #0xff0000, a0
373 .macro test_lb_s sr, dr
384 movem.l (sp)+, d2-d7/a2
390 movea.l #0xc00004, a0
391 movea.l #0xc00008, a1
402 movea.l #0xff0000, a1
403 movea.l #0xff0000, a1
422 .macro ymwrite areg, dreg addr dat
423 move.b \addr, (\areg) /* 12 addr */
424 nbcd d0 /* 6 delay to reach 17 ym cycles (M/7) */
425 move.b \dat, (\dreg) /* 12 data */
428 .global test_ym_stopped_tick
429 test_ym_stopped_tick:
431 movea.l #0xa04000, a0
432 movea.l #0xa04001, a1
433 movea.l #0xc00007, a2
434 movea.l #0xfff000, a3
436 ymwrite a0, a1, #0x27, #0x30 /* 30 disable, clear */
437 ymwrite a0, a1, #0x26, #0xff /* 30 timer b shortest interval */
438 move.b #0x27, (a0) /* 12 addr prep */
441 beq 0b /* not blanking */
444 bne 0b /* blanking */
449 bne 0b /* not line 0 - waiting for sequential vcnt */
451 move.b #0x0a, (a1) /* 12 start timer b */
459 # move.w (a2), (a3)+ /* 12 save hvcnt */
464 move.b #0x30, (a1) /* 12 stop b, clear */
466 move.w #(1900/10-1), d0 /* waste cycles */
471 move.w (a0), (a3)+ /* 12 save status */
472 move.b #0x0a, (a1) /* 12 start b */
479 # move.w (a2), (a3)+ /* 12 save hvcnt */
484 move.w d0, (a3)+ /* 12 save status */
489 .global test_ym_ab_sync
491 movea.l #0xa04000, a0
492 movea.l #0xa04001, a1
494 ymwrite a0, a1, #0x27, #0x30 /* 30 disable, clear */
495 ymwrite a0, a1, #0x24, #0xfc /* 30 timer a */
496 ymwrite a0, a1, #0x25, #0x01 /* 30 =15 */
497 ymwrite a0, a1, #0x26, #0xff /* 30 timer b shortest interval */
498 move.b #0x27, (a0) /* 12 addr prep */
502 move.b #0x0a, (a1) /* 12 start timer b */
506 move.b (a0), d0 /* 8 */
510 move.b #0x3f, (a1) /* 12 start a, clear */
512 move.w #(488/10), d0 /* waste cycles */
515 ymwrite a0, a1, #0x24, #0xf0 /* 30 show that rewriting count */
516 ymwrite a0, a1, #0x25, #0x00 /* 30 does nothing until timer expires */
518 move.w #(488*2/10), d0 /* waste cycles */
521 ymwrite a0, a1, #0x26, #0xfc /* 30 same for timer b */
522 ymwrite a0, a1, #0x27, #0x0f /* 30 setting already set bits too */
529 move.b (a0), d0 /* re-read, else very occasionally get 1 */
532 .global test_ym_ab_sync2
534 movea.l #0xa04000, a0
535 movea.l #0xa04001, a1
537 move.b #0x0f, (a1) /* 12 enable */
540 nop /* 4 need ~12c to clear */
542 move.b (a0), d0 /* 8 */
545 move.b (a0), d0 /* re-read */
546 move.b #0x3c, (a1) /* 12 clear, disable */
549 # vim:filetype=asmM68k:ts=4:sw=4:expandtab