3 * (C) notaz, 2009,2010,2013
5 * This work is licensed under the terms of MAME license.
6 * See COPYING file in the top-level directory.
9 * - tcache, block descriptor, link buffer overflows result in sh2_translate()
10 * failure, followed by full tcache invalidation for that region
11 * - jumps between blocks are tracked for SMC handling (in block_entry->links),
12 * except jumps between different tcaches
15 * - static register allocation
16 * - remaining register caching and tracking in temporaries
17 * - block-local branch linking
18 * - block linking (except between tcaches)
19 * - some constant propagation
22 * - better constant propagation
31 #include "../../pico/pico_int.h"
32 #include "../../pico/arm_features.h"
35 #include "../drc/cmn.h"
39 #define PROPAGATE_CONSTANTS 1
40 #define LINK_BRANCHES 1
43 #define MAX_BLOCK_SIZE (BLOCK_INSN_LIMIT * 6 * 6)
45 // max literal offset from the block end
46 #define MAX_LITERAL_OFFSET 32*2
47 #define MAX_LITERALS (BLOCK_INSN_LIMIT / 4)
48 #define MAX_LOCAL_BRANCHES 32
51 // 01 - warnings/errors
52 // 02 - block info/smc
54 // 08 - runtime block entry log
55 // 10 - smc self-check
62 #define dbg(l,...) { \
63 if ((l) & DRC_DEBUG) \
64 elprintf(EL_STATUS, ##__VA_ARGS__); \
66 #include "mame/sh2dasm.h"
67 #include <platform/libpicofe/linux/host_dasm.h>
68 static int insns_compiled, hash_collisions, host_insn_count;
77 #define FETCH_OP(pc) \
81 ((dr_pc_base[(a) / 2] << 16) | dr_pc_base[(a) / 2 + 1])
83 #define CHECK_UNHANDLED_BITS(mask, label) { \
84 if ((op & (mask)) != 0) \
96 #define BITMASK1(v0) (1 << (v0))
97 #define BITMASK2(v0,v1) ((1 << (v0)) | (1 << (v1)))
98 #define BITMASK3(v0,v1,v2) (BITMASK2(v0,v1) | (1 << (v2)))
99 #define BITMASK4(v0,v1,v2,v3) (BITMASK3(v0,v1,v2) | (1 << (v3)))
100 #define BITMASK5(v0,v1,v2,v3,v4) (BITMASK4(v0,v1,v2,v3) | (1 << (v4)))
102 #define SHR_T SHR_SR // might make them separate someday
104 static struct op_data {
107 u8 size; // 0, 1, 2 - byte, word, long
108 s8 rm; // branch or load/store data reg
109 u32 source; // bitmask of src regs
110 u32 dest; // bitmask of dest regs
111 u32 imm; // immediate/io address/branch target
112 // (for literal - address, not value)
113 } ops[BLOCK_INSN_LIMIT];
118 OP_BRANCH_CT, // conditional, branch if T set
119 OP_BRANCH_CF, // conditional, branch if T clear
120 OP_BRANCH_R, // indirect
121 OP_BRANCH_RF, // indirect far (PC + Rm)
122 OP_SETCLRT, // T flag set/clear
123 OP_MOVE, // register move
124 OP_LOAD_POOL, // literal pool load, imm is address
132 static int literal_disabled_frames;
135 static u8 *tcache_dsm_ptrs[3];
136 static char sh2dasm_buff[64];
137 #define do_host_disasm(tcid) \
138 host_dasm(tcache_dsm_ptrs[tcid], tcache_ptr - tcache_dsm_ptrs[tcid]); \
139 tcache_dsm_ptrs[tcid] = tcache_ptr
141 #define do_host_disasm(x)
144 #if (DRC_DEBUG & 8) || defined(PDB)
145 static void REGPARM(3) *sh2_drc_log_entry(void *block, SH2 *sh2, u32 sr)
148 dbg(8, "= %csh2 enter %08x %p, c=%d", sh2->is_slave ? 's' : 'm',
149 sh2->pc, block, (signed int)sr >> 12);
150 pdb_step(sh2, sh2->pc);
157 #define TCACHE_BUFFERS 3
159 // we have 3 translation cache buffers, split from one drc/cmn buffer.
160 // BIOS shares tcache with data array because it's only used for init
161 // and can be discarded early
162 // XXX: need to tune sizes
163 static const int tcache_sizes[TCACHE_BUFFERS] = {
164 DRC_TCACHE_SIZE * 6 / 8, // ROM (rarely used), DRAM
165 DRC_TCACHE_SIZE / 8, // BIOS, data array in master sh2
166 DRC_TCACHE_SIZE / 8, // ... slave
169 static u8 *tcache_bases[TCACHE_BUFFERS];
170 static u8 *tcache_ptrs[TCACHE_BUFFERS];
172 // ptr for code emiters
173 static u8 *tcache_ptr;
175 #define MAX_BLOCK_ENTRIES (BLOCK_INSN_LIMIT / 8)
179 void *jump; // insn address
180 struct block_link *next; // either in block_entry->links or
185 void *tcache_ptr; // translated block for above PC
186 struct block_entry *next; // next block in hash_table with same pc hash
187 struct block_link *links; // links to this entry
189 struct block_desc *block;
194 u32 addr; // block start SH2 PC address
195 u16 size; // ..of recompiled insns+lit. pool
196 u16 size_nolit; // same without literals
201 struct block_entry entryp[MAX_BLOCK_ENTRIES];
204 static const int block_max_counts[TCACHE_BUFFERS] = {
209 static struct block_desc *block_tables[TCACHE_BUFFERS];
210 static int block_counts[TCACHE_BUFFERS];
212 // we have block_link_pool to avoid using mallocs
213 static const int block_link_pool_max_counts[TCACHE_BUFFERS] = {
218 static struct block_link *block_link_pool[TCACHE_BUFFERS];
219 static int block_link_pool_counts[TCACHE_BUFFERS];
220 static struct block_link *unresolved_links[TCACHE_BUFFERS];
222 // used for invalidation
223 static const int ram_sizes[TCACHE_BUFFERS] = {
228 #define INVAL_PAGE_SIZE 0x100
231 struct block_desc *block;
232 struct block_list *next;
235 // array of pointers to block_lists for RAM and 2 data arrays
236 // each array has len: sizeof(mem) / INVAL_PAGE_SIZE
237 static struct block_list **inval_lookup[TCACHE_BUFFERS];
239 static const int hash_table_sizes[TCACHE_BUFFERS] = {
244 static struct block_entry **hash_tables[TCACHE_BUFFERS];
246 #define HASH_FUNC(hash_tab, addr, mask) \
247 (hash_tab)[(((addr) >> 20) ^ ((addr) >> 2)) & (mask)]
249 // host register tracking
252 HR_CACHED, // 'val' has sh2_reg_e
253 // HR_CONST, // 'val' has a constant
254 HR_TEMP, // reg used for temp storage
258 HRF_DIRTY = 1 << 0, // reg has "dirty" value to be written to ctx
259 HRF_LOCKED = 1 << 1, // HR_CACHED can't be evicted
263 u32 hreg:5; // "host" reg
264 u32 greg:5; // "guest" reg
267 u32 stamp:16; // kind of a timestamp
270 // note: reg_temp[] must have at least the amount of
271 // registers used by handlers in worst case (currently 4)
273 #include "../drc/emit_arm.c"
277 static const int reg_map_g2h[] = {
281 -1, -1, -1, 9, // r12 .. sp
282 -1, -1, -1, 10, // SHR_PC, SHR_PPC, SHR_PR, SHR_SR,
283 -1, -1, -1, -1, // SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,
289 static const int reg_map_g2h[] = {
293 -1, -1, -1, 8, // r12 .. sp
294 -1, -1, -1, 10, // SHR_PC, SHR_PPC, SHR_PR, SHR_SR,
295 -1, -1, -1, -1, // SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,
300 static temp_reg_t reg_temp[] = {
309 #elif defined(__i386__)
310 #include "../drc/emit_x86.c"
312 static const int reg_map_g2h[] = {
321 // ax, cx, dx are usually temporaries by convention
322 static temp_reg_t reg_temp[] = {
329 #elif defined(__x86_64__)
330 #include "../drc/emit_x86.c"
332 static const int reg_map_g2h[] = {
341 // ax, cx, dx are usually temporaries by convention
342 static temp_reg_t reg_temp[] = {
351 #error unsupported arch
359 #define T_save 0x00000800
365 static void REGPARM(1) (*sh2_drc_entry)(SH2 *sh2);
366 static void (*sh2_drc_dispatcher)(void);
367 static void (*sh2_drc_exit)(void);
368 static void (*sh2_drc_test_irq)(void);
370 static u32 REGPARM(2) (*sh2_drc_read8)(u32 a, SH2 *sh2);
371 static u32 REGPARM(2) (*sh2_drc_read16)(u32 a, SH2 *sh2);
372 static u32 REGPARM(2) (*sh2_drc_read32)(u32 a, SH2 *sh2);
373 static void REGPARM(2) (*sh2_drc_write8)(u32 a, u32 d);
374 static void REGPARM(2) (*sh2_drc_write16)(u32 a, u32 d);
375 static void REGPARM(3) (*sh2_drc_write32)(u32 a, u32 d, SH2 *sh2);
377 // address space stuff
378 static int dr_ctx_get_mem_ptr(u32 a, u32 *mask)
382 if ((a & ~0x7ff) == 0) {
384 poffs = offsetof(SH2, p_bios);
387 else if ((a & 0xfffff000) == 0xc0000000) {
389 // FIXME: access sh2->data_array instead
390 poffs = offsetof(SH2, p_da);
393 else if ((a & 0xc6000000) == 0x06000000) {
395 poffs = offsetof(SH2, p_sdram);
398 else if ((a & 0xc6000000) == 0x02000000) {
400 poffs = offsetof(SH2, p_rom);
407 static struct block_entry *dr_get_entry(u32 pc, int is_slave, int *tcache_id)
409 struct block_entry *be;
412 // data arrays have their own caches
413 if ((pc & 0xe0000000) == 0xc0000000 || (pc & ~0xfff) == 0)
418 mask = hash_table_sizes[tcid] - 1;
419 be = HASH_FUNC(hash_tables[tcid], pc, mask);
420 for (; be != NULL; be = be->next)
427 // ---------------------------------------------------------------
430 static void add_to_block_list(struct block_list **blist, struct block_desc *block)
432 struct block_list *added = malloc(sizeof(*added));
434 elprintf(EL_ANOMALY, "drc OOM (1)");
437 added->block = block;
438 added->next = *blist;
442 static void rm_from_block_list(struct block_list **blist, struct block_desc *block)
444 struct block_list *prev = NULL, *current = *blist;
445 for (; current != NULL; current = current->next) {
446 if (current->block == block) {
448 *blist = current->next;
450 prev->next = current->next;
456 dbg(1, "can't rm block %p (%08x-%08x)",
457 block, block->addr, block->addr + block->size);
460 static void rm_block_list(struct block_list **blist)
462 struct block_list *tmp, *current = *blist;
463 while (current != NULL) {
465 current = current->next;
471 static void REGPARM(1) flush_tcache(int tcid)
475 dbg(1, "tcache #%d flush! (%d/%d, bds %d/%d)", tcid,
476 tcache_ptrs[tcid] - tcache_bases[tcid], tcache_sizes[tcid],
477 block_counts[tcid], block_max_counts[tcid]);
479 block_counts[tcid] = 0;
480 block_link_pool_counts[tcid] = 0;
481 unresolved_links[tcid] = NULL;
482 memset(hash_tables[tcid], 0, sizeof(*hash_tables[0]) * hash_table_sizes[tcid]);
483 tcache_ptrs[tcid] = tcache_bases[tcid];
484 if (Pico32xMem != NULL) {
485 if (tcid == 0) // ROM, RAM
486 memset(Pico32xMem->drcblk_ram, 0,
487 sizeof(Pico32xMem->drcblk_ram));
489 memset(Pico32xMem->drcblk_da[tcid - 1], 0,
490 sizeof(Pico32xMem->drcblk_da[0]));
493 tcache_dsm_ptrs[tcid] = tcache_bases[tcid];
496 for (i = 0; i < ram_sizes[tcid] / INVAL_PAGE_SIZE; i++)
497 rm_block_list(&inval_lookup[tcid][i]);
500 static void add_to_hashlist(struct block_entry *be, int tcache_id)
502 u32 tcmask = hash_table_sizes[tcache_id] - 1;
504 be->next = HASH_FUNC(hash_tables[tcache_id], be->pc, tcmask);
505 HASH_FUNC(hash_tables[tcache_id], be->pc, tcmask) = be;
508 if (be->next != NULL) {
509 printf(" %08x: hash collision with %08x\n",
510 be->pc, be->next->pc);
516 static void rm_from_hashlist(struct block_entry *be, int tcache_id)
518 u32 tcmask = hash_table_sizes[tcache_id] - 1;
519 struct block_entry *cur, *prev;
521 cur = HASH_FUNC(hash_tables[tcache_id], be->pc, tcmask);
525 if (be == cur) { // first
526 HASH_FUNC(hash_tables[tcache_id], be->pc, tcmask) = be->next;
530 for (prev = cur, cur = cur->next; cur != NULL; cur = cur->next) {
532 prev->next = cur->next;
538 dbg(1, "rm_from_hashlist: be %p %08x missing?", be, be->pc);
541 static void unregister_links(struct block_entry *be, int tcache_id)
543 struct block_link *bl_unresolved = unresolved_links[tcache_id];
544 struct block_link *bl, *bl_next;
546 for (bl = be->links; bl != NULL; ) {
548 bl->next = bl_unresolved;
553 unresolved_links[tcache_id] = bl_unresolved;
556 // unlike sh2_smc_rm_block, the block stays and can still be accessed
557 // by other already directly linked blocks, just not preferred
558 static void kill_block_entry(struct block_entry *be, int tcache_id)
560 rm_from_hashlist(be, tcache_id);
561 unregister_links(be, tcache_id);
564 static struct block_desc *dr_add_block(u32 addr, u16 size_lit,
565 u16 size_nolit, int is_slave, int *blk_id)
567 struct block_entry *be;
568 struct block_desc *bd;
572 // do a lookup to get tcache_id and override check
573 be = dr_get_entry(addr, is_slave, &tcache_id);
575 dbg(1, "block override for %08x, was %p", addr, be->tcache_ptr);
576 kill_block_entry(be, tcache_id);
579 bcount = &block_counts[tcache_id];
580 if (*bcount >= block_max_counts[tcache_id]) {
581 dbg(1, "bd overflow for tcache %d", tcache_id);
585 bd = &block_tables[tcache_id][*bcount];
588 bd->size_nolit = size_nolit;
591 bd->entryp[0].pc = addr;
592 bd->entryp[0].tcache_ptr = tcache_ptr;
593 bd->entryp[0].links = NULL;
595 bd->entryp[0].block = bd;
598 add_to_hashlist(&bd->entryp[0], tcache_id);
606 static void REGPARM(3) *dr_lookup_block(u32 pc, int is_slave, int *tcache_id)
608 struct block_entry *be = NULL;
611 be = dr_get_entry(pc, is_slave, tcache_id);
613 block = be->tcache_ptr;
617 be->block->refcount++;
622 static void *dr_failure(void)
624 lprintf("recompilation failed\n");
628 static void *dr_prepare_ext_branch(u32 pc, int is_slave, int tcache_id)
631 struct block_link *bl = block_link_pool[tcache_id];
632 int cnt = block_link_pool_counts[tcache_id];
633 struct block_entry *be = NULL;
634 int target_tcache_id;
637 be = dr_get_entry(pc, is_slave, &target_tcache_id);
638 if (target_tcache_id != tcache_id)
639 return sh2_drc_dispatcher;
641 // if pool has been freed, reuse
642 for (i = cnt - 1; i >= 0; i--)
643 if (bl[i].target_pc != 0)
646 if (cnt >= block_link_pool_max_counts[tcache_id]) {
647 dbg(1, "bl overflow for tcache %d", tcache_id);
651 block_link_pool_counts[tcache_id]++;
654 bl->jump = tcache_ptr;
657 dbg(2, "- early link from %p to pc %08x", bl->jump, pc);
658 bl->next = be->links;
660 return be->tcache_ptr;
663 bl->next = unresolved_links[tcache_id];
664 unresolved_links[tcache_id] = bl;
665 return sh2_drc_dispatcher;
668 return sh2_drc_dispatcher;
672 static void dr_link_blocks(struct block_entry *be, int tcache_id)
675 struct block_link *first = unresolved_links[tcache_id];
676 struct block_link *bl, *prev, *tmp;
679 for (bl = prev = first; bl != NULL; ) {
680 if (bl->target_pc == pc) {
681 dbg(2, "- link from %p to pc %08x", bl->jump, pc);
682 emith_jump_patch(bl->jump, tcache_ptr);
684 // move bl from unresolved_links to block_entry
686 bl->next = be->links;
690 first = prev = bl = tmp;
692 prev->next = bl = tmp;
698 unresolved_links[tcache_id] = first;
700 // could sync arm caches here, but that's unnecessary
704 #define ADD_TO_ARRAY(array, count, item, failcode) \
705 if (count >= ARRAY_SIZE(array)) { \
706 dbg(1, "warning: " #array " overflow"); \
709 array[count++] = item;
711 static int find_in_array(u32 *array, size_t size, u32 what)
714 for (i = 0; i < size; i++)
715 if (what == array[i])
721 // ---------------------------------------------------------------
723 // register cache / constant propagation stuff
730 static int rcache_get_reg_(sh2_reg_e r, rc_gr_mode mode, int do_locking);
732 // guest regs with constants
733 static u32 dr_gcregs[24];
734 // a mask of constant/dirty regs
735 static u32 dr_gcregs_mask;
736 static u32 dr_gcregs_dirty;
738 #if PROPAGATE_CONSTANTS
739 static void gconst_new(sh2_reg_e r, u32 val)
743 dr_gcregs_mask |= 1 << r;
744 dr_gcregs_dirty |= 1 << r;
747 // throw away old r that we might have cached
748 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
749 if ((reg_temp[i].type == HR_CACHED) &&
750 reg_temp[i].greg == r) {
751 reg_temp[i].type = HR_FREE;
752 reg_temp[i].flags = 0;
758 static int gconst_get(sh2_reg_e r, u32 *val)
760 if (dr_gcregs_mask & (1 << r)) {
767 static int gconst_check(sh2_reg_e r)
769 if ((dr_gcregs_mask | dr_gcregs_dirty) & (1 << r))
774 // update hr if dirty, else do nothing
775 static int gconst_try_read(int hr, sh2_reg_e r)
777 if (dr_gcregs_dirty & (1 << r)) {
778 emith_move_r_imm(hr, dr_gcregs[r]);
779 dr_gcregs_dirty &= ~(1 << r);
785 static void gconst_check_evict(sh2_reg_e r)
787 if (dr_gcregs_mask & (1 << r))
788 // no longer cached in reg, make dirty again
789 dr_gcregs_dirty |= 1 << r;
792 static void gconst_kill(sh2_reg_e r)
794 dr_gcregs_mask &= ~(1 << r);
795 dr_gcregs_dirty &= ~(1 << r);
798 static void gconst_clean(void)
802 for (i = 0; i < ARRAY_SIZE(dr_gcregs); i++)
803 if (dr_gcregs_dirty & (1 << i)) {
804 // using RC_GR_READ here: it will call gconst_try_read,
805 // cache the reg and mark it dirty.
806 rcache_get_reg_(i, RC_GR_READ, 0);
810 static void gconst_invalidate(void)
812 dr_gcregs_mask = dr_gcregs_dirty = 0;
815 static u16 rcache_counter;
817 static temp_reg_t *rcache_evict(void)
819 // evict reg with oldest stamp
821 u16 min_stamp = (u16)-1;
823 for (i = 0; i < ARRAY_SIZE(reg_temp); i++) {
824 if (reg_temp[i].type == HR_CACHED && !(reg_temp[i].flags & HRF_LOCKED) &&
825 reg_temp[i].stamp <= min_stamp) {
826 min_stamp = reg_temp[i].stamp;
832 printf("no registers to evict, aborting\n");
837 if (reg_temp[i].type == HR_CACHED) {
838 if (reg_temp[i].flags & HRF_DIRTY)
840 emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4);
841 gconst_check_evict(reg_temp[i].greg);
844 reg_temp[i].type = HR_FREE;
845 reg_temp[i].flags = 0;
849 static int get_reg_static(sh2_reg_e r, rc_gr_mode mode)
851 int i = reg_map_g2h[r];
853 if (mode != RC_GR_WRITE)
854 gconst_try_read(i, r);
859 // note: must not be called when doing conditional code
860 static int rcache_get_reg_(sh2_reg_e r, rc_gr_mode mode, int do_locking)
865 // maybe statically mapped?
866 ret = get_reg_static(r, mode);
872 // maybe already cached?
873 // if so, prefer against gconst (they must be in sync)
874 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
875 if (reg_temp[i].type == HR_CACHED && reg_temp[i].greg == r) {
876 reg_temp[i].stamp = rcache_counter;
877 if (mode != RC_GR_READ)
878 reg_temp[i].flags |= HRF_DIRTY;
879 ret = reg_temp[i].hreg;
885 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
886 if (reg_temp[i].type == HR_FREE) {
895 tr->type = HR_CACHED;
897 tr->flags |= HRF_LOCKED;
898 if (mode != RC_GR_READ)
899 tr->flags |= HRF_DIRTY;
901 tr->stamp = rcache_counter;
904 if (mode != RC_GR_WRITE) {
905 if (gconst_check(r)) {
906 if (gconst_try_read(ret, r))
907 tr->flags |= HRF_DIRTY;
910 emith_ctx_read(tr->hreg, r * 4);
914 if (mode != RC_GR_READ)
920 static int rcache_get_reg(sh2_reg_e r, rc_gr_mode mode)
922 return rcache_get_reg_(r, mode, 1);
925 static int rcache_get_tmp(void)
930 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
931 if (reg_temp[i].type == HR_FREE) {
943 static int rcache_get_hr_id(int hr)
947 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
948 if (reg_temp[i].hreg == hr)
951 if (i == ARRAY_SIZE(reg_temp)) // can't happen
954 if (reg_temp[i].type == HR_CACHED) {
956 if (reg_temp[i].flags & HRF_DIRTY)
957 emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4);
958 gconst_check_evict(reg_temp[i].greg);
960 else if (reg_temp[i].type == HR_TEMP) {
961 printf("host reg %d already used, aborting\n", hr);
965 reg_temp[i].type = HR_FREE;
966 reg_temp[i].flags = 0;
971 static int rcache_get_arg_id(int arg)
974 host_arg2reg(r, arg);
975 return rcache_get_hr_id(r);
978 // get a reg to be used as function arg
979 static int rcache_get_tmp_arg(int arg)
981 int id = rcache_get_arg_id(arg);
982 reg_temp[id].type = HR_TEMP;
984 return reg_temp[id].hreg;
987 // ... as return value after a call
988 static int rcache_get_tmp_ret(void)
990 int id = rcache_get_hr_id(RET_REG);
991 reg_temp[id].type = HR_TEMP;
993 return reg_temp[id].hreg;
996 // same but caches a reg. RC_GR_READ only.
997 static int rcache_get_reg_arg(int arg, sh2_reg_e r)
999 int i, srcr, dstr, dstid;
1000 int dirty = 0, src_dirty = 0;
1002 dstid = rcache_get_arg_id(arg);
1003 dstr = reg_temp[dstid].hreg;
1005 // maybe already statically mapped?
1006 srcr = get_reg_static(r, RC_GR_READ);
1010 // maybe already cached?
1011 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
1012 if ((reg_temp[i].type == HR_CACHED) &&
1013 reg_temp[i].greg == r)
1015 srcr = reg_temp[i].hreg;
1016 if (reg_temp[i].flags & HRF_DIRTY)
1024 if (gconst_check(r)) {
1025 if (gconst_try_read(srcr, r))
1029 emith_ctx_read(srcr, r * 4);
1033 emith_move_r_r(dstr, srcr);
1039 // must clean, callers might want to modify the arg before call
1040 emith_ctx_write(dstr, r * 4);
1043 reg_temp[dstid].flags |= HRF_DIRTY;
1046 reg_temp[dstid].stamp = ++rcache_counter;
1047 reg_temp[dstid].type = HR_CACHED;
1048 reg_temp[dstid].greg = r;
1049 reg_temp[dstid].flags |= HRF_LOCKED;
1053 static void rcache_free_tmp(int hr)
1056 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
1057 if (reg_temp[i].hreg == hr)
1060 if (i == ARRAY_SIZE(reg_temp) || reg_temp[i].type != HR_TEMP) {
1061 printf("rcache_free_tmp fail: #%i hr %d, type %d\n", i, hr, reg_temp[i].type);
1065 reg_temp[i].type = HR_FREE;
1066 reg_temp[i].flags = 0;
1069 static void rcache_unlock(int hr)
1072 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
1073 if (reg_temp[i].type == HR_CACHED && reg_temp[i].hreg == hr)
1074 reg_temp[i].flags &= ~HRF_LOCKED;
1077 static void rcache_unlock_all(void)
1080 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
1081 reg_temp[i].flags &= ~HRF_LOCKED;
1085 static u32 rcache_used_hreg_mask(void)
1090 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
1091 if (reg_temp[i].type != HR_FREE)
1092 mask |= 1 << reg_temp[i].hreg;
1098 static void rcache_clean(void)
1103 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
1104 if (reg_temp[i].type == HR_CACHED && (reg_temp[i].flags & HRF_DIRTY)) {
1106 emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4);
1107 reg_temp[i].flags &= ~HRF_DIRTY;
1111 static void rcache_invalidate(void)
1114 for (i = 0; i < ARRAY_SIZE(reg_temp); i++) {
1115 reg_temp[i].type = HR_FREE;
1116 reg_temp[i].flags = 0;
1120 gconst_invalidate();
1123 static void rcache_flush(void)
1126 rcache_invalidate();
1129 // ---------------------------------------------------------------
1131 static int emit_get_rbase_and_offs(u32 a, u32 *offs)
1137 poffs = dr_ctx_get_mem_ptr(a, &mask);
1141 // XXX: could use some related reg
1142 hr = rcache_get_tmp();
1143 emith_ctx_read_ptr(hr, poffs);
1144 emith_add_r_r_ptr_imm(hr, hr, a & mask & ~0xff);
1145 *offs = a & 0xff; // XXX: ARM oriented..
1149 static void emit_move_r_imm32(sh2_reg_e dst, u32 imm)
1151 #if PROPAGATE_CONSTANTS
1152 gconst_new(dst, imm);
1154 int hr = rcache_get_reg(dst, RC_GR_WRITE);
1155 emith_move_r_imm(hr, imm);
1159 static void emit_move_r_r(sh2_reg_e dst, sh2_reg_e src)
1161 int hr_d = rcache_get_reg(dst, RC_GR_WRITE);
1162 int hr_s = rcache_get_reg(src, RC_GR_READ);
1164 emith_move_r_r(hr_d, hr_s);
1167 // T must be clear, and comparison done just before this
1168 static void emit_or_t_if_eq(int srr)
1170 EMITH_SJMP_START(DCOND_NE);
1171 emith_or_r_imm_c(DCOND_EQ, srr, T);
1172 EMITH_SJMP_END(DCOND_NE);
1175 // arguments must be ready
1176 // reg cache must be clean before call
1177 static int emit_memhandler_read_(int size, int ram_check)
1182 host_arg2reg(arg0, 0);
1187 // must writeback cycles for poll detection stuff
1189 if (reg_map_g2h[SHR_SR] != -1)
1190 emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
1192 arg1 = rcache_get_tmp_arg(1);
1193 emith_move_r_r_ptr(arg1, CONTEXT_REG);
1195 #if 0 // can't do this because of unmapped reads
1197 if (ram_check && Pico.rom == (void *)0x02000000 && Pico32xMem->sdram == (void *)0x06000000) {
1198 int tmp = rcache_get_tmp();
1199 emith_and_r_r_imm(tmp, arg0, 0xfb000000);
1200 emith_cmp_r_imm(tmp, 0x02000000);
1203 EMITH_SJMP3_START(DCOND_NE);
1204 emith_eor_r_imm_c(DCOND_EQ, arg0, 1);
1205 emith_read8_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
1206 EMITH_SJMP3_MID(DCOND_NE);
1207 emith_call_cond(DCOND_NE, sh2_drc_read8);
1211 EMITH_SJMP3_START(DCOND_NE);
1212 emith_read16_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
1213 EMITH_SJMP3_MID(DCOND_NE);
1214 emith_call_cond(DCOND_NE, sh2_drc_read16);
1218 EMITH_SJMP3_START(DCOND_NE);
1219 emith_read_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
1220 emith_ror_c(DCOND_EQ, arg0, arg0, 16);
1221 EMITH_SJMP3_MID(DCOND_NE);
1222 emith_call_cond(DCOND_NE, sh2_drc_read32);
1232 emith_call(sh2_drc_read8);
1235 emith_call(sh2_drc_read16);
1238 emith_call(sh2_drc_read32);
1242 rcache_invalidate();
1244 if (reg_map_g2h[SHR_SR] != -1)
1245 emith_ctx_read(reg_map_g2h[SHR_SR], SHR_SR * 4);
1247 return rcache_get_tmp_ret();
1250 static int emit_memhandler_read(int size)
1252 return emit_memhandler_read_(size, 1);
1255 static int emit_memhandler_read_rr(sh2_reg_e rd, sh2_reg_e rs, u32 offs, int size)
1257 int hr, hr2, ram_check = 1;
1260 if (gconst_get(rs, &val)) {
1261 hr = emit_get_rbase_and_offs(val + offs, &offs2);
1263 hr2 = rcache_get_reg(rd, RC_GR_WRITE);
1266 emith_read8_r_r_offs(hr2, hr, offs2 ^ 1);
1267 emith_sext(hr2, hr2, 8);
1270 emith_read16_r_r_offs(hr2, hr, offs2);
1271 emith_sext(hr2, hr2, 16);
1274 emith_read_r_r_offs(hr2, hr, offs2);
1275 emith_ror(hr2, hr2, 16);
1278 rcache_free_tmp(hr);
1285 hr = rcache_get_reg_arg(0, rs);
1287 emith_add_r_imm(hr, offs);
1288 hr = emit_memhandler_read_(size, ram_check);
1289 hr2 = rcache_get_reg(rd, RC_GR_WRITE);
1291 emith_sext(hr2, hr, (size == 1) ? 16 : 8);
1293 emith_move_r_r(hr2, hr);
1294 rcache_free_tmp(hr);
1299 static void emit_memhandler_write(int size)
1302 host_arg2reg(ctxr, 2);
1303 if (reg_map_g2h[SHR_SR] != -1)
1304 emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
1310 // XXX: consider inlining sh2_drc_write8
1311 emith_call(sh2_drc_write8);
1314 emith_call(sh2_drc_write16);
1317 emith_move_r_r_ptr(ctxr, CONTEXT_REG);
1318 emith_call(sh2_drc_write32);
1322 rcache_invalidate();
1323 if (reg_map_g2h[SHR_SR] != -1)
1324 emith_ctx_read(reg_map_g2h[SHR_SR], SHR_SR * 4);
1328 static int emit_indirect_indexed_read(int rx, int ry, int size)
1331 a0 = rcache_get_reg_arg(0, rx);
1332 t = rcache_get_reg(ry, RC_GR_READ);
1333 emith_add_r_r(a0, t);
1334 return emit_memhandler_read(size);
1338 static void emit_indirect_read_double(u32 *rnr, u32 *rmr, int rn, int rm, int size)
1342 rcache_get_reg_arg(0, rn);
1343 tmp = emit_memhandler_read(size);
1344 emith_ctx_write(tmp, offsetof(SH2, drc_tmp));
1345 rcache_free_tmp(tmp);
1346 tmp = rcache_get_reg(rn, RC_GR_RMW);
1347 emith_add_r_imm(tmp, 1 << size);
1350 rcache_get_reg_arg(0, rm);
1351 *rmr = emit_memhandler_read(size);
1352 *rnr = rcache_get_tmp();
1353 emith_ctx_read(*rnr, offsetof(SH2, drc_tmp));
1354 tmp = rcache_get_reg(rm, RC_GR_RMW);
1355 emith_add_r_imm(tmp, 1 << size);
1359 static void emit_do_static_regs(int is_write, int tmpr)
1363 for (i = 0; i < ARRAY_SIZE(reg_map_g2h); i++) {
1368 for (count = 1; i < ARRAY_SIZE(reg_map_g2h) - 1; i++, r++) {
1369 if (reg_map_g2h[i + 1] != r + 1)
1375 // i, r point to last item
1377 emith_ctx_write_multiple(r - count + 1, (i - count + 1) * 4, count, tmpr);
1379 emith_ctx_read_multiple(r - count + 1, (i - count + 1) * 4, count, tmpr);
1382 emith_ctx_write(r, i * 4);
1384 emith_ctx_read(r, i * 4);
1389 /* just after lookup function, jump to address returned */
1390 static void emit_block_entry(void)
1392 #if (DRC_DEBUG & 8) || defined(PDB)
1394 host_arg2reg(arg1, 1);
1395 host_arg2reg(arg2, 2);
1397 emit_do_static_regs(1, arg2);
1398 emith_move_r_r_ptr(arg1, CONTEXT_REG);
1399 emith_move_r_r(arg2, rcache_get_reg(SHR_SR, RC_GR_READ));
1400 emith_call(sh2_drc_log_entry);
1401 rcache_invalidate();
1403 emith_tst_r_r(RET_REG, RET_REG);
1404 EMITH_SJMP_START(DCOND_EQ);
1405 emith_jump_reg_c(DCOND_NE, RET_REG);
1406 EMITH_SJMP_END(DCOND_EQ);
1409 #define DELAY_SAVE_T(sr) { \
1410 emith_bic_r_imm(sr, T_save); \
1411 emith_tst_r_imm(sr, T); \
1412 EMITH_SJMP_START(DCOND_EQ); \
1413 emith_or_r_imm_c(DCOND_NE, sr, T_save); \
1414 EMITH_SJMP_END(DCOND_EQ); \
1417 #define FLUSH_CYCLES(sr) \
1419 emith_sub_r_imm(sr, cycles << 12); \
1423 static void *dr_get_pc_base(u32 pc, int is_slave);
1425 static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
1427 u32 branch_target_pc[MAX_LOCAL_BRANCHES];
1428 void *branch_target_ptr[MAX_LOCAL_BRANCHES];
1429 int branch_target_count = 0;
1430 void *branch_patch_ptr[MAX_LOCAL_BRANCHES];
1431 u32 branch_patch_pc[MAX_LOCAL_BRANCHES];
1432 int branch_patch_count = 0;
1433 u32 literal_addr[MAX_LITERALS];
1434 int literal_addr_count = 0;
1435 u8 op_flags[BLOCK_INSN_LIMIT];
1438 u32 pending_branch_direct:1;
1439 u32 pending_branch_indirect:1;
1440 u32 literals_disabled:1;
1443 // PC of current, first, last SH2 insn
1444 u32 pc, base_pc, end_pc;
1446 void *block_entry_ptr;
1447 struct block_desc *block;
1449 struct op_data *opd;
1458 drcf.literals_disabled = literal_disabled_frames != 0;
1460 // get base/validate PC
1461 dr_pc_base = dr_get_pc_base(base_pc, sh2->is_slave);
1462 if (dr_pc_base == (void *)-1) {
1463 printf("invalid PC, aborting: %08x\n", base_pc);
1464 // FIXME: be less destructive
1468 tcache_ptr = tcache_ptrs[tcache_id];
1470 // predict tcache overflow
1471 tmp = tcache_ptr - tcache_bases[tcache_id];
1472 if (tmp > tcache_sizes[tcache_id] - MAX_BLOCK_SIZE) {
1473 dbg(1, "tcache %d overflow", tcache_id);
1477 // initial passes to disassemble and analyze the block
1478 scan_block(base_pc, sh2->is_slave, op_flags, &end_pc, &end_literals);
1480 if (drcf.literals_disabled)
1481 end_literals = end_pc;
1483 block = dr_add_block(base_pc, end_literals - base_pc,
1484 end_pc - base_pc, sh2->is_slave, &blkid_main);
1488 block_entry_ptr = tcache_ptr;
1489 dbg(2, "== %csh2 block #%d,%d %08x-%08x -> %p", sh2->is_slave ? 's' : 'm',
1490 tcache_id, blkid_main, base_pc, end_pc, block_entry_ptr);
1492 dr_link_blocks(&block->entryp[0], tcache_id);
1494 // collect branch_targets that don't land on delay slots
1495 for (pc = base_pc, i = 0; pc < end_pc; i++, pc += 2) {
1496 if (!(op_flags[i] & OF_BTARGET))
1498 if (op_flags[i] & OF_DELAY_OP) {
1499 op_flags[i] &= ~OF_BTARGET;
1502 ADD_TO_ARRAY(branch_target_pc, branch_target_count, pc, break);
1505 if (branch_target_count > 0) {
1506 memset(branch_target_ptr, 0, sizeof(branch_target_ptr[0]) * branch_target_count);
1509 // clear stale state after compile errors
1510 rcache_invalidate();
1512 // -------------------------------------------------
1513 // 3rd pass: actual compilation
1516 for (i = 0; pc < end_pc; i++)
1518 u32 delay_dep_fw = 0, delay_dep_bk = 0;
1528 DasmSH2(sh2dasm_buff, pc, op);
1529 printf("%c%08x %04x %s\n", (op_flags[i] & OF_BTARGET) ? '*' : ' ',
1530 pc, op, sh2dasm_buff);
1533 if ((op_flags[i] & OF_BTARGET) || pc == base_pc)
1537 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1542 v = block->entry_count;
1543 if (v < ARRAY_SIZE(block->entryp))
1545 struct block_entry *be_old;
1547 block->entryp[v].pc = pc;
1548 block->entryp[v].tcache_ptr = tcache_ptr;
1549 block->entryp[v].links = NULL;
1551 block->entryp[v].block = block;
1553 be_old = dr_get_entry(pc, sh2->is_slave, &tcache_id);
1554 if (be_old != NULL) {
1555 dbg(1, "entry override for %08x, was %p", pc, be_old->tcache_ptr);
1556 kill_block_entry(be_old, tcache_id);
1559 add_to_hashlist(&block->entryp[v], tcache_id);
1560 block->entry_count++;
1562 dbg(2, "-- %csh2 block #%d,%d entry %08x -> %p",
1563 sh2->is_slave ? 's' : 'm', tcache_id, blkid_main,
1566 // since we made a block entry, link any other blocks
1567 // that jump to current pc
1568 dr_link_blocks(&block->entryp[v], tcache_id);
1571 dbg(1, "too many entryp for block #%d,%d pc=%08x",
1572 tcache_id, blkid_main, pc);
1575 do_host_disasm(tcache_id);
1578 v = find_in_array(branch_target_pc, branch_target_count, pc);
1580 branch_target_ptr[v] = tcache_ptr;
1583 emit_move_r_imm32(SHR_PC, pc);
1586 #if (DRC_DEBUG & 0x10)
1587 rcache_get_reg_arg(0, SHR_PC);
1588 tmp = emit_memhandler_read(2);
1589 tmp2 = rcache_get_tmp();
1590 tmp3 = rcache_get_tmp();
1591 emith_move_r_imm(tmp2, FETCH32(pc));
1592 emith_move_r_imm(tmp3, 0);
1593 emith_cmp_r_r(tmp, tmp2);
1594 EMITH_SJMP_START(DCOND_EQ);
1595 emith_read_r_r_offs_c(DCOND_NE, tmp3, tmp3, 0); // crash
1596 EMITH_SJMP_END(DCOND_EQ);
1597 rcache_free_tmp(tmp);
1598 rcache_free_tmp(tmp2);
1599 rcache_free_tmp(tmp3);
1603 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1604 emith_cmp_r_imm(sr, 0);
1605 emith_jump_cond(DCOND_LE, sh2_drc_exit);
1606 do_host_disasm(tcache_id);
1607 rcache_unlock_all();
1611 if (!(op_flags[i] & OF_DELAY_OP)) {
1612 emit_move_r_imm32(SHR_PC, pc);
1613 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1617 tmp = rcache_used_hreg_mask();
1618 emith_save_caller_regs(tmp);
1619 emit_do_static_regs(1, 0);
1620 emith_pass_arg_r(0, CONTEXT_REG);
1621 emith_call(do_sh2_cmp);
1622 emith_restore_caller_regs(tmp);
1633 if (op_flags[i] & OF_DELAY_OP)
1635 // handle delay slot dependencies
1636 delay_dep_fw = opd->dest & ops[i-1].source;
1637 delay_dep_bk = opd->source & ops[i-1].dest;
1638 if (delay_dep_fw & BITMASK1(SHR_T)) {
1639 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1642 if (delay_dep_bk & BITMASK1(SHR_PC)) {
1643 if (opd->op != OP_LOAD_POOL && opd->op != OP_MOVA) {
1644 // can only be those 2 really..
1645 elprintf_sh2(sh2, EL_ANOMALY,
1646 "drc: illegal slot insn %04x @ %08x?", op, pc - 2);
1649 ; // addr already resolved somehow
1651 switch (ops[i-1].op) {
1653 emit_move_r_imm32(SHR_PC, ops[i-1].imm);
1657 tmp = rcache_get_reg(SHR_PC, RC_GR_WRITE);
1658 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1659 emith_move_r_imm(tmp, pc);
1660 emith_tst_r_imm(sr, T);
1661 tmp2 = ops[i-1].op == OP_BRANCH_CT ? DCOND_NE : DCOND_EQ;
1662 emith_move_r_imm_c(tmp2, tmp, ops[i-1].imm);
1664 // case OP_BRANCH_R OP_BRANCH_RF - PC already loaded
1668 //if (delay_dep_fw & ~BITMASK1(SHR_T))
1669 // dbg(1, "unhandled delay_dep_fw: %x", delay_dep_fw & ~BITMASK1(SHR_T));
1670 if (delay_dep_bk & ~BITMASK2(SHR_PC, SHR_PR))
1671 dbg(1, "unhandled delay_dep_bk: %x", delay_dep_bk);
1679 if (opd->dest & BITMASK1(SHR_PR))
1680 emit_move_r_imm32(SHR_PR, pc + 2);
1681 drcf.pending_branch_direct = 1;
1685 if (opd->dest & BITMASK1(SHR_PR))
1686 emit_move_r_imm32(SHR_PR, pc + 2);
1687 emit_move_r_r(SHR_PC, opd->rm);
1688 drcf.pending_branch_indirect = 1;
1692 tmp = rcache_get_reg(SHR_PC, RC_GR_WRITE);
1693 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1694 if (opd->dest & BITMASK1(SHR_PR)) {
1695 tmp3 = rcache_get_reg(SHR_PR, RC_GR_WRITE);
1696 emith_move_r_imm(tmp3, pc + 2);
1697 emith_add_r_r_r(tmp, tmp2, tmp3);
1700 emith_move_r_r(tmp, tmp2);
1701 emith_add_r_imm(tmp, pc + 2);
1703 drcf.pending_branch_indirect = 1;
1707 printf("TODO sleep\n");
1712 emit_memhandler_read_rr(SHR_PC, SHR_SP, 0, 2);
1714 tmp = rcache_get_reg_arg(0, SHR_SP);
1715 emith_add_r_imm(tmp, 4);
1716 tmp = emit_memhandler_read(2);
1717 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1718 emith_write_sr(sr, tmp);
1719 rcache_free_tmp(tmp);
1720 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
1721 emith_add_r_imm(tmp, 4*2);
1723 drcf.pending_branch_indirect = 1;
1727 #if PROPAGATE_CONSTANTS
1728 if (opd->imm != 0 && opd->imm < end_literals
1729 && literal_addr_count < MAX_LITERALS)
1731 ADD_TO_ARRAY(literal_addr, literal_addr_count, opd->imm,);
1733 tmp = FETCH32(opd->imm);
1735 tmp = (u32)(int)(signed short)FETCH_OP(opd->imm);
1736 gconst_new(GET_Rn(), tmp);
1741 tmp = rcache_get_tmp_arg(0);
1743 emith_move_r_imm(tmp, opd->imm);
1745 // have to calculate read addr from PC
1746 tmp2 = rcache_get_reg(SHR_PC, RC_GR_READ);
1747 if (opd->size == 2) {
1748 emith_add_r_r_imm(tmp, tmp2, 2 + (op & 0xff) * 4);
1749 emith_bic_r_imm(tmp, 3);
1752 emith_add_r_r_imm(tmp, tmp2, 2 + (op & 0xff) * 2);
1754 tmp2 = emit_memhandler_read(opd->size);
1755 tmp3 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1757 emith_move_r_r(tmp3, tmp2);
1759 emith_sext(tmp3, tmp2, 16);
1760 rcache_free_tmp(tmp2);
1766 emit_move_r_imm32(SHR_R0, opd->imm);
1768 tmp = rcache_get_reg(SHR_R0, RC_GR_WRITE);
1769 tmp2 = rcache_get_reg(SHR_PC, RC_GR_READ);
1770 emith_add_r_r_imm(tmp, tmp2, 2 + (op & 0xff) * 4);
1771 emith_bic_r_imm(tmp, 3);
1776 switch ((op >> 12) & 0x0f)
1778 /////////////////////////////////////////////
1783 tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1786 case 0: // STC SR,Rn 0000nnnn00000010
1789 case 1: // STC GBR,Rn 0000nnnn00010010
1792 case 2: // STC VBR,Rn 0000nnnn00100010
1798 tmp3 = rcache_get_reg(tmp2, RC_GR_READ);
1799 emith_move_r_r(tmp, tmp3);
1801 emith_clear_msb(tmp, tmp, 22); // reserved bits defined by ISA as 0
1803 case 0x04: // MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100
1804 case 0x05: // MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101
1805 case 0x06: // MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110
1807 tmp = rcache_get_reg_arg(1, GET_Rm());
1808 tmp2 = rcache_get_reg_arg(0, SHR_R0);
1809 tmp3 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1810 emith_add_r_r(tmp2, tmp3);
1811 emit_memhandler_write(op & 3);
1814 // MUL.L Rm,Rn 0000nnnnmmmm0111
1815 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
1816 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1817 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1818 emith_mul(tmp3, tmp2, tmp);
1823 case 0: // CLRT 0000000000001000
1824 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1825 emith_bic_r_imm(sr, T);
1827 case 1: // SETT 0000000000011000
1828 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1829 emith_or_r_imm(sr, T);
1831 case 2: // CLRMAC 0000000000101000
1832 emit_move_r_imm32(SHR_MACL, 0);
1833 emit_move_r_imm32(SHR_MACH, 0);
1842 case 0: // NOP 0000000000001001
1844 case 1: // DIV0U 0000000000011001
1845 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1846 emith_bic_r_imm(sr, M|Q|T);
1848 case 2: // MOVT Rn 0000nnnn00101001
1849 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1850 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1851 emith_clear_msb(tmp2, sr, 31);
1858 tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1861 case 0: // STS MACH,Rn 0000nnnn00001010
1864 case 1: // STS MACL,Rn 0000nnnn00011010
1867 case 2: // STS PR,Rn 0000nnnn00101010
1873 tmp2 = rcache_get_reg(tmp2, RC_GR_READ);
1874 emith_move_r_r(tmp, tmp2);
1876 case 0x0c: // MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100
1877 case 0x0d: // MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101
1878 case 0x0e: // MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110
1879 tmp = emit_indirect_indexed_read(SHR_R0, GET_Rm(), op & 3);
1880 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1881 if ((op & 3) != 2) {
1882 emith_sext(tmp2, tmp, (op & 1) ? 16 : 8);
1884 emith_move_r_r(tmp2, tmp);
1885 rcache_free_tmp(tmp);
1887 case 0x0f: // MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111
1888 emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 2);
1889 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW);
1890 /* MS 16 MAC bits unused if saturated */
1891 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1892 emith_tst_r_imm(sr, S);
1893 EMITH_SJMP_START(DCOND_EQ);
1894 emith_clear_msb_c(DCOND_NE, tmp4, tmp4, 16);
1895 EMITH_SJMP_END(DCOND_EQ);
1897 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW); // might evict SR
1898 emith_mula_s64(tmp3, tmp4, tmp, tmp2);
1899 rcache_free_tmp(tmp2);
1900 sr = rcache_get_reg(SHR_SR, RC_GR_READ); // reget just in case
1901 emith_tst_r_imm(sr, S);
1903 EMITH_JMP_START(DCOND_EQ);
1904 emith_asr(tmp, tmp4, 15);
1905 emith_cmp_r_imm(tmp, -1); // negative overflow (0x80000000..0xffff7fff)
1906 EMITH_SJMP_START(DCOND_GE);
1907 emith_move_r_imm_c(DCOND_LT, tmp4, 0x8000);
1908 emith_move_r_imm_c(DCOND_LT, tmp3, 0x0000);
1909 EMITH_SJMP_END(DCOND_GE);
1910 emith_cmp_r_imm(tmp, 0); // positive overflow (0x00008000..0x7fffffff)
1911 EMITH_SJMP_START(DCOND_LE);
1912 emith_move_r_imm_c(DCOND_GT, tmp4, 0x00007fff);
1913 emith_move_r_imm_c(DCOND_GT, tmp3, 0xffffffff);
1914 EMITH_SJMP_END(DCOND_LE);
1915 EMITH_JMP_END(DCOND_EQ);
1917 rcache_free_tmp(tmp);
1922 /////////////////////////////////////////////
1924 // MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd
1926 tmp = rcache_get_reg_arg(0, GET_Rn());
1927 tmp2 = rcache_get_reg_arg(1, GET_Rm());
1929 emith_add_r_imm(tmp, (op & 0x0f) * 4);
1930 emit_memhandler_write(2);
1936 case 0x00: // MOV.B Rm,@Rn 0010nnnnmmmm0000
1937 case 0x01: // MOV.W Rm,@Rn 0010nnnnmmmm0001
1938 case 0x02: // MOV.L Rm,@Rn 0010nnnnmmmm0010
1940 rcache_get_reg_arg(0, GET_Rn());
1941 rcache_get_reg_arg(1, GET_Rm());
1942 emit_memhandler_write(op & 3);
1944 case 0x04: // MOV.B Rm,@-Rn 0010nnnnmmmm0100
1945 case 0x05: // MOV.W Rm,@-Rn 0010nnnnmmmm0101
1946 case 0x06: // MOV.L Rm,@-Rn 0010nnnnmmmm0110
1947 rcache_get_reg_arg(1, GET_Rm()); // for Rm == Rn
1948 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1949 emith_sub_r_imm(tmp, (1 << (op & 3)));
1951 rcache_get_reg_arg(0, GET_Rn());
1952 emit_memhandler_write(op & 3);
1954 case 0x07: // DIV0S Rm,Rn 0010nnnnmmmm0111
1955 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1956 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1957 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1958 emith_bic_r_imm(sr, M|Q|T);
1959 emith_tst_r_imm(tmp2, (1<<31));
1960 EMITH_SJMP_START(DCOND_EQ);
1961 emith_or_r_imm_c(DCOND_NE, sr, Q);
1962 EMITH_SJMP_END(DCOND_EQ);
1963 emith_tst_r_imm(tmp3, (1<<31));
1964 EMITH_SJMP_START(DCOND_EQ);
1965 emith_or_r_imm_c(DCOND_NE, sr, M);
1966 EMITH_SJMP_END(DCOND_EQ);
1967 emith_teq_r_r(tmp2, tmp3);
1968 EMITH_SJMP_START(DCOND_PL);
1969 emith_or_r_imm_c(DCOND_MI, sr, T);
1970 EMITH_SJMP_END(DCOND_PL);
1972 case 0x08: // TST Rm,Rn 0010nnnnmmmm1000
1973 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1974 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1975 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1976 emith_bic_r_imm(sr, T);
1977 emith_tst_r_r(tmp2, tmp3);
1978 emit_or_t_if_eq(sr);
1980 case 0x09: // AND Rm,Rn 0010nnnnmmmm1001
1981 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1982 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1983 emith_and_r_r(tmp, tmp2);
1985 case 0x0a: // XOR Rm,Rn 0010nnnnmmmm1010
1986 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1987 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1988 emith_eor_r_r(tmp, tmp2);
1990 case 0x0b: // OR Rm,Rn 0010nnnnmmmm1011
1991 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1992 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1993 emith_or_r_r(tmp, tmp2);
1995 case 0x0c: // CMP/STR Rm,Rn 0010nnnnmmmm1100
1996 tmp = rcache_get_tmp();
1997 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1998 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1999 emith_eor_r_r_r(tmp, tmp2, tmp3);
2000 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2001 emith_bic_r_imm(sr, T);
2002 emith_tst_r_imm(tmp, 0x000000ff);
2003 emit_or_t_if_eq(sr);
2004 emith_tst_r_imm(tmp, 0x0000ff00);
2005 emit_or_t_if_eq(sr);
2006 emith_tst_r_imm(tmp, 0x00ff0000);
2007 emit_or_t_if_eq(sr);
2008 emith_tst_r_imm(tmp, 0xff000000);
2009 emit_or_t_if_eq(sr);
2010 rcache_free_tmp(tmp);
2012 case 0x0d: // XTRCT Rm,Rn 0010nnnnmmmm1101
2013 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2014 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
2015 emith_lsr(tmp, tmp, 16);
2016 emith_or_r_r_lsl(tmp, tmp2, 16);
2018 case 0x0e: // MULU.W Rm,Rn 0010nnnnmmmm1110
2019 case 0x0f: // MULS.W Rm,Rn 0010nnnnmmmm1111
2020 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
2021 tmp = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
2023 emith_sext(tmp, tmp2, 16);
2025 emith_clear_msb(tmp, tmp2, 16);
2026 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
2027 tmp2 = rcache_get_tmp();
2029 emith_sext(tmp2, tmp3, 16);
2031 emith_clear_msb(tmp2, tmp3, 16);
2032 emith_mul(tmp, tmp, tmp2);
2033 rcache_free_tmp(tmp2);
2038 /////////////////////////////////////////////
2042 case 0x00: // CMP/EQ Rm,Rn 0011nnnnmmmm0000
2043 case 0x02: // CMP/HS Rm,Rn 0011nnnnmmmm0010
2044 case 0x03: // CMP/GE Rm,Rn 0011nnnnmmmm0011
2045 case 0x06: // CMP/HI Rm,Rn 0011nnnnmmmm0110
2046 case 0x07: // CMP/GT Rm,Rn 0011nnnnmmmm0111
2047 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2048 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
2049 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
2050 emith_bic_r_imm(sr, T);
2051 emith_cmp_r_r(tmp2, tmp3);
2054 case 0x00: // CMP/EQ
2055 emit_or_t_if_eq(sr);
2057 case 0x02: // CMP/HS
2058 EMITH_SJMP_START(DCOND_LO);
2059 emith_or_r_imm_c(DCOND_HS, sr, T);
2060 EMITH_SJMP_END(DCOND_LO);
2062 case 0x03: // CMP/GE
2063 EMITH_SJMP_START(DCOND_LT);
2064 emith_or_r_imm_c(DCOND_GE, sr, T);
2065 EMITH_SJMP_END(DCOND_LT);
2067 case 0x06: // CMP/HI
2068 EMITH_SJMP_START(DCOND_LS);
2069 emith_or_r_imm_c(DCOND_HI, sr, T);
2070 EMITH_SJMP_END(DCOND_LS);
2072 case 0x07: // CMP/GT
2073 EMITH_SJMP_START(DCOND_LE);
2074 emith_or_r_imm_c(DCOND_GT, sr, T);
2075 EMITH_SJMP_END(DCOND_LE);
2079 case 0x04: // DIV1 Rm,Rn 0011nnnnmmmm0100
2080 // Q1 = carry(Rn = (Rn << 1) | T)
2082 // Q2 = carry(Rn += Rm)
2084 // Q2 = carry(Rn -= Rm)
2086 // T = (Q == M) = !(Q ^ M) = !(Q1 ^ Q2)
2087 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2088 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
2089 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2090 emith_tpop_carry(sr, 0);
2091 emith_adcf_r_r(tmp2, tmp2);
2092 emith_tpush_carry(sr, 0); // keep Q1 in T for now
2093 tmp4 = rcache_get_tmp();
2094 emith_and_r_r_imm(tmp4, sr, M);
2095 emith_eor_r_r_lsr(sr, tmp4, M_SHIFT - Q_SHIFT); // Q ^= M
2096 rcache_free_tmp(tmp4);
2097 // add or sub, invert T if carry to get Q1 ^ Q2
2098 // in: (Q ^ M) passed in Q, Q1 in T
2099 emith_sh2_div1_step(tmp2, tmp3, sr);
2100 emith_bic_r_imm(sr, Q);
2101 emith_tst_r_imm(sr, M);
2102 EMITH_SJMP_START(DCOND_EQ);
2103 emith_or_r_imm_c(DCOND_NE, sr, Q); // Q = M
2104 EMITH_SJMP_END(DCOND_EQ);
2105 emith_tst_r_imm(sr, T);
2106 EMITH_SJMP_START(DCOND_EQ);
2107 emith_eor_r_imm_c(DCOND_NE, sr, Q); // Q = M ^ Q1 ^ Q2
2108 EMITH_SJMP_END(DCOND_EQ);
2109 emith_eor_r_imm(sr, T); // T = !(Q1 ^ Q2)
2111 case 0x05: // DMULU.L Rm,Rn 0011nnnnmmmm0101
2112 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
2113 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
2114 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
2115 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE);
2116 emith_mul_u64(tmp3, tmp4, tmp, tmp2);
2118 case 0x08: // SUB Rm,Rn 0011nnnnmmmm1000
2119 case 0x0c: // ADD Rm,Rn 0011nnnnmmmm1100
2120 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2121 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
2123 emith_add_r_r(tmp, tmp2);
2125 emith_sub_r_r(tmp, tmp2);
2127 case 0x0a: // SUBC Rm,Rn 0011nnnnmmmm1010
2128 case 0x0e: // ADDC Rm,Rn 0011nnnnmmmm1110
2129 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2130 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
2131 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2132 if (op & 4) { // adc
2133 emith_tpop_carry(sr, 0);
2134 emith_adcf_r_r(tmp, tmp2);
2135 emith_tpush_carry(sr, 0);
2137 emith_tpop_carry(sr, 1);
2138 emith_sbcf_r_r(tmp, tmp2);
2139 emith_tpush_carry(sr, 1);
2142 case 0x0b: // SUBV Rm,Rn 0011nnnnmmmm1011
2143 case 0x0f: // ADDV Rm,Rn 0011nnnnmmmm1111
2144 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2145 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
2146 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2147 emith_bic_r_imm(sr, T);
2149 emith_addf_r_r(tmp, tmp2);
2151 emith_subf_r_r(tmp, tmp2);
2152 EMITH_SJMP_START(DCOND_VC);
2153 emith_or_r_imm_c(DCOND_VS, sr, T);
2154 EMITH_SJMP_END(DCOND_VC);
2156 case 0x0d: // DMULS.L Rm,Rn 0011nnnnmmmm1101
2157 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
2158 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
2159 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
2160 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE);
2161 emith_mul_s64(tmp3, tmp4, tmp, tmp2);
2166 /////////////////////////////////////////////
2173 case 0: // SHLL Rn 0100nnnn00000000
2174 case 2: // SHAL Rn 0100nnnn00100000
2175 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2176 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2177 emith_tpop_carry(sr, 0); // dummy
2178 emith_lslf(tmp, tmp, 1);
2179 emith_tpush_carry(sr, 0);
2181 case 1: // DT Rn 0100nnnn00010000
2182 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2183 #if 0 // scheduling needs tuning
2184 if (FETCH_OP(pc) == 0x8bfd) { // BF #-2
2185 if (gconst_get(GET_Rn(), &tmp)) {
2186 // XXX: limit burned cycles
2187 emit_move_r_imm32(GET_Rn(), 0);
2188 emith_or_r_imm(sr, T);
2189 cycles += tmp * 4 + 1; // +1 syncs with noconst version, not sure why
2193 emith_sh2_dtbf_loop();
2197 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2198 emith_bic_r_imm(sr, T);
2199 emith_subf_r_imm(tmp, 1);
2200 emit_or_t_if_eq(sr);
2207 case 0: // SHLR Rn 0100nnnn00000001
2208 case 2: // SHAR Rn 0100nnnn00100001
2209 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2210 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2211 emith_tpop_carry(sr, 0); // dummy
2213 emith_asrf(tmp, tmp, 1);
2215 emith_lsrf(tmp, tmp, 1);
2216 emith_tpush_carry(sr, 0);
2218 case 1: // CMP/PZ Rn 0100nnnn00010001
2219 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
2220 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2221 emith_bic_r_imm(sr, T);
2222 emith_cmp_r_imm(tmp, 0);
2223 EMITH_SJMP_START(DCOND_LT);
2224 emith_or_r_imm_c(DCOND_GE, sr, T);
2225 EMITH_SJMP_END(DCOND_LT);
2233 case 0x02: // STS.L MACH,@-Rn 0100nnnn00000010
2236 case 0x12: // STS.L MACL,@-Rn 0100nnnn00010010
2239 case 0x22: // STS.L PR,@-Rn 0100nnnn00100010
2242 case 0x03: // STC.L SR,@-Rn 0100nnnn00000011
2245 case 0x13: // STC.L GBR,@-Rn 0100nnnn00010011
2248 case 0x23: // STC.L VBR,@-Rn 0100nnnn00100011
2254 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2255 emith_sub_r_imm(tmp2, 4);
2257 rcache_get_reg_arg(0, GET_Rn());
2258 tmp3 = rcache_get_reg_arg(1, tmp);
2260 emith_clear_msb(tmp3, tmp3, 22); // reserved bits defined by ISA as 0
2261 emit_memhandler_write(2);
2267 case 0x04: // ROTL Rn 0100nnnn00000100
2268 case 0x05: // ROTR Rn 0100nnnn00000101
2269 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2270 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2271 emith_tpop_carry(sr, 0); // dummy
2273 emith_rorf(tmp, tmp, 1);
2275 emith_rolf(tmp, tmp, 1);
2276 emith_tpush_carry(sr, 0);
2278 case 0x24: // ROTCL Rn 0100nnnn00100100
2279 case 0x25: // ROTCR Rn 0100nnnn00100101
2280 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2281 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2282 emith_tpop_carry(sr, 0);
2287 emith_tpush_carry(sr, 0);
2289 case 0x15: // CMP/PL Rn 0100nnnn00010101
2290 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2291 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2292 emith_bic_r_imm(sr, T);
2293 emith_cmp_r_imm(tmp, 0);
2294 EMITH_SJMP_START(DCOND_LE);
2295 emith_or_r_imm_c(DCOND_GT, sr, T);
2296 EMITH_SJMP_END(DCOND_LE);
2304 case 0x06: // LDS.L @Rm+,MACH 0100mmmm00000110
2307 case 0x16: // LDS.L @Rm+,MACL 0100mmmm00010110
2310 case 0x26: // LDS.L @Rm+,PR 0100mmmm00100110
2313 case 0x07: // LDC.L @Rm+,SR 0100mmmm00000111
2316 case 0x17: // LDC.L @Rm+,GBR 0100mmmm00010111
2319 case 0x27: // LDC.L @Rm+,VBR 0100mmmm00100111
2325 rcache_get_reg_arg(0, GET_Rn());
2326 tmp2 = emit_memhandler_read(2);
2327 if (tmp == SHR_SR) {
2328 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2329 emith_write_sr(sr, tmp2);
2332 tmp = rcache_get_reg(tmp, RC_GR_WRITE);
2333 emith_move_r_r(tmp, tmp2);
2335 rcache_free_tmp(tmp2);
2336 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2337 emith_add_r_imm(tmp, 4);
2344 // SHLL2 Rn 0100nnnn00001000
2345 // SHLR2 Rn 0100nnnn00001001
2349 // SHLL8 Rn 0100nnnn00011000
2350 // SHLR8 Rn 0100nnnn00011001
2354 // SHLL16 Rn 0100nnnn00101000
2355 // SHLR16 Rn 0100nnnn00101001
2361 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2363 emith_lsr(tmp2, tmp2, tmp);
2365 emith_lsl(tmp2, tmp2, tmp);
2370 case 0: // LDS Rm,MACH 0100mmmm00001010
2373 case 1: // LDS Rm,MACL 0100mmmm00011010
2376 case 2: // LDS Rm,PR 0100mmmm00101010
2382 emit_move_r_r(tmp2, GET_Rn());
2387 case 1: // TAS.B @Rn 0100nnnn00011011
2388 // XXX: is TAS working on 32X?
2389 rcache_get_reg_arg(0, GET_Rn());
2390 tmp = emit_memhandler_read(0);
2391 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2392 emith_bic_r_imm(sr, T);
2393 emith_cmp_r_imm(tmp, 0);
2394 emit_or_t_if_eq(sr);
2396 emith_or_r_imm(tmp, 0x80);
2397 tmp2 = rcache_get_tmp_arg(1); // assuming it differs to tmp
2398 emith_move_r_r(tmp2, tmp);
2399 rcache_free_tmp(tmp);
2400 rcache_get_reg_arg(0, GET_Rn());
2401 emit_memhandler_write(0);
2408 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
2411 case 0: // LDC Rm,SR 0100mmmm00001110
2414 case 1: // LDC Rm,GBR 0100mmmm00011110
2417 case 2: // LDC Rm,VBR 0100mmmm00101110
2423 if (tmp2 == SHR_SR) {
2424 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2425 emith_write_sr(sr, tmp);
2428 tmp2 = rcache_get_reg(tmp2, RC_GR_WRITE);
2429 emith_move_r_r(tmp2, tmp);
2433 // MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111
2434 emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 1);
2435 emith_sext(tmp, tmp, 16);
2436 emith_sext(tmp2, tmp2, 16);
2437 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW);
2438 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW);
2439 emith_mula_s64(tmp3, tmp4, tmp, tmp2);
2440 rcache_free_tmp(tmp2);
2441 // XXX: MACH should be untouched when S is set?
2442 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2443 emith_tst_r_imm(sr, S);
2444 EMITH_JMP_START(DCOND_EQ);
2446 emith_asr(tmp, tmp3, 31);
2447 emith_eorf_r_r(tmp, tmp4); // tmp = ((signed)macl >> 31) ^ mach
2448 EMITH_JMP_START(DCOND_EQ);
2449 emith_move_r_imm(tmp3, 0x80000000);
2450 emith_tst_r_r(tmp4, tmp4);
2451 EMITH_SJMP_START(DCOND_MI);
2452 emith_sub_r_imm_c(DCOND_PL, tmp3, 1); // positive
2453 EMITH_SJMP_END(DCOND_MI);
2454 EMITH_JMP_END(DCOND_EQ);
2456 EMITH_JMP_END(DCOND_EQ);
2457 rcache_free_tmp(tmp);
2462 /////////////////////////////////////////////
2464 // MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd
2465 emit_memhandler_read_rr(GET_Rn(), GET_Rm(), (op & 0x0f) * 4, 2);
2468 /////////////////////////////////////////////
2472 case 0x00: // MOV.B @Rm,Rn 0110nnnnmmmm0000
2473 case 0x01: // MOV.W @Rm,Rn 0110nnnnmmmm0001
2474 case 0x02: // MOV.L @Rm,Rn 0110nnnnmmmm0010
2475 case 0x04: // MOV.B @Rm+,Rn 0110nnnnmmmm0100
2476 case 0x05: // MOV.W @Rm+,Rn 0110nnnnmmmm0101
2477 case 0x06: // MOV.L @Rm+,Rn 0110nnnnmmmm0110
2478 emit_memhandler_read_rr(GET_Rn(), GET_Rm(), 0, op & 3);
2479 if ((op & 7) >= 4 && GET_Rn() != GET_Rm()) {
2480 tmp = rcache_get_reg(GET_Rm(), RC_GR_RMW);
2481 emith_add_r_imm(tmp, (1 << (op & 3)));
2486 tmp = rcache_get_reg(GET_Rm(), RC_GR_READ);
2487 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
2490 case 0x03: // MOV Rm,Rn 0110nnnnmmmm0011
2491 emith_move_r_r(tmp2, tmp);
2493 case 0x07: // NOT Rm,Rn 0110nnnnmmmm0111
2494 emith_mvn_r_r(tmp2, tmp);
2496 case 0x08: // SWAP.B Rm,Rn 0110nnnnmmmm1000
2499 tmp3 = rcache_get_tmp();
2500 tmp4 = rcache_get_tmp();
2501 emith_lsr(tmp3, tmp, 16);
2502 emith_or_r_r_lsl(tmp3, tmp, 24);
2503 emith_and_r_r_imm(tmp4, tmp, 0xff00);
2504 emith_or_r_r_lsl(tmp3, tmp4, 8);
2505 emith_rol(tmp2, tmp3, 16);
2506 rcache_free_tmp(tmp4);
2508 rcache_free_tmp(tmp3);
2510 case 0x09: // SWAP.W Rm,Rn 0110nnnnmmmm1001
2511 emith_rol(tmp2, tmp, 16);
2513 case 0x0a: // NEGC Rm,Rn 0110nnnnmmmm1010
2514 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2515 emith_tpop_carry(sr, 1);
2516 emith_negcf_r_r(tmp2, tmp);
2517 emith_tpush_carry(sr, 1);
2519 case 0x0b: // NEG Rm,Rn 0110nnnnmmmm1011
2520 emith_neg_r_r(tmp2, tmp);
2522 case 0x0c: // EXTU.B Rm,Rn 0110nnnnmmmm1100
2523 emith_clear_msb(tmp2, tmp, 24);
2525 case 0x0d: // EXTU.W Rm,Rn 0110nnnnmmmm1101
2526 emith_clear_msb(tmp2, tmp, 16);
2528 case 0x0e: // EXTS.B Rm,Rn 0110nnnnmmmm1110
2529 emith_sext(tmp2, tmp, 8);
2531 case 0x0f: // EXTS.W Rm,Rn 0110nnnnmmmm1111
2532 emith_sext(tmp2, tmp, 16);
2539 /////////////////////////////////////////////
2541 // ADD #imm,Rn 0111nnnniiiiiiii
2542 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2543 if (op & 0x80) { // adding negative
2544 emith_sub_r_imm(tmp, -op & 0xff);
2546 emith_add_r_imm(tmp, op & 0xff);
2549 /////////////////////////////////////////////
2551 switch (op & 0x0f00)
2553 case 0x0000: // MOV.B R0,@(disp,Rn) 10000000nnnndddd
2554 case 0x0100: // MOV.W R0,@(disp,Rn) 10000001nnnndddd
2556 tmp = rcache_get_reg_arg(0, GET_Rm());
2557 tmp2 = rcache_get_reg_arg(1, SHR_R0);
2558 tmp3 = (op & 0x100) >> 8;
2560 emith_add_r_imm(tmp, (op & 0x0f) << tmp3);
2561 emit_memhandler_write(tmp3);
2563 case 0x0400: // MOV.B @(disp,Rm),R0 10000100mmmmdddd
2564 case 0x0500: // MOV.W @(disp,Rm),R0 10000101mmmmdddd
2565 tmp = (op & 0x100) >> 8;
2566 emit_memhandler_read_rr(SHR_R0, GET_Rm(), (op & 0x0f) << tmp, tmp);
2568 case 0x0800: // CMP/EQ #imm,R0 10001000iiiiiiii
2569 // XXX: could use cmn
2570 tmp = rcache_get_tmp();
2571 tmp2 = rcache_get_reg(0, RC_GR_READ);
2572 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2573 emith_move_r_imm_s8(tmp, op & 0xff);
2574 emith_bic_r_imm(sr, T);
2575 emith_cmp_r_r(tmp2, tmp);
2576 emit_or_t_if_eq(sr);
2577 rcache_free_tmp(tmp);
2582 /////////////////////////////////////////////
2584 switch (op & 0x0f00)
2586 case 0x0000: // MOV.B R0,@(disp,GBR) 11000000dddddddd
2587 case 0x0100: // MOV.W R0,@(disp,GBR) 11000001dddddddd
2588 case 0x0200: // MOV.L R0,@(disp,GBR) 11000010dddddddd
2590 tmp = rcache_get_reg_arg(0, SHR_GBR);
2591 tmp2 = rcache_get_reg_arg(1, SHR_R0);
2592 tmp3 = (op & 0x300) >> 8;
2593 emith_add_r_imm(tmp, (op & 0xff) << tmp3);
2594 emit_memhandler_write(tmp3);
2596 case 0x0400: // MOV.B @(disp,GBR),R0 11000100dddddddd
2597 case 0x0500: // MOV.W @(disp,GBR),R0 11000101dddddddd
2598 case 0x0600: // MOV.L @(disp,GBR),R0 11000110dddddddd
2599 tmp = (op & 0x300) >> 8;
2600 emit_memhandler_read_rr(SHR_R0, SHR_GBR, (op & 0xff) << tmp, tmp);
2602 case 0x0300: // TRAPA #imm 11000011iiiiiiii
2603 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
2604 emith_sub_r_imm(tmp, 4*2);
2606 tmp = rcache_get_reg_arg(0, SHR_SP);
2607 emith_add_r_imm(tmp, 4);
2608 tmp = rcache_get_reg_arg(1, SHR_SR);
2609 emith_clear_msb(tmp, tmp, 22);
2610 emit_memhandler_write(2);
2612 rcache_get_reg_arg(0, SHR_SP);
2613 tmp = rcache_get_tmp_arg(1);
2614 emith_move_r_imm(tmp, pc);
2615 emit_memhandler_write(2);
2617 emit_memhandler_read_rr(SHR_PC, SHR_VBR, (op & 0xff) * 4, 2);
2618 // indirect jump -> back to dispatcher
2620 emith_jump(sh2_drc_dispatcher);
2622 case 0x0800: // TST #imm,R0 11001000iiiiiiii
2623 tmp = rcache_get_reg(SHR_R0, RC_GR_READ);
2624 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2625 emith_bic_r_imm(sr, T);
2626 emith_tst_r_imm(tmp, op & 0xff);
2627 emit_or_t_if_eq(sr);
2629 case 0x0900: // AND #imm,R0 11001001iiiiiiii
2630 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
2631 emith_and_r_imm(tmp, op & 0xff);
2633 case 0x0a00: // XOR #imm,R0 11001010iiiiiiii
2634 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
2635 emith_eor_r_imm(tmp, op & 0xff);
2637 case 0x0b00: // OR #imm,R0 11001011iiiiiiii
2638 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
2639 emith_or_r_imm(tmp, op & 0xff);
2641 case 0x0c00: // TST.B #imm,@(R0,GBR) 11001100iiiiiiii
2642 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2643 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2644 emith_bic_r_imm(sr, T);
2645 emith_tst_r_imm(tmp, op & 0xff);
2646 emit_or_t_if_eq(sr);
2647 rcache_free_tmp(tmp);
2649 case 0x0d00: // AND.B #imm,@(R0,GBR) 11001101iiiiiiii
2650 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2651 emith_and_r_imm(tmp, op & 0xff);
2653 case 0x0e00: // XOR.B #imm,@(R0,GBR) 11001110iiiiiiii
2654 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2655 emith_eor_r_imm(tmp, op & 0xff);
2657 case 0x0f00: // OR.B #imm,@(R0,GBR) 11001111iiiiiiii
2658 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2659 emith_or_r_imm(tmp, op & 0xff);
2661 tmp2 = rcache_get_tmp_arg(1);
2662 emith_move_r_r(tmp2, tmp);
2663 rcache_free_tmp(tmp);
2664 tmp3 = rcache_get_reg_arg(0, SHR_GBR);
2665 tmp4 = rcache_get_reg(SHR_R0, RC_GR_READ);
2666 emith_add_r_r(tmp3, tmp4);
2667 emit_memhandler_write(0);
2672 /////////////////////////////////////////////
2674 // MOV #imm,Rn 1110nnnniiiiiiii
2675 emit_move_r_imm32(GET_Rn(), (u32)(signed int)(signed char)op);
2680 if (!(op_flags[i] & OF_B_IN_DS))
2681 elprintf_sh2(sh2, EL_ANOMALY,
2682 "drc: illegal op %04x @ %08x", op, pc - 2);
2684 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
2685 emith_sub_r_imm(tmp, 4*2);
2687 tmp = rcache_get_reg_arg(0, SHR_SP);
2688 emith_add_r_imm(tmp, 4);
2689 tmp = rcache_get_reg_arg(1, SHR_SR);
2690 emith_clear_msb(tmp, tmp, 22);
2691 emit_memhandler_write(2);
2693 rcache_get_reg_arg(0, SHR_SP);
2694 tmp = rcache_get_tmp_arg(1);
2695 if (drcf.pending_branch_indirect) {
2696 tmp2 = rcache_get_reg(SHR_PC, RC_GR_READ);
2697 emith_move_r_r(tmp, tmp2);
2700 emith_move_r_imm(tmp, pc - 2);
2701 emit_memhandler_write(2);
2703 v = (op_flags[i] & OF_B_IN_DS) ? 6 : 4;
2704 emit_memhandler_read_rr(SHR_PC, SHR_VBR, v * 4, 2);
2705 // indirect jump -> back to dispatcher
2707 emith_jump(sh2_drc_dispatcher);
2712 rcache_unlock_all();
2714 cycles += opd->cycles;
2716 if (op_flags[i+1] & OF_DELAY_OP) {
2717 do_host_disasm(tcache_id);
2722 if (drcf.test_irq && !drcf.pending_branch_direct) {
2723 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2725 if (!drcf.pending_branch_indirect)
2726 emit_move_r_imm32(SHR_PC, pc);
2728 emith_call(sh2_drc_test_irq);
2732 // branch handling (with/without delay)
2733 if (drcf.pending_branch_direct)
2735 struct op_data *opd_b =
2736 (op_flags[i] & OF_DELAY_OP) ? &ops[i-1] : opd;
2737 u32 target_pc = opd_b->imm;
2738 int cond = -1, ncond = -1;
2739 void *target = NULL;
2742 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2746 if (opd_b->op != OP_BRANCH) {
2747 cond = (opd_b->op == OP_BRANCH_CF) ? DCOND_EQ : DCOND_NE;
2748 ncond = (opd_b->op == OP_BRANCH_CF) ? DCOND_NE : DCOND_EQ;
2751 int ctaken = (op_flags[i] & OF_DELAY_OP) ? 1 : 2;
2753 if (delay_dep_fw & BITMASK1(SHR_T))
2754 emith_tst_r_imm(sr, T_save);
2756 emith_tst_r_imm(sr, T);
2758 EMITH_SJMP_START_(ncond);
2759 emith_sub_r_imm_c(cond, sr, ctaken<<12);
2763 if (find_in_array(branch_target_pc, branch_target_count, target_pc) >= 0)
2766 // XXX: jumps back can be linked already
2767 if (branch_patch_count < MAX_LOCAL_BRANCHES) {
2768 target = tcache_ptr;
2769 branch_patch_pc[branch_patch_count] = target_pc;
2770 branch_patch_ptr[branch_patch_count] = target;
2771 branch_patch_count++;
2774 dbg(1, "warning: too many local branches");
2780 // can't resolve branch locally, make a block exit
2781 emit_move_r_imm32(SHR_PC, target_pc);
2784 target = dr_prepare_ext_branch(target_pc, sh2->is_slave, tcache_id);
2790 emith_jump_cond_patchable(cond, target);
2791 EMITH_SJMP_END_(ncond);
2794 emith_jump_patchable(target);
2795 rcache_invalidate();
2798 drcf.pending_branch_direct = 0;
2800 else if (drcf.pending_branch_indirect) {
2801 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2804 emith_jump(sh2_drc_dispatcher);
2805 drcf.pending_branch_indirect = 0;
2808 do_host_disasm(tcache_id);
2811 tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
2815 // check the last op
2816 if (op_flags[i-1] & OF_DELAY_OP)
2821 if (opd->op != OP_BRANCH && opd->op != OP_BRANCH_R
2822 && opd->op != OP_BRANCH_RF && opd->op != OP_RTE)
2826 emit_move_r_imm32(SHR_PC, pc);
2829 target = dr_prepare_ext_branch(pc, sh2->is_slave, tcache_id);
2832 emith_jump_patchable(target);
2835 // link local branches
2836 for (i = 0; i < branch_patch_count; i++) {
2839 t = find_in_array(branch_target_pc, branch_target_count, branch_patch_pc[i]);
2840 target = branch_target_ptr[t];
2841 if (target == NULL) {
2842 // flush pc and go back to dispatcher (this should no longer happen)
2843 dbg(1, "stray branch to %08x %p", branch_patch_pc[i], tcache_ptr);
2844 target = tcache_ptr;
2845 emit_move_r_imm32(SHR_PC, branch_patch_pc[i]);
2847 emith_jump(sh2_drc_dispatcher);
2849 emith_jump_patch(branch_patch_ptr[i], target);
2852 // mark memory blocks as containing compiled code
2853 // override any overlay blocks as they become unreachable anyway
2854 if ((block->addr & 0xc7fc0000) == 0x06000000
2855 || (block->addr & 0xfffff000) == 0xc0000000)
2857 u16 *drc_ram_blk = NULL;
2858 u32 addr, mask = 0, shift = 0;
2860 if (tcache_id != 0) {
2862 drc_ram_blk = Pico32xMem->drcblk_da[sh2->is_slave];
2863 shift = SH2_DRCBLK_DA_SHIFT;
2868 drc_ram_blk = Pico32xMem->drcblk_ram;
2869 shift = SH2_DRCBLK_RAM_SHIFT;
2873 // mark recompiled insns
2874 drc_ram_blk[(base_pc & mask) >> shift] = 1;
2875 for (pc = base_pc; pc < end_pc; pc += 2)
2876 drc_ram_blk[(pc & mask) >> shift] = 1;
2879 for (i = 0; i < literal_addr_count; i++) {
2880 tmp = literal_addr[i];
2881 drc_ram_blk[(tmp & mask) >> shift] = 1;
2884 // add to invalidation lookup lists
2885 addr = base_pc & ~(INVAL_PAGE_SIZE - 1);
2886 for (; addr < end_literals; addr += INVAL_PAGE_SIZE) {
2887 i = (addr & mask) / INVAL_PAGE_SIZE;
2888 add_to_block_list(&inval_lookup[tcache_id][i], block);
2892 tcache_ptrs[tcache_id] = tcache_ptr;
2894 host_instructions_updated(block_entry_ptr, tcache_ptr);
2896 do_host_disasm(tcache_id);
2898 if (drcf.literals_disabled && literal_addr_count)
2899 dbg(1, "literals_disabled && literal_addr_count?");
2900 dbg(2, " block #%d,%d tcache %d/%d, insns %d -> %d %.3f",
2901 tcache_id, blkid_main,
2902 tcache_ptr - tcache_bases[tcache_id], tcache_sizes[tcache_id],
2903 insns_compiled, host_insn_count, (float)host_insn_count / insns_compiled);
2904 if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM
2905 dbg(2, " hash collisions %d/%d", hash_collisions, block_counts[tcache_id]);
2908 tcache_dsm_ptrs[tcache_id] = block_entry_ptr;
2909 do_host_disasm(tcache_id);
2917 return block_entry_ptr;
2920 static void sh2_generate_utils(void)
2922 int arg0, arg1, arg2, sr, tmp;
2924 sh2_drc_write32 = p32x_sh2_write32;
2925 sh2_drc_read8 = p32x_sh2_read8;
2926 sh2_drc_read16 = p32x_sh2_read16;
2927 sh2_drc_read32 = p32x_sh2_read32;
2929 host_arg2reg(arg0, 0);
2930 host_arg2reg(arg1, 1);
2931 host_arg2reg(arg2, 2);
2932 emith_move_r_r(arg0, arg0); // nop
2934 // sh2_drc_exit(void)
2935 sh2_drc_exit = (void *)tcache_ptr;
2936 emit_do_static_regs(1, arg2);
2937 emith_sh2_drc_exit();
2939 // sh2_drc_dispatcher(void)
2940 sh2_drc_dispatcher = (void *)tcache_ptr;
2941 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2942 emith_cmp_r_imm(sr, 0);
2943 emith_jump_cond(DCOND_LT, sh2_drc_exit);
2944 rcache_invalidate();
2945 emith_ctx_read(arg0, SHR_PC * 4);
2946 emith_ctx_read(arg1, offsetof(SH2, is_slave));
2947 emith_add_r_r_ptr_imm(arg2, CONTEXT_REG, offsetof(SH2, drc_tmp));
2948 emith_call(dr_lookup_block);
2950 // lookup failed, call sh2_translate()
2951 emith_move_r_r_ptr(arg0, CONTEXT_REG);
2952 emith_ctx_read(arg1, offsetof(SH2, drc_tmp)); // tcache_id
2953 emith_call(sh2_translate);
2955 // sh2_translate() failed, flush cache and retry
2956 emith_ctx_read(arg0, offsetof(SH2, drc_tmp));
2957 emith_call(flush_tcache);
2958 emith_move_r_r_ptr(arg0, CONTEXT_REG);
2959 emith_ctx_read(arg1, offsetof(SH2, drc_tmp));
2960 emith_call(sh2_translate);
2962 // XXX: can't translate, fail
2963 emith_call(dr_failure);
2965 // sh2_drc_test_irq(void)
2966 // assumes it's called from main function (may jump to dispatcher)
2967 sh2_drc_test_irq = (void *)tcache_ptr;
2968 emith_ctx_read(arg1, offsetof(SH2, pending_level));
2969 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2970 emith_lsr(arg0, sr, I_SHIFT);
2971 emith_and_r_imm(arg0, 0x0f);
2972 emith_cmp_r_r(arg1, arg0); // pending_level > ((sr >> 4) & 0x0f)?
2973 EMITH_SJMP_START(DCOND_GT);
2974 emith_ret_c(DCOND_LE); // nope, return
2975 EMITH_SJMP_END(DCOND_GT);
2977 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
2978 emith_sub_r_imm(tmp, 4*2);
2981 tmp = rcache_get_reg_arg(0, SHR_SP);
2982 emith_add_r_imm(tmp, 4);
2983 tmp = rcache_get_reg_arg(1, SHR_SR);
2984 emith_clear_msb(tmp, tmp, 22);
2985 emith_move_r_r_ptr(arg2, CONTEXT_REG);
2986 emith_call(p32x_sh2_write32); // XXX: use sh2_drc_write32?
2987 rcache_invalidate();
2989 rcache_get_reg_arg(0, SHR_SP);
2990 emith_ctx_read(arg1, SHR_PC * 4);
2991 emith_move_r_r_ptr(arg2, CONTEXT_REG);
2992 emith_call(p32x_sh2_write32);
2993 rcache_invalidate();
2994 // update I, cycles, do callback
2995 emith_ctx_read(arg1, offsetof(SH2, pending_level));
2996 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2997 emith_bic_r_imm(sr, I);
2998 emith_or_r_r_lsl(sr, arg1, I_SHIFT);
2999 emith_sub_r_imm(sr, 13 << 12); // at least 13 cycles
3001 emith_move_r_r_ptr(arg0, CONTEXT_REG);
3002 emith_call_ctx(offsetof(SH2, irq_callback)); // vector = sh2->irq_callback(sh2, level);
3004 emith_lsl(arg0, RET_REG, 2);
3005 emith_ctx_read(arg1, SHR_VBR * 4);
3006 emith_add_r_r(arg0, arg1);
3007 tmp = emit_memhandler_read(2);
3008 emith_ctx_write(tmp, SHR_PC * 4);
3009 #if defined(__i386__) || defined(__x86_64__)
3010 emith_add_r_r_ptr_imm(xSP, xSP, sizeof(void *)); // fix stack
3012 emith_jump(sh2_drc_dispatcher);
3013 rcache_invalidate();
3015 // sh2_drc_entry(SH2 *sh2)
3016 sh2_drc_entry = (void *)tcache_ptr;
3017 emith_sh2_drc_entry();
3018 emith_move_r_r_ptr(CONTEXT_REG, arg0); // move ctx, arg0
3019 emit_do_static_regs(0, arg2);
3020 emith_call(sh2_drc_test_irq);
3021 emith_jump(sh2_drc_dispatcher);
3023 // sh2_drc_write8(u32 a, u32 d)
3024 sh2_drc_write8 = (void *)tcache_ptr;
3025 emith_ctx_read_ptr(arg2, offsetof(SH2, write8_tab));
3026 emith_sh2_wcall(arg0, arg2);
3028 // sh2_drc_write16(u32 a, u32 d)
3029 sh2_drc_write16 = (void *)tcache_ptr;
3030 emith_ctx_read_ptr(arg2, offsetof(SH2, write16_tab));
3031 emith_sh2_wcall(arg0, arg2);
3035 #define MAKE_READ_WRAPPER(func) { \
3036 void *tmp = (void *)tcache_ptr; \
3039 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[0])); \
3040 emith_addf_r_r(arg2, arg0); \
3041 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[0])); \
3042 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[1])); \
3043 emith_adc_r_imm(arg2, 0x01000000); \
3044 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[1])); \
3045 emith_pop_and_ret(); \
3048 #define MAKE_WRITE_WRAPPER(func) { \
3049 void *tmp = (void *)tcache_ptr; \
3050 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[0])); \
3051 emith_addf_r_r(arg2, arg1); \
3052 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[0])); \
3053 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[1])); \
3054 emith_adc_r_imm(arg2, 0x01000000); \
3055 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[1])); \
3056 emith_move_r_r_ptr(arg2, CONTEXT_REG); \
3061 MAKE_READ_WRAPPER(sh2_drc_read8);
3062 MAKE_READ_WRAPPER(sh2_drc_read16);
3063 MAKE_READ_WRAPPER(sh2_drc_read32);
3064 MAKE_WRITE_WRAPPER(sh2_drc_write8);
3065 MAKE_WRITE_WRAPPER(sh2_drc_write16);
3066 MAKE_WRITE_WRAPPER(sh2_drc_write32);
3068 host_dasm_new_symbol(sh2_drc_read8);
3069 host_dasm_new_symbol(sh2_drc_read16);
3070 host_dasm_new_symbol(sh2_drc_read32);
3071 host_dasm_new_symbol(sh2_drc_write32);
3075 rcache_invalidate();
3077 host_dasm_new_symbol(sh2_drc_entry);
3078 host_dasm_new_symbol(sh2_drc_dispatcher);
3079 host_dasm_new_symbol(sh2_drc_exit);
3080 host_dasm_new_symbol(sh2_drc_test_irq);
3081 host_dasm_new_symbol(sh2_drc_write8);
3082 host_dasm_new_symbol(sh2_drc_write16);
3086 static void sh2_smc_rm_block(struct block_desc *bd, int tcache_id, u32 ram_mask)
3088 u32 i, addr, end_addr;
3091 dbg(2, " killing block %08x-%08x-%08x, blkid %d,%d",
3092 bd->addr, bd->addr + bd->size_nolit, bd->addr + bd->size,
3093 tcache_id, bd - block_tables[tcache_id]);
3094 if (bd->addr == 0 || bd->entry_count == 0) {
3095 dbg(1, " killing dead block!? %08x", bd->addr);
3099 // remove from inval_lookup
3100 addr = bd->addr & ~(INVAL_PAGE_SIZE - 1);
3101 end_addr = bd->addr + bd->size;
3102 for (; addr < end_addr; addr += INVAL_PAGE_SIZE) {
3103 i = (addr & ram_mask) / INVAL_PAGE_SIZE;
3104 rm_from_block_list(&inval_lookup[tcache_id][i], bd);
3109 // remove from hash table, make incoming links unresolved
3110 // XXX: maybe patch branches w/flush instead?
3111 for (i = 0; i < bd->entry_count; i++) {
3112 rm_from_hashlist(&bd->entryp[i], tcache_id);
3114 // since we never reuse tcache space of dead blocks,
3115 // insert jump to dispatcher for blocks that are linked to this
3116 tcache_ptr = bd->entryp[i].tcache_ptr;
3117 emit_move_r_imm32(SHR_PC, bd->entryp[i].pc);
3119 emith_jump(sh2_drc_dispatcher);
3121 host_instructions_updated(bd->entryp[i].tcache_ptr, tcache_ptr);
3123 unregister_links(&bd->entryp[i], tcache_id);
3128 bd->addr = bd->size = bd->size_nolit = 0;
3129 bd->entry_count = 0;
3133 04205:243: == msh2 block #0,200 060017a8-060017f0 -> 0x27cb9c
3134 060017a8 d11c MOV.L @($70,PC),R1 ; @$0600181c
3136 04230:261: msh2 xsh w32 [260017a8] d225e304
3137 04230:261: msh2 smc check @260017a8
3138 04239:226: = ssh2 enter 060017a8 0x27cb9c, c=173
3140 static void sh2_smc_rm_blocks(u32 a, u16 *drc_ram_blk, int tcache_id, u32 shift, u32 mask)
3142 struct block_list **blist = NULL, *entry;
3143 struct block_desc *block;
3144 u32 start_addr, end_addr, taddr, i;
3145 u32 from = ~0, to = 0;
3147 // ignore cache-through
3150 blist = &inval_lookup[tcache_id][(a & mask) / INVAL_PAGE_SIZE];
3152 while (entry != NULL) {
3153 block = entry->block;
3154 start_addr = block->addr & ~0x20000000;
3155 end_addr = start_addr + block->size;
3156 if (start_addr <= a && a < end_addr) {
3157 // get addr range that includes all removed blocks
3158 if (from > start_addr)
3163 if (a >= start_addr + block->size_nolit)
3164 literal_disabled_frames = 3;
3165 sh2_smc_rm_block(block, tcache_id, mask);
3167 // entry lost, restart search
3171 entry = entry->next;
3177 // update range around a to match latest state
3178 from &= ~(INVAL_PAGE_SIZE - 1);
3179 to |= (INVAL_PAGE_SIZE - 1);
3180 for (taddr = from; taddr < to; taddr += INVAL_PAGE_SIZE) {
3181 i = (taddr & mask) / INVAL_PAGE_SIZE;
3182 entry = inval_lookup[tcache_id][i];
3184 for (; entry != NULL; entry = entry->next) {
3185 block = entry->block;
3187 start_addr = block->addr & ~0x20000000;
3188 if (start_addr > a) {
3189 if (to > start_addr)
3193 end_addr = start_addr + block->size;
3194 if (from < end_addr)
3202 u16 *p = drc_ram_blk + ((from & mask) >> shift);
3203 memset(p, 0, (to - from) >> (shift - 1));
3207 void sh2_drc_wcheck_ram(unsigned int a, int val, int cpuid)
3209 dbg(2, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
3210 sh2_smc_rm_blocks(a, Pico32xMem->drcblk_ram, 0, SH2_DRCBLK_RAM_SHIFT, 0x3ffff);
3213 void sh2_drc_wcheck_da(unsigned int a, int val, int cpuid)
3215 dbg(2, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
3216 sh2_smc_rm_blocks(a, Pico32xMem->drcblk_da[cpuid],
3217 1 + cpuid, SH2_DRCBLK_DA_SHIFT, 0xfff);
3220 int sh2_execute_drc(SH2 *sh2c, int cycles)
3224 // cycles are kept in SHR_SR unused bits (upper 20)
3225 // bit11 contains T saved for delay slot
3226 // others are usual SH2 flags
3228 sh2c->sr |= cycles << 12;
3229 sh2_drc_entry(sh2c);
3232 ret_cycles = (signed int)sh2c->sr >> 12;
3234 dbg(1, "warning: drc returned with cycles: %d", ret_cycles);
3241 void block_stats(void)
3243 int c, b, i, total = 0;
3245 printf("block stats:\n");
3246 for (b = 0; b < ARRAY_SIZE(block_tables); b++)
3247 for (i = 0; i < block_counts[b]; i++)
3248 if (block_tables[b][i].addr != 0)
3249 total += block_tables[b][i].refcount;
3251 for (c = 0; c < 10; c++) {
3252 struct block_desc *blk, *maxb = NULL;
3254 for (b = 0; b < ARRAY_SIZE(block_tables); b++) {
3255 for (i = 0; i < block_counts[b]; i++) {
3256 blk = &block_tables[b][i];
3257 if (blk->addr != 0 && blk->refcount > max) {
3258 max = blk->refcount;
3265 printf("%08x %9d %2.3f%%\n", maxb->addr, maxb->refcount,
3266 (double)maxb->refcount / total * 100.0);
3270 for (b = 0; b < ARRAY_SIZE(block_tables); b++)
3271 for (i = 0; i < block_counts[b]; i++)
3272 block_tables[b][i].refcount = 0;
3275 #define block_stats()
3278 void sh2_drc_flush_all(void)
3286 void sh2_drc_mem_setup(SH2 *sh2)
3288 // fill the convenience pointers
3289 sh2->p_bios = sh2->is_slave ? Pico32xMem->sh2_rom_s.w : Pico32xMem->sh2_rom_m.w;
3290 sh2->p_da = sh2->data_array;
3291 sh2->p_sdram = Pico32xMem->sdram;
3292 sh2->p_rom = Pico.rom;
3295 void sh2_drc_frame(void)
3297 if (literal_disabled_frames > 0)
3298 literal_disabled_frames--;
3301 int sh2_drc_init(SH2 *sh2)
3305 if (block_tables[0] == NULL)
3307 for (i = 0; i < TCACHE_BUFFERS; i++) {
3308 block_tables[i] = calloc(block_max_counts[i], sizeof(*block_tables[0]));
3309 if (block_tables[i] == NULL)
3311 // max 2 block links (exits) per block
3312 block_link_pool[i] = calloc(block_link_pool_max_counts[i],
3313 sizeof(*block_link_pool[0]));
3314 if (block_link_pool[i] == NULL)
3317 inval_lookup[i] = calloc(ram_sizes[i] / INVAL_PAGE_SIZE,
3318 sizeof(inval_lookup[0]));
3319 if (inval_lookup[i] == NULL)
3322 hash_tables[i] = calloc(hash_table_sizes[i], sizeof(*hash_tables[0]));
3323 if (hash_tables[i] == NULL)
3326 memset(block_counts, 0, sizeof(block_counts));
3327 memset(block_link_pool_counts, 0, sizeof(block_link_pool_counts));
3330 tcache_ptr = tcache;
3331 sh2_generate_utils();
3332 host_instructions_updated(tcache, tcache_ptr);
3334 tcache_bases[0] = tcache_ptrs[0] = tcache_ptr;
3335 for (i = 1; i < ARRAY_SIZE(tcache_bases); i++)
3336 tcache_bases[i] = tcache_ptrs[i] = tcache_bases[i - 1] + tcache_sizes[i - 1];
3339 for (i = 0; i < ARRAY_SIZE(block_tables); i++)
3340 tcache_dsm_ptrs[i] = tcache_bases[i];
3342 tcache_dsm_ptrs[0] = tcache;
3346 hash_collisions = 0;
3353 sh2_drc_finish(sh2);
3357 void sh2_drc_finish(SH2 *sh2)
3361 if (block_tables[0] == NULL)
3364 sh2_drc_flush_all();
3366 for (i = 0; i < TCACHE_BUFFERS; i++) {
3368 printf("~~~ tcache %d\n", i);
3369 tcache_dsm_ptrs[i] = tcache_bases[i];
3370 tcache_ptr = tcache_ptrs[i];
3374 if (block_tables[i] != NULL)
3375 free(block_tables[i]);
3376 block_tables[i] = NULL;
3377 if (block_link_pool[i] == NULL)
3378 free(block_link_pool[i]);
3379 block_link_pool[i] = NULL;
3381 if (inval_lookup[i] == NULL)
3382 free(inval_lookup[i]);
3383 inval_lookup[i] = NULL;
3385 if (hash_tables[i] != NULL) {
3386 free(hash_tables[i]);
3387 hash_tables[i] = NULL;
3394 #endif /* DRC_SH2 */
3396 static void *dr_get_pc_base(u32 pc, int is_slave)
3401 if ((pc & ~0x7ff) == 0) {
3403 ret = is_slave ? Pico32xMem->sh2_rom_s.w : Pico32xMem->sh2_rom_m.w;
3406 else if ((pc & 0xfffff000) == 0xc0000000) {
3408 ret = sh2s[is_slave].data_array;
3411 else if ((pc & 0xc6000000) == 0x06000000) {
3413 ret = Pico32xMem->sdram;
3416 else if ((pc & 0xc6000000) == 0x02000000) {
3418 if ((pc & 0x3fffff) < Pico.romsize)
3424 return (void *)-1; // NULL is valid value
3426 return (char *)ret - (pc & ~mask);
3429 void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
3430 u32 *end_literals_out)
3434 u32 end_pc, end_literals = 0;
3435 u32 lowest_mova = 0;
3436 struct op_data *opd;
3437 int next_is_delay = 0;
3441 memset(op_flags, 0, BLOCK_INSN_LIMIT);
3443 dr_pc_base = dr_get_pc_base(base_pc, is_slave);
3445 // 1st pass: disassemble
3446 for (i = 0, pc = base_pc; ; i++, pc += 2) {
3447 // we need an ops[] entry after the last one initialized,
3448 // so do it before end_block checks
3450 opd->op = OP_UNHANDLED;
3452 opd->source = opd->dest = 0;
3456 if (next_is_delay) {
3457 op_flags[i] |= OF_DELAY_OP;
3460 else if (end_block || i >= BLOCK_INSN_LIMIT - 2)
3464 switch ((op & 0xf000) >> 12)
3466 /////////////////////////////////////////////
3473 case 0: // STC SR,Rn 0000nnnn00000010
3476 case 1: // STC GBR,Rn 0000nnnn00010010
3479 case 2: // STC VBR,Rn 0000nnnn00100010
3486 opd->source = BITMASK1(tmp);
3487 opd->dest = BITMASK1(GET_Rn());
3490 CHECK_UNHANDLED_BITS(0xd0, undefined);
3491 // BRAF Rm 0000mmmm00100011
3492 // BSRF Rm 0000mmmm00000011
3493 opd->op = OP_BRANCH_RF;
3495 opd->source = BITMASK1(opd->rm);
3496 opd->dest = BITMASK1(SHR_PC);
3498 opd->dest |= BITMASK1(SHR_PR);
3503 case 0x04: // MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100
3504 case 0x05: // MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101
3505 case 0x06: // MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110
3506 opd->source = BITMASK3(GET_Rm(), SHR_R0, GET_Rn());
3509 // MUL.L Rm,Rn 0000nnnnmmmm0111
3510 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3511 opd->dest = BITMASK1(SHR_MACL);
3515 CHECK_UNHANDLED_BITS(0xf00, undefined);
3518 case 0: // CLRT 0000000000001000
3519 opd->op = OP_SETCLRT;
3520 opd->dest = BITMASK1(SHR_T);
3523 case 1: // SETT 0000000000011000
3524 opd->op = OP_SETCLRT;
3525 opd->dest = BITMASK1(SHR_T);
3528 case 2: // CLRMAC 0000000000101000
3529 opd->dest = BITMASK3(SHR_T, SHR_MACL, SHR_MACH);
3538 case 0: // NOP 0000000000001001
3539 CHECK_UNHANDLED_BITS(0xf00, undefined);
3541 case 1: // DIV0U 0000000000011001
3542 CHECK_UNHANDLED_BITS(0xf00, undefined);
3543 opd->dest = BITMASK2(SHR_SR, SHR_T);
3545 case 2: // MOVT Rn 0000nnnn00101001
3546 opd->source = BITMASK1(SHR_T);
3547 opd->dest = BITMASK1(GET_Rn());
3556 case 0: // STS MACH,Rn 0000nnnn00001010
3559 case 1: // STS MACL,Rn 0000nnnn00011010
3562 case 2: // STS PR,Rn 0000nnnn00101010
3569 opd->source = BITMASK1(tmp);
3570 opd->dest = BITMASK1(GET_Rn());
3573 CHECK_UNHANDLED_BITS(0xf00, undefined);
3576 case 0: // RTS 0000000000001011
3577 opd->op = OP_BRANCH_R;
3579 opd->source = BITMASK1(opd->rm);
3580 opd->dest = BITMASK1(SHR_PC);
3585 case 1: // SLEEP 0000000000011011
3589 case 2: // RTE 0000000000101011
3591 opd->source = BITMASK1(SHR_SP);
3592 opd->dest = BITMASK2(SHR_SR, SHR_PC);
3601 case 0x0c: // MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100
3602 case 0x0d: // MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101
3603 case 0x0e: // MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110
3604 opd->source = BITMASK2(GET_Rm(), SHR_R0);
3605 opd->dest = BITMASK1(GET_Rn());
3607 case 0x0f: // MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111
3608 opd->source = BITMASK5(GET_Rm(), GET_Rn(), SHR_SR, SHR_MACL, SHR_MACH);
3609 opd->dest = BITMASK4(GET_Rm(), GET_Rn(), SHR_MACL, SHR_MACH);
3617 /////////////////////////////////////////////
3619 // MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd
3620 opd->source = BITMASK1(GET_Rm());
3621 opd->source = BITMASK1(GET_Rn());
3622 opd->imm = (op & 0x0f) * 4;
3625 /////////////////////////////////////////////
3629 case 0x00: // MOV.B Rm,@Rn 0010nnnnmmmm0000
3630 case 0x01: // MOV.W Rm,@Rn 0010nnnnmmmm0001
3631 case 0x02: // MOV.L Rm,@Rn 0010nnnnmmmm0010
3632 opd->source = BITMASK1(GET_Rm());
3633 opd->source = BITMASK1(GET_Rn());
3635 case 0x04: // MOV.B Rm,@-Rn 0010nnnnmmmm0100
3636 case 0x05: // MOV.W Rm,@-Rn 0010nnnnmmmm0101
3637 case 0x06: // MOV.L Rm,@-Rn 0010nnnnmmmm0110
3638 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3639 opd->dest = BITMASK1(GET_Rn());
3641 case 0x07: // DIV0S Rm,Rn 0010nnnnmmmm0111
3642 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3643 opd->dest = BITMASK1(SHR_SR);
3645 case 0x08: // TST Rm,Rn 0010nnnnmmmm1000
3646 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3647 opd->dest = BITMASK1(SHR_T);
3649 case 0x09: // AND Rm,Rn 0010nnnnmmmm1001
3650 case 0x0a: // XOR Rm,Rn 0010nnnnmmmm1010
3651 case 0x0b: // OR Rm,Rn 0010nnnnmmmm1011
3652 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3653 opd->dest = BITMASK1(GET_Rn());
3655 case 0x0c: // CMP/STR Rm,Rn 0010nnnnmmmm1100
3656 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3657 opd->dest = BITMASK1(SHR_T);
3659 case 0x0d: // XTRCT Rm,Rn 0010nnnnmmmm1101
3660 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3661 opd->dest = BITMASK1(GET_Rn());
3663 case 0x0e: // MULU.W Rm,Rn 0010nnnnmmmm1110
3664 case 0x0f: // MULS.W Rm,Rn 0010nnnnmmmm1111
3665 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3666 opd->dest = BITMASK1(SHR_MACL);
3673 /////////////////////////////////////////////
3677 case 0x00: // CMP/EQ Rm,Rn 0011nnnnmmmm0000
3678 case 0x02: // CMP/HS Rm,Rn 0011nnnnmmmm0010
3679 case 0x03: // CMP/GE Rm,Rn 0011nnnnmmmm0011
3680 case 0x06: // CMP/HI Rm,Rn 0011nnnnmmmm0110
3681 case 0x07: // CMP/GT Rm,Rn 0011nnnnmmmm0111
3682 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3683 opd->dest = BITMASK1(SHR_T);
3685 case 0x04: // DIV1 Rm,Rn 0011nnnnmmmm0100
3686 opd->source = BITMASK3(GET_Rm(), GET_Rn(), SHR_SR);
3687 opd->dest = BITMASK2(GET_Rn(), SHR_SR);
3689 case 0x05: // DMULU.L Rm,Rn 0011nnnnmmmm0101
3690 case 0x0d: // DMULS.L Rm,Rn 0011nnnnmmmm1101
3691 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3692 opd->dest = BITMASK2(SHR_MACL, SHR_MACH);
3695 case 0x08: // SUB Rm,Rn 0011nnnnmmmm1000
3696 case 0x0c: // ADD Rm,Rn 0011nnnnmmmm1100
3697 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3698 opd->dest = BITMASK1(GET_Rn());
3700 case 0x0a: // SUBC Rm,Rn 0011nnnnmmmm1010
3701 case 0x0e: // ADDC Rm,Rn 0011nnnnmmmm1110
3702 opd->source = BITMASK3(GET_Rm(), GET_Rn(), SHR_T);
3703 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3705 case 0x0b: // SUBV Rm,Rn 0011nnnnmmmm1011
3706 case 0x0f: // ADDV Rm,Rn 0011nnnnmmmm1111
3707 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3708 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3715 /////////////////////////////////////////////
3722 case 0: // SHLL Rn 0100nnnn00000000
3723 case 2: // SHAL Rn 0100nnnn00100000
3724 opd->source = BITMASK1(GET_Rn());
3725 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3727 case 1: // DT Rn 0100nnnn00010000
3728 opd->source = BITMASK1(GET_Rn());
3729 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3738 case 0: // SHLR Rn 0100nnnn00000001
3739 case 2: // SHAR Rn 0100nnnn00100001
3740 opd->source = BITMASK1(GET_Rn());
3741 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3743 case 1: // CMP/PZ Rn 0100nnnn00010001
3744 opd->source = BITMASK1(GET_Rn());
3745 opd->dest = BITMASK1(SHR_T);
3755 case 0x02: // STS.L MACH,@-Rn 0100nnnn00000010
3758 case 0x12: // STS.L MACL,@-Rn 0100nnnn00010010
3761 case 0x22: // STS.L PR,@-Rn 0100nnnn00100010
3764 case 0x03: // STC.L SR,@-Rn 0100nnnn00000011
3768 case 0x13: // STC.L GBR,@-Rn 0100nnnn00010011
3772 case 0x23: // STC.L VBR,@-Rn 0100nnnn00100011
3779 opd->source = BITMASK2(GET_Rn(), tmp);
3780 opd->dest = BITMASK1(GET_Rn());
3786 case 0x04: // ROTL Rn 0100nnnn00000100
3787 case 0x05: // ROTR Rn 0100nnnn00000101
3788 opd->source = BITMASK1(GET_Rn());
3789 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3791 case 0x24: // ROTCL Rn 0100nnnn00100100
3792 case 0x25: // ROTCR Rn 0100nnnn00100101
3793 opd->source = BITMASK2(GET_Rn(), SHR_T);
3794 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3796 case 0x15: // CMP/PL Rn 0100nnnn00010101
3797 opd->source = BITMASK1(GET_Rn());
3798 opd->dest = BITMASK1(SHR_T);
3808 case 0x06: // LDS.L @Rm+,MACH 0100mmmm00000110
3811 case 0x16: // LDS.L @Rm+,MACL 0100mmmm00010110
3814 case 0x26: // LDS.L @Rm+,PR 0100mmmm00100110
3817 case 0x07: // LDC.L @Rm+,SR 0100mmmm00000111
3821 case 0x17: // LDC.L @Rm+,GBR 0100mmmm00010111
3825 case 0x27: // LDC.L @Rm+,VBR 0100mmmm00100111
3832 opd->source = BITMASK1(GET_Rn());
3833 opd->dest = BITMASK2(GET_Rn(), tmp);
3840 // SHLL2 Rn 0100nnnn00001000
3841 // SHLR2 Rn 0100nnnn00001001
3844 // SHLL8 Rn 0100nnnn00011000
3845 // SHLR8 Rn 0100nnnn00011001
3848 // SHLL16 Rn 0100nnnn00101000
3849 // SHLR16 Rn 0100nnnn00101001
3854 opd->source = BITMASK1(GET_Rn());
3855 opd->dest = BITMASK1(GET_Rn());
3860 case 0: // LDS Rm,MACH 0100mmmm00001010
3863 case 1: // LDS Rm,MACL 0100mmmm00011010
3866 case 2: // LDS Rm,PR 0100mmmm00101010
3873 opd->source = BITMASK1(GET_Rn());
3874 opd->dest = BITMASK1(tmp);
3879 case 0: // JSR @Rm 0100mmmm00001011
3880 opd->dest = BITMASK1(SHR_PR);
3881 case 2: // JMP @Rm 0100mmmm00101011
3882 opd->op = OP_BRANCH_R;
3884 opd->source = BITMASK1(opd->rm);
3885 opd->dest |= BITMASK1(SHR_PC);
3890 case 1: // TAS.B @Rn 0100nnnn00011011
3891 opd->source = BITMASK1(GET_Rn());
3892 opd->dest = BITMASK1(SHR_T);
3902 case 0: // LDC Rm,SR 0100mmmm00001110
3905 case 1: // LDC Rm,GBR 0100mmmm00011110
3908 case 2: // LDC Rm,VBR 0100mmmm00101110
3915 opd->source = BITMASK1(GET_Rn());
3916 opd->dest = BITMASK1(tmp);
3919 // MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111
3920 opd->source = BITMASK5(GET_Rm(), GET_Rn(), SHR_SR, SHR_MACL, SHR_MACH);
3921 opd->dest = BITMASK4(GET_Rm(), GET_Rn(), SHR_MACL, SHR_MACH);
3929 /////////////////////////////////////////////
3931 // MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd
3932 opd->source = BITMASK1(GET_Rm());
3933 opd->dest = BITMASK1(GET_Rn());
3934 opd->imm = (op & 0x0f) * 4;
3937 /////////////////////////////////////////////
3941 case 0x04: // MOV.B @Rm+,Rn 0110nnnnmmmm0100
3942 case 0x05: // MOV.W @Rm+,Rn 0110nnnnmmmm0101
3943 case 0x06: // MOV.L @Rm+,Rn 0110nnnnmmmm0110
3944 opd->dest = BITMASK1(GET_Rm());
3945 case 0x00: // MOV.B @Rm,Rn 0110nnnnmmmm0000
3946 case 0x01: // MOV.W @Rm,Rn 0110nnnnmmmm0001
3947 case 0x02: // MOV.L @Rm,Rn 0110nnnnmmmm0010
3948 opd->source = BITMASK1(GET_Rm());
3949 opd->dest |= BITMASK1(GET_Rn());
3951 case 0x0a: // NEGC Rm,Rn 0110nnnnmmmm1010
3952 opd->source = BITMASK2(GET_Rm(), SHR_T);
3953 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3955 case 0x03: // MOV Rm,Rn 0110nnnnmmmm0011
3958 case 0x07: // NOT Rm,Rn 0110nnnnmmmm0111
3959 case 0x08: // SWAP.B Rm,Rn 0110nnnnmmmm1000
3960 case 0x09: // SWAP.W Rm,Rn 0110nnnnmmmm1001
3961 case 0x0b: // NEG Rm,Rn 0110nnnnmmmm1011
3962 case 0x0c: // EXTU.B Rm,Rn 0110nnnnmmmm1100
3963 case 0x0d: // EXTU.W Rm,Rn 0110nnnnmmmm1101
3964 case 0x0e: // EXTS.B Rm,Rn 0110nnnnmmmm1110
3965 case 0x0f: // EXTS.W Rm,Rn 0110nnnnmmmm1111
3967 opd->source = BITMASK1(GET_Rm());
3968 opd->dest = BITMASK1(GET_Rn());
3973 /////////////////////////////////////////////
3975 // ADD #imm,Rn 0111nnnniiiiiiii
3976 opd->source = opd->dest = BITMASK1(GET_Rn());
3977 opd->imm = (int)(signed char)op;
3980 /////////////////////////////////////////////
3982 switch (op & 0x0f00)
3984 case 0x0000: // MOV.B R0,@(disp,Rn) 10000000nnnndddd
3985 opd->source = BITMASK2(GET_Rm(), SHR_R0);
3986 opd->imm = (op & 0x0f);
3988 case 0x0100: // MOV.W R0,@(disp,Rn) 10000001nnnndddd
3989 opd->source = BITMASK2(GET_Rm(), SHR_R0);
3990 opd->imm = (op & 0x0f) * 2;
3992 case 0x0400: // MOV.B @(disp,Rm),R0 10000100mmmmdddd
3993 opd->source = BITMASK1(GET_Rm());
3994 opd->dest = BITMASK1(SHR_R0);
3995 opd->imm = (op & 0x0f);
3997 case 0x0500: // MOV.W @(disp,Rm),R0 10000101mmmmdddd
3998 opd->source = BITMASK1(GET_Rm());
3999 opd->dest = BITMASK1(SHR_R0);
4000 opd->imm = (op & 0x0f) * 2;
4002 case 0x0800: // CMP/EQ #imm,R0 10001000iiiiiiii
4003 opd->source = BITMASK1(SHR_R0);
4004 opd->dest = BITMASK1(SHR_T);
4005 opd->imm = (int)(signed char)op;
4007 case 0x0d00: // BT/S label 10001101dddddddd
4008 case 0x0f00: // BF/S label 10001111dddddddd
4011 case 0x0900: // BT label 10001001dddddddd
4012 case 0x0b00: // BF label 10001011dddddddd
4013 opd->op = (op & 0x0200) ? OP_BRANCH_CF : OP_BRANCH_CT;
4014 opd->source = BITMASK1(SHR_T);
4015 opd->dest = BITMASK1(SHR_PC);
4016 opd->imm = ((signed int)(op << 24) >> 23);
4018 if (base_pc <= opd->imm && opd->imm < base_pc + BLOCK_INSN_LIMIT * 2)
4019 op_flags[(opd->imm - base_pc) / 2] |= OF_BTARGET;
4026 /////////////////////////////////////////////
4028 // MOV.W @(disp,PC),Rn 1001nnnndddddddd
4029 opd->op = OP_LOAD_POOL;
4031 if (op_flags[i] & OF_DELAY_OP) {
4032 if (ops[i-1].op == OP_BRANCH)
4037 opd->source = BITMASK1(SHR_PC);
4038 opd->dest = BITMASK1(GET_Rn());
4040 opd->imm = tmp + 2 + (op & 0xff) * 2;
4044 /////////////////////////////////////////////
4046 // BSR label 1011dddddddddddd
4047 opd->dest = BITMASK1(SHR_PR);
4049 // BRA label 1010dddddddddddd
4050 opd->op = OP_BRANCH;
4051 opd->dest |= BITMASK1(SHR_PC);
4052 opd->imm = ((signed int)(op << 20) >> 19);
4057 if (base_pc <= opd->imm && opd->imm < base_pc + BLOCK_INSN_LIMIT * 2)
4058 op_flags[(opd->imm - base_pc) / 2] |= OF_BTARGET;
4061 /////////////////////////////////////////////
4063 switch (op & 0x0f00)
4065 case 0x0000: // MOV.B R0,@(disp,GBR) 11000000dddddddd
4066 case 0x0100: // MOV.W R0,@(disp,GBR) 11000001dddddddd
4067 case 0x0200: // MOV.L R0,@(disp,GBR) 11000010dddddddd
4068 opd->source = BITMASK2(SHR_GBR, SHR_R0);
4069 opd->size = (op & 0x300) >> 8;
4070 opd->imm = (op & 0xff) << opd->size;
4072 case 0x0400: // MOV.B @(disp,GBR),R0 11000100dddddddd
4073 case 0x0500: // MOV.W @(disp,GBR),R0 11000101dddddddd
4074 case 0x0600: // MOV.L @(disp,GBR),R0 11000110dddddddd
4075 opd->source = BITMASK1(SHR_GBR);
4076 opd->dest = BITMASK1(SHR_R0);
4077 opd->size = (op & 0x300) >> 8;
4078 opd->imm = (op & 0xff) << opd->size;
4080 case 0x0300: // TRAPA #imm 11000011iiiiiiii
4081 opd->source = BITMASK2(SHR_PC, SHR_SR);
4082 opd->dest = BITMASK1(SHR_PC);
4083 opd->imm = (op & 0xff) * 4;
4085 end_block = 1; // FIXME
4087 case 0x0700: // MOVA @(disp,PC),R0 11000111dddddddd
4090 if (op_flags[i] & OF_DELAY_OP) {
4091 if (ops[i-1].op == OP_BRANCH)
4096 opd->dest = BITMASK1(SHR_R0);
4098 opd->imm = (tmp + 2 + (op & 0xff) * 4) & ~3;
4099 if (opd->imm >= base_pc) {
4100 if (lowest_mova == 0 || opd->imm < lowest_mova)
4101 lowest_mova = opd->imm;
4105 case 0x0800: // TST #imm,R0 11001000iiiiiiii
4106 opd->source = BITMASK1(SHR_R0);
4107 opd->dest = BITMASK1(SHR_T);
4108 opd->imm = op & 0xff;
4110 case 0x0900: // AND #imm,R0 11001001iiiiiiii
4111 opd->source = opd->dest = BITMASK1(SHR_R0);
4112 opd->imm = op & 0xff;
4114 case 0x0a00: // XOR #imm,R0 11001010iiiiiiii
4115 opd->source = opd->dest = BITMASK1(SHR_R0);
4116 opd->imm = op & 0xff;
4118 case 0x0b00: // OR #imm,R0 11001011iiiiiiii
4119 opd->source = opd->dest = BITMASK1(SHR_R0);
4120 opd->imm = op & 0xff;
4122 case 0x0c00: // TST.B #imm,@(R0,GBR) 11001100iiiiiiii
4123 opd->source = BITMASK2(SHR_GBR, SHR_R0);
4124 opd->dest = BITMASK1(SHR_T);
4125 opd->imm = op & 0xff;
4128 case 0x0d00: // AND.B #imm,@(R0,GBR) 11001101iiiiiiii
4129 case 0x0e00: // XOR.B #imm,@(R0,GBR) 11001110iiiiiiii
4130 case 0x0f00: // OR.B #imm,@(R0,GBR) 11001111iiiiiiii
4131 opd->source = BITMASK2(SHR_GBR, SHR_R0);
4132 opd->imm = op & 0xff;
4140 /////////////////////////////////////////////
4142 // MOV.L @(disp,PC),Rn 1101nnnndddddddd
4143 opd->op = OP_LOAD_POOL;
4145 if (op_flags[i] & OF_DELAY_OP) {
4146 if (ops[i-1].op == OP_BRANCH)
4151 opd->source = BITMASK1(SHR_PC);
4152 opd->dest = BITMASK1(GET_Rn());
4154 opd->imm = (tmp + 2 + (op & 0xff) * 4) & ~3;
4158 /////////////////////////////////////////////
4160 // MOV #imm,Rn 1110nnnniiiiiiii
4161 opd->dest = BITMASK1(GET_Rn());
4162 opd->imm = (u32)(signed int)(signed char)op;
4167 elprintf(EL_ANOMALY, "%csh2 drc: unhandled op %04x @ %08x",
4168 is_slave ? 's' : 'm', op, pc);
4172 if (op_flags[i] & OF_DELAY_OP) {
4179 elprintf(EL_ANOMALY, "%csh2 drc: branch in DS @ %08x",
4180 is_slave ? 's' : 'm', pc);
4181 opd->op = OP_UNHANDLED;
4182 op_flags[i] |= OF_B_IN_DS;
4191 // 2nd pass: some analysis
4192 for (i = 0; i < i_end; i++) {
4195 // propagate T (TODO: DIV0U)
4196 if ((opd->op == OP_SETCLRT && !opd->imm) || opd->op == OP_BRANCH_CT)
4197 op_flags[i + 1] |= OF_T_CLEAR;
4198 else if ((opd->op == OP_SETCLRT && opd->imm) || opd->op == OP_BRANCH_CF)
4199 op_flags[i + 1] |= OF_T_SET;
4201 if ((op_flags[i] & OF_BTARGET) || (opd->dest & BITMASK1(SHR_T)))
4202 op_flags[i] &= ~(OF_T_SET | OF_T_CLEAR);
4204 op_flags[i + 1] |= op_flags[i] & (OF_T_SET | OF_T_CLEAR);
4206 if ((opd->op == OP_BRANCH_CT && (op_flags[i] & OF_T_SET))
4207 || (opd->op == OP_BRANCH_CF && (op_flags[i] & OF_T_CLEAR)))
4209 opd->op = OP_BRANCH;
4212 if (op_flags[i + 1] & OF_DELAY_OP) {
4217 else if (opd->op == OP_LOAD_POOL)
4219 if (opd->imm < end_pc + MAX_LITERAL_OFFSET) {
4220 if (end_literals < opd->imm + opd->size * 2)
4221 end_literals = opd->imm + opd->size * 2;
4225 end_pc = base_pc + i_end * 2;
4226 if (end_literals < end_pc)
4227 end_literals = end_pc;
4229 // end_literals is used to decide to inline a literal or not
4230 // XXX: need better detection if this actually is used in write
4231 if (lowest_mova >= base_pc) {
4232 if (lowest_mova < end_literals) {
4233 dbg(1, "mova for %08x, block %08x", lowest_mova, base_pc);
4234 end_literals = end_pc;
4236 if (lowest_mova < end_pc) {
4237 dbg(1, "warning: mova inside of blk for %08x, block %08x",
4238 lowest_mova, base_pc);
4239 end_literals = end_pc;
4243 *end_pc_out = end_pc;
4244 if (end_literals_out != NULL)
4245 *end_literals_out = end_literals;
4248 // vim:shiftwidth=2:ts=2:expandtab