1 // SSP1601 to ARM recompiler
3 // (c) Copyright 2008, Grazvydas "notaz" Ignotas
4 // Free for non-commercial use.
6 #include "../../PicoInt.h"
9 #define u32 unsigned int
11 static u32 *tcache_ptr = NULL;
13 static int nblocks = 0;
14 static int n_in_ops = 0;
16 extern ssp1601_t *ssp;
18 #define rPC ssp->gr[SSP_PC].h
19 #define rPMC ssp->gr[SSP_PMC]
21 #define SSP_FLAG_Z (1<<0xd)
22 #define SSP_FLAG_N (1<<0xf)
25 #define DUMP_BLOCK 0x0c9a
26 u32 *ssp_block_table[0x5090/2];
27 u32 *ssp_block_table_iram[15][0x800/2];
28 u32 tcache[SSP_TCACHE_SIZE/4];
29 void ssp_drc_next(void){}
30 void ssp_drc_next_patch(void){}
31 void ssp_drc_end(void){}
36 // -----------------------------------------------------
38 static int get_inc(int mode)
40 int inc = (mode >> 11) & 7;
43 inc = 1 << inc; // 0 1 2 4 8 16 32 128
44 if (mode & 0x8000) inc = -inc; // decrement mode
49 u32 ssp_pm_read(int reg)
53 if (ssp->emu_status & SSP_PMC_SET)
55 ssp->pmac_read[reg] = rPMC.v;
56 ssp->emu_status &= ~SSP_PMC_SET;
61 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
63 mode = ssp->pmac_read[reg]>>16;
64 if ((mode & 0xfff0) == 0x0800) // ROM
66 d = ((unsigned short *)Pico.rom)[ssp->pmac_read[reg]&0xfffff];
67 ssp->pmac_read[reg] += 1;
69 else if ((mode & 0x47ff) == 0x0018) // DRAM
71 unsigned short *dram = (unsigned short *)svp->dram;
72 int inc = get_inc(mode);
73 d = dram[ssp->pmac_read[reg]&0xffff];
74 ssp->pmac_read[reg] += inc;
77 // PMC value corresponds to last PMR accessed
78 rPMC.v = ssp->pmac_read[reg];
83 #define overwrite_write(dst, d) \
85 if (d & 0xf000) { dst &= ~0xf000; dst |= d & 0xf000; } \
86 if (d & 0x0f00) { dst &= ~0x0f00; dst |= d & 0x0f00; } \
87 if (d & 0x00f0) { dst &= ~0x00f0; dst |= d & 0x00f0; } \
88 if (d & 0x000f) { dst &= ~0x000f; dst |= d & 0x000f; } \
91 void ssp_pm_write(u32 d, int reg)
96 if (ssp->emu_status & SSP_PMC_SET)
98 ssp->pmac_write[reg] = rPMC.v;
99 ssp->emu_status &= ~SSP_PMC_SET;
104 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
106 dram = (unsigned short *)svp->dram;
107 mode = ssp->pmac_write[reg]>>16;
108 addr = ssp->pmac_write[reg]&0xffff;
109 if ((mode & 0x43ff) == 0x0018) // DRAM
111 int inc = get_inc(mode);
113 overwrite_write(dram[addr], d);
114 } else dram[addr] = d;
115 ssp->pmac_write[reg] += inc;
117 else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
120 overwrite_write(dram[addr], d);
121 } else dram[addr] = d;
122 ssp->pmac_write[reg] += (addr&1) ? 0x1f : 1;
124 else if ((mode & 0x47ff) == 0x001c) // IRAM
126 int inc = get_inc(mode);
127 ((unsigned short *)svp->iram_rom)[addr&0x3ff] = d;
128 ssp->pmac_write[reg] += inc;
129 ssp->drc.iram_dirty = 1;
132 rPMC.v = ssp->pmac_write[reg];
136 // -----------------------------------------------------
139 static unsigned char iram_context_map[] =
141 0, 0, 0, 0, 1, 0, 0, 0, // 04
142 0, 0, 0, 0, 0, 0, 2, 0, // 0e
143 0, 0, 0, 0, 0, 3, 0, 4, // 15 17
144 5, 0, 0, 6, 0, 7, 0, 0, // 18 1b 1d
145 8, 9, 0, 0, 0,10, 0, 0, // 20 21 25
146 0, 0, 0, 0, 0, 0, 0, 0,
147 0, 0,11, 0, 0,12, 0, 0, // 32 35
148 13,14, 0, 0, 0, 0, 0, 0 // 38 39
151 int ssp_get_iram_context(void)
153 unsigned char *ir = (unsigned char *)svp->iram_rom;
154 int val1, val = ir[0x083^1] + ir[0x4FA^1] + ir[0x5F7^1] + ir[0x47B^1];
155 val1 = iram_context_map[(val>>1)&0x3f];
158 elprintf(EL_ANOMALY, "svp: iram ctx val: %02x PC=%04x\n", (val>>1)&0x3f, rPC);
159 //debug_dump2file(name, svp->iram_rom, 0x800);
165 // -----------------------------------------------------
167 /* regs with known values */
172 unsigned int pmac_read[5];
173 unsigned int pmac_write[5];
175 unsigned int emu_status;
178 #define KRREG_X (1 << SSP_X)
179 #define KRREG_Y (1 << SSP_Y)
180 #define KRREG_A (1 << SSP_A) /* AH only */
181 #define KRREG_ST (1 << SSP_ST)
182 #define KRREG_STACK (1 << SSP_STACK)
183 #define KRREG_PC (1 << SSP_PC)
184 #define KRREG_P (1 << SSP_P)
185 #define KRREG_PR0 (1 << 8)
186 #define KRREG_PR4 (1 << 12)
187 #define KRREG_AL (1 << 16)
188 #define KRREG_PMCM (1 << 18) /* only mode word of PMC */
189 #define KRREG_PMC (1 << 19)
190 #define KRREG_PM0R (1 << 20)
191 #define KRREG_PM1R (1 << 21)
192 #define KRREG_PM2R (1 << 22)
193 #define KRREG_PM3R (1 << 23)
194 #define KRREG_PM4R (1 << 24)
195 #define KRREG_PM0W (1 << 25)
196 #define KRREG_PM1W (1 << 26)
197 #define KRREG_PM2W (1 << 27)
198 #define KRREG_PM3W (1 << 28)
199 #define KRREG_PM4W (1 << 29)
201 /* bitfield of known register values */
202 static u32 known_regb = 0;
204 /* known vals, which need to be flushed
205 * (only ST, P, r0-r7, PMCx, PMxR, PMxW)
206 * ST means flags are being held in ARM PSR
207 * P means that it needs to be recalculated
209 static u32 dirty_regb = 0;
211 /* known values of host regs.
213 * 000000-00ffff - 16bit value
214 * 100000-10ffff - base reg (r7) + 16bit val
215 * 0r0000 - means reg (low) eq gr[r].h, r != AL
217 static int hostreg_r[4];
219 static void hostreg_clear(void)
222 for (i = 0; i < 4; i++)
226 static void hostreg_sspreg_changed(int sspreg)
229 for (i = 0; i < 4; i++)
230 if (hostreg_r[i] == (sspreg<<16)) hostreg_r[i] = -1;
234 #define PROGRAM(x) ((unsigned short *)svp->iram_rom)[x]
235 #define PROGRAM_P(x) ((unsigned short *)svp->iram_rom + (x))
237 void tr_unhandled(void)
239 //FILE *f = fopen("tcache.bin", "wb");
240 //fwrite(tcache, 1, (tcache_ptr - tcache)*4, f);
242 elprintf(EL_ANOMALY, "unhandled @ %04x\n", known_regs.gr[SSP_PC].h<<1);
246 /* update P, if needed. Trashes r0 */
247 static void tr_flush_dirty_P(void)
250 if (!(dirty_regb & KRREG_P)) return;
251 EOP_MOV_REG_ASR(10, 4, 16); // mov r10, r4, asr #16
252 EOP_MOV_REG_LSL( 0, 4, 16); // mov r0, r4, lsl #16
253 EOP_MOV_REG_ASR( 0, 0, 15); // mov r0, r0, asr #15
254 EOP_MUL(10, 0, 10); // mul r10, r0, r10
255 dirty_regb &= ~KRREG_P;
259 /* write dirty pr to host reg. Nothing is trashed */
260 static void tr_flush_dirty_pr(int r)
264 if (!(dirty_regb & (1 << (r+8)))) return;
267 case 0: ror = 0; break;
268 case 1: ror = 24/2; break;
269 case 2: ror = 16/2; break;
271 reg = (r < 4) ? 8 : 9;
272 EOP_BIC_IMM(reg,reg,ror,0xff);
273 if (known_regs.r[r] != 0)
274 EOP_ORR_IMM(reg,reg,ror,known_regs.r[r]);
275 dirty_regb &= ~(1 << (r+8));
278 /* write all dirty pr0-pr7 to host regs. Nothing is trashed */
279 static void tr_flush_dirty_prs(void)
282 int dirty = dirty_regb >> 8;
283 if ((dirty&7) == 7) {
284 emit_mov_const(A_COND_AL, 8, known_regs.r[0]|(known_regs.r[1]<<8)|(known_regs.r[2]<<16));
287 if ((dirty&0x70) == 0x70) {
288 emit_mov_const(A_COND_AL, 9, known_regs.r[4]|(known_regs.r[5]<<8)|(known_regs.r[6]<<16));
292 for (i = 0; dirty && i < 8; i++, dirty >>= 1)
294 if (!(dirty&1)) continue;
296 case 0: ror = 0; break;
297 case 1: ror = 24/2; break;
298 case 2: ror = 16/2; break;
300 reg = (i < 4) ? 8 : 9;
301 EOP_BIC_IMM(reg,reg,ror,0xff);
302 if (known_regs.r[i] != 0)
303 EOP_ORR_IMM(reg,reg,ror,known_regs.r[i]);
305 dirty_regb &= ~0xff00;
308 /* write dirty pr and "forget" it. Nothing is trashed. */
309 static void tr_release_pr(int r)
311 tr_flush_dirty_pr(r);
312 known_regb &= ~(1 << (r+8));
315 /* fush ARM PSR to r6. Trashes r1 */
316 static void tr_flush_dirty_ST(void)
318 if (!(dirty_regb & KRREG_ST)) return;
319 EOP_BIC_IMM(6,6,0,0x0f);
321 EOP_ORR_REG_LSR(6,6,1,28);
322 dirty_regb &= ~KRREG_ST;
326 /* inverse of above. Trashes r1 */
327 static void tr_make_dirty_ST(void)
329 if (dirty_regb & KRREG_ST) return;
330 if (known_regb & KRREG_ST) {
332 if (known_regs.gr[SSP_ST].h & SSP_FLAG_N) flags |= 8;
333 if (known_regs.gr[SSP_ST].h & SSP_FLAG_Z) flags |= 4;
334 EOP_MSR_IMM(4/2, flags);
336 EOP_MOV_REG_LSL(1, 6, 28);
340 dirty_regb |= KRREG_ST;
343 /* load 16bit val into host reg r0-r3. Nothing is trashed */
344 static void tr_mov16(int r, int val)
346 if (hostreg_r[r] != val) {
347 emit_mov_const(A_COND_AL, r, val);
352 static void tr_mov16_cond(int cond, int r, int val)
354 emit_mov_const(cond, r, val);
359 static void tr_flush_dirty_pmcrs(void)
361 u32 i, val = (u32)-1;
362 if (!(dirty_regb & 0x3ff80000)) return;
364 if (dirty_regb & KRREG_PMC) {
365 val = known_regs.pmc.v;
366 emit_mov_const(A_COND_AL, 1, val);
367 EOP_STR_IMM(1,7,0x400+SSP_PMC*4);
369 if (known_regs.emu_status & (SSP_PMC_SET|SSP_PMC_HAVE_ADDR)) {
370 elprintf(EL_ANOMALY, "!! SSP_PMC_SET|SSP_PMC_HAVE_ADDR set on flush\n");
374 for (i = 0; i < 5; i++)
376 if (dirty_regb & (1 << (20+i))) {
377 if (val != known_regs.pmac_read[i]) {
378 val = known_regs.pmac_read[i];
379 emit_mov_const(A_COND_AL, 1, val);
381 EOP_STR_IMM(1,7,0x454+i*4); // pmac_read
383 if (dirty_regb & (1 << (25+i))) {
384 if (val != known_regs.pmac_write[i]) {
385 val = known_regs.pmac_write[i];
386 emit_mov_const(A_COND_AL, 1, val);
388 EOP_STR_IMM(1,7,0x46c+i*4); // pmac_write
391 dirty_regb &= ~0x3ff80000;
395 /* read bank word to r0 (upper bits zero). Thrashes r1. */
396 static void tr_bank_read(int addr) /* word addr 0-0x1ff */
400 if (hostreg_r[1] != (0x100000|((addr&0x180)<<1))) {
401 EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1); // add r1, r7, ((op&0x180)<<1)
402 hostreg_r[1] = 0x100000|((addr&0x180)<<1);
406 EOP_LDRH_IMM(0,breg,(addr&0x7f)<<1); // ldrh r0, [r1, (op&0x7f)<<1]
410 /* write r0 to bank. Trashes r1. */
411 static void tr_bank_write(int addr)
415 if (hostreg_r[1] != (0x100000|((addr&0x180)<<1))) {
416 EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1); // add r1, r7, ((op&0x180)<<1)
417 hostreg_r[1] = 0x100000|((addr&0x180)<<1);
421 EOP_STRH_IMM(0,breg,(addr&0x7f)<<1); // strh r0, [r1, (op&0x7f)<<1]
424 /* handle RAM bank pointer modifiers. if need_modulo, trash r1-r3, else nothing */
425 static void tr_ptrr_mod(int r, int mod, int need_modulo, int count)
427 int modulo_shift = -1; /* unknown */
429 if (mod == 0) return;
431 if (!need_modulo || mod == 1) // +!
433 else if (need_modulo && (known_regb & KRREG_ST)) {
434 modulo_shift = known_regs.gr[SSP_ST].h & 7;
435 if (modulo_shift == 0) modulo_shift = 8;
438 if (modulo_shift == -1)
440 int reg = (r < 4) ? 8 : 9;
442 if (dirty_regb & KRREG_ST) {
443 // avoid flushing ARM flags
444 EOP_AND_IMM(1, 6, 0, 0x70);
445 EOP_SUB_IMM(1, 1, 0, 0x10);
446 EOP_AND_IMM(1, 1, 0, 0x70);
447 EOP_ADD_IMM(1, 1, 0, 0x10);
449 EOP_C_DOP_IMM(A_COND_AL,A_OP_AND,1,6,1,0,0x70); // ands r1, r6, #0x70
450 EOP_C_DOP_IMM(A_COND_EQ,A_OP_MOV,0,0,1,0,0x80); // moveq r1, #0x80
452 EOP_MOV_REG_LSR(1, 1, 4); // mov r1, r1, lsr #4
453 EOP_RSB_IMM(2, 1, 0, 8); // rsb r1, r1, #8
454 EOP_MOV_IMM(3, 8/2, count); // mov r3, #0x01000000
456 EOP_ADD_IMM(1, 1, 0, (r&3)*8); // add r1, r1, #(r&3)*8
457 EOP_MOV_REG2_ROR(reg,reg,1); // mov reg, reg, ror r1
459 EOP_SUB_REG2_LSL(reg,reg,3,2); // sub reg, reg, #0x01000000 << r2
460 else EOP_ADD_REG2_LSL(reg,reg,3,2);
461 EOP_RSB_IMM(1, 1, 0, 32); // rsb r1, r1, #32
462 EOP_MOV_REG2_ROR(reg,reg,1); // mov reg, reg, ror r1
463 hostreg_r[1] = hostreg_r[2] = hostreg_r[3] = -1;
465 else if (known_regb & (1 << (r + 8)))
467 int modulo = (1 << modulo_shift) - 1;
469 known_regs.r[r] = (known_regs.r[r] & ~modulo) | ((known_regs.r[r] - count) & modulo);
470 else known_regs.r[r] = (known_regs.r[r] & ~modulo) | ((known_regs.r[r] + count) & modulo);
474 int reg = (r < 4) ? 8 : 9;
475 int ror = ((r&3) + 1)*8 - (8 - modulo_shift);
476 EOP_MOV_REG_ROR(reg,reg,ror);
477 // {add|sub} reg, reg, #1<<shift
478 EOP_C_DOP_IMM(A_COND_AL,(mod==2)?A_OP_SUB:A_OP_ADD,0,reg,reg, 8/2, count << (8 - modulo_shift));
479 EOP_MOV_REG_ROR(reg,reg,32-ror);
483 /* handle writes r0 to (rX). Trashes r1.
484 * fortunately we can ignore modulo increment modes for writes. */
485 static void tr_rX_write(int op)
489 int mod = (op>>2) & 3; // direct addressing
490 tr_bank_write((op & 0x100) + mod);
494 int r = (op&3) | ((op>>6)&4);
495 if (known_regb & (1 << (r + 8))) {
496 tr_bank_write((op&0x100) | known_regs.r[r]);
498 int reg = (r < 4) ? 8 : 9;
499 int ror = ((4 - (r&3))*8) & 0x1f;
500 EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask>
502 EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift
503 if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr
504 else EOP_ADD_REG_LSL(1,7,1,1);
505 EOP_STRH_SIMPLE(0,1); // strh r0, [r1]
508 tr_ptrr_mod(r, (op>>2) & 3, 0, 1);
512 /* read (rX) to r0. Trashes r1-r3. */
513 static void tr_rX_read(int r, int mod)
517 tr_bank_read(((r << 6) & 0x100) + mod); // direct addressing
521 if (known_regb & (1 << (r + 8))) {
522 tr_bank_read(((r << 6) & 0x100) | known_regs.r[r]);
524 int reg = (r < 4) ? 8 : 9;
525 int ror = ((4 - (r&3))*8) & 0x1f;
526 EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask>
528 EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift
529 if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr
530 else EOP_ADD_REG_LSL(1,7,1,1);
531 EOP_LDRH_SIMPLE(0,1); // ldrh r0, [r1]
532 hostreg_r[0] = hostreg_r[1] = -1;
534 tr_ptrr_mod(r, mod, 1, 1);
538 /* read ((rX)) to r0. Trashes r1,r2. */
539 static void tr_rX_read2(int op)
541 int r = (op&3) | ((op>>6)&4); // src
544 tr_bank_read((op&0x100) | ((op>>2)&3));
545 } else if (known_regb & (1 << (r+8))) {
546 tr_bank_read((op&0x100) | known_regs.r[r]);
548 int reg = (r < 4) ? 8 : 9;
549 int ror = ((4 - (r&3))*8) & 0x1f;
550 EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask>
552 EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift
553 if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr
554 else EOP_ADD_REG_LSL(1,7,1,1);
555 EOP_LDRH_SIMPLE(0,1); // ldrh r0, [r1]
557 EOP_LDR_IMM(2,7,0x48c); // ptr_iram_rom
558 EOP_ADD_REG_LSL(2,2,0,1); // add r2, r2, r0, lsl #1
559 EOP_ADD_IMM(0,0,0,1); // add r0, r0, #1
561 tr_bank_write((op&0x100) | ((op>>2)&3));
562 } else if (known_regb & (1 << (r+8))) {
563 tr_bank_write((op&0x100) | known_regs.r[r]);
565 EOP_STRH_SIMPLE(0,1); // strh r0, [r1]
568 EOP_LDRH_SIMPLE(0,2); // ldrh r0, [r2]
569 hostreg_r[0] = hostreg_r[2] = -1;
572 // check if AL is going to be used later in block
573 static int tr_predict_al_need(void)
575 int tmpv, tmpv2, op, pc = known_regs.gr[SSP_PC].h;
584 tmpv2 = (op >> 4) & 0xf; // dst
585 tmpv = op & 0xf; // src
586 if ((tmpv2 == SSP_A && tmpv == SSP_P) || tmpv2 == SSP_AL) // ld A, P; ld AL, *
595 case 0x10: case 0x30: case 0x40: case 0x60: case 0x70:
596 tmpv = op & 0xf; // src
597 if (tmpv == SSP_AL) // OP *, AL
607 case 0x74: pc++; break;
617 // mpya (rj), (ri), b
621 case 0x5b: return 0; // cleared anyway
625 tmpv = op & 0xf; // src
626 if (tmpv == SSP_AL) return 1;
627 case 0x51: case 0x53: case 0x54: case 0x55: case 0x59: case 0x5c:
635 /* get ARM cond which would mean that SSP cond is satisfied. No trash. */
636 static int tr_cond_check(int op)
638 int f = (op & 0x100) >> 8;
640 case 0x00: return A_COND_AL; /* always true */
641 case 0x50: /* Z matches f(?) bit */
642 if (dirty_regb & KRREG_ST) return f ? A_COND_EQ : A_COND_NE;
643 EOP_TST_IMM(6, 0, 4);
644 return f ? A_COND_NE : A_COND_EQ;
645 case 0x70: /* N matches f(?) bit */
646 if (dirty_regb & KRREG_ST) return f ? A_COND_MI : A_COND_PL;
647 EOP_TST_IMM(6, 0, 8);
648 return f ? A_COND_NE : A_COND_EQ;
650 elprintf(EL_ANOMALY, "unimplemented cond?\n");
656 static int tr_neg_cond(int cond)
659 case A_COND_AL: elprintf(EL_ANOMALY, "neg for AL?\n"); exit(1);
660 case A_COND_EQ: return A_COND_NE;
661 case A_COND_NE: return A_COND_EQ;
662 case A_COND_MI: return A_COND_PL;
663 case A_COND_PL: return A_COND_MI;
664 default: elprintf(EL_ANOMALY, "bad cond for neg\n"); exit(1);
669 static int tr_aop_ssp2arm(int op)
672 case 1: return A_OP_SUB;
673 case 3: return A_OP_CMP;
674 case 4: return A_OP_ADD;
675 case 5: return A_OP_AND;
676 case 6: return A_OP_ORR;
677 case 7: return A_OP_EOR;
684 // -----------------------------------------------------
688 //@ r6: STACK and emu flags
692 // read general reg to r0. Trashes r1
693 static void tr_GR0_to_r0(int op)
698 static void tr_X_to_r0(int op)
700 if (hostreg_r[0] != (SSP_X<<16)) {
701 EOP_MOV_REG_LSR(0, 4, 16); // mov r0, r4, lsr #16
702 hostreg_r[0] = SSP_X<<16;
706 static void tr_Y_to_r0(int op)
708 if (hostreg_r[0] != (SSP_Y<<16)) {
709 EOP_MOV_REG_SIMPLE(0, 4); // mov r0, r4
710 hostreg_r[0] = SSP_Y<<16;
714 static void tr_A_to_r0(int op)
716 if (hostreg_r[0] != (SSP_A<<16)) {
717 EOP_MOV_REG_LSR(0, 5, 16); // mov r0, r5, lsr #16 @ AH
718 hostreg_r[0] = SSP_A<<16;
722 static void tr_ST_to_r0(int op)
724 // VR doesn't need much accuracy here..
725 EOP_MOV_REG_LSR(0, 6, 4); // mov r0, r6, lsr #4
726 EOP_AND_IMM(0, 0, 0, 0x67); // and r0, r0, #0x67
730 static void tr_STACK_to_r0(int op)
733 EOP_SUB_IMM(6, 6, 8/2, 0x20); // sub r6, r6, #1<<29
734 EOP_ADD_IMM(1, 7, 24/2, 0x04); // add r1, r7, 0x400
735 EOP_ADD_IMM(1, 1, 0, 0x48); // add r1, r1, 0x048
736 EOP_ADD_REG_LSR(1, 1, 6, 28); // add r1, r1, r6, lsr #28
737 EOP_LDRH_SIMPLE(0, 1); // ldrh r0, [r1]
738 hostreg_r[0] = hostreg_r[1] = -1;
741 static void tr_PC_to_r0(int op)
743 tr_mov16(0, known_regs.gr[SSP_PC].h);
746 static void tr_P_to_r0(int op)
749 EOP_MOV_REG_LSR(0, 10, 16); // mov r0, r10, lsr #16
753 static void tr_AL_to_r0(int op)
756 if (known_regb & KRREG_PMC) {
757 known_regs.emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR);
759 EOP_LDR_IMM(0,7,0x484); // ldr r1, [r7, #0x484] // emu_status
760 EOP_BIC_IMM(0,0,0,SSP_PMC_SET|SSP_PMC_HAVE_ADDR);
761 EOP_STR_IMM(0,7,0x484);
765 if (hostreg_r[0] != (SSP_AL<<16)) {
766 EOP_MOV_REG_SIMPLE(0, 5); // mov r0, r5
767 hostreg_r[0] = SSP_AL<<16;
771 static void tr_PMX_to_r0(int reg)
773 if ((known_regb & KRREG_PMC) && (known_regs.emu_status & SSP_PMC_SET))
775 known_regs.pmac_read[reg] = known_regs.pmc.v;
776 known_regs.emu_status &= ~SSP_PMC_SET;
777 known_regb |= 1 << (20+reg);
778 dirty_regb |= 1 << (20+reg);
782 if ((known_regb & KRREG_PMC) && (known_regb & (1 << (20+reg))))
784 u32 pmcv = known_regs.pmac_read[reg];
786 known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
788 if ((mode & 0xfff0) == 0x0800)
790 EOP_LDR_IMM(1,7,0x488); // rom_ptr
791 emit_mov_const(A_COND_AL, 0, (pmcv&0xfffff)<<1);
792 EOP_LDRH_REG(0,1,0); // ldrh r0, [r1, r0]
793 known_regs.pmac_read[reg] += 1;
795 else if ((mode & 0x47ff) == 0x0018) // DRAM
797 int inc = get_inc(mode);
798 EOP_LDR_IMM(1,7,0x490); // dram_ptr
799 emit_mov_const(A_COND_AL, 0, (pmcv&0xffff)<<1);
800 EOP_LDRH_REG(0,1,0); // ldrh r0, [r1, r0]
801 if (reg == 4 && (pmcv == 0x187f03 || pmcv == 0x187f04)) // wait loop detection
803 int flag = (pmcv == 0x187f03) ? SSP_WAIT_30FE06 : SSP_WAIT_30FE08;
805 EOP_LDR_IMM(1,7,0x484); // ldr r1, [r7, #0x484] // emu_status
806 EOP_TST_REG_SIMPLE(0,0);
807 EOP_C_DOP_IMM(A_COND_EQ,A_OP_SUB,0,11,11,22/2,1); // subeq r11, r11, #1024
808 EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1,24/2,flag>>8); // orreq r1, r1, #SSP_WAIT_30FE08
809 EOP_STR_IMM(1,7,0x484); // str r1, [r7, #0x484] // emu_status
811 known_regs.pmac_read[reg] += inc;
817 known_regs.pmc.v = known_regs.pmac_read[reg];
818 //known_regb |= KRREG_PMC;
819 dirty_regb |= KRREG_PMC;
820 dirty_regb |= 1 << (20+reg);
821 hostreg_r[0] = hostreg_r[1] = -1;
825 known_regb &= ~KRREG_PMC;
826 dirty_regb &= ~KRREG_PMC;
827 known_regb &= ~(1 << (20+reg));
828 dirty_regb &= ~(1 << (20+reg));
830 // call the C code to handle this
832 //tr_flush_dirty_pmcrs();
834 emit_call(A_COND_AL, ssp_pm_read);
838 static void tr_PM0_to_r0(int op)
843 static void tr_PM1_to_r0(int op)
848 static void tr_PM2_to_r0(int op)
853 static void tr_XST_to_r0(int op)
855 EOP_ADD_IMM(0, 7, 24/2, 4); // add r0, r7, #0x400
856 EOP_LDRH_IMM(0, 0, SSP_XST*4+2);
859 static void tr_PM4_to_r0(int op)
864 static void tr_PMC_to_r0(int op)
866 if (known_regb & KRREG_PMC)
868 if (known_regs.emu_status & SSP_PMC_HAVE_ADDR) {
869 known_regs.emu_status |= SSP_PMC_SET;
870 known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
871 // do nothing - this is handled elsewhere
873 tr_mov16(0, known_regs.pmc.l);
874 known_regs.emu_status |= SSP_PMC_HAVE_ADDR;
879 EOP_LDR_IMM(1,7,0x484); // ldr r1, [r7, #0x484] // emu_status
882 EOP_LDR_IMM(0, 7, 0x400+SSP_PMC*4);
883 EOP_TST_IMM(1, 0, SSP_PMC_HAVE_ADDR);
884 EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // orreq r1, r1, #..
885 EOP_C_DOP_IMM(A_COND_NE,A_OP_BIC,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // bicne r1, r1, #..
886 EOP_C_DOP_IMM(A_COND_NE,A_OP_ORR,0, 1, 1, 0, SSP_PMC_SET); // orrne r1, r1, #..
887 EOP_STR_IMM(1,7,0x484);
888 hostreg_r[0] = hostreg_r[1] = -1;
893 typedef void (tr_read_func)(int op);
895 static tr_read_func *tr_read_funcs[16] =
910 (tr_read_func *)tr_unhandled,
916 // write r0 to general reg handlers. Trashes r1
917 #define TR_WRITE_R0_TO_REG(reg) \
919 hostreg_sspreg_changed(reg); \
920 hostreg_r[0] = (reg)<<16; \
921 if (const_val != -1) { \
922 known_regs.gr[reg].h = const_val; \
923 known_regb |= 1 << (reg); \
925 known_regb &= ~(1 << (reg)); \
929 static void tr_r0_to_GR0(int const_val)
934 static void tr_r0_to_X(int const_val)
936 EOP_MOV_REG_LSL(4, 4, 16); // mov r4, r4, lsl #16
937 EOP_MOV_REG_LSR(4, 4, 16); // mov r4, r4, lsr #16
938 EOP_ORR_REG_LSL(4, 4, 0, 16); // orr r4, r4, r0, lsl #16
939 dirty_regb |= KRREG_P; // touching X or Y makes P dirty.
940 TR_WRITE_R0_TO_REG(SSP_X);
943 static void tr_r0_to_Y(int const_val)
945 EOP_MOV_REG_LSR(4, 4, 16); // mov r4, r4, lsr #16
946 EOP_ORR_REG_LSL(4, 4, 0, 16); // orr r4, r4, r0, lsl #16
947 EOP_MOV_REG_ROR(4, 4, 16); // mov r4, r4, ror #16
948 dirty_regb |= KRREG_P;
949 TR_WRITE_R0_TO_REG(SSP_Y);
952 static void tr_r0_to_A(int const_val)
954 if (tr_predict_al_need()) {
955 EOP_MOV_REG_LSL(5, 5, 16); // mov r5, r5, lsl #16
956 EOP_MOV_REG_LSR(5, 5, 16); // mov r5, r5, lsr #16 @ AL
957 EOP_ORR_REG_LSL(5, 5, 0, 16); // orr r5, r5, r0, lsl #16
960 EOP_MOV_REG_LSL(5, 0, 16);
961 TR_WRITE_R0_TO_REG(SSP_A);
964 static void tr_r0_to_ST(int const_val)
966 // VR doesn't need much accuracy here..
967 EOP_AND_IMM(1, 0, 0, 0x67); // and r1, r0, #0x67
968 EOP_AND_IMM(6, 6, 8/2, 0xe0); // and r6, r6, #7<<29 @ preserve STACK
969 EOP_ORR_REG_LSL(6, 6, 1, 4); // orr r6, r6, r1, lsl #4
970 TR_WRITE_R0_TO_REG(SSP_ST);
972 dirty_regb &= ~KRREG_ST;
975 static void tr_r0_to_STACK(int const_val)
978 EOP_ADD_IMM(1, 7, 24/2, 0x04); // add r1, r7, 0x400
979 EOP_ADD_IMM(1, 1, 0, 0x48); // add r1, r1, 0x048
980 EOP_ADD_REG_LSR(1, 1, 6, 28); // add r1, r1, r6, lsr #28
981 EOP_STRH_SIMPLE(0, 1); // strh r0, [r1]
982 EOP_ADD_IMM(6, 6, 8/2, 0x20); // add r6, r6, #1<<29
986 static void tr_r0_to_PC(int const_val)
989 * do nothing - dispatcher will take care of this
990 EOP_MOV_REG_LSL(1, 0, 16); // mov r1, r0, lsl #16
991 EOP_STR_IMM(1,7,0x400+6*4); // str r1, [r7, #(0x400+6*8)]
996 static void tr_r0_to_AL(int const_val)
998 EOP_MOV_REG_LSR(5, 5, 16); // mov r5, r5, lsr #16
999 EOP_ORR_REG_LSL(5, 5, 0, 16); // orr r5, r5, r0, lsl #16
1000 EOP_MOV_REG_ROR(5, 5, 16); // mov r5, r5, ror #16
1001 hostreg_sspreg_changed(SSP_AL);
1002 if (const_val != -1) {
1003 known_regs.gr[SSP_A].l = const_val;
1004 known_regb |= 1 << SSP_AL;
1006 known_regb &= ~(1 << SSP_AL);
1009 static void tr_r0_to_PMX(int reg)
1011 if ((known_regb & KRREG_PMC) && (known_regs.emu_status & SSP_PMC_SET))
1013 known_regs.pmac_write[reg] = known_regs.pmc.v;
1014 known_regs.emu_status &= ~SSP_PMC_SET;
1015 known_regb |= 1 << (25+reg);
1016 dirty_regb |= 1 << (25+reg);
1020 if ((known_regb & KRREG_PMC) && (known_regb & (1 << (25+reg))))
1024 known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
1026 mode = known_regs.pmac_write[reg]>>16;
1027 addr = known_regs.pmac_write[reg]&0xffff;
1028 if ((mode & 0x43ff) == 0x0018) // DRAM
1030 int inc = get_inc(mode);
1031 if (mode & 0x0400) tr_unhandled();
1032 EOP_LDR_IMM(1,7,0x490); // dram_ptr
1033 emit_mov_const(A_COND_AL, 2, addr<<1);
1034 EOP_STRH_REG(0,1,2); // strh r0, [r1, r2]
1035 known_regs.pmac_write[reg] += inc;
1037 else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
1039 if (mode & 0x0400) tr_unhandled();
1040 EOP_LDR_IMM(1,7,0x490); // dram_ptr
1041 emit_mov_const(A_COND_AL, 2, addr<<1);
1042 EOP_STRH_REG(0,1,2); // strh r0, [r1, r2]
1043 known_regs.pmac_write[reg] += (addr&1) ? 31 : 1;
1045 else if ((mode & 0x47ff) == 0x001c) // IRAM
1047 int inc = get_inc(mode);
1048 EOP_LDR_IMM(1,7,0x48c); // iram_ptr
1049 emit_mov_const(A_COND_AL, 2, (addr&0x3ff)<<1);
1050 EOP_STRH_REG(0,1,2); // strh r0, [r1, r2]
1052 EOP_STR_IMM(1,7,0x494); // iram_dirty
1053 known_regs.pmac_write[reg] += inc;
1058 known_regs.pmc.v = known_regs.pmac_write[reg];
1059 //known_regb |= KRREG_PMC;
1060 dirty_regb |= KRREG_PMC;
1061 dirty_regb |= 1 << (25+reg);
1062 hostreg_r[1] = hostreg_r[2] = -1;
1066 known_regb &= ~KRREG_PMC;
1067 dirty_regb &= ~KRREG_PMC;
1068 known_regb &= ~(1 << (25+reg));
1069 dirty_regb &= ~(1 << (25+reg));
1071 // call the C code to handle this
1072 tr_flush_dirty_ST();
1073 //tr_flush_dirty_pmcrs();
1075 emit_call(A_COND_AL, ssp_pm_write);
1079 static void tr_r0_to_PM0(int const_val)
1084 static void tr_r0_to_PM1(int const_val)
1089 static void tr_r0_to_PM2(int const_val)
1094 static void tr_r0_to_PM4(int const_val)
1099 static void tr_r0_to_PMC(int const_val)
1101 if ((known_regb & KRREG_PMC) && const_val != -1)
1103 if (known_regs.emu_status & SSP_PMC_HAVE_ADDR) {
1104 known_regs.emu_status |= SSP_PMC_SET;
1105 known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
1106 known_regs.pmc.h = const_val;
1108 known_regs.emu_status |= SSP_PMC_HAVE_ADDR;
1109 known_regs.pmc.l = const_val;
1114 tr_flush_dirty_ST();
1115 if (known_regb & KRREG_PMC) {
1116 emit_mov_const(A_COND_AL, 1, known_regs.pmc.v);
1117 EOP_STR_IMM(1,7,0x400+SSP_PMC*4);
1118 known_regb &= ~KRREG_PMC;
1119 dirty_regb &= ~KRREG_PMC;
1121 EOP_LDR_IMM(1,7,0x484); // ldr r1, [r7, #0x484] // emu_status
1122 EOP_ADD_IMM(2,7,24/2,4); // add r2, r7, #0x400
1123 EOP_TST_IMM(1, 0, SSP_PMC_HAVE_ADDR);
1124 EOP_C_AM3_IMM(A_COND_EQ,1,0,2,0,0,1,SSP_PMC*4); // strxx r0, [r2, #SSP_PMC]
1125 EOP_C_AM3_IMM(A_COND_NE,1,0,2,0,0,1,SSP_PMC*4+2);
1126 EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // orreq r1, r1, #..
1127 EOP_C_DOP_IMM(A_COND_NE,A_OP_BIC,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // bicne r1, r1, #..
1128 EOP_C_DOP_IMM(A_COND_NE,A_OP_ORR,0, 1, 1, 0, SSP_PMC_SET); // orrne r1, r1, #..
1129 EOP_STR_IMM(1,7,0x484);
1130 hostreg_r[1] = hostreg_r[2] = -1;
1134 typedef void (tr_write_func)(int const_val);
1136 static tr_write_func *tr_write_funcs[16] =
1145 (tr_write_func *)tr_unhandled,
1149 (tr_write_func *)tr_unhandled,
1151 (tr_write_func *)tr_unhandled,
1156 static void tr_mac_load_XY(int op)
1158 tr_rX_read(op&3, (op>>2)&3); // X
1159 EOP_MOV_REG_LSL(4, 0, 16);
1160 tr_rX_read(((op>>4)&3)|4, (op>>6)&3); // Y
1161 EOP_ORR_REG_SIMPLE(4, 0);
1162 dirty_regb |= KRREG_P;
1163 hostreg_sspreg_changed(SSP_X);
1164 hostreg_sspreg_changed(SSP_Y);
1165 known_regb &= ~KRREG_X;
1166 known_regb &= ~KRREG_Y;
1169 // -----------------------------------------------------
1171 static int tr_detect_set_pm(unsigned int op, int *pc, int imm)
1174 if (!((op&0xfef0) == 0x08e0 && (PROGRAM(*pc)&0xfef0) == 0x08e0)) return 0;
1180 pmcv = imm | (PROGRAM((*pc)++) << 16);
1181 known_regs.pmc.v = pmcv;
1182 known_regb |= KRREG_PMC;
1183 dirty_regb |= KRREG_PMC;
1184 known_regs.emu_status |= SSP_PMC_SET;
1187 // check for possible reg programming
1188 tmpv = PROGRAM(*pc);
1189 if ((tmpv & 0xfff8) == 0x08 || (tmpv & 0xff8f) == 0x80)
1191 int is_write = (tmpv & 0xff8f) == 0x80;
1192 int reg = is_write ? ((tmpv>>4)&0x7) : (tmpv&0x7);
1193 if (reg > 4) tr_unhandled();
1194 if ((tmpv & 0x0f) != 0 && (tmpv & 0xf0) != 0) tr_unhandled();
1195 known_regs.pmac_read[is_write ? reg + 5 : reg] = pmcv;
1196 known_regb |= is_write ? (1 << (reg+25)) : (1 << (reg+20));
1197 dirty_regb |= is_write ? (1 << (reg+25)) : (1 << (reg+20));
1198 known_regs.emu_status &= ~SSP_PMC_SET;
1208 static const short pm0_block_seq[] = { 0x0880, 0, 0x0880, 0, 0x0840, 0x60 };
1210 static int tr_detect_pm0_block(unsigned int op, int *pc, int imm)
1217 if (op != 0x0840 || imm != 0) return 0;
1218 pp = PROGRAM_P(*pc);
1219 if (memcmp(pp, pm0_block_seq, sizeof(pm0_block_seq)) != 0) return 0;
1221 EOP_AND_IMM(6, 6, 8/2, 0xe0); // and r6, r6, #7<<29 @ preserve STACK
1222 EOP_ORR_IMM(6, 6, 24/2, 6); // orr r6, r6, 0x600
1223 hostreg_sspreg_changed(SSP_ST);
1224 known_regs.gr[SSP_ST].h = 0x60;
1225 known_regb |= 1 << SSP_ST;
1226 dirty_regb &= ~KRREG_ST;
1232 static int tr_detect_rotate(unsigned int op, int *pc, int imm)
1238 if (op != 0x02e3 || PROGRAM(*pc) != 0x04e3 || PROGRAM(*pc + 1) != 0x000f) return 0;
1241 EOP_MOV_REG_LSL(0, 0, 4);
1242 EOP_ORR_REG_LSR(0, 0, 0, 16);
1249 // -----------------------------------------------------
1251 static int translate_op(unsigned int op, int *pc, int imm, int *end_cond, int *jump_pc)
1253 u32 tmpv, tmpv2, tmpv3;
1255 known_regs.gr[SSP_PC].h = *pc;
1261 if (op == 0) { ret++; break; } // nop
1262 tmpv = op & 0xf; // src
1263 tmpv2 = (op >> 4) & 0xf; // dst
1264 if (tmpv2 == SSP_A && tmpv == SSP_P) { // ld A, P
1266 EOP_MOV_REG_SIMPLE(5, 10);
1267 hostreg_sspreg_changed(SSP_A);
1268 known_regb &= ~(KRREG_A|KRREG_AL);
1271 tr_read_funcs[tmpv](op);
1272 tr_write_funcs[tmpv2]((known_regb & (1 << tmpv)) ? known_regs.gr[tmpv].h : -1);
1273 if (tmpv2 == SSP_PC) {
1275 *end_cond = -A_COND_AL;
1281 int r = (op&3) | ((op>>6)&4);
1282 int mod = (op>>2)&3;
1283 tmpv = (op >> 4) & 0xf; // dst
1284 ret = tr_detect_rotate(op, pc, imm);
1290 while (PROGRAM(*pc) == op) {
1291 (*pc)++; cnt++; ret++;
1294 tr_ptrr_mod(r, mod, 1, cnt); // skip
1296 tr_write_funcs[tmpv](-1);
1297 if (tmpv == SSP_PC) {
1299 *end_cond = -A_COND_AL;
1306 tmpv = (op >> 4) & 0xf; // src
1307 tr_read_funcs[tmpv](op);
1313 tr_bank_read(op&0x1ff);
1319 tmpv = (op & 0xf0) >> 4; // dst
1320 ret = tr_detect_pm0_block(op, pc, imm);
1322 ret = tr_detect_set_pm(op, pc, imm);
1325 tr_write_funcs[tmpv](imm);
1326 if (tmpv == SSP_PC) {
1334 tmpv2 = (op >> 4) & 0xf; // dst
1336 tr_write_funcs[tmpv2](-1);
1337 if (tmpv2 == SSP_PC) {
1339 *end_cond = -A_COND_AL;
1352 tr_bank_write(op&0x1ff);
1358 r = (op&3) | ((op>>6)&4); // src
1359 tmpv2 = (op >> 4) & 0xf; // dst
1360 if ((r&3) == 3) tr_unhandled();
1362 if (known_regb & (1 << (r+8))) {
1363 tr_mov16(0, known_regs.r[r]);
1364 tr_write_funcs[tmpv2](known_regs.r[r]);
1366 int reg = (r < 4) ? 8 : 9;
1367 if (r&3) EOP_MOV_REG_LSR(0, reg, (r&3)*8); // mov r0, r{7,8}, lsr #lsr
1368 EOP_AND_IMM(0, (r&3)?0:reg, 0, 0xff); // and r0, r{7,8}, <mask>
1370 tr_write_funcs[tmpv2](-1);
1378 r = (op&3) | ((op>>6)&4); // dst
1379 tmpv = (op >> 4) & 0xf; // src
1380 if ((r&3) == 3) tr_unhandled();
1382 if (known_regb & (1 << tmpv)) {
1383 known_regs.r[r] = known_regs.gr[tmpv].h;
1384 known_regb |= 1 << (r + 8);
1385 dirty_regb |= 1 << (r + 8);
1387 int reg = (r < 4) ? 8 : 9;
1388 int ror = ((4 - (r&3))*8) & 0x1f;
1389 tr_read_funcs[tmpv](op);
1390 EOP_BIC_IMM(reg, reg, ror/2, 0xff); // bic r{7,8}, r{7,8}, <mask>
1391 EOP_AND_IMM(0, 0, 0, 0xff); // and r0, r0, 0xff
1392 EOP_ORR_REG_LSL(reg, reg, 0, (r&3)*8); // orr r{7,8}, r{7,8}, r0, lsl #lsl
1394 known_regb &= ~(1 << (r+8));
1395 dirty_regb &= ~(1 << (r+8));
1401 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
1403 known_regs.r[tmpv] = op;
1404 known_regb |= 1 << (tmpv + 8);
1405 dirty_regb |= 1 << (tmpv + 8);
1410 u32 *jump_op = NULL;
1411 tmpv = tr_cond_check(op);
1412 if (tmpv != A_COND_AL) {
1413 jump_op = tcache_ptr;
1414 EOP_MOV_IMM(0, 0, 0); // placeholder for branch
1417 tr_r0_to_STACK(*pc);
1418 if (tmpv != A_COND_AL) {
1419 u32 *real_ptr = tcache_ptr;
1420 tcache_ptr = jump_op;
1421 EOP_C_B(tr_neg_cond(tmpv),0,real_ptr - jump_op - 2);
1422 tcache_ptr = real_ptr;
1424 tr_mov16_cond(tmpv, 0, imm);
1425 if (tmpv != A_COND_AL)
1426 tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc);
1427 tr_r0_to_PC(tmpv == A_COND_AL ? imm : -1);
1436 tmpv2 = (op >> 4) & 0xf; // dst
1438 EOP_LDR_IMM(1,7,0x48c); // ptr_iram_rom
1439 EOP_ADD_REG_LSL(0,1,0,1); // add r0, r1, r0, lsl #1
1440 EOP_LDRH_SIMPLE(0,0); // ldrh r0, [r0]
1441 hostreg_r[0] = hostreg_r[1] = -1;
1442 tr_write_funcs[tmpv2](-1);
1443 if (tmpv2 == SSP_PC) {
1445 *end_cond = -A_COND_AL;
1451 tmpv = tr_cond_check(op);
1452 tr_mov16_cond(tmpv, 0, imm);
1453 if (tmpv != A_COND_AL)
1454 tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc);
1455 tr_r0_to_PC(tmpv == A_COND_AL ? imm : -1);
1463 // check for repeats of this op
1465 while (PROGRAM(*pc) == op && (op & 7) != 6) {
1469 if ((op&0xf0) != 0) // !always
1472 tmpv2 = tr_cond_check(op);
1474 case 2: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_MOV,1,0,5,tmpv,A_AM1_ASR,5); break; // shr (arithmetic)
1475 case 3: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_MOV,1,0,5,tmpv,A_AM1_LSL,5); break; // shl
1476 case 6: EOP_C_DOP_IMM(tmpv2,A_OP_RSB,1,5,5,0,0); break; // neg
1477 case 7: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_EOR,0,5,1,31,A_AM1_ASR,5); // eor r1, r5, r5, asr #31
1478 EOP_C_DOP_REG_XIMM(tmpv2,A_OP_ADD,1,1,5,31,A_AM1_LSR,5); // adds r5, r1, r5, lsr #31
1479 hostreg_r[1] = -1; break; // abs
1480 default: tr_unhandled();
1483 hostreg_sspreg_changed(SSP_A);
1484 dirty_regb |= KRREG_ST;
1485 known_regb &= ~KRREG_ST;
1486 known_regb &= ~(KRREG_A|KRREG_AL);
1495 EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_SUB,1,5,5,0,A_AM1_LSL,10); // subs r5, r5, r10
1496 hostreg_sspreg_changed(SSP_A);
1497 known_regb &= ~(KRREG_A|KRREG_AL);
1498 dirty_regb |= KRREG_ST;
1501 // mpya (rj), (ri), b
1506 EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_ADD,1,5,5,0,A_AM1_LSL,10); // adds r5, r5, r10
1507 hostreg_sspreg_changed(SSP_A);
1508 known_regb &= ~(KRREG_A|KRREG_AL);
1509 dirty_regb |= KRREG_ST;
1512 // mld (rj), (ri), b
1514 EOP_C_DOP_IMM(A_COND_AL,A_OP_MOV,1,0,5,0,0); // movs r5, #0
1515 hostreg_sspreg_changed(SSP_A);
1516 known_regs.gr[SSP_A].v = 0;
1517 known_regb |= (KRREG_A|KRREG_AL);
1518 dirty_regb |= KRREG_ST;
1529 tmpv = op & 0xf; // src
1530 tmpv2 = tr_aop_ssp2arm(op>>13); // op
1531 tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1532 if (tmpv == SSP_P) {
1534 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3, 0,A_AM1_LSL,10); // OPs r5, r5, r10
1535 } else if (tmpv == SSP_A) {
1536 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3, 0,A_AM1_LSL, 5); // OPs r5, r5, r5
1538 tr_read_funcs[tmpv](op);
1539 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL, 0); // OPs r5, r5, r0, lsl #16
1541 hostreg_sspreg_changed(SSP_A);
1542 known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1543 dirty_regb |= KRREG_ST;
1553 tmpv2 = tr_aop_ssp2arm(op>>13); // op
1554 tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1555 tr_rX_read((op&3)|((op>>6)&4), (op>>2)&3);
1556 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
1557 hostreg_sspreg_changed(SSP_A);
1558 known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1559 dirty_regb |= KRREG_ST;
1569 tmpv2 = tr_aop_ssp2arm(op>>13); // op
1570 tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1571 tr_bank_read(op&0x1ff);
1572 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
1573 hostreg_sspreg_changed(SSP_A);
1574 known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1575 dirty_regb |= KRREG_ST;
1585 tmpv = (op & 0xf0) >> 4;
1586 tmpv2 = tr_aop_ssp2arm(op>>13); // op
1587 tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1589 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
1590 hostreg_sspreg_changed(SSP_A);
1591 known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1592 dirty_regb |= KRREG_ST;
1602 tmpv2 = tr_aop_ssp2arm(op>>13); // op
1603 tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1605 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
1606 hostreg_sspreg_changed(SSP_A);
1607 known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1608 dirty_regb |= KRREG_ST;
1619 tmpv2 = tr_aop_ssp2arm(op>>13); // op
1620 tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1621 r = (op&3) | ((op>>6)&4); // src
1622 if ((r&3) == 3) tr_unhandled();
1624 if (known_regb & (1 << (r+8))) {
1625 EOP_C_DOP_IMM(A_COND_AL,tmpv2,1,5,tmpv3,16/2,known_regs.r[r]); // OPs r5, r5, #val<<16
1627 int reg = (r < 4) ? 8 : 9;
1628 if (r&3) EOP_MOV_REG_LSR(0, reg, (r&3)*8); // mov r0, r{7,8}, lsr #lsr
1629 EOP_AND_IMM(0, (r&3)?0:reg, 0, 0xff); // and r0, r{7,8}, <mask>
1630 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
1633 hostreg_sspreg_changed(SSP_A);
1634 known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1635 dirty_regb |= KRREG_ST;
1646 tmpv2 = tr_aop_ssp2arm(op>>13); // op
1647 tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1648 EOP_C_DOP_IMM(A_COND_AL,tmpv2,1,5,tmpv3,16/2,op & 0xff); // OPs r5, r5, #val<<16
1649 hostreg_sspreg_changed(SSP_A);
1650 known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1651 dirty_regb |= KRREG_ST;
1660 static void emit_block_prologue(void)
1662 // check if there are enough cycles..
1663 // note: r0 must contain PC of current block
1664 EOP_CMP_IMM(11,0,0); // cmp r11, #0
1665 emit_call(A_COND_LE, ssp_drc_end);
1669 * >0: direct (un)conditional jump
1672 static void emit_block_epilogue(int cycles, int cond, int pc, int end_pc)
1674 if (cycles > 0xff) { elprintf(EL_ANOMALY, "large cycle count: %i\n", cycles); cycles = 0xff; }
1675 EOP_SUB_IMM(11,11,0,cycles); // sub r11, r11, #cycles
1677 if (cond < 0 || (end_pc >= 0x400 && pc < 0x400)) {
1678 // indirect jump, or rom -> iram jump, must use dispatcher
1679 emit_jump(A_COND_AL, ssp_drc_next);
1681 else if (cond == A_COND_AL) {
1682 u32 *target = (pc < 0x400) ? ssp_block_table_iram[ssp->drc.iram_context][pc] : ssp_block_table[pc];
1684 emit_jump(A_COND_AL, target);
1686 emit_jump(A_COND_AL, ssp_drc_next);
1687 // cause the next block to be emitted over jump instrction
1692 u32 *target1 = (pc < 0x400) ? ssp_block_table_iram[ssp->drc.iram_context][pc] : ssp_block_table[pc];
1693 u32 *target2 = (end_pc < 0x400) ? ssp_block_table_iram[ssp->drc.iram_context][end_pc] : ssp_block_table[end_pc];
1694 if (target1 != NULL)
1695 emit_jump(cond, target1);
1696 else emit_call(cond, ssp_drc_next_patch);
1697 if (target2 != NULL)
1698 emit_jump(tr_neg_cond(cond), target2); // neg_cond, to be able to swap jumps if needed
1699 else emit_call(tr_neg_cond(cond), ssp_drc_next_patch);
1703 void *ssp_translate_block(int pc)
1705 unsigned int op, op1, imm, ccount = 0;
1706 unsigned int *block_start;
1707 int ret, end_cond = A_COND_AL, jump_pc = -1;
1709 //printf("translate %04x -> %04x\n", pc<<1, (tcache_ptr-tcache)<<2);
1710 block_start = tcache_ptr;
1712 dirty_regb = KRREG_P;
1713 known_regs.emu_status = 0;
1716 emit_block_prologue();
1718 for (; ccount < 100;)
1724 if ((op1 & 0xf) == 4 || (op1 & 0xf) == 6)
1725 imm = PROGRAM(pc++); // immediate
1727 ret = translate_op(op, &pc, imm, &end_cond, &jump_pc);
1730 elprintf(EL_ANOMALY, "NULL func! op=%08x (%02x)\n", op, op1);
1734 ccount += ret & 0xffff;
1735 if (ret & 0x10000) break;
1738 if (ccount >= 100) {
1739 end_cond = A_COND_AL;
1741 emit_mov_const(A_COND_AL, 0, pc);
1744 tr_flush_dirty_prs();
1745 tr_flush_dirty_ST();
1746 tr_flush_dirty_pmcrs();
1747 emit_block_epilogue(ccount, end_cond, jump_pc, pc);
1749 if (tcache_ptr - tcache > SSP_TCACHE_SIZE/4) {
1750 elprintf(EL_ANOMALY, "tcache overflow!\n");
1757 //printf("%i blocks, %i bytes, k=%.3f\n", nblocks, (tcache_ptr - tcache)*4,
1758 // (double)(tcache_ptr - tcache) / (double)n_in_ops);
1762 FILE *f = fopen("tcache.bin", "wb");
1763 fwrite(tcache, 1, (tcache_ptr - tcache)*4, f);
1776 // -----------------------------------------------------
1778 static void ssp1601_state_load(void)
1780 ssp->drc.iram_dirty = 1;
1781 ssp->drc.iram_context = 0;
1784 int ssp1601_dyn_startup(void)
1786 memset(tcache, 0, SSP_TCACHE_SIZE);
1787 memset(ssp_block_table, 0, sizeof(ssp_block_table));
1788 memset(ssp_block_table_iram, 0, sizeof(ssp_block_table_iram));
1789 tcache_ptr = tcache;
1791 PicoLoadStateHook = ssp1601_state_load;
1796 ssp_block_table[0x800/2] = (void *) ssp_hle_800;
1797 ssp_block_table[0x902/2] = (void *) ssp_hle_902;
1798 ssp_block_table_iram[ 7][0x030/2] = (void *) ssp_hle_07_030;
1799 ssp_block_table_iram[ 7][0x036/2] = (void *) ssp_hle_07_036;
1800 ssp_block_table_iram[ 7][0x6d6/2] = (void *) ssp_hle_07_6d6;
1801 ssp_block_table_iram[11][0x12c/2] = (void *) ssp_hle_11_12c;
1802 ssp_block_table_iram[11][0x384/2] = (void *) ssp_hle_11_384;
1803 ssp_block_table_iram[11][0x38a/2] = (void *) ssp_hle_11_38a;
1810 void ssp1601_dyn_reset(ssp1601_t *ssp)
1813 ssp->drc.iram_dirty = 1;
1814 ssp->drc.iram_context = 0;
1815 // must do this here because ssp is not available @ startup()
1816 ssp->drc.ptr_rom = (u32) Pico.rom;
1817 ssp->drc.ptr_iram_rom = (u32) svp->iram_rom;
1818 ssp->drc.ptr_dram = (u32) svp->dram;
1819 ssp->drc.ptr_btable = (u32) ssp_block_table;
1820 ssp->drc.ptr_btable_iram = (u32) ssp_block_table_iram;
1822 // prevent new versions of IRAM from appearing
1823 memset(svp->iram_rom, 0, 0x800);
1826 void ssp1601_dyn_run(int cycles)
1828 if (ssp->emu_status & SSP_WAIT_MASK) return;
1831 ssp_translate_block(DUMP_BLOCK >> 1);
1834 ssp_drc_entry(cycles);