1 /******************************************************************************
\r
3 * CZ80 (Z80 CPU emulator) version 0.9
\r
4 * Compiled with Dev-C++
\r
5 * Copyright 2004-2005 Stéphane Dallongeville
\r
9 *****************************************************************************/
\r
24 #include <pico/pico_port.h>
\r
26 /******************************/
\r
27 /* Compiler dependant defines */
\r
28 /******************************/
\r
58 /*************************************/
\r
59 /* Z80 core Structures & definitions */
\r
60 /*************************************/
\r
62 // NB this must have at least the value of (16-Z80_MEM_SHIFT)
\r
63 #define CZ80_FETCH_BITS 6 // [4-12] default = 8
\r
65 #define CZ80_FETCH_SFT (16 - CZ80_FETCH_BITS)
\r
66 #define CZ80_FETCH_BANK (1 << CZ80_FETCH_BITS)
\r
68 #define PICODRIVE_HACKS 1
\r
69 #define CZ80_LITTLE_ENDIAN CPU_IS_LE
\r
70 #define CZ80_USE_JUMPTABLE 1
\r
71 #define CZ80_BIG_FLAGS_ARRAY 1
\r
72 //#ifdef BUILD_CPS1PSP
\r
73 //#define CZ80_ENCRYPTED_ROM 1
\r
75 #define CZ80_ENCRYPTED_ROM 0
\r
77 #define CZ80_EMULATE_R_EXACTLY 1
\r
79 #define zR8(A) (*CPU->pzR8[A])
\r
80 #define zR16(A) (CPU->pzR16[A]->W)
\r
82 #define pzFA &(CPU->FA)
\r
83 #define zFA CPU->FA.W
\r
84 #define zlFA CPU->FA.B.L
\r
85 #define zhFA CPU->FA.B.H
\r
89 #define pzBC &(CPU->BC)
\r
90 #define zBC CPU->BC.W
\r
91 #define zlBC CPU->BC.B.L
\r
92 #define zhBC CPU->BC.B.H
\r
96 #define pzDE &(CPU->DE)
\r
97 #define zDE CPU->DE.W
\r
98 #define zlDE CPU->DE.B.L
\r
99 #define zhDE CPU->DE.B.H
\r
103 #define pzHL &(CPU->HL)
\r
104 #define zHL CPU->HL.W
\r
105 #define zlHL CPU->HL.B.L
\r
106 #define zhHL CPU->HL.B.H
\r
110 #define zFA2 CPU->FA2.W
\r
111 #define zlFA2 CPU->FA2.B.L
\r
112 #define zhFA2 CPU->FA2.B.H
\r
116 #define zBC2 CPU->BC2.W
\r
117 #define zDE2 CPU->DE2.W
\r
118 #define zHL2 CPU->HL2.W
\r
120 #define pzIX &(CPU->IX)
\r
121 #define zIX CPU->IX.W
\r
122 #define zlIX CPU->IX.B.L
\r
123 #define zhIX CPU->IX.B.H
\r
125 #define pzIY &(CPU->IY)
\r
126 #define zIY CPU->IY.W
\r
127 #define zlIY CPU->IY.B.L
\r
128 #define zhIY CPU->IY.B.H
\r
130 #define pzSP &(CPU->SP)
\r
131 #define zSP CPU->SP.W
\r
132 #define zlSP CPU->SP.B.L
\r
133 #define zhSP CPU->SP.B.H
\r
135 #define zRealPC (PC - CPU->BasePC)
\r
139 #define zIM CPU->IM
\r
141 #define zwR CPU->R.W
\r
142 #define zR1 CPU->R.B.L
\r
143 #define zR2 CPU->R.B.H
\r
146 #define zIFF CPU->IFF.W
\r
147 #define zIFF1 CPU->IFF.B.L
\r
148 #define zIFF2 CPU->IFF.B.H
\r
150 #define CZ80_SF_SFT 7
\r
151 #define CZ80_ZF_SFT 6
\r
152 #define CZ80_YF_SFT 5
\r
153 #define CZ80_HF_SFT 4
\r
154 #define CZ80_XF_SFT 3
\r
155 #define CZ80_PF_SFT 2
\r
156 #define CZ80_VF_SFT 2
\r
157 #define CZ80_NF_SFT 1
\r
158 #define CZ80_CF_SFT 0
\r
160 #define CZ80_SF (1 << CZ80_SF_SFT)
\r
161 #define CZ80_ZF (1 << CZ80_ZF_SFT)
\r
162 #define CZ80_YF (1 << CZ80_YF_SFT)
\r
163 #define CZ80_HF (1 << CZ80_HF_SFT)
\r
164 #define CZ80_XF (1 << CZ80_XF_SFT)
\r
165 #define CZ80_PF (1 << CZ80_PF_SFT)
\r
166 #define CZ80_VF (1 << CZ80_VF_SFT)
\r
167 #define CZ80_NF (1 << CZ80_NF_SFT)
\r
168 #define CZ80_CF (1 << CZ80_CF_SFT)
\r
170 #define CZ80_IFF_SFT CZ80_PF_SFT
\r
171 #define CZ80_IFF CZ80_PF
\r
173 #define CZ80_HAS_INT 0x1
\r
174 #define CZ80_HAS_NMI 0x2
\r
175 #define CZ80_HALTED 0x4
\r
177 #ifndef IRQ_LINE_STATE
\r
178 #define IRQ_LINE_STATE
\r
179 #define CLEAR_LINE 0 /* clear (a fired, held or pulsed) line */
\r
180 #define ASSERT_LINE 1 /* assert an interrupt immediately */
\r
181 #define HOLD_LINE 2 /* hold interrupt line until acknowledged */
\r
182 #define PULSE_LINE 3 /* pulse interrupt line for one instruction */
\r
183 #define IRQ_LINE_NMI 127 /* IRQ line for NMIs */
\r
213 #if CZ80_LITTLE_ENDIAN
\r
224 typedef struct cz80_t
\r
242 UINT32 unusedPC; /* left for binary compat */
\r
264 FPTR Fetch[CZ80_FETCH_BANK];
\r
265 #if CZ80_ENCRYPTED_ROM
\r
267 FPTR OPFetch[CZ80_FETCH_BANK];
\r
273 UINT8 (*Read_Byte)(UINT32 address);
\r
274 void (*Write_Byte)(UINT32 address, UINT8 data);
\r
276 UINT8 (*IN_Port)(UINT16 port);
\r
277 void (*OUT_Port)(UINT16 port, UINT8 value);
\r
279 INT32 (*Interrupt_Callback)(INT32 irqline);
\r
284 /*************************/
\r
285 /* Publics Z80 variables */
\r
286 /*************************/
\r
288 extern cz80_struc CZ80;
\r
290 /*************************/
\r
291 /* Publics Z80 functions */
\r
292 /*************************/
\r
294 void Cz80_Init(cz80_struc *CPU);
\r
296 void Cz80_Reset(cz80_struc *CPU);
\r
298 INT32 Cz80_Exec(cz80_struc *CPU, INT32 cycles);
\r
300 void Cz80_Set_IRQ(cz80_struc *CPU, INT32 line, INT32 state);
\r
302 UINT32 Cz80_Get_Reg(cz80_struc *CPU, INT32 regnum);
\r
303 void Cz80_Set_Reg(cz80_struc *CPU, INT32 regnum, UINT32 value);
\r
305 void Cz80_Set_Fetch(cz80_struc *CPU, UINT32 low_adr, UINT32 high_adr, FPTR fetch_adr);
\r
306 #if CZ80_ENCRYPTED_ROM
\r
307 void Cz80_Set_Encrypt_Range(cz80_struc *CPU, UINT32 low_adr, UINT32 high_adr, UINT32 decrypted_rom);
\r
310 void Cz80_Set_ReadB(cz80_struc *CPU, UINT8 (*Func)(UINT32 address));
\r
311 void Cz80_Set_WriteB(cz80_struc *CPU, void (*Func)(UINT32 address, UINT8 data));
\r
313 void Cz80_Set_INPort(cz80_struc *CPU, UINT8 (*Func)(UINT16 port));
\r
314 void Cz80_Set_OUTPort(cz80_struc *CPU, void (*Func)(UINT16 port, UINT8 value));
\r
316 void Cz80_Set_IRQ_Callback(cz80_struc *CPU, INT32 (*Func)(INT32 irqline));
\r
322 #endif /* CZ80_H */
\r