4 static int reg_map_g2h[] = {
13 enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
15 #define EMIT_PTR(ptr, val, type) \
18 #define EMIT(val, type) { \
19 EMIT_PTR(tcache_ptr, val, type); \
20 tcache_ptr = (char *)tcache_ptr + sizeof(type); \
23 #define EMIT_MODRM(mod,r,rm) \
24 EMIT(((mod)<<6) | ((r)<<3) | (rm), u8)
26 #define EMIT_OP_MODRM(op,mod,r,rm) { \
28 EMIT_MODRM(mod, r, rm); \
31 #define emith_move_r_r(dst, src) \
32 EMIT_OP_MODRM(0x8b, 3, dst, src)
34 #define emith_move_r_imm(r, imm) { \
35 EMIT(0xb8 + (r), u8); \
39 #define emith_add_r_imm(r, imm) { \
40 EMIT_OP_MODRM(0x81, 3, 0, r); \
44 #define emith_sub_r_imm(r, imm) { \
45 EMIT_OP_MODRM(0x81, 3, 5, r); \
49 // XXX: offs is 8bit only
50 #define emith_ctx_read(r, offs) { \
51 EMIT_OP_MODRM(0x8b, 1, r, 5); \
52 EMIT(offs, u8); /* mov tmp, [ebp+#offs] */ \
55 #define emith_ctx_write(r, offs) { \
56 EMIT_OP_MODRM(0x89, 1, r, 5); \
57 EMIT(offs, u8); /* mov [ebp+#offs], tmp */ \
60 #define emith_ctx_sub(val, offs) { \
61 EMIT_OP_MODRM(0x81, 1, 5, 5); \
63 EMIT(val, u32); /* sub [ebp+#offs], dword val */ \
66 #define emith_test_t() { \
67 if (reg_map_g2h[SHR_SR] == -1) { \
69 EMIT_MODRM(1, 0, 5); \
70 EMIT(SHR_SR * 4, u8); \
71 EMIT(0x01, u8); /* test [ebp+SHR_SR], byte 1 */ \
74 EMIT_MODRM(3, 0, reg_map_g2h[SHR_SR]); \
75 EMIT(0x01, u16); /* test <reg>, word 1 */ \
79 #define emith_jump(ptr) { \
80 u32 disp = (u32)ptr - ((u32)tcache_ptr + 5); \
85 #define emith_call(ptr) { \
86 u32 disp = (u32)ptr - ((u32)tcache_ptr + 5); \
91 #define EMIT_CONDITIONAL(code, is_nonzero) { \
92 char *ptr = tcache_ptr; \
93 tcache_ptr = (char *)tcache_ptr + 2; \
95 EMIT_PTR(ptr, ((is_nonzero) ? 0x75 : 0x74), u8); \
96 EMIT_PTR(ptr + 1, ((char *)tcache_ptr - (ptr + 2)), u8); \
99 static void emith_pass_arg(int count, ...)
106 for (i = 0; i < count; i++) {
107 long av = va_arg(vl, long);
111 case 0: r = xAX; break;
112 case 1: r = xDX; break;
113 case 2: r = xCX; break;
115 emith_move_r_imm(r, av);