3 * temp registers must be eax-edx due to use of SETcc.
4 * note about silly things like emith_eor_r_r_r:
5 * these are here because the compiler was designed
6 * for ARM as it's primary target.
10 enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
12 #define CONTEXT_REG xBP
15 #define ICOND_JNO 0x01
17 #define ICOND_JAE 0x03
19 #define ICOND_JNE 0x05
20 #define ICOND_JBE 0x06
23 #define ICOND_JNS 0x09
25 #define ICOND_JGE 0x0d
26 #define ICOND_JLE 0x0e
31 // unified conditions (we just use rel8 jump instructions for x86)
32 #define DCOND_EQ ICOND_JE
33 #define DCOND_NE ICOND_JNE
34 #define DCOND_MI ICOND_JS // MInus
35 #define DCOND_PL ICOND_JNS // PLus or zero
36 #define DCOND_HI ICOND_JA // higher (unsigned)
37 #define DCOND_HS ICOND_JAE // higher || same (unsigned)
38 #define DCOND_LO ICOND_JB // lower (unsigned)
39 #define DCOND_LS ICOND_JBE // lower || same (unsigned)
40 #define DCOND_GE ICOND_JGE // greater || equal (signed)
41 #define DCOND_GT ICOND_JG // greater (signed)
42 #define DCOND_LE ICOND_JLE // less || equal (signed)
43 #define DCOND_LT ICOND_JL // less (signed)
44 #define DCOND_VS ICOND_JO // oVerflow Set
45 #define DCOND_VC ICOND_JNO // oVerflow Clear
47 #define EMIT_PTR(ptr, val, type) \
50 #define EMIT(val, type) { \
51 EMIT_PTR(tcache_ptr, val, type); \
52 tcache_ptr += sizeof(type); \
55 #define EMIT_OP(op) { \
60 #define EMIT_MODRM(mod,r,rm) \
61 EMIT(((mod)<<6) | ((r)<<3) | (rm), u8)
63 #define EMIT_SIB(scale,index,base) \
64 EMIT(((scale)<<6) | ((index)<<3) | (base), u8)
66 #define EMIT_OP_MODRM(op,mod,r,rm) { \
68 EMIT_MODRM(mod, r, rm); \
71 #define JMP8_POS(ptr) \
75 #define JMP8_EMIT(op, ptr) \
76 EMIT_PTR(ptr, 0x70|(op), u8); \
77 EMIT_PTR(ptr + 1, (tcache_ptr - (ptr+2)), u8)
79 #define JMP8_EMIT_NC(ptr) \
80 EMIT_PTR(ptr, IOP_JMP, u8); \
81 EMIT_PTR(ptr + 1, (tcache_ptr - (ptr+2)), u8)
84 #define emith_move_r_r(dst, src) \
85 EMIT_OP_MODRM(0x8b, 3, dst, src)
87 #define emith_add_r_r(d, s) \
88 EMIT_OP_MODRM(0x01, 3, s, d)
90 #define emith_sub_r_r(d, s) \
91 EMIT_OP_MODRM(0x29, 3, s, d)
93 #define emith_adc_r_r(d, s) \
94 EMIT_OP_MODRM(0x11, 3, s, d)
96 #define emith_sbc_r_r(d, s) \
97 EMIT_OP_MODRM(0x19, 3, s, d) /* SBB */
99 #define emith_or_r_r(d, s) \
100 EMIT_OP_MODRM(0x09, 3, s, d)
102 #define emith_and_r_r(d, s) \
103 EMIT_OP_MODRM(0x21, 3, s, d)
105 #define emith_eor_r_r(d, s) \
106 EMIT_OP_MODRM(0x31, 3, s, d) /* XOR */
108 #define emith_tst_r_r(d, s) \
109 EMIT_OP_MODRM(0x85, 3, s, d) /* TEST */
111 #define emith_cmp_r_r(d, s) \
112 EMIT_OP_MODRM(0x39, 3, s, d)
114 // fake teq - test equivalence - get_flags(d ^ s)
115 #define emith_teq_r_r(d, s) { \
117 emith_eor_r_r(d, s); \
121 #define emith_mvn_r_r(d, s) { \
123 emith_move_r_r(d, s); \
124 EMIT_OP_MODRM(0xf7, 3, 2, d); /* NOT d */ \
127 #define emith_negc_r_r(d, s) { \
128 int tmp_ = rcache_get_tmp(); \
129 emith_move_r_imm(tmp_, 0); \
130 emith_sbc_r_r(tmp_, s); \
131 emith_move_r_r(d, tmp_); \
132 rcache_free_tmp(tmp_); \
135 #define emith_neg_r_r(d, s) { \
137 emith_move_r_r(d, s); \
138 EMIT_OP_MODRM(0xf7, 3, 3, d); /* NEG d */ \
142 #define emith_eor_r_r_r(d, s1, s2) { \
144 emith_eor_r_r(d, s2); \
145 } else if (d == s2) { \
146 emith_eor_r_r(d, s1); \
148 emith_move_r_r(d, s1); \
149 emith_eor_r_r(d, s2); \
154 #define emith_or_r_r_lsl(d, s, lslimm) { \
155 int tmp_ = rcache_get_tmp(); \
156 emith_lsl(tmp_, s, lslimm); \
157 emith_or_r_r(d, tmp_); \
158 rcache_free_tmp(tmp_); \
162 #define emith_eor_r_r_lsr(d, s, lsrimm) { \
164 emith_lsr(s, s, lsrimm); \
165 emith_eor_r_r(d, s); \
170 #define emith_move_r_imm(r, imm) { \
171 EMIT_OP(0xb8 + (r)); \
175 #define emith_move_r_imm_s8(r, imm) \
176 emith_move_r_imm(r, (u32)(signed int)(signed char)(imm))
178 #define emith_arith_r_imm(op, r, imm) do { \
179 EMIT_OP_MODRM(0x81, 3, op, r); \
184 #define emith_add_r_imm(r, imm) \
185 emith_arith_r_imm(0, r, imm)
187 #define emith_or_r_imm(r, imm) \
188 emith_arith_r_imm(1, r, imm)
190 #define emith_and_r_imm(r, imm) \
191 emith_arith_r_imm(4, r, imm)
193 #define emith_sub_r_imm(r, imm) \
194 emith_arith_r_imm(5, r, imm)
196 #define emith_eor_r_imm(r, imm) \
197 emith_arith_r_imm(6, r, imm)
199 #define emith_cmp_r_imm(r, imm) \
200 emith_arith_r_imm(7, r, imm)
202 #define emith_tst_r_imm(r, imm) do { \
203 EMIT_OP_MODRM(0xf7, 3, 0, r); \
208 #define emith_bic_r_imm(r, imm) \
209 emith_arith_r_imm(4, r, ~(imm))
211 // fake conditionals (using SJMP instead)
212 #define emith_move_r_imm_c(cond, r, imm) { \
214 emith_move_r_imm(r, imm); \
217 #define emith_add_r_imm_c(cond, r, imm) { \
219 emith_add_r_imm(r, imm); \
222 #define emith_sub_r_imm_c(cond, r, imm) { \
224 emith_sub_r_imm(r, imm); \
227 #define emith_or_r_imm_c(cond, r, imm) \
228 emith_or_r_imm(r, imm)
229 #define emith_eor_r_imm_c(cond, r, imm) \
230 emith_eor_r_imm(r, imm)
231 #define emith_bic_r_imm_c(cond, r, imm) \
232 emith_bic_r_imm(r, imm)
233 #define emith_ror_c(cond, d, s, cnt) \
236 #define emith_read_r_r_offs_c(cond, r, rs, offs) \
237 emith_read_r_r_offs(r, rs, offs)
238 #define emith_write_r_r_offs_c(cond, r, rs, offs) \
239 emith_write_r_r_offs(r, rs, offs)
240 #define emith_read8_r_r_offs_c(cond, r, rs, offs) \
241 emith_read8_r_r_offs(r, rs, offs)
242 #define emith_write8_r_r_offs_c(cond, r, rs, offs) \
243 emith_write8_r_r_offs(r, rs, offs)
244 #define emith_read16_r_r_offs_c(cond, r, rs, offs) \
245 emith_read16_r_r_offs(r, rs, offs)
246 #define emith_write16_r_r_offs_c(cond, r, rs, offs) \
247 emith_write16_r_r_offs(r, rs, offs)
248 #define emith_jump_reg_c(cond, r) \
250 #define emith_jump_ctx_c(cond, offs) \
252 #define emith_ret_c(cond) \
256 #define emith_add_r_r_imm(d, s, imm) { \
258 emith_move_r_r(d, s); \
259 emith_add_r_imm(d, imm); \
262 #define emith_and_r_r_imm(d, s, imm) { \
264 emith_move_r_r(d, s); \
265 emith_and_r_imm(d, imm); \
269 #define emith_shift(op, d, s, cnt) { \
271 emith_move_r_r(d, s); \
272 EMIT_OP_MODRM(0xc1, 3, op, d); \
276 #define emith_lsl(d, s, cnt) \
277 emith_shift(4, d, s, cnt)
279 #define emith_lsr(d, s, cnt) \
280 emith_shift(5, d, s, cnt)
282 #define emith_asr(d, s, cnt) \
283 emith_shift(7, d, s, cnt)
285 #define emith_rol(d, s, cnt) \
286 emith_shift(0, d, s, cnt)
288 #define emith_ror(d, s, cnt) \
289 emith_shift(1, d, s, cnt)
291 #define emith_rolc(r) \
292 EMIT_OP_MODRM(0xd1, 3, 2, r)
294 #define emith_rorc(r) \
295 EMIT_OP_MODRM(0xd1, 3, 3, r)
298 #define emith_push(r) \
301 #define emith_push_imm(imm) { \
306 #define emith_pop(r) \
309 #define emith_neg_r(r) \
310 EMIT_OP_MODRM(0xf7, 3, 3, r)
312 #define emith_clear_msb(d, s, count) { \
316 emith_move_r_r(d, s); \
317 emith_and_r_imm(d, t); \
320 #define emith_clear_msb_c(cond, d, s, count) { \
322 emith_clear_msb(d, s, count); \
325 #define emith_sext(d, s, bits) { \
326 emith_lsl(d, s, 32 - (bits)); \
327 emith_asr(d, d, 32 - (bits)); \
330 #define emith_setc(r) { \
332 EMIT_OP_MODRM(0x92, 3, 0, r); /* SETC r */ \
336 #define emith_mul_(op, dlo, dhi, s1, s2) { \
338 if (dlo != xAX && dhi != xAX) \
340 if (dlo != xDX && dhi != xDX) \
344 else if ((s2) == xAX) \
347 emith_move_r_r(xAX, s1); \
350 EMIT_OP_MODRM(0xf7, 3, op, rmr); /* xMUL rmr */ \
351 /* XXX: using push/pop for the case of edx->eax; eax->edx */ \
352 if (dhi != xDX && dhi != -1) \
355 emith_move_r_r(dlo, xAX); \
356 if (dhi != xDX && dhi != -1) \
358 if (dlo != xDX && dhi != xDX) \
360 if (dlo != xAX && dhi != xAX) \
364 #define emith_mul_u64(dlo, dhi, s1, s2) \
365 emith_mul_(4, dlo, dhi, s1, s2) /* MUL */
367 #define emith_mul_s64(dlo, dhi, s1, s2) \
368 emith_mul_(5, dlo, dhi, s1, s2) /* IMUL */
370 #define emith_mul(d, s1, s2) \
371 emith_mul_(4, d, -1, s1, s2)
373 // (dlo,dhi) += signed(s1) * signed(s2)
374 #define emith_mula_s64(dlo, dhi, s1, s2) { \
377 emith_mul_(5, dlo, dhi, s1, s2); \
378 EMIT_OP_MODRM(0x03, 0, dlo, 4); \
379 EMIT_SIB(0, 4, 4); /* add dlo, [esp] */ \
380 EMIT_OP_MODRM(0x13, 1, dhi, 4); \
382 EMIT(4, u8); /* adc dhi, [esp+4] */ \
383 emith_add_r_imm(xSP, 4*2); \
386 // "flag" instructions are the same
387 #define emith_subf_r_imm emith_sub_r_imm
388 #define emith_addf_r_r emith_add_r_r
389 #define emith_subf_r_r emith_sub_r_r
390 #define emith_adcf_r_r emith_adc_r_r
391 #define emith_sbcf_r_r emith_sbc_r_r
392 #define emith_eorf_r_r emith_eor_r_r
393 #define emith_negcf_r_r emith_negc_r_r
395 #define emith_lslf emith_lsl
396 #define emith_lsrf emith_lsr
397 #define emith_asrf emith_asr
398 #define emith_rolf emith_rol
399 #define emith_rorf emith_ror
400 #define emith_rolcf emith_rolc
401 #define emith_rorcf emith_rorc
403 #define emith_deref_op(op, r, rs, offs) do { \
404 /* mov r <-> [ebp+#offs] */ \
405 if ((offs) >= 0x80) { \
406 EMIT_OP_MODRM(op, 2, r, rs); \
409 EMIT_OP_MODRM(op, 1, r, rs); \
414 #define emith_read_r_r_offs(r, rs, offs) \
415 emith_deref_op(0x8b, r, rs, offs)
417 #define emith_write_r_r_offs(r, rs, offs) \
418 emith_deref_op(0x89, r, rs, offs)
420 #define emith_read8_r_r_offs(r, rs, offs) \
421 emith_deref_op(0x8a, r, rs, offs)
423 #define emith_write8_r_r_offs(r, rs, offs) \
424 emith_deref_op(0x88, r, rs, offs)
426 #define emith_read16_r_r_offs(r, rs, offs) { \
427 EMIT(0x66, u8); /* operand override */ \
428 emith_read_r_r_offs(r, rs, offs); \
431 #define emith_write16_r_r_offs(r, rs, offs) { \
433 emith_write16_r_r_offs(r, rs, offs) \
436 #define emith_ctx_read(r, offs) \
437 emith_read_r_r_offs(r, CONTEXT_REG, offs)
439 #define emith_ctx_write(r, offs) \
440 emith_write_r_r_offs(r, CONTEXT_REG, offs)
442 #define emith_ctx_read_multiple(r, offs, cnt, tmpr) do { \
443 int r_ = r, offs_ = offs, cnt_ = cnt; \
444 for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
445 emith_ctx_read(r_, offs_); \
448 #define emith_ctx_write_multiple(r, offs, cnt, tmpr) do { \
449 int r_ = r, offs_ = offs, cnt_ = cnt; \
450 for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
451 emith_ctx_write(r_, offs_); \
454 // assumes EBX is free
455 #define emith_ret_to_ctx(offs) { \
457 emith_ctx_write(xBX, offs); \
460 #define emith_jump(ptr) { \
461 u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 5); \
466 #define emith_jump_patchable(target) \
469 #define emith_jump_cond(cond, ptr) { \
470 u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 6); \
472 EMIT_OP(0x80 | (cond)); \
476 #define emith_jump_cond_patchable(cond, target) \
477 emith_jump_cond(cond, target)
479 #define emith_jump_patch(ptr, target) do { \
480 u32 disp_ = (u32)(target) - ((u32)(ptr) + 4); \
481 u32 offs_ = (*(u8 *)(ptr) == 0x0f) ? 2 : 1; \
482 EMIT_PTR((u8 *)(ptr) + offs_, disp_ - offs_, u32); \
485 #define emith_call(ptr) { \
486 u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 5); \
491 #define emith_call_cond(cond, ptr) \
494 #define emith_call_reg(r) \
495 EMIT_OP_MODRM(0xff, 3, 2, r)
497 #define emith_call_ctx(offs) { \
498 EMIT_OP_MODRM(0xff, 2, 2, CONTEXT_REG); \
502 #define emith_ret() \
505 #define emith_jump_reg(r) \
506 EMIT_OP_MODRM(0xff, 3, 4, r)
508 #define emith_jump_ctx(offs) { \
509 EMIT_OP_MODRM(0xff, 2, 4, CONTEXT_REG); \
513 #define EMITH_JMP_START(cond) { \
517 #define EMITH_JMP_END(cond) \
518 JMP8_EMIT(cond, cond_ptr); \
521 #define EMITH_JMP3_START(cond) { \
522 u8 *cond_ptr, *else_ptr; \
525 #define EMITH_JMP3_MID(cond) \
526 JMP8_POS(else_ptr); \
527 JMP8_EMIT(cond, cond_ptr);
529 #define EMITH_JMP3_END() \
530 JMP8_EMIT_NC(else_ptr); \
533 // "simple" jump (no more then a few insns)
534 // ARM will use conditional instructions here
535 #define EMITH_SJMP_START EMITH_JMP_START
536 #define EMITH_SJMP_END EMITH_JMP_END
538 #define EMITH_SJMP3_START EMITH_JMP3_START
539 #define EMITH_SJMP3_MID EMITH_JMP3_MID
540 #define EMITH_SJMP3_END EMITH_JMP3_END
542 #define host_arg2reg(rd, arg) \
544 case 0: rd = xAX; break; \
545 case 1: rd = xDX; break; \
546 case 2: rd = xCX; break; \
549 #define emith_pass_arg_r(arg, reg) { \
551 host_arg2reg(rd, arg); \
552 emith_move_r_r(rd, reg); \
555 #define emith_pass_arg_imm(arg, imm) { \
557 host_arg2reg(rd, arg); \
558 emith_move_r_imm(rd, imm); \
561 /* SH2 drc specific */
562 #define emith_sh2_drc_entry() { \
569 #define emith_sh2_drc_exit() { \
577 // assumes EBX is free temporary
578 #define emith_sh2_wcall(a, tab, ret_ptr) { \
580 host_arg2reg(arg2_, 2); \
581 emith_lsr(xBX, a, SH2_WRITE_SHIFT); \
582 EMIT_OP_MODRM(0x8b, 0, xBX, 4); \
583 EMIT_SIB(2, xBX, tab); /* mov ebx, [tab + ebx * 4] */ \
584 emith_ctx_read(arg2_, offsetof(SH2, is_slave)); \
585 emith_push_imm((long)(ret_ptr)); \
586 emith_jump_reg(xBX); \
589 #define emith_sh2_dtbf_loop() { \
590 u8 *jmp0; /* negative cycles check */ \
591 u8 *jmp1; /* unsinged overflow check */ \
593 int tmp_ = rcache_get_tmp(); \
594 cr = rcache_get_reg(SHR_SR, RC_GR_RMW); \
595 rn = rcache_get_reg((op >> 8) & 0x0f, RC_GR_RMW);\
596 emith_sub_r_imm(rn, 1); \
597 emith_sub_r_imm(cr, (cycles+1) << 12); \
599 emith_asr(tmp_, cr, 2+12); \
600 JMP8_POS(jmp0); /* no negative cycles */ \
601 emith_move_r_imm(tmp_, 0); \
602 JMP8_EMIT(ICOND_JNS, jmp0); \
603 emith_and_r_imm(cr, 0xffe); \
604 emith_subf_r_r(rn, tmp_); \
605 JMP8_POS(jmp1); /* no overflow */ \
606 emith_neg_r(rn); /* count left */ \
607 emith_lsl(rn, rn, 2+12); \
608 emith_or_r_r(cr, rn); \
609 emith_or_r_imm(cr, 1); \
610 emith_move_r_imm(rn, 0); \
611 JMP8_EMIT(ICOND_JA, jmp1); \
612 rcache_free_tmp(tmp_); \
615 #define emith_write_sr(sr, srcr) { \
616 int tmp_ = rcache_get_tmp(); \
617 emith_clear_msb(tmp_, srcr, 22); \
618 emith_bic_r_imm(sr, 0x3ff); \
619 emith_or_r_r(sr, tmp_); \
620 rcache_free_tmp(tmp_); \
623 #define emith_tpop_carry(sr, is_sub) \
626 #define emith_tpush_carry(sr, is_sub) \
627 emith_adc_r_r(sr, sr)
631 * t = carry(Rn += Rm)
633 * t = carry(Rn -= Rm)
636 #define emith_sh2_div1_step(rn, rm, sr) { \
638 int tmp_ = rcache_get_tmp(); \
639 emith_eor_r_r(tmp_, tmp_); \
640 emith_tst_r_imm(sr, Q); /* if (Q ^ M) */ \
641 JMP8_POS(jmp0); /* je do_sub */ \
642 emith_add_r_r(rn, rm); \
643 JMP8_POS(jmp1); /* jmp done */ \
644 JMP8_EMIT(ICOND_JE, jmp0); /* do_sub: */ \
645 emith_sub_r_r(rn, rm); \
646 JMP8_EMIT_NC(jmp1); /* done: */ \
648 EMIT_OP_MODRM(0x31, 3, tmp_, sr); /* T = Q1 ^ Q2 */ \
649 rcache_free_tmp(tmp_); \