6 /* ======================================================================== */
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7 /* ========================= LICENSING & COPYRIGHT ======================== */
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8 /* ======================================================================== */
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13 * A portable Motorola M680x0 processor emulation engine.
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14 * Copyright 1998-2007 Karl Stenerud. All rights reserved.
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16 * This code may be freely used for non-commercial purposes as long as this
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17 * copyright notice remains unaltered in the source code and any binary files
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18 * containing this code in compiled form.
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20 * All other lisencing terms must be negotiated with the author
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23 * The latest version of this code can be obtained at:
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24 * http://kstenerud.cjb.net
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27 /* Special thanks to Bart Trzynadlowski for his insight into the
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28 * undocumented features of this chip:
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30 * http://dynarec.com/~bart/files/68knotes.txt
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34 /* Input file for m68kmake
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35 * -----------------------
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37 * All sections begin with 80 X's in a row followed by an end-of-line
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39 * After this, m68kmake will expect to find one of the following section
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41 * M68KMAKE_PROTOTYPE_HEADER - header for opcode handler prototypes
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42 * M68KMAKE_PROTOTYPE_FOOTER - footer for opcode handler prototypes
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43 * M68KMAKE_TABLE_HEADER - header for opcode handler jumptable
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44 * M68KMAKE_TABLE_FOOTER - footer for opcode handler jumptable
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45 * M68KMAKE_TABLE_BODY - the table itself
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46 * M68KMAKE_OPCODE_HANDLER_HEADER - header for opcode handler implementation
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47 * M68KMAKE_OPCODE_HANDLER_FOOTER - footer for opcode handler implementation
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48 * M68KMAKE_OPCODE_HANDLER_BODY - body section for opcode handler implementation
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50 * NOTE: M68KMAKE_OPCODE_HANDLER_BODY must be last in the file and
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51 * M68KMAKE_TABLE_BODY must be second last in the file.
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53 * The M68KMAKE_OPHANDLER_BODY section contains the opcode handler
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54 * primitives themselves. Each opcode handler begins with:
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55 * M68KMAKE_OP(A, B, C, D)
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57 * where A is the opcode handler name, B is the size of the operation,
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58 * C denotes any special processing mode, and D denotes a specific
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60 * For C and D where nothing is specified, use "."
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63 * M68KMAKE_OP(abcd, 8, rr, .) abcd, size 8, register to register, default EA
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64 * M68KMAKE_OP(abcd, 8, mm, ax7) abcd, size 8, memory to memory, register X is A7
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65 * M68KMAKE_OP(tst, 16, ., pcix) tst, size 16, PCIX addressing
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67 * All opcode handler primitives end with a closing curly brace "}" at column 1
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69 * NOTE: Do not place a M68KMAKE_OP() directive inside the opcode handler,
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70 * and do not put a closing curly brace at column 1 unless it is
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71 * marking the end of the handler!
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73 * Inside the handler, m68kmake will recognize M68KMAKE_GET_OPER_xx_xx,
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74 * M68KMAKE_GET_EA_xx_xx, and M68KMAKE_CC directives, and create multiple
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75 * opcode handlers to handle variations in the opcode handler.
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76 * Note: M68KMAKE_CC will only be interpreted in condition code opcodes.
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77 * As well, M68KMAKE_GET_EA_xx_xx and M68KMAKE_GET_OPER_xx_xx will only
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78 * be interpreted on instructions where the corresponding table entry
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79 * specifies multiple effective addressing modes.
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81 * clr 32 . . 0100001010...... A+-DXWL... U U U 12 6 4
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83 * This table entry says that the clr.l opcde has 7 variations (A+-DXWL).
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84 * It is run in user or supervisor mode for all CPUs, and uses 12 cycles for
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85 * 68000, 6 cycles for 68010, and 4 cycles for 68020.
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88 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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89 M68KMAKE_PROTOTYPE_HEADER
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91 #ifndef M68KOPS__HEADER
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92 #define M68KOPS__HEADER
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94 /* ======================================================================== */
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95 /* ============================ OPCODE HANDLERS =========================== */
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96 /* ======================================================================== */
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100 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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101 M68KMAKE_PROTOTYPE_FOOTER
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104 /* Build the opcode handler table */
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105 void m68ki_build_opcode_table(void);
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107 extern void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */
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108 extern unsigned char m68ki_cycles[][0x10000];
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111 /* ======================================================================== */
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112 /* ============================== END OF FILE ============================= */
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113 /* ======================================================================== */
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115 #endif /* M68KOPS__HEADER */
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119 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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120 M68KMAKE_TABLE_HEADER
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122 /* ======================================================================== */
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123 /* ========================= OPCODE TABLE BUILDER ========================= */
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124 /* ======================================================================== */
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126 #include "m68kops.h"
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128 #define NUM_CPU_TYPES 4
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130 void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */
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131 unsigned char m68ki_cycles[NUM_CPU_TYPES][0x10000]; /* Cycles used by CPU type */
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133 /* This is used to generate the opcode handler jump table */
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136 void (*opcode_handler)(void); /* handler function */
\r
137 unsigned int mask; /* mask on opcode */
\r
138 unsigned int match; /* what to match after masking */
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139 unsigned char cycles[NUM_CPU_TYPES]; /* cycles each cpu type takes */
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140 } opcode_handler_struct;
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143 /* Opcode handler table */
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144 static opcode_handler_struct m68k_opcode_handler_table[] =
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146 /* function mask match 000 010 020 040 */
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150 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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151 M68KMAKE_TABLE_FOOTER
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153 {0, 0, 0, {0, 0, 0, 0}}
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157 /* Build the opcode handler jump table */
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158 void m68ki_build_opcode_table(void)
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160 opcode_handler_struct *ostruct;
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166 for(i = 0; i < 0x10000; i++)
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168 /* default to illegal */
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169 m68ki_instruction_jump_table[i] = m68k_op_illegal;
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170 for(k=0;k<NUM_CPU_TYPES;k++)
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171 m68ki_cycles[k][i] = 0;
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174 ostruct = m68k_opcode_handler_table;
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175 while(ostruct->mask != 0xff00)
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177 for(i = 0;i < 0x10000;i++)
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179 if((i & ostruct->mask) == ostruct->match)
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181 m68ki_instruction_jump_table[i] = ostruct->opcode_handler;
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182 for(k=0;k<NUM_CPU_TYPES;k++)
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183 m68ki_cycles[k][i] = ostruct->cycles[k];
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188 while(ostruct->mask == 0xff00)
\r
190 for(i = 0;i <= 0xff;i++)
\r
192 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
\r
193 for(k=0;k<NUM_CPU_TYPES;k++)
\r
194 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
\r
198 while(ostruct->mask == 0xf1f8)
\r
200 for(i = 0;i < 8;i++)
\r
202 for(j = 0;j < 8;j++)
\r
204 instr = ostruct->match | (i << 9) | j;
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205 m68ki_instruction_jump_table[instr] = ostruct->opcode_handler;
\r
206 for(k=0;k<NUM_CPU_TYPES;k++)
\r
207 m68ki_cycles[k][instr] = ostruct->cycles[k];
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212 while(ostruct->mask == 0xfff0)
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214 for(i = 0;i <= 0x0f;i++)
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216 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
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217 for(k=0;k<NUM_CPU_TYPES;k++)
\r
218 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
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222 while(ostruct->mask == 0xf1ff)
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224 for(i = 0;i <= 0x07;i++)
\r
226 m68ki_instruction_jump_table[ostruct->match | (i << 9)] = ostruct->opcode_handler;
\r
227 for(k=0;k<NUM_CPU_TYPES;k++)
\r
228 m68ki_cycles[k][ostruct->match | (i << 9)] = ostruct->cycles[k];
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232 while(ostruct->mask == 0xfff8)
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234 for(i = 0;i <= 0x07;i++)
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236 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
\r
237 for(k=0;k<NUM_CPU_TYPES;k++)
\r
238 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
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242 while(ostruct->mask == 0xffff)
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244 m68ki_instruction_jump_table[ostruct->match] = ostruct->opcode_handler;
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245 for(k=0;k<NUM_CPU_TYPES;k++)
\r
246 m68ki_cycles[k][ostruct->match] = ostruct->cycles[k];
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252 /* ======================================================================== */
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253 /* ============================== END OF FILE ============================= */
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254 /* ======================================================================== */
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258 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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259 M68KMAKE_OPCODE_HANDLER_HEADER
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261 #include "m68kcpu.h"
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262 extern void m68040_fpu_op0(void);
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263 extern void m68040_fpu_op1(void);
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265 /* ======================================================================== */
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266 /* ========================= INSTRUCTION HANDLERS ========================= */
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267 /* ======================================================================== */
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271 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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272 M68KMAKE_OPCODE_HANDLER_FOOTER
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274 /* ======================================================================== */
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275 /* ============================== END OF FILE ============================= */
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276 /* ======================================================================== */
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280 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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281 M68KMAKE_TABLE_BODY
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283 The following table is arranged as follows:
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285 name: Opcode mnemonic
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287 size: Operation size
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289 spec proc: Special processing mode:
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292 r: register operand
\r
293 rr: register to register
\r
294 mm: memory to memory
\r
295 er: effective address to register
\r
296 re: register to effective address
\r
297 dd: data register to data register
\r
298 da: data register to address register
\r
299 aa: address register to address register
\r
300 cr: control register to register
\r
301 rc: register to control register
\r
302 toc: to condition code register
\r
303 tos: to status register
\r
304 tou: to user stack pointer
\r
305 frc: from condition code register
\r
306 frs: from status register
\r
307 fru: from user stack pointer
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308 * for move.x, the special processing mode is a specific
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309 destination effective addressing mode.
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311 spec ea: Specific effective addressing mode:
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315 a: address register
\r
316 ai: address register indirect
\r
317 pi: address register indirect with postincrement
\r
318 pd: address register indirect with predecrement
\r
319 di: address register indirect with displacement
\r
320 ix: address register indirect with index
\r
321 aw: absolute word address
\r
322 al: absolute long address
\r
323 pcdi: program counter relative with displacement
\r
324 pcix: program counter relative with index
\r
325 a7: register specified in instruction is A7
\r
326 ax7: register field X of instruction is A7
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327 ay7: register field Y of instruction is A7
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328 axy7: register fields X and Y of instruction are A7
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330 bit pattern: Pattern to recognize this opcode. "." means don't care.
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332 allowed ea: List of allowed addressing modes:
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334 A: address register indirect
\r
335 +: ARI (address register indirect) with postincrement
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336 -: ARI with predecrement
\r
337 D: ARI with displacement
\r
339 W: absolute word address
\r
340 L: absolute long address
\r
341 d: program counter indirect with displacement
\r
342 x: program counter indirect with index
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344 mode: CPU operating mode for each cpu type. U = user or supervisor,
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345 S = supervisor only, "." = opcode not present.
\r
347 cpu cycles: Base number of cycles required to execute this opcode on the
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348 specified CPU type.
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349 Use "." if CPU does not have this opcode.
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353 spec spec allowed ea mode cpu cycles
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354 name size proc ea bit pattern A+-DXWLdxI 0 1 2 4 000 010 020 040 comments
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355 ====== ==== ==== ==== ================ ========== = = = = === === === === =============
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356 M68KMAKE_TABLE_START
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357 1010 0 . . 1010............ .......... U U U U 4 4 4 4
\r
358 1111 0 . . 1111............ .......... U U U U 4 4 4 4
\r
359 040fpu0 32 . . 11110010........ .......... . . . U . . . 0
\r
360 040fpu1 32 . . 11110011........ .......... . . . U . . . 0
\r
361 abcd 8 rr . 1100...100000... .......... U U U U 6 6 4 4
\r
362 abcd 8 mm ax7 1100111100001... .......... U U U U 18 18 16 16
\r
363 abcd 8 mm ay7 1100...100001111 .......... U U U U 18 18 16 16
\r
364 abcd 8 mm axy7 1100111100001111 .......... U U U U 18 18 16 16
\r
365 abcd 8 mm . 1100...100001... .......... U U U U 18 18 16 16
\r
366 add 8 er d 1101...000000... .......... U U U U 4 4 2 2
\r
367 add 8 er . 1101...000...... A+-DXWLdxI U U U U 4 4 2 2
\r
368 add 16 er d 1101...001000... .......... U U U U 4 4 2 2
\r
369 add 16 er a 1101...001001... .......... U U U U 4 4 2 2
\r
370 add 16 er . 1101...001...... A+-DXWLdxI U U U U 4 4 2 2
\r
371 add 32 er d 1101...010000... .......... U U U U 6 6 2 2
\r
372 add 32 er a 1101...010001... .......... U U U U 6 6 2 2
\r
373 add 32 er . 1101...010...... A+-DXWLdxI U U U U 6 6 2 2
\r
374 add 8 re . 1101...100...... A+-DXWL... U U U U 8 8 4 4
\r
375 add 16 re . 1101...101...... A+-DXWL... U U U U 8 8 4 4
\r
376 add 32 re . 1101...110...... A+-DXWL... U U U U 12 12 4 4
\r
377 adda 16 . d 1101...011000... .......... U U U U 8 8 2 2
\r
378 adda 16 . a 1101...011001... .......... U U U U 8 8 2 2
\r
379 adda 16 . . 1101...011...... A+-DXWLdxI U U U U 8 8 2 2
\r
380 adda 32 . d 1101...111000... .......... U U U U 6 6 2 2
\r
381 adda 32 . a 1101...111001... .......... U U U U 6 6 2 2
\r
382 adda 32 . . 1101...111...... A+-DXWLdxI U U U U 6 6 2 2
\r
383 addi 8 . d 0000011000000... .......... U U U U 8 8 2 2
\r
384 addi 8 . . 0000011000...... A+-DXWL... U U U U 12 12 4 4
\r
385 addi 16 . d 0000011001000... .......... U U U U 8 8 2 2
\r
386 addi 16 . . 0000011001...... A+-DXWL... U U U U 12 12 4 4
\r
387 addi 32 . d 0000011010000... .......... U U U U 16 14 2 2
\r
388 addi 32 . . 0000011010...... A+-DXWL... U U U U 20 20 4 4
\r
389 addq 8 . d 0101...000000... .......... U U U U 4 4 2 2
\r
390 addq 8 . . 0101...000...... A+-DXWL... U U U U 8 8 4 4
\r
391 addq 16 . d 0101...001000... .......... U U U U 4 4 2 2
\r
392 addq 16 . a 0101...001001... .......... U U U U 4 4 2 2
\r
393 addq 16 . . 0101...001...... A+-DXWL... U U U U 8 8 4 4
\r
394 addq 32 . d 0101...010000... .......... U U U U 8 8 2 2
\r
395 addq 32 . a 0101...010001... .......... U U U U 8 8 2 2
\r
396 addq 32 . . 0101...010...... A+-DXWL... U U U U 12 12 4 4
\r
397 addx 8 rr . 1101...100000... .......... U U U U 4 4 2 2
\r
398 addx 16 rr . 1101...101000... .......... U U U U 4 4 2 2
\r
399 addx 32 rr . 1101...110000... .......... U U U U 8 6 2 2
\r
400 addx 8 mm ax7 1101111100001... .......... U U U U 18 18 12 12
\r
401 addx 8 mm ay7 1101...100001111 .......... U U U U 18 18 12 12
\r
402 addx 8 mm axy7 1101111100001111 .......... U U U U 18 18 12 12
\r
403 addx 8 mm . 1101...100001... .......... U U U U 18 18 12 12
\r
404 addx 16 mm . 1101...101001... .......... U U U U 18 18 12 12
\r
405 addx 32 mm . 1101...110001... .......... U U U U 30 30 12 12
\r
406 and 8 er d 1100...000000... .......... U U U U 4 4 2 2
\r
407 and 8 er . 1100...000...... A+-DXWLdxI U U U U 4 4 2 2
\r
408 and 16 er d 1100...001000... .......... U U U U 4 4 2 2
\r
409 and 16 er . 1100...001...... A+-DXWLdxI U U U U 4 4 2 2
\r
410 and 32 er d 1100...010000... .......... U U U U 6 6 2 2
\r
411 and 32 er . 1100...010...... A+-DXWLdxI U U U U 6 6 2 2
\r
412 and 8 re . 1100...100...... A+-DXWL... U U U U 8 8 4 4
\r
413 and 16 re . 1100...101...... A+-DXWL... U U U U 8 8 4 4
\r
414 and 32 re . 1100...110...... A+-DXWL... U U U U 12 12 4 4
\r
415 andi 16 toc . 0000001000111100 .......... U U U U 20 16 12 12
\r
416 andi 16 tos . 0000001001111100 .......... S S S S 20 16 12 12
\r
417 andi 8 . d 0000001000000... .......... U U U U 8 8 2 2
\r
418 andi 8 . . 0000001000...... A+-DXWL... U U U U 12 12 4 4
\r
419 andi 16 . d 0000001001000... .......... U U U U 8 8 2 2
\r
420 andi 16 . . 0000001001...... A+-DXWL... U U U U 12 12 4 4
\r
421 andi 32 . d 0000001010000... .......... U U U U 14 14 2 2
\r
422 andi 32 . . 0000001010...... A+-DXWL... U U U U 20 20 4 4
\r
423 asr 8 s . 1110...000000... .......... U U U U 6 6 6 6
\r
424 asr 16 s . 1110...001000... .......... U U U U 6 6 6 6
\r
425 asr 32 s . 1110...010000... .......... U U U U 8 8 6 6
\r
426 asr 8 r . 1110...000100... .......... U U U U 6 6 6 6
\r
427 asr 16 r . 1110...001100... .......... U U U U 6 6 6 6
\r
428 asr 32 r . 1110...010100... .......... U U U U 8 8 6 6
\r
429 asr 16 . . 1110000011...... A+-DXWL... U U U U 8 8 5 5
\r
430 asl 8 s . 1110...100000... .......... U U U U 6 6 8 8
\r
431 asl 16 s . 1110...101000... .......... U U U U 6 6 8 8
\r
432 asl 32 s . 1110...110000... .......... U U U U 8 8 8 8
\r
433 asl 8 r . 1110...100100... .......... U U U U 6 6 8 8
\r
434 asl 16 r . 1110...101100... .......... U U U U 6 6 8 8
\r
435 asl 32 r . 1110...110100... .......... U U U U 8 8 8 8
\r
436 asl 16 . . 1110000111...... A+-DXWL... U U U U 8 8 6 6
\r
437 bcc 8 . . 0110............ .......... U U U U 10 10 6 6
\r
438 bcc 16 . . 0110....00000000 .......... U U U U 10 10 6 6
\r
439 bcc 32 . . 0110....11111111 .......... U U U U 10 10 6 6
\r
440 bchg 8 r . 0000...101...... A+-DXWL... U U U U 8 8 4 4
\r
441 bchg 32 r d 0000...101000... .......... U U U U 8 8 4 4
\r
442 bchg 8 s . 0000100001...... A+-DXWL... U U U U 12 12 4 4
\r
443 bchg 32 s d 0000100001000... .......... U U U U 12 12 4 4
\r
444 bclr 8 r . 0000...110...... A+-DXWL... U U U U 8 10 4 4
\r
445 bclr 32 r d 0000...110000... .......... U U U U 10 10 4 4
\r
446 bclr 8 s . 0000100010...... A+-DXWL... U U U U 12 12 4 4
\r
447 bclr 32 s d 0000100010000... .......... U U U U 14 14 4 4
\r
448 bfchg 32 . d 1110101011000... .......... . . U U . . 12 12 timing not quite correct
\r
449 bfchg 32 . . 1110101011...... A..DXWL... . . U U . . 20 20
\r
450 bfclr 32 . d 1110110011000... .......... . . U U . . 12 12
\r
451 bfclr 32 . . 1110110011...... A..DXWL... . . U U . . 20 20
\r
452 bfexts 32 . d 1110101111000... .......... . . U U . . 8 8
\r
453 bfexts 32 . . 1110101111...... A..DXWLdx. . . U U . . 15 15
\r
454 bfextu 32 . d 1110100111000... .......... . . U U . . 8 8
\r
455 bfextu 32 . . 1110100111...... A..DXWLdx. . . U U . . 15 15
\r
456 bfffo 32 . d 1110110111000... .......... . . U U . . 18 18
\r
457 bfffo 32 . . 1110110111...... A..DXWLdx. . . U U . . 28 28
\r
458 bfins 32 . d 1110111111000... .......... . . U U . . 10 10
\r
459 bfins 32 . . 1110111111...... A..DXWL... . . U U . . 17 17
\r
460 bfset 32 . d 1110111011000... .......... . . U U . . 12 12
\r
461 bfset 32 . . 1110111011...... A..DXWL... . . U U . . 20 20
\r
462 bftst 32 . d 1110100011000... .......... . . U U . . 6 6
\r
463 bftst 32 . . 1110100011...... A..DXWLdx. . . U U . . 13 13
\r
464 bkpt 0 . . 0100100001001... .......... . U U U . 10 10 10
\r
465 bra 8 . . 01100000........ .......... U U U U 10 10 10 10
\r
466 bra 16 . . 0110000000000000 .......... U U U U 10 10 10 10
\r
467 bra 32 . . 0110000011111111 .......... U U U U 10 10 10 10
\r
468 bset 32 r d 0000...111000... .......... U U U U 8 8 4 4
\r
469 bset 8 r . 0000...111...... A+-DXWL... U U U U 8 8 4 4
\r
470 bset 8 s . 0000100011...... A+-DXWL... U U U U 12 12 4 4
\r
471 bset 32 s d 0000100011000... .......... U U U U 12 12 4 4
\r
472 bsr 8 . . 01100001........ .......... U U U U 18 18 7 7
\r
473 bsr 16 . . 0110000100000000 .......... U U U U 18 18 7 7
\r
474 bsr 32 . . 0110000111111111 .......... U U U U 18 18 7 7
\r
475 btst 8 r . 0000...100...... A+-DXWLdxI U U U U 4 4 4 4
\r
476 btst 32 r d 0000...100000... .......... U U U U 6 6 4 4
\r
477 btst 8 s . 0000100000...... A+-DXWLdx. U U U U 8 8 4 4
\r
478 btst 32 s d 0000100000000... .......... U U U U 10 10 4 4
\r
479 callm 32 . . 0000011011...... A..DXWLdx. . . U U . . 60 60 not properly emulated
\r
480 cas 8 . . 0000101011...... A+-DXWL... . . U U . . 12 12
\r
481 cas 16 . . 0000110011...... A+-DXWL... . . U U . . 12 12
\r
482 cas 32 . . 0000111011...... A+-DXWL... . . U U . . 12 12
\r
483 cas2 16 . . 0000110011111100 .......... . . U U . . 12 12
\r
484 cas2 32 . . 0000111011111100 .......... . . U U . . 12 12
\r
485 chk 16 . d 0100...110000... .......... U U U U 10 8 8 8
\r
486 chk 16 . . 0100...110...... A+-DXWLdxI U U U U 10 8 8 8
\r
487 chk 32 . d 0100...100000... .......... . . U U . . 8 8
\r
488 chk 32 . . 0100...100...... A+-DXWLdxI . . U U . . 8 8
\r
489 chk2cmp2 8 . pcdi 0000000011111010 .......... . . U U . . 23 23
\r
490 chk2cmp2 8 . pcix 0000000011111011 .......... . . U U . . 23 23
\r
491 chk2cmp2 8 . . 0000000011...... A..DXWL... . . U U . . 18 18
\r
492 chk2cmp2 16 . pcdi 0000001011111010 .......... . . U U . . 23 23
\r
493 chk2cmp2 16 . pcix 0000001011111011 .......... . . U U . . 23 23
\r
494 chk2cmp2 16 . . 0000001011...... A..DXWL... . . U U . . 18 18
\r
495 chk2cmp2 32 . pcdi 0000010011111010 .......... . . U U . . 23 23
\r
496 chk2cmp2 32 . pcix 0000010011111011 .......... . . U U . . 23 23
\r
497 chk2cmp2 32 . . 0000010011...... A..DXWL... . . U U . . 18 18
\r
498 clr 8 . d 0100001000000... .......... U U U U 4 4 2 2
\r
499 clr 8 . . 0100001000...... A+-DXWL... U U U U 6 4 4 4 notaz hack: changed 000 cycles 8 -> 6 like in starscream for Fatal Rewind
\r
500 clr 16 . d 0100001001000... .......... U U U U 4 4 2 2
\r
501 clr 16 . . 0100001001...... A+-DXWL... U U U U 6 4 4 4 notaz hack: ditto
\r
502 clr 32 . d 0100001010000... .......... U U U U 6 6 2 2
\r
503 clr 32 . . 0100001010...... A+-DXWL... U U U U 12 6 4 4
\r
504 cmp 8 . d 1011...000000... .......... U U U U 4 4 2 2
\r
505 cmp 8 . . 1011...000...... A+-DXWLdxI U U U U 4 4 2 2
\r
506 cmp 16 . d 1011...001000... .......... U U U U 4 4 2 2
\r
507 cmp 16 . a 1011...001001... .......... U U U U 4 4 2 2
\r
508 cmp 16 . . 1011...001...... A+-DXWLdxI U U U U 4 4 2 2
\r
509 cmp 32 . d 1011...010000... .......... U U U U 6 6 2 2
\r
510 cmp 32 . a 1011...010001... .......... U U U U 6 6 2 2
\r
511 cmp 32 . . 1011...010...... A+-DXWLdxI U U U U 6 6 2 2
\r
512 cmpa 16 . d 1011...011000... .......... U U U U 6 6 4 4
\r
513 cmpa 16 . a 1011...011001... .......... U U U U 6 6 4 4
\r
514 cmpa 16 . . 1011...011...... A+-DXWLdxI U U U U 6 6 4 4
\r
515 cmpa 32 . d 1011...111000... .......... U U U U 6 6 4 4
\r
516 cmpa 32 . a 1011...111001... .......... U U U U 6 6 4 4
\r
517 cmpa 32 . . 1011...111...... A+-DXWLdxI U U U U 6 6 4 4
\r
518 cmpi 8 . d 0000110000000... .......... U U U U 8 8 2 2
\r
519 cmpi 8 . . 0000110000...... A+-DXWL... U U U U 8 8 2 2
\r
520 cmpi 8 . pcdi 0000110000111010 .......... . . U U . . 7 7
\r
521 cmpi 8 . pcix 0000110000111011 .......... . . U U . . 9 9
\r
522 cmpi 16 . d 0000110001000... .......... U U U U 8 8 2 2
\r
523 cmpi 16 . . 0000110001...... A+-DXWL... U U U U 8 8 2 2
\r
524 cmpi 16 . pcdi 0000110001111010 .......... . . U U . . 7 7
\r
525 cmpi 16 . pcix 0000110001111011 .......... . . U U . . 9 9
\r
526 cmpi 32 . d 0000110010000... .......... U U U U 14 12 2 2
\r
527 cmpi 32 . . 0000110010...... A+-DXWL... U U U U 12 12 2 2
\r
528 cmpi 32 . pcdi 0000110010111010 .......... . . U U . . 7 7
\r
529 cmpi 32 . pcix 0000110010111011 .......... . . U U . . 9 9
\r
530 cmpm 8 . ax7 1011111100001... .......... U U U U 12 12 9 9
\r
531 cmpm 8 . ay7 1011...100001111 .......... U U U U 12 12 9 9
\r
532 cmpm 8 . axy7 1011111100001111 .......... U U U U 12 12 9 9
\r
533 cmpm 8 . . 1011...100001... .......... U U U U 12 12 9 9
\r
534 cmpm 16 . . 1011...101001... .......... U U U U 12 12 9 9
\r
535 cmpm 32 . . 1011...110001... .......... U U U U 20 20 9 9
\r
536 cpbcc 32 . . 1111...01....... .......... . . U . . . 4 . unemulated
\r
537 cpdbcc 32 . . 1111...001001... .......... . . U . . . 4 . unemulated
\r
538 cpgen 32 . . 1111...000...... .......... . . U . . . 4 . unemulated
\r
539 cpscc 32 . . 1111...001...... .......... . . U . . . 4 . unemulated
\r
540 cptrapcc 32 . . 1111...001111... .......... . . U . . . 4 . unemulated
\r
541 dbt 16 . . 0101000011001... .......... U U U U 12 12 6 6
\r
542 dbf 16 . . 0101000111001... .......... U U U U 12 12 6 6
\r
543 dbcc 16 . . 0101....11001... .......... U U U U 12 12 6 6
\r
544 divs 16 . d 1000...111000... .......... U U U U 158 122 56 56
\r
545 divs 16 . . 1000...111...... A+-DXWLdxI U U U U 158 122 56 56
\r
546 divu 16 . d 1000...011000... .......... U U U U 140 108 44 44
\r
547 divu 16 . . 1000...011...... A+-DXWLdxI U U U U 140 108 44 44
\r
548 divl 32 . d 0100110001000... .......... . . U U . . 84 84
\r
549 divl 32 . . 0100110001...... A+-DXWLdxI . . U U . . 84 84
\r
550 eor 8 . d 1011...100000... .......... U U U U 4 4 2 2
\r
551 eor 8 . . 1011...100...... A+-DXWL... U U U U 8 8 4 4
\r
552 eor 16 . d 1011...101000... .......... U U U U 4 4 2 2
\r
553 eor 16 . . 1011...101...... A+-DXWL... U U U U 8 8 4 4
\r
554 eor 32 . d 1011...110000... .......... U U U U 8 6 2 2
\r
555 eor 32 . . 1011...110...... A+-DXWL... U U U U 12 12 4 4
\r
556 eori 16 toc . 0000101000111100 .......... U U U U 20 16 12 12
\r
557 eori 16 tos . 0000101001111100 .......... S S S S 20 16 12 12
\r
558 eori 8 . d 0000101000000... .......... U U U U 8 8 2 2
\r
559 eori 8 . . 0000101000...... A+-DXWL... U U U U 12 12 4 4
\r
560 eori 16 . d 0000101001000... .......... U U U U 8 8 2 2
\r
561 eori 16 . . 0000101001...... A+-DXWL... U U U U 12 12 4 4
\r
562 eori 32 . d 0000101010000... .......... U U U U 16 14 2 2
\r
563 eori 32 . . 0000101010...... A+-DXWL... U U U U 20 20 4 4
\r
564 exg 32 dd . 1100...101000... .......... U U U U 6 6 2 2
\r
565 exg 32 aa . 1100...101001... .......... U U U U 6 6 2 2
\r
566 exg 32 da . 1100...110001... .......... U U U U 6 6 2 2
\r
567 ext 16 . . 0100100010000... .......... U U U U 4 4 4 4
\r
568 ext 32 . . 0100100011000... .......... U U U U 4 4 4 4
\r
569 extb 32 . . 0100100111000... .......... . . U U . . 4 4
\r
570 illegal 0 . . 0100101011111100 .......... U U U U 4 4 4 4
\r
571 jmp 32 . . 0100111011...... A..DXWLdx. U U U U 4 4 0 0
\r
572 jsr 32 . . 0100111010...... A..DXWLdx. U U U U 12 12 0 0
\r
573 lea 32 . . 0100...111...... A..DXWLdx. U U U U 0 0 2 2
\r
574 link 16 . a7 0100111001010111 .......... U U U U 16 16 5 5
\r
575 link 16 . . 0100111001010... .......... U U U U 16 16 5 5
\r
576 link 32 . a7 0100100000001111 .......... . . U U . . 6 6
\r
577 link 32 . . 0100100000001... .......... . . U U . . 6 6
\r
578 lsr 8 s . 1110...000001... .......... U U U U 6 6 4 4
\r
579 lsr 16 s . 1110...001001... .......... U U U U 6 6 4 4
\r
580 lsr 32 s . 1110...010001... .......... U U U U 8 8 4 4
\r
581 lsr 8 r . 1110...000101... .......... U U U U 6 6 6 6
\r
582 lsr 16 r . 1110...001101... .......... U U U U 6 6 6 6
\r
583 lsr 32 r . 1110...010101... .......... U U U U 8 8 6 6
\r
584 lsr 16 . . 1110001011...... A+-DXWL... U U U U 8 8 5 5
\r
585 lsl 8 s . 1110...100001... .......... U U U U 6 6 4 4
\r
586 lsl 16 s . 1110...101001... .......... U U U U 6 6 4 4
\r
587 lsl 32 s . 1110...110001... .......... U U U U 8 8 4 4
\r
588 lsl 8 r . 1110...100101... .......... U U U U 6 6 6 6
\r
589 lsl 16 r . 1110...101101... .......... U U U U 6 6 6 6
\r
590 lsl 32 r . 1110...110101... .......... U U U U 8 8 6 6
\r
591 lsl 16 . . 1110001111...... A+-DXWL... U U U U 8 8 5 5
\r
592 move 8 d d 0001...000000... .......... U U U U 4 4 2 2
\r
593 move 8 d . 0001...000...... A+-DXWLdxI U U U U 4 4 2 2
\r
594 move 8 ai d 0001...010000... .......... U U U U 8 8 4 4
\r
595 move 8 ai . 0001...010...... A+-DXWLdxI U U U U 8 8 4 4
\r
596 move 8 pi d 0001...011000... .......... U U U U 8 8 4 4
\r
597 move 8 pi . 0001...011...... A+-DXWLdxI U U U U 8 8 4 4
\r
598 move 8 pi7 d 0001111011000... .......... U U U U 8 8 4 4
\r
599 move 8 pi7 . 0001111011...... A+-DXWLdxI U U U U 8 8 4 4
\r
600 move 8 pd d 0001...100000... .......... U U U U 8 8 5 5
\r
601 move 8 pd . 0001...100...... A+-DXWLdxI U U U U 8 8 5 5
\r
602 move 8 pd7 d 0001111100000... .......... U U U U 8 8 5 5
\r
603 move 8 pd7 . 0001111100...... A+-DXWLdxI U U U U 8 8 5 5
\r
604 move 8 di d 0001...101000... .......... U U U U 12 12 5 5
\r
605 move 8 di . 0001...101...... A+-DXWLdxI U U U U 12 12 5 5
\r
606 move 8 ix d 0001...110000... .......... U U U U 14 14 7 7
\r
607 move 8 ix . 0001...110...... A+-DXWLdxI U U U U 14 14 7 7
\r
608 move 8 aw d 0001000111000... .......... U U U U 12 12 4 4
\r
609 move 8 aw . 0001000111...... A+-DXWLdxI U U U U 12 12 4 4
\r
610 move 8 al d 0001001111000... .......... U U U U 16 16 6 6
\r
611 move 8 al . 0001001111...... A+-DXWLdxI U U U U 16 16 6 6
\r
612 move 16 d d 0011...000000... .......... U U U U 4 4 2 2
\r
613 move 16 d a 0011...000001... .......... U U U U 4 4 2 2
\r
614 move 16 d . 0011...000...... A+-DXWLdxI U U U U 4 4 2 2
\r
615 move 16 ai d 0011...010000... .......... U U U U 8 8 4 4
\r
616 move 16 ai a 0011...010001... .......... U U U U 8 8 4 4
\r
617 move 16 ai . 0011...010...... A+-DXWLdxI U U U U 8 8 4 4
\r
618 move 16 pi d 0011...011000... .......... U U U U 8 8 4 4
\r
619 move 16 pi a 0011...011001... .......... U U U U 8 8 4 4
\r
620 move 16 pi . 0011...011...... A+-DXWLdxI U U U U 8 8 4 4
\r
621 move 16 pd d 0011...100000... .......... U U U U 8 8 5 5
\r
622 move 16 pd a 0011...100001... .......... U U U U 8 8 5 5
\r
623 move 16 pd . 0011...100...... A+-DXWLdxI U U U U 8 8 5 5
\r
624 move 16 di d 0011...101000... .......... U U U U 12 12 5 5
\r
625 move 16 di a 0011...101001... .......... U U U U 12 12 5 5
\r
626 move 16 di . 0011...101...... A+-DXWLdxI U U U U 12 12 5 5
\r
627 move 16 ix d 0011...110000... .......... U U U U 14 14 7 7
\r
628 move 16 ix a 0011...110001... .......... U U U U 14 14 7 7
\r
629 move 16 ix . 0011...110...... A+-DXWLdxI U U U U 14 14 7 7
\r
630 move 16 aw d 0011000111000... .......... U U U U 12 12 4 4
\r
631 move 16 aw a 0011000111001... .......... U U U U 12 12 4 4
\r
632 move 16 aw . 0011000111...... A+-DXWLdxI U U U U 12 12 4 4
\r
633 move 16 al d 0011001111000... .......... U U U U 16 16 6 6
\r
634 move 16 al a 0011001111001... .......... U U U U 16 16 6 6
\r
635 move 16 al . 0011001111...... A+-DXWLdxI U U U U 16 16 6 6
\r
636 move 32 d d 0010...000000... .......... U U U U 4 4 2 2
\r
637 move 32 d a 0010...000001... .......... U U U U 4 4 2 2
\r
638 move 32 d . 0010...000...... A+-DXWLdxI U U U U 4 4 2 2
\r
639 move 32 ai d 0010...010000... .......... U U U U 12 12 4 4
\r
640 move 32 ai a 0010...010001... .......... U U U U 12 12 4 4
\r
641 move 32 ai . 0010...010...... A+-DXWLdxI U U U U 12 12 4 4
\r
642 move 32 pi d 0010...011000... .......... U U U U 12 12 4 4
\r
643 move 32 pi a 0010...011001... .......... U U U U 12 12 4 4
\r
644 move 32 pi . 0010...011...... A+-DXWLdxI U U U U 12 12 4 4
\r
645 move 32 pd d 0010...100000... .......... U U U U 12 14 5 5
\r
646 move 32 pd a 0010...100001... .......... U U U U 12 14 5 5
\r
647 move 32 pd . 0010...100...... A+-DXWLdxI U U U U 12 14 5 5
\r
648 move 32 di d 0010...101000... .......... U U U U 16 16 5 5
\r
649 move 32 di a 0010...101001... .......... U U U U 16 16 5 5
\r
650 move 32 di . 0010...101...... A+-DXWLdxI U U U U 16 16 5 5
\r
651 move 32 ix d 0010...110000... .......... U U U U 18 18 7 7
\r
652 move 32 ix a 0010...110001... .......... U U U U 18 18 7 7
\r
653 move 32 ix . 0010...110...... A+-DXWLdxI U U U U 18 18 7 7
\r
654 move 32 aw d 0010000111000... .......... U U U U 16 16 4 4
\r
655 move 32 aw a 0010000111001... .......... U U U U 16 16 4 4
\r
656 move 32 aw . 0010000111...... A+-DXWLdxI U U U U 16 16 4 4
\r
657 move 32 al d 0010001111000... .......... U U U U 20 20 6 6
\r
658 move 32 al a 0010001111001... .......... U U U U 20 20 6 6
\r
659 move 32 al . 0010001111...... A+-DXWLdxI U U U U 20 20 6 6
\r
660 movea 16 . d 0011...001000... .......... U U U U 4 4 2 2
\r
661 movea 16 . a 0011...001001... .......... U U U U 4 4 2 2
\r
662 movea 16 . . 0011...001...... A+-DXWLdxI U U U U 4 4 2 2
\r
663 movea 32 . d 0010...001000... .......... U U U U 4 4 2 2
\r
664 movea 32 . a 0010...001001... .......... U U U U 4 4 2 2
\r
665 movea 32 . . 0010...001...... A+-DXWLdxI U U U U 4 4 2 2
\r
666 move 16 frc d 0100001011000... .......... . U U U . 4 4 4
\r
667 move 16 frc . 0100001011...... A+-DXWL... . U U U . 8 4 4
\r
668 move 16 toc d 0100010011000... .......... U U U U 12 12 4 4
\r
669 move 16 toc . 0100010011...... A+-DXWLdxI U U U U 12 12 4 4
\r
670 move 16 frs d 0100000011000... .......... U S S S 6 4 8 8 U only for 000
\r
671 move 16 frs . 0100000011...... A+-DXWL... U S S S 8 8 8 8 U only for 000
\r
672 move 16 tos d 0100011011000... .......... S S S S 12 12 8 8
\r
673 move 16 tos . 0100011011...... A+-DXWLdxI S S S S 12 12 8 8
\r
674 move 32 fru . 0100111001101... .......... S S S S 4 6 2 2
\r
675 move 32 tou . 0100111001100... .......... S S S S 4 6 2 2
\r
676 movec 32 cr . 0100111001111010 .......... . S S S . 12 6 6
\r
677 movec 32 rc . 0100111001111011 .......... . S S S . 10 12 12
\r
678 movem 16 re pd 0100100010100... .......... U U U U 8 8 4 4
\r
679 movem 16 re . 0100100010...... A..DXWL... U U U U 8 8 4 4
\r
680 movem 32 re pd 0100100011100... .......... U U U U 8 8 4 4
\r
681 movem 32 re . 0100100011...... A..DXWL... U U U U 8 8 4 4
\r
682 movem 16 er pi 0100110010011... .......... U U U U 12 12 8 8
\r
683 movem 16 er pcdi 0100110010111010 .......... U U U U 16 16 9 9
\r
684 movem 16 er pcix 0100110010111011 .......... U U U U 18 18 11 11
\r
685 movem 16 er . 0100110010...... A..DXWL... U U U U 12 12 8 8
\r
686 movem 32 er pi 0100110011011... .......... U U U U 12 12 8 8
\r
687 movem 32 er pcdi 0100110011111010 .......... U U U U 16 16 9 9
\r
688 movem 32 er pcix 0100110011111011 .......... U U U U 18 18 11 11
\r
689 movem 32 er . 0100110011...... A..DXWL... U U U U 12 12 8 8
\r
690 movep 16 er . 0000...100001... .......... U U U U 16 16 12 12
\r
691 movep 32 er . 0000...101001... .......... U U U U 24 24 18 18
\r
692 movep 16 re . 0000...110001... .......... U U U U 16 16 11 11
\r
693 movep 32 re . 0000...111001... .......... U U U U 24 24 17 17
\r
694 moveq 32 . . 0111...0........ .......... U U U U 4 4 2 2
\r
695 moves 8 . . 0000111000...... A+-DXWL... . S S S . 14 5 5
\r
696 moves 16 . . 0000111001...... A+-DXWL... . S S S . 14 5 5
\r
697 moves 32 . . 0000111010...... A+-DXWL... . S S S . 16 5 5
\r
698 move16 32 . . 1111011000100... .......... . . . U . . . 4 TODO: correct timing
\r
699 muls 16 . d 1100...111000... .......... U U U U 54 32 27 27
\r
700 muls 16 . . 1100...111...... A+-DXWLdxI U U U U 54 32 27 27
\r
701 mulu 16 . d 1100...011000... .......... U U U U 54 30 27 27
\r
702 mulu 16 . . 1100...011...... A+-DXWLdxI U U U U 54 30 27 27
\r
703 mull 32 . d 0100110000000... .......... . . U U . . 43 43
\r
704 mull 32 . . 0100110000...... A+-DXWLdxI . . U U . . 43 43
\r
705 nbcd 8 . d 0100100000000... .......... U U U U 6 6 6 6
\r
706 nbcd 8 . . 0100100000...... A+-DXWL... U U U U 8 8 6 6
\r
707 neg 8 . d 0100010000000... .......... U U U U 4 4 2 2
\r
708 neg 8 . . 0100010000...... A+-DXWL... U U U U 8 8 4 4
\r
709 neg 16 . d 0100010001000... .......... U U U U 4 4 2 2
\r
710 neg 16 . . 0100010001...... A+-DXWL... U U U U 8 8 4 4
\r
711 neg 32 . d 0100010010000... .......... U U U U 6 6 2 2
\r
712 neg 32 . . 0100010010...... A+-DXWL... U U U U 12 12 4 4
\r
713 negx 8 . d 0100000000000... .......... U U U U 4 4 2 2
\r
714 negx 8 . . 0100000000...... A+-DXWL... U U U U 8 8 4 4
\r
715 negx 16 . d 0100000001000... .......... U U U U 4 4 2 2
\r
716 negx 16 . . 0100000001...... A+-DXWL... U U U U 8 8 4 4
\r
717 negx 32 . d 0100000010000... .......... U U U U 6 6 2 2
\r
718 negx 32 . . 0100000010...... A+-DXWL... U U U U 12 12 4 4
\r
719 nop 0 . . 0100111001110001 .......... U U U U 4 4 2 2
\r
720 not 8 . d 0100011000000... .......... U U U U 4 4 2 2
\r
721 not 8 . . 0100011000...... A+-DXWL... U U U U 8 8 4 4
\r
722 not 16 . d 0100011001000... .......... U U U U 4 4 2 2
\r
723 not 16 . . 0100011001...... A+-DXWL... U U U U 8 8 4 4
\r
724 not 32 . d 0100011010000... .......... U U U U 6 6 2 2
\r
725 not 32 . . 0100011010...... A+-DXWL... U U U U 12 12 4 4
\r
726 or 8 er d 1000...000000... .......... U U U U 4 4 2 2
\r
727 or 8 er . 1000...000...... A+-DXWLdxI U U U U 4 4 2 2
\r
728 or 16 er d 1000...001000... .......... U U U U 4 4 2 2
\r
729 or 16 er . 1000...001...... A+-DXWLdxI U U U U 4 4 2 2
\r
730 or 32 er d 1000...010000... .......... U U U U 6 6 2 2
\r
731 or 32 er . 1000...010...... A+-DXWLdxI U U U U 6 6 2 2
\r
732 or 8 re . 1000...100...... A+-DXWL... U U U U 8 8 4 4
\r
733 or 16 re . 1000...101...... A+-DXWL... U U U U 8 8 4 4
\r
734 or 32 re . 1000...110...... A+-DXWL... U U U U 12 12 4 4
\r
735 ori 16 toc . 0000000000111100 .......... U U U U 20 16 12 12
\r
736 ori 16 tos . 0000000001111100 .......... S S S S 20 16 12 12
\r
737 ori 8 . d 0000000000000... .......... U U U U 8 8 2 2
\r
738 ori 8 . . 0000000000...... A+-DXWL... U U U U 12 12 4 4
\r
739 ori 16 . d 0000000001000... .......... U U U U 8 8 2 2
\r
740 ori 16 . . 0000000001...... A+-DXWL... U U U U 12 12 4 4
\r
741 ori 32 . d 0000000010000... .......... U U U U 16 14 2 2
\r
742 ori 32 . . 0000000010...... A+-DXWL... U U U U 20 20 4 4
\r
743 pack 16 rr . 1000...101000... .......... . . U U . . 6 6
\r
744 pack 16 mm ax7 1000111101001... .......... . . U U . . 13 13
\r
745 pack 16 mm ay7 1000...101001111 .......... . . U U . . 13 13
\r
746 pack 16 mm axy7 1000111101001111 .......... . . U U . . 13 13
\r
747 pack 16 mm . 1000...101001... .......... . . U U . . 13 13
\r
748 pea 32 . . 0100100001...... A..DXWLdx. U U U U 6 6 5 5
\r
749 pflush 32 . . 1111010100011000 .......... . . . S . . . 4 TODO: correct timing
\r
750 reset 0 . . 0100111001110000 .......... S S S S 0 0 0 0
\r
751 ror 8 s . 1110...000011... .......... U U U U 6 6 8 8
\r
752 ror 16 s . 1110...001011... .......... U U U U 6 6 8 8
\r
753 ror 32 s . 1110...010011... .......... U U U U 8 8 8 8
\r
754 ror 8 r . 1110...000111... .......... U U U U 6 6 8 8
\r
755 ror 16 r . 1110...001111... .......... U U U U 6 6 8 8
\r
756 ror 32 r . 1110...010111... .......... U U U U 8 8 8 8
\r
757 ror 16 . . 1110011011...... A+-DXWL... U U U U 8 8 7 7
\r
758 rol 8 s . 1110...100011... .......... U U U U 6 6 8 8
\r
759 rol 16 s . 1110...101011... .......... U U U U 6 6 8 8
\r
760 rol 32 s . 1110...110011... .......... U U U U 8 8 8 8
\r
761 rol 8 r . 1110...100111... .......... U U U U 6 6 8 8
\r
762 rol 16 r . 1110...101111... .......... U U U U 6 6 8 8
\r
763 rol 32 r . 1110...110111... .......... U U U U 8 8 8 8
\r
764 rol 16 . . 1110011111...... A+-DXWL... U U U U 8 8 7 7
\r
765 roxr 8 s . 1110...000010... .......... U U U U 6 6 12 12
\r
766 roxr 16 s . 1110...001010... .......... U U U U 6 6 12 12
\r
767 roxr 32 s . 1110...010010... .......... U U U U 8 8 12 12
\r
768 roxr 8 r . 1110...000110... .......... U U U U 6 6 12 12
\r
769 roxr 16 r . 1110...001110... .......... U U U U 6 6 12 12
\r
770 roxr 32 r . 1110...010110... .......... U U U U 8 8 12 12
\r
771 roxr 16 . . 1110010011...... A+-DXWL... U U U U 8 8 5 5
\r
772 roxl 8 s . 1110...100010... .......... U U U U 6 6 12 12
\r
773 roxl 16 s . 1110...101010... .......... U U U U 6 6 12 12
\r
774 roxl 32 s . 1110...110010... .......... U U U U 8 8 12 12
\r
775 roxl 8 r . 1110...100110... .......... U U U U 6 6 12 12
\r
776 roxl 16 r . 1110...101110... .......... U U U U 6 6 12 12
\r
777 roxl 32 r . 1110...110110... .......... U U U U 8 8 12 12
\r
778 roxl 16 . . 1110010111...... A+-DXWL... U U U U 8 8 5 5
\r
779 rtd 32 . . 0100111001110100 .......... . U U U . 16 10 10
\r
780 rte 32 . . 0100111001110011 .......... S S S S 20 24 20 20 bus fault not emulated
\r
781 rtm 32 . . 000001101100.... .......... . . U U . . 19 19 not properly emulated
\r
782 rtr 32 . . 0100111001110111 .......... U U U U 20 20 14 14
\r
783 rts 32 . . 0100111001110101 .......... U U U U 16 16 10 10
\r
784 sbcd 8 rr . 1000...100000... .......... U U U U 6 6 4 4
\r
785 sbcd 8 mm ax7 1000111100001... .......... U U U U 18 18 16 16
\r
786 sbcd 8 mm ay7 1000...100001111 .......... U U U U 18 18 16 16
\r
787 sbcd 8 mm axy7 1000111100001111 .......... U U U U 18 18 16 16
\r
788 sbcd 8 mm . 1000...100001... .......... U U U U 18 18 16 16
\r
789 st 8 . d 0101000011000... .......... U U U U 6 4 4 4
\r
790 st 8 . . 0101000011...... A+-DXWL... U U U U 8 8 6 6
\r
791 sf 8 . d 0101000111000... .......... U U U U 4 4 4 4
\r
792 sf 8 . . 0101000111...... A+-DXWL... U U U U 8 8 6 6
\r
793 scc 8 . d 0101....11000... .......... U U U U 4 4 4 4
\r
794 scc 8 . . 0101....11...... A+-DXWL... U U U U 8 8 6 6
\r
795 stop 0 . . 0100111001110010 .......... S S S S 4 4 8 8
\r
796 sub 8 er d 1001...000000... .......... U U U U 4 4 2 2
\r
797 sub 8 er . 1001...000...... A+-DXWLdxI U U U U 4 4 2 2
\r
798 sub 16 er d 1001...001000... .......... U U U U 4 4 2 2
\r
799 sub 16 er a 1001...001001... .......... U U U U 4 4 2 2
\r
800 sub 16 er . 1001...001...... A+-DXWLdxI U U U U 4 4 2 2
\r
801 sub 32 er d 1001...010000... .......... U U U U 6 6 2 2
\r
802 sub 32 er a 1001...010001... .......... U U U U 6 6 2 2
\r
803 sub 32 er . 1001...010...... A+-DXWLdxI U U U U 6 6 2 2
\r
804 sub 8 re . 1001...100...... A+-DXWL... U U U U 8 8 4 4
\r
805 sub 16 re . 1001...101...... A+-DXWL... U U U U 8 8 4 4
\r
806 sub 32 re . 1001...110...... A+-DXWL... U U U U 12 12 4 4
\r
807 suba 16 . d 1001...011000... .......... U U U U 8 8 2 2
\r
808 suba 16 . a 1001...011001... .......... U U U U 8 8 2 2
\r
809 suba 16 . . 1001...011...... A+-DXWLdxI U U U U 8 8 2 2
\r
810 suba 32 . d 1001...111000... .......... U U U U 6 6 2 2
\r
811 suba 32 . a 1001...111001... .......... U U U U 6 6 2 2
\r
812 suba 32 . . 1001...111...... A+-DXWLdxI U U U U 6 6 2 2
\r
813 subi 8 . d 0000010000000... .......... U U U U 8 8 2 2
\r
814 subi 8 . . 0000010000...... A+-DXWL... U U U U 12 12 4 4
\r
815 subi 16 . d 0000010001000... .......... U U U U 8 8 2 2
\r
816 subi 16 . . 0000010001...... A+-DXWL... U U U U 12 12 4 4
\r
817 subi 32 . d 0000010010000... .......... U U U U 16 14 2 2
\r
818 subi 32 . . 0000010010...... A+-DXWL... U U U U 20 20 4 4
\r
819 subq 8 . d 0101...100000... .......... U U U U 4 4 2 2
\r
820 subq 8 . . 0101...100...... A+-DXWL... U U U U 8 8 4 4
\r
821 subq 16 . d 0101...101000... .......... U U U U 4 4 2 2
\r
822 subq 16 . a 0101...101001... .......... U U U U 8 4 2 2
\r
823 subq 16 . . 0101...101...... A+-DXWL... U U U U 8 8 4 4
\r
824 subq 32 . d 0101...110000... .......... U U U U 8 8 2 2
\r
825 subq 32 . a 0101...110001... .......... U U U U 8 8 2 2
\r
826 subq 32 . . 0101...110...... A+-DXWL... U U U U 12 12 4 4
\r
827 subx 8 rr . 1001...100000... .......... U U U U 4 4 2 2
\r
828 subx 16 rr . 1001...101000... .......... U U U U 4 4 2 2
\r
829 subx 32 rr . 1001...110000... .......... U U U U 8 6 2 2
\r
830 subx 8 mm ax7 1001111100001... .......... U U U U 18 18 12 12
\r
831 subx 8 mm ay7 1001...100001111 .......... U U U U 18 18 12 12
\r
832 subx 8 mm axy7 1001111100001111 .......... U U U U 18 18 12 12
\r
833 subx 8 mm . 1001...100001... .......... U U U U 18 18 12 12
\r
834 subx 16 mm . 1001...101001... .......... U U U U 18 18 12 12
\r
835 subx 32 mm . 1001...110001... .......... U U U U 30 30 12 12
\r
836 swap 32 . . 0100100001000... .......... U U U U 4 4 4 4
\r
837 tas 8 . d 0100101011000... .......... U U U U 4 4 4 4
\r
838 tas 8 . . 0100101011...... A+-DXWL... U U U U 14 14 12 12
\r
839 trap 0 . . 010011100100.... .......... U U U U 4 4 4 4
\r
840 trapt 0 . . 0101000011111100 .......... . . U U . . 4 4
\r
841 trapt 16 . . 0101000011111010 .......... . . U U . . 6 6
\r
842 trapt 32 . . 0101000011111011 .......... . . U U . . 8 8
\r
843 trapf 0 . . 0101000111111100 .......... . . U U . . 4 4
\r
844 trapf 16 . . 0101000111111010 .......... . . U U . . 6 6
\r
845 trapf 32 . . 0101000111111011 .......... . . U U . . 8 8
\r
846 trapcc 0 . . 0101....11111100 .......... . . U U . . 4 4
\r
847 trapcc 16 . . 0101....11111010 .......... . . U U . . 6 6
\r
848 trapcc 32 . . 0101....11111011 .......... . . U U . . 8 8
\r
849 trapv 0 . . 0100111001110110 .......... U U U U 4 4 4 4
\r
850 tst 8 . d 0100101000000... .......... U U U U 4 4 2 2
\r
851 tst 8 . . 0100101000...... A+-DXWL... U U U U 4 4 2 2
\r
852 tst 8 . pcdi 0100101000111010 .......... . . U U . . 7 7
\r
853 tst 8 . pcix 0100101000111011 .......... . . U U . . 9 9
\r
854 tst 8 . i 0100101000111100 .......... . . U U . . 6 6
\r
855 tst 16 . d 0100101001000... .......... U U U U 4 4 2 2
\r
856 tst 16 . a 0100101001001... .......... . . U U . . 2 2
\r
857 tst 16 . . 0100101001...... A+-DXWL... U U U U 4 4 2 2
\r
858 tst 16 . pcdi 0100101001111010 .......... . . U U . . 7 7
\r
859 tst 16 . pcix 0100101001111011 .......... . . U U . . 9 9
\r
860 tst 16 . i 0100101001111100 .......... . . U U . . 6 6
\r
861 tst 32 . d 0100101010000... .......... U U U U 4 4 2 2
\r
862 tst 32 . a 0100101010001... .......... . . U U . . 2 2
\r
863 tst 32 . . 0100101010...... A+-DXWL... U U U U 4 4 2 2
\r
864 tst 32 . pcdi 0100101010111010 .......... . . U U . . 7 7
\r
865 tst 32 . pcix 0100101010111011 .......... . . U U . . 9 9
\r
866 tst 32 . i 0100101010111100 .......... . . U U . . 6 6
\r
867 unlk 32 . a7 0100111001011111 .......... U U U U 12 12 6 6
\r
868 unlk 32 . . 0100111001011... .......... U U U U 12 12 6 6
\r
869 unpk 16 rr . 1000...110000... .......... . . U U . . 8 8
\r
870 unpk 16 mm ax7 1000111110001... .......... . . U U . . 13 13
\r
871 unpk 16 mm ay7 1000...110001111 .......... . . U U . . 13 13
\r
872 unpk 16 mm axy7 1000111110001111 .......... . . U U . . 13 13
\r
873 unpk 16 mm . 1000...110001... .......... . . U U . . 13 13
\r
877 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
\r
878 M68KMAKE_OPCODE_HANDLER_BODY
\r
880 M68KMAKE_OP(1010, 0, ., .)
\r
882 m68ki_exception_1010();
\r
886 M68KMAKE_OP(1111, 0, ., .)
\r
888 m68ki_exception_1111();
\r
892 M68KMAKE_OP(040fpu0, 32, ., .)
\r
894 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
899 m68ki_exception_1111();
\r
903 M68KMAKE_OP(040fpu1, 32, ., .)
\r
905 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
910 m68ki_exception_1111();
\r
915 M68KMAKE_OP(abcd, 8, rr, .)
\r
920 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
\r
922 FLAG_V = ~res; /* Undefined V behavior */
\r
926 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
\r
927 FLAG_X = FLAG_C = (res > 0x99) << 8;
\r
931 FLAG_V &= res; /* Undefined V behavior part II */
\r
932 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
934 res = MASK_OUT_ABOVE_8(res);
\r
937 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
941 M68KMAKE_OP(abcd, 8, mm, ax7)
\r
943 uint src = OPER_AY_PD_8();
\r
944 uint ea = EA_A7_PD_8();
\r
945 uint dst = m68ki_read_8(ea);
\r
946 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
\r
948 FLAG_V = ~res; /* Undefined V behavior */
\r
952 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
\r
953 FLAG_X = FLAG_C = (res > 0x99) << 8;
\r
957 FLAG_V &= res; /* Undefined V behavior part II */
\r
958 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
960 res = MASK_OUT_ABOVE_8(res);
\r
963 m68ki_write_8(ea, res);
\r
967 M68KMAKE_OP(abcd, 8, mm, ay7)
\r
969 uint src = OPER_A7_PD_8();
\r
970 uint ea = EA_AX_PD_8();
\r
971 uint dst = m68ki_read_8(ea);
\r
972 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
\r
974 FLAG_V = ~res; /* Undefined V behavior */
\r
978 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
\r
979 FLAG_X = FLAG_C = (res > 0x99) << 8;
\r
983 FLAG_V &= res; /* Undefined V behavior part II */
\r
984 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
986 res = MASK_OUT_ABOVE_8(res);
\r
989 m68ki_write_8(ea, res);
\r
993 M68KMAKE_OP(abcd, 8, mm, axy7)
\r
995 uint src = OPER_A7_PD_8();
\r
996 uint ea = EA_A7_PD_8();
\r
997 uint dst = m68ki_read_8(ea);
\r
998 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
\r
1000 FLAG_V = ~res; /* Undefined V behavior */
\r
1004 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
\r
1005 FLAG_X = FLAG_C = (res > 0x99) << 8;
\r
1009 FLAG_V &= res; /* Undefined V behavior part II */
\r
1010 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
1012 res = MASK_OUT_ABOVE_8(res);
\r
1015 m68ki_write_8(ea, res);
\r
1019 M68KMAKE_OP(abcd, 8, mm, .)
\r
1021 uint src = OPER_AY_PD_8();
\r
1022 uint ea = EA_AX_PD_8();
\r
1023 uint dst = m68ki_read_8(ea);
\r
1024 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
\r
1026 FLAG_V = ~res; /* Undefined V behavior */
\r
1030 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
\r
1031 FLAG_X = FLAG_C = (res > 0x99) << 8;
\r
1035 FLAG_V &= res; /* Undefined V behavior part II */
\r
1036 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
1038 res = MASK_OUT_ABOVE_8(res);
\r
1041 m68ki_write_8(ea, res);
\r
1045 M68KMAKE_OP(add, 8, er, d)
\r
1047 uint* r_dst = &DX;
\r
1048 uint src = MASK_OUT_ABOVE_8(DY);
\r
1049 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
1050 uint res = src + dst;
\r
1052 FLAG_N = NFLAG_8(res);
\r
1053 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1054 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1055 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1057 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
1061 M68KMAKE_OP(add, 8, er, .)
\r
1063 uint* r_dst = &DX;
\r
1064 uint src = M68KMAKE_GET_OPER_AY_8;
\r
1065 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
1066 uint res = src + dst;
\r
1068 FLAG_N = NFLAG_8(res);
\r
1069 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1070 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1071 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1073 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
1077 M68KMAKE_OP(add, 16, er, d)
\r
1079 uint* r_dst = &DX;
\r
1080 uint src = MASK_OUT_ABOVE_16(DY);
\r
1081 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
1082 uint res = src + dst;
\r
1084 FLAG_N = NFLAG_16(res);
\r
1085 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1086 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1087 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1089 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
1093 M68KMAKE_OP(add, 16, er, a)
\r
1095 uint* r_dst = &DX;
\r
1096 uint src = MASK_OUT_ABOVE_16(AY);
\r
1097 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
1098 uint res = src + dst;
\r
1100 FLAG_N = NFLAG_16(res);
\r
1101 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1102 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1103 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1105 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
1109 M68KMAKE_OP(add, 16, er, .)
\r
1111 uint* r_dst = &DX;
\r
1112 uint src = M68KMAKE_GET_OPER_AY_16;
\r
1113 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
1114 uint res = src + dst;
\r
1116 FLAG_N = NFLAG_16(res);
\r
1117 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1118 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1119 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1121 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
1125 M68KMAKE_OP(add, 32, er, d)
\r
1127 uint* r_dst = &DX;
\r
1129 uint dst = *r_dst;
\r
1130 uint res = src + dst;
\r
1132 FLAG_N = NFLAG_32(res);
\r
1133 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1134 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1135 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1141 M68KMAKE_OP(add, 32, er, a)
\r
1143 uint* r_dst = &DX;
\r
1145 uint dst = *r_dst;
\r
1146 uint res = src + dst;
\r
1148 FLAG_N = NFLAG_32(res);
\r
1149 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1150 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1151 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1157 M68KMAKE_OP(add, 32, er, .)
\r
1159 uint* r_dst = &DX;
\r
1160 uint src = M68KMAKE_GET_OPER_AY_32;
\r
1161 uint dst = *r_dst;
\r
1162 uint res = src + dst;
\r
1164 FLAG_N = NFLAG_32(res);
\r
1165 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1166 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1167 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1173 M68KMAKE_OP(add, 8, re, .)
\r
1175 uint ea = M68KMAKE_GET_EA_AY_8;
\r
1176 uint src = MASK_OUT_ABOVE_8(DX);
\r
1177 uint dst = m68ki_read_8(ea);
\r
1178 uint res = src + dst;
\r
1180 FLAG_N = NFLAG_8(res);
\r
1181 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1182 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1183 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1185 m68ki_write_8(ea, FLAG_Z);
\r
1189 M68KMAKE_OP(add, 16, re, .)
\r
1191 uint ea = M68KMAKE_GET_EA_AY_16;
\r
1192 uint src = MASK_OUT_ABOVE_16(DX);
\r
1193 uint dst = m68ki_read_16(ea);
\r
1194 uint res = src + dst;
\r
1196 FLAG_N = NFLAG_16(res);
\r
1197 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1198 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1199 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1201 m68ki_write_16(ea, FLAG_Z);
\r
1205 M68KMAKE_OP(add, 32, re, .)
\r
1207 uint ea = M68KMAKE_GET_EA_AY_32;
\r
1209 uint dst = m68ki_read_32(ea);
\r
1210 uint res = src + dst;
\r
1212 FLAG_N = NFLAG_32(res);
\r
1213 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1214 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1215 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1217 m68ki_write_32(ea, FLAG_Z);
\r
1221 M68KMAKE_OP(adda, 16, ., d)
\r
1223 uint* r_dst = &AX;
\r
1225 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(DY));
\r
1229 M68KMAKE_OP(adda, 16, ., a)
\r
1231 uint* r_dst = &AX;
\r
1233 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(AY));
\r
1237 M68KMAKE_OP(adda, 16, ., .)
\r
1239 uint* r_dst = &AX;
\r
1240 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
\r
1242 *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
\r
1246 M68KMAKE_OP(adda, 32, ., d)
\r
1248 uint* r_dst = &AX;
\r
1250 *r_dst = MASK_OUT_ABOVE_32(*r_dst + DY);
\r
1254 M68KMAKE_OP(adda, 32, ., a)
\r
1256 uint* r_dst = &AX;
\r
1258 *r_dst = MASK_OUT_ABOVE_32(*r_dst + AY);
\r
1262 M68KMAKE_OP(adda, 32, ., .)
\r
1264 uint* r_dst = &AX;
\r
1265 uint src = M68KMAKE_GET_OPER_AY_32; // notaz
\r
1267 *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
\r
1271 M68KMAKE_OP(addi, 8, ., d)
\r
1273 uint* r_dst = &DY;
\r
1274 uint src = OPER_I_8();
\r
1275 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
1276 uint res = src + dst;
\r
1278 FLAG_N = NFLAG_8(res);
\r
1279 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1280 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1281 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1283 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
1287 M68KMAKE_OP(addi, 8, ., .)
\r
1289 uint src = OPER_I_8();
\r
1290 uint ea = M68KMAKE_GET_EA_AY_8;
\r
1291 uint dst = m68ki_read_8(ea);
\r
1292 uint res = src + dst;
\r
1294 FLAG_N = NFLAG_8(res);
\r
1295 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1296 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1297 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1299 m68ki_write_8(ea, FLAG_Z);
\r
1303 M68KMAKE_OP(addi, 16, ., d)
\r
1305 uint* r_dst = &DY;
\r
1306 uint src = OPER_I_16();
\r
1307 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
1308 uint res = src + dst;
\r
1310 FLAG_N = NFLAG_16(res);
\r
1311 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1312 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1313 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1315 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
1319 M68KMAKE_OP(addi, 16, ., .)
\r
1321 uint src = OPER_I_16();
\r
1322 uint ea = M68KMAKE_GET_EA_AY_16;
\r
1323 uint dst = m68ki_read_16(ea);
\r
1324 uint res = src + dst;
\r
1326 FLAG_N = NFLAG_16(res);
\r
1327 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1328 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1329 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1331 m68ki_write_16(ea, FLAG_Z);
\r
1335 M68KMAKE_OP(addi, 32, ., d)
\r
1337 uint* r_dst = &DY;
\r
1338 uint src = OPER_I_32();
\r
1339 uint dst = *r_dst;
\r
1340 uint res = src + dst;
\r
1342 FLAG_N = NFLAG_32(res);
\r
1343 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1344 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1345 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1351 M68KMAKE_OP(addi, 32, ., .)
\r
1353 uint src = OPER_I_32();
\r
1354 uint ea = M68KMAKE_GET_EA_AY_32;
\r
1355 uint dst = m68ki_read_32(ea);
\r
1356 uint res = src + dst;
\r
1358 FLAG_N = NFLAG_32(res);
\r
1359 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1360 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1361 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1363 m68ki_write_32(ea, FLAG_Z);
\r
1367 M68KMAKE_OP(addq, 8, ., d)
\r
1369 uint* r_dst = &DY;
\r
1370 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1371 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
1372 uint res = src + dst;
\r
1374 FLAG_N = NFLAG_8(res);
\r
1375 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1376 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1377 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1379 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
1383 M68KMAKE_OP(addq, 8, ., .)
\r
1385 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1386 uint ea = M68KMAKE_GET_EA_AY_8;
\r
1387 uint dst = m68ki_read_8(ea);
\r
1388 uint res = src + dst;
\r
1390 FLAG_N = NFLAG_8(res);
\r
1391 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1392 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1393 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1395 m68ki_write_8(ea, FLAG_Z);
\r
1399 M68KMAKE_OP(addq, 16, ., d)
\r
1401 uint* r_dst = &DY;
\r
1402 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1403 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
1404 uint res = src + dst;
\r
1406 FLAG_N = NFLAG_16(res);
\r
1407 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1408 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1409 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1411 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
1415 M68KMAKE_OP(addq, 16, ., a)
\r
1417 uint* r_dst = &AY;
\r
1419 *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);
\r
1423 M68KMAKE_OP(addq, 16, ., .)
\r
1425 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1426 uint ea = M68KMAKE_GET_EA_AY_16;
\r
1427 uint dst = m68ki_read_16(ea);
\r
1428 uint res = src + dst;
\r
1430 FLAG_N = NFLAG_16(res);
\r
1431 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1432 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1433 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1435 m68ki_write_16(ea, FLAG_Z);
\r
1439 M68KMAKE_OP(addq, 32, ., d)
\r
1441 uint* r_dst = &DY;
\r
1442 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1443 uint dst = *r_dst;
\r
1444 uint res = src + dst;
\r
1446 FLAG_N = NFLAG_32(res);
\r
1447 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1448 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1449 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1455 M68KMAKE_OP(addq, 32, ., a)
\r
1457 uint* r_dst = &AY;
\r
1459 *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);
\r
1463 M68KMAKE_OP(addq, 32, ., .)
\r
1465 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1466 uint ea = M68KMAKE_GET_EA_AY_32;
\r
1467 uint dst = m68ki_read_32(ea);
\r
1468 uint res = src + dst;
\r
1471 FLAG_N = NFLAG_32(res);
\r
1472 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1473 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1474 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1476 m68ki_write_32(ea, FLAG_Z);
\r
1480 M68KMAKE_OP(addx, 8, rr, .)
\r
1482 uint* r_dst = &DX;
\r
1483 uint src = MASK_OUT_ABOVE_8(DY);
\r
1484 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
1485 uint res = src + dst + XFLAG_AS_1();
\r
1487 FLAG_N = NFLAG_8(res);
\r
1488 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1489 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1491 res = MASK_OUT_ABOVE_8(res);
\r
1494 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
1498 M68KMAKE_OP(addx, 16, rr, .)
\r
1500 uint* r_dst = &DX;
\r
1501 uint src = MASK_OUT_ABOVE_16(DY);
\r
1502 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
1503 uint res = src + dst + XFLAG_AS_1();
\r
1505 FLAG_N = NFLAG_16(res);
\r
1506 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1507 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1509 res = MASK_OUT_ABOVE_16(res);
\r
1512 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
1516 M68KMAKE_OP(addx, 32, rr, .)
\r
1518 uint* r_dst = &DX;
\r
1520 uint dst = *r_dst;
\r
1521 uint res = src + dst + XFLAG_AS_1();
\r
1523 FLAG_N = NFLAG_32(res);
\r
1524 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1525 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1527 res = MASK_OUT_ABOVE_32(res);
\r
1534 M68KMAKE_OP(addx, 8, mm, ax7)
\r
1536 uint src = OPER_AY_PD_8();
\r
1537 uint ea = EA_A7_PD_8();
\r
1538 uint dst = m68ki_read_8(ea);
\r
1539 uint res = src + dst + XFLAG_AS_1();
\r
1541 FLAG_N = NFLAG_8(res);
\r
1542 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1543 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1545 res = MASK_OUT_ABOVE_8(res);
\r
1548 m68ki_write_8(ea, res);
\r
1552 M68KMAKE_OP(addx, 8, mm, ay7)
\r
1554 uint src = OPER_A7_PD_8();
\r
1555 uint ea = EA_AX_PD_8();
\r
1556 uint dst = m68ki_read_8(ea);
\r
1557 uint res = src + dst + XFLAG_AS_1();
\r
1559 FLAG_N = NFLAG_8(res);
\r
1560 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1561 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1563 res = MASK_OUT_ABOVE_8(res);
\r
1566 m68ki_write_8(ea, res);
\r
1570 M68KMAKE_OP(addx, 8, mm, axy7)
\r
1572 uint src = OPER_A7_PD_8();
\r
1573 uint ea = EA_A7_PD_8();
\r
1574 uint dst = m68ki_read_8(ea);
\r
1575 uint res = src + dst + XFLAG_AS_1();
\r
1577 FLAG_N = NFLAG_8(res);
\r
1578 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1579 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1581 res = MASK_OUT_ABOVE_8(res);
\r
1584 m68ki_write_8(ea, res);
\r
1588 M68KMAKE_OP(addx, 8, mm, .)
\r
1590 uint src = OPER_AY_PD_8();
\r
1591 uint ea = EA_AX_PD_8();
\r
1592 uint dst = m68ki_read_8(ea);
\r
1593 uint res = src + dst + XFLAG_AS_1();
\r
1595 FLAG_N = NFLAG_8(res);
\r
1596 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1597 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1599 res = MASK_OUT_ABOVE_8(res);
\r
1602 m68ki_write_8(ea, res);
\r
1606 M68KMAKE_OP(addx, 16, mm, .)
\r
1608 uint src = OPER_AY_PD_16();
\r
1609 uint ea = EA_AX_PD_16();
\r
1610 uint dst = m68ki_read_16(ea);
\r
1611 uint res = src + dst + XFLAG_AS_1();
\r
1613 FLAG_N = NFLAG_16(res);
\r
1614 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1615 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1617 res = MASK_OUT_ABOVE_16(res);
\r
1620 m68ki_write_16(ea, res);
\r
1624 M68KMAKE_OP(addx, 32, mm, .)
\r
1626 uint src = OPER_AY_PD_32();
\r
1627 uint ea = EA_AX_PD_32();
\r
1628 uint dst = m68ki_read_32(ea);
\r
1629 uint res = src + dst + XFLAG_AS_1();
\r
1631 FLAG_N = NFLAG_32(res);
\r
1632 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1633 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1635 res = MASK_OUT_ABOVE_32(res);
\r
1638 m68ki_write_32(ea, res);
\r
1642 M68KMAKE_OP(and, 8, er, d)
\r
1644 FLAG_Z = MASK_OUT_ABOVE_8(DX &= (DY | 0xffffff00));
\r
1646 FLAG_N = NFLAG_8(FLAG_Z);
\r
1647 FLAG_C = CFLAG_CLEAR;
\r
1648 FLAG_V = VFLAG_CLEAR;
\r
1652 M68KMAKE_OP(and, 8, er, .)
\r
1654 FLAG_Z = MASK_OUT_ABOVE_8(DX &= (M68KMAKE_GET_OPER_AY_8 | 0xffffff00));
\r
1656 FLAG_N = NFLAG_8(FLAG_Z);
\r
1657 FLAG_C = CFLAG_CLEAR;
\r
1658 FLAG_V = VFLAG_CLEAR;
\r
1662 M68KMAKE_OP(and, 16, er, d)
\r
1664 FLAG_Z = MASK_OUT_ABOVE_16(DX &= (DY | 0xffff0000));
\r
1666 FLAG_N = NFLAG_16(FLAG_Z);
\r
1667 FLAG_C = CFLAG_CLEAR;
\r
1668 FLAG_V = VFLAG_CLEAR;
\r
1672 M68KMAKE_OP(and, 16, er, .)
\r
1674 FLAG_Z = MASK_OUT_ABOVE_16(DX &= (M68KMAKE_GET_OPER_AY_16 | 0xffff0000));
\r
1676 FLAG_N = NFLAG_16(FLAG_Z);
\r
1677 FLAG_C = CFLAG_CLEAR;
\r
1678 FLAG_V = VFLAG_CLEAR;
\r
1682 M68KMAKE_OP(and, 32, er, d)
\r
1684 FLAG_Z = DX &= DY;
\r
1686 FLAG_N = NFLAG_32(FLAG_Z);
\r
1687 FLAG_C = CFLAG_CLEAR;
\r
1688 FLAG_V = VFLAG_CLEAR;
\r
1692 M68KMAKE_OP(and, 32, er, .)
\r
1694 FLAG_Z = DX &= M68KMAKE_GET_OPER_AY_32;
\r
1696 FLAG_N = NFLAG_32(FLAG_Z);
\r
1697 FLAG_C = CFLAG_CLEAR;
\r
1698 FLAG_V = VFLAG_CLEAR;
\r
1702 M68KMAKE_OP(and, 8, re, .)
\r
1704 uint ea = M68KMAKE_GET_EA_AY_8;
\r
1705 uint res = DX & m68ki_read_8(ea);
\r
1707 FLAG_N = NFLAG_8(res);
\r
1708 FLAG_C = CFLAG_CLEAR;
\r
1709 FLAG_V = VFLAG_CLEAR;
\r
1710 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1712 m68ki_write_8(ea, FLAG_Z);
\r
1716 M68KMAKE_OP(and, 16, re, .)
\r
1718 uint ea = M68KMAKE_GET_EA_AY_16;
\r
1719 uint res = DX & m68ki_read_16(ea);
\r
1721 FLAG_N = NFLAG_16(res);
\r
1722 FLAG_C = CFLAG_CLEAR;
\r
1723 FLAG_V = VFLAG_CLEAR;
\r
1724 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1726 m68ki_write_16(ea, FLAG_Z);
\r
1730 M68KMAKE_OP(and, 32, re, .)
\r
1732 uint ea = M68KMAKE_GET_EA_AY_32;
\r
1733 uint res = DX & m68ki_read_32(ea);
\r
1735 FLAG_N = NFLAG_32(res);
\r
1737 FLAG_C = CFLAG_CLEAR;
\r
1738 FLAG_V = VFLAG_CLEAR;
\r
1740 m68ki_write_32(ea, res);
\r
1744 M68KMAKE_OP(andi, 8, ., d)
\r
1746 FLAG_Z = MASK_OUT_ABOVE_8(DY &= (OPER_I_8() | 0xffffff00));
\r
1748 FLAG_N = NFLAG_8(FLAG_Z);
\r
1749 FLAG_C = CFLAG_CLEAR;
\r
1750 FLAG_V = VFLAG_CLEAR;
\r
1754 M68KMAKE_OP(andi, 8, ., .)
\r
1756 uint src = OPER_I_8();
\r
1757 uint ea = M68KMAKE_GET_EA_AY_8;
\r
1758 uint res = src & m68ki_read_8(ea);
\r
1760 FLAG_N = NFLAG_8(res);
\r
1762 FLAG_C = CFLAG_CLEAR;
\r
1763 FLAG_V = VFLAG_CLEAR;
\r
1765 m68ki_write_8(ea, res);
\r
1769 M68KMAKE_OP(andi, 16, ., d)
\r
1771 FLAG_Z = MASK_OUT_ABOVE_16(DY &= (OPER_I_16() | 0xffff0000));
\r
1773 FLAG_N = NFLAG_16(FLAG_Z);
\r
1774 FLAG_C = CFLAG_CLEAR;
\r
1775 FLAG_V = VFLAG_CLEAR;
\r
1779 M68KMAKE_OP(andi, 16, ., .)
\r
1781 uint src = OPER_I_16();
\r
1782 uint ea = M68KMAKE_GET_EA_AY_16;
\r
1783 uint res = src & m68ki_read_16(ea);
\r
1785 FLAG_N = NFLAG_16(res);
\r
1787 FLAG_C = CFLAG_CLEAR;
\r
1788 FLAG_V = VFLAG_CLEAR;
\r
1790 m68ki_write_16(ea, res);
\r
1794 M68KMAKE_OP(andi, 32, ., d)
\r
1796 FLAG_Z = DY &= (OPER_I_32());
\r
1798 FLAG_N = NFLAG_32(FLAG_Z);
\r
1799 FLAG_C = CFLAG_CLEAR;
\r
1800 FLAG_V = VFLAG_CLEAR;
\r
1804 M68KMAKE_OP(andi, 32, ., .)
\r
1806 uint src = OPER_I_32();
\r
1807 uint ea = M68KMAKE_GET_EA_AY_32;
\r
1808 uint res = src & m68ki_read_32(ea);
\r
1810 FLAG_N = NFLAG_32(res);
\r
1812 FLAG_C = CFLAG_CLEAR;
\r
1813 FLAG_V = VFLAG_CLEAR;
\r
1815 m68ki_write_32(ea, res);
\r
1819 M68KMAKE_OP(andi, 16, toc, .)
\r
1821 m68ki_set_ccr(m68ki_get_ccr() & OPER_I_16());
\r
1825 M68KMAKE_OP(andi, 16, tos, .)
\r
1829 uint src = OPER_I_16();
\r
1830 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
1831 m68ki_set_sr(m68ki_get_sr() & src);
\r
1834 m68ki_exception_privilege_violation();
\r
1838 M68KMAKE_OP(asr, 8, s, .)
\r
1840 uint* r_dst = &DY;
\r
1841 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1842 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
1843 uint res = src >> shift;
\r
1846 USE_CYCLES(shift<<CYC_SHIFT);
\r
1848 if(GET_MSB_8(src))
\r
1849 res |= m68ki_shift_8_table[shift];
\r
1851 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
1853 FLAG_N = NFLAG_8(res);
\r
1855 FLAG_V = VFLAG_CLEAR;
\r
1856 FLAG_X = FLAG_C = src << (9-shift);
\r
1860 M68KMAKE_OP(asr, 16, s, .)
\r
1862 uint* r_dst = &DY;
\r
1863 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1864 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
1865 uint res = src >> shift;
\r
1868 USE_CYCLES(shift<<CYC_SHIFT);
\r
1870 if(GET_MSB_16(src))
\r
1871 res |= m68ki_shift_16_table[shift];
\r
1873 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
1875 FLAG_N = NFLAG_16(res);
\r
1877 FLAG_V = VFLAG_CLEAR;
\r
1878 FLAG_X = FLAG_C = src << (9-shift);
\r
1882 M68KMAKE_OP(asr, 32, s, .)
\r
1884 uint* r_dst = &DY;
\r
1885 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1886 uint src = *r_dst;
\r
1887 uint res = src >> shift;
\r
1890 USE_CYCLES(shift<<CYC_SHIFT);
\r
1892 if(GET_MSB_32(src))
\r
1893 res |= m68ki_shift_32_table[shift];
\r
1897 FLAG_N = NFLAG_32(res);
\r
1899 FLAG_V = VFLAG_CLEAR;
\r
1900 FLAG_X = FLAG_C = src << (9-shift);
\r
1904 M68KMAKE_OP(asr, 8, r, .)
\r
1906 uint* r_dst = &DY;
\r
1907 uint shift = DX & 0x3f;
\r
1908 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
1909 uint res = src >> shift;
\r
1913 USE_CYCLES(shift<<CYC_SHIFT);
\r
1917 if(GET_MSB_8(src))
\r
1918 res |= m68ki_shift_8_table[shift];
\r
1920 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
1922 FLAG_X = FLAG_C = src << (9-shift);
\r
1923 FLAG_N = NFLAG_8(res);
\r
1925 FLAG_V = VFLAG_CLEAR;
\r
1929 if(GET_MSB_8(src))
\r
1932 FLAG_C = CFLAG_SET;
\r
1933 FLAG_X = XFLAG_SET;
\r
1934 FLAG_N = NFLAG_SET;
\r
1935 FLAG_Z = ZFLAG_CLEAR;
\r
1936 FLAG_V = VFLAG_CLEAR;
\r
1940 *r_dst &= 0xffffff00;
\r
1941 FLAG_C = CFLAG_CLEAR;
\r
1942 FLAG_X = XFLAG_CLEAR;
\r
1943 FLAG_N = NFLAG_CLEAR;
\r
1944 FLAG_Z = ZFLAG_SET;
\r
1945 FLAG_V = VFLAG_CLEAR;
\r
1949 FLAG_C = CFLAG_CLEAR;
\r
1950 FLAG_N = NFLAG_8(src);
\r
1952 FLAG_V = VFLAG_CLEAR;
\r
1956 M68KMAKE_OP(asr, 16, r, .)
\r
1958 uint* r_dst = &DY;
\r
1959 uint shift = DX & 0x3f;
\r
1960 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
1961 uint res = src >> shift;
\r
1965 USE_CYCLES(shift<<CYC_SHIFT);
\r
1969 if(GET_MSB_16(src))
\r
1970 res |= m68ki_shift_16_table[shift];
\r
1972 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
1974 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
\r
1975 FLAG_N = NFLAG_16(res);
\r
1977 FLAG_V = VFLAG_CLEAR;
\r
1981 if(GET_MSB_16(src))
\r
1984 FLAG_C = CFLAG_SET;
\r
1985 FLAG_X = XFLAG_SET;
\r
1986 FLAG_N = NFLAG_SET;
\r
1987 FLAG_Z = ZFLAG_CLEAR;
\r
1988 FLAG_V = VFLAG_CLEAR;
\r
1992 *r_dst &= 0xffff0000;
\r
1993 FLAG_C = CFLAG_CLEAR;
\r
1994 FLAG_X = XFLAG_CLEAR;
\r
1995 FLAG_N = NFLAG_CLEAR;
\r
1996 FLAG_Z = ZFLAG_SET;
\r
1997 FLAG_V = VFLAG_CLEAR;
\r
2001 FLAG_C = CFLAG_CLEAR;
\r
2002 FLAG_N = NFLAG_16(src);
\r
2004 FLAG_V = VFLAG_CLEAR;
\r
2008 M68KMAKE_OP(asr, 32, r, .)
\r
2010 uint* r_dst = &DY;
\r
2011 uint shift = DX & 0x3f;
\r
2012 uint src = *r_dst;
\r
2013 uint res = src >> shift;
\r
2017 USE_CYCLES(shift<<CYC_SHIFT);
\r
2021 if(GET_MSB_32(src))
\r
2022 res |= m68ki_shift_32_table[shift];
\r
2026 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
\r
2027 FLAG_N = NFLAG_32(res);
\r
2029 FLAG_V = VFLAG_CLEAR;
\r
2033 if(GET_MSB_32(src))
\r
2035 *r_dst = 0xffffffff;
\r
2036 FLAG_C = CFLAG_SET;
\r
2037 FLAG_X = XFLAG_SET;
\r
2038 FLAG_N = NFLAG_SET;
\r
2039 FLAG_Z = ZFLAG_CLEAR;
\r
2040 FLAG_V = VFLAG_CLEAR;
\r
2045 FLAG_C = CFLAG_CLEAR;
\r
2046 FLAG_X = XFLAG_CLEAR;
\r
2047 FLAG_N = NFLAG_CLEAR;
\r
2048 FLAG_Z = ZFLAG_SET;
\r
2049 FLAG_V = VFLAG_CLEAR;
\r
2053 FLAG_C = CFLAG_CLEAR;
\r
2054 FLAG_N = NFLAG_32(src);
\r
2056 FLAG_V = VFLAG_CLEAR;
\r
2060 M68KMAKE_OP(asr, 16, ., .)
\r
2062 uint ea = M68KMAKE_GET_EA_AY_16;
\r
2063 uint src = m68ki_read_16(ea);
\r
2064 uint res = src >> 1;
\r
2066 if(GET_MSB_16(src))
\r
2069 m68ki_write_16(ea, res);
\r
2071 FLAG_N = NFLAG_16(res);
\r
2073 FLAG_V = VFLAG_CLEAR;
\r
2074 FLAG_C = FLAG_X = src << 8;
\r
2078 M68KMAKE_OP(asl, 8, s, .)
\r
2080 uint* r_dst = &DY;
\r
2081 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
2082 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
2083 uint res = MASK_OUT_ABOVE_8(src << shift);
\r
2086 USE_CYCLES(shift<<CYC_SHIFT);
\r
2088 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
2090 FLAG_X = FLAG_C = src << shift;
\r
2091 FLAG_N = NFLAG_8(res);
\r
2093 src &= m68ki_shift_8_table[shift + 1];
\r
2094 FLAG_V = (!(src == 0 || (src == m68ki_shift_8_table[shift + 1] && shift < 8)))<<7;
\r
2098 M68KMAKE_OP(asl, 16, s, .)
\r
2100 uint* r_dst = &DY;
\r
2101 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
2102 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
2103 uint res = MASK_OUT_ABOVE_16(src << shift);
\r
2106 USE_CYCLES(shift<<CYC_SHIFT);
\r
2108 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
2110 FLAG_N = NFLAG_16(res);
\r
2112 FLAG_X = FLAG_C = src >> (8-shift);
\r
2113 src &= m68ki_shift_16_table[shift + 1];
\r
2114 FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
\r
2118 M68KMAKE_OP(asl, 32, s, .)
\r
2120 uint* r_dst = &DY;
\r
2121 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
2122 uint src = *r_dst;
\r
2123 uint res = MASK_OUT_ABOVE_32(src << shift);
\r
2126 USE_CYCLES(shift<<CYC_SHIFT);
\r
2130 FLAG_N = NFLAG_32(res);
\r
2132 FLAG_X = FLAG_C = src >> (24-shift);
\r
2133 src &= m68ki_shift_32_table[shift + 1];
\r
2134 FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
\r
2138 M68KMAKE_OP(asl, 8, r, .)
\r
2140 uint* r_dst = &DY;
\r
2141 uint shift = DX & 0x3f;
\r
2142 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
2143 uint res = MASK_OUT_ABOVE_8(src << shift);
\r
2147 USE_CYCLES(shift<<CYC_SHIFT);
\r
2151 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
2152 FLAG_X = FLAG_C = src << shift;
\r
2153 FLAG_N = NFLAG_8(res);
\r
2155 src &= m68ki_shift_8_table[shift + 1];
\r
2156 FLAG_V = (!(src == 0 || src == m68ki_shift_8_table[shift + 1]))<<7;
\r
2160 *r_dst &= 0xffffff00;
\r
2161 FLAG_X = FLAG_C = ((shift == 8 ? src & 1 : 0))<<8;
\r
2162 FLAG_N = NFLAG_CLEAR;
\r
2163 FLAG_Z = ZFLAG_SET;
\r
2164 FLAG_V = (!(src == 0))<<7;
\r
2168 FLAG_C = CFLAG_CLEAR;
\r
2169 FLAG_N = NFLAG_8(src);
\r
2171 FLAG_V = VFLAG_CLEAR;
\r
2175 M68KMAKE_OP(asl, 16, r, .)
\r
2177 uint* r_dst = &DY;
\r
2178 uint shift = DX & 0x3f;
\r
2179 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
2180 uint res = MASK_OUT_ABOVE_16(src << shift);
\r
2184 USE_CYCLES(shift<<CYC_SHIFT);
\r
2188 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
2189 FLAG_X = FLAG_C = (src << shift) >> 8;
\r
2190 FLAG_N = NFLAG_16(res);
\r
2192 src &= m68ki_shift_16_table[shift + 1];
\r
2193 FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
\r
2197 *r_dst &= 0xffff0000;
\r
2198 FLAG_X = FLAG_C = ((shift == 16 ? src & 1 : 0))<<8;
\r
2199 FLAG_N = NFLAG_CLEAR;
\r
2200 FLAG_Z = ZFLAG_SET;
\r
2201 FLAG_V = (!(src == 0))<<7;
\r
2205 FLAG_C = CFLAG_CLEAR;
\r
2206 FLAG_N = NFLAG_16(src);
\r
2208 FLAG_V = VFLAG_CLEAR;
\r
2212 M68KMAKE_OP(asl, 32, r, .)
\r
2214 uint* r_dst = &DY;
\r
2215 uint shift = DX & 0x3f;
\r
2216 uint src = *r_dst;
\r
2217 uint res = MASK_OUT_ABOVE_32(src << shift);
\r
2221 USE_CYCLES(shift<<CYC_SHIFT);
\r
2226 FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;
\r
2227 FLAG_N = NFLAG_32(res);
\r
2229 src &= m68ki_shift_32_table[shift + 1];
\r
2230 FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
\r
2235 FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;
\r
2236 FLAG_N = NFLAG_CLEAR;
\r
2237 FLAG_Z = ZFLAG_SET;
\r
2238 FLAG_V = (!(src == 0))<<7;
\r
2242 FLAG_C = CFLAG_CLEAR;
\r
2243 FLAG_N = NFLAG_32(src);
\r
2245 FLAG_V = VFLAG_CLEAR;
\r
2249 M68KMAKE_OP(asl, 16, ., .)
\r
2251 uint ea = M68KMAKE_GET_EA_AY_16;
\r
2252 uint src = m68ki_read_16(ea);
\r
2253 uint res = MASK_OUT_ABOVE_16(src << 1);
\r
2255 m68ki_write_16(ea, res);
\r
2257 FLAG_N = NFLAG_16(res);
\r
2259 FLAG_X = FLAG_C = src >> 7;
\r
2261 FLAG_V = (!(src == 0 || src == 0xc000))<<7;
\r
2265 M68KMAKE_OP(bcc, 8, ., .)
\r
2269 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
2270 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
\r
2273 USE_CYCLES(CYC_BCC_NOTAKE_B);
\r
2277 M68KMAKE_OP(bcc, 16, ., .)
\r
2281 uint offset = OPER_I_16();
\r
2283 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
2284 m68ki_branch_16(offset);
\r
2288 USE_CYCLES(CYC_BCC_NOTAKE_W);
\r
2292 M68KMAKE_OP(bcc, 32, ., .)
\r
2294 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2298 uint offset = OPER_I_32();
\r
2300 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
2301 m68ki_branch_32(offset);
\r
2311 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
2312 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
\r
2315 USE_CYCLES(CYC_BCC_NOTAKE_B);
\r
2320 M68KMAKE_OP(bchg, 32, r, d)
\r
2322 uint* r_dst = &DY;
\r
2323 uint mask = 1 << (DX & 0x1f);
\r
2325 FLAG_Z = *r_dst & mask;
\r
2330 M68KMAKE_OP(bchg, 8, r, .)
\r
2332 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2333 uint src = m68ki_read_8(ea);
\r
2334 uint mask = 1 << (DX & 7);
\r
2336 FLAG_Z = src & mask;
\r
2337 m68ki_write_8(ea, src ^ mask);
\r
2341 M68KMAKE_OP(bchg, 32, s, d)
\r
2343 uint* r_dst = &DY;
\r
2344 uint mask = 1 << (OPER_I_8() & 0x1f);
\r
2346 FLAG_Z = *r_dst & mask;
\r
2351 M68KMAKE_OP(bchg, 8, s, .)
\r
2353 uint mask = 1 << (OPER_I_8() & 7);
\r
2354 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2355 uint src = m68ki_read_8(ea);
\r
2357 FLAG_Z = src & mask;
\r
2358 m68ki_write_8(ea, src ^ mask);
\r
2362 M68KMAKE_OP(bclr, 32, r, d)
\r
2364 uint* r_dst = &DY;
\r
2365 uint mask = 1 << (DX & 0x1f);
\r
2367 FLAG_Z = *r_dst & mask;
\r
2372 M68KMAKE_OP(bclr, 8, r, .)
\r
2374 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2375 uint src = m68ki_read_8(ea);
\r
2376 uint mask = 1 << (DX & 7);
\r
2378 FLAG_Z = src & mask;
\r
2379 m68ki_write_8(ea, src & ~mask);
\r
2383 M68KMAKE_OP(bclr, 32, s, d)
\r
2385 uint* r_dst = &DY;
\r
2386 uint mask = 1 << (OPER_I_8() & 0x1f);
\r
2388 FLAG_Z = *r_dst & mask;
\r
2393 M68KMAKE_OP(bclr, 8, s, .)
\r
2395 uint mask = 1 << (OPER_I_8() & 7);
\r
2396 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2397 uint src = m68ki_read_8(ea);
\r
2399 FLAG_Z = src & mask;
\r
2400 m68ki_write_8(ea, src & ~mask);
\r
2404 M68KMAKE_OP(bfchg, 32, ., d)
\r
2406 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2408 uint word2 = OPER_I_16();
\r
2409 uint offset = (word2>>6)&31;
\r
2410 uint width = word2;
\r
2416 offset = REG_D[offset&7];
\r
2418 width = REG_D[width&7];
\r
2421 width = ((width-1) & 31) + 1;
\r
2423 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2424 mask = ROR_32(mask, offset);
\r
2426 FLAG_N = NFLAG_32(*data<<offset);
\r
2427 FLAG_Z = *data & mask;
\r
2428 FLAG_V = VFLAG_CLEAR;
\r
2429 FLAG_C = CFLAG_CLEAR;
\r
2435 m68ki_exception_illegal();
\r
2439 M68KMAKE_OP(bfchg, 32, ., .)
\r
2441 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2443 uint word2 = OPER_I_16();
\r
2444 sint offset = (word2>>6)&31;
\r
2445 uint width = word2;
\r
2449 uint data_byte = 0;
\r
2450 uint mask_byte = 0;
\r
2451 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2455 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2457 width = REG_D[width&7];
\r
2459 /* Offset is signed so we have to use ugly math =( */
\r
2467 width = ((width-1) & 31) + 1;
\r
2469 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2470 mask_long = mask_base >> offset;
\r
2472 data_long = m68ki_read_32(ea);
\r
2473 FLAG_N = NFLAG_32(data_long << offset);
\r
2474 FLAG_Z = data_long & mask_long;
\r
2475 FLAG_V = VFLAG_CLEAR;
\r
2476 FLAG_C = CFLAG_CLEAR;
\r
2478 m68ki_write_32(ea, data_long ^ mask_long);
\r
2480 if((width + offset) > 32)
\r
2482 mask_byte = MASK_OUT_ABOVE_8(mask_base);
\r
2483 data_byte = m68ki_read_8(ea+4);
\r
2484 FLAG_Z |= (data_byte & mask_byte);
\r
2485 m68ki_write_8(ea+4, data_byte ^ mask_byte);
\r
2489 m68ki_exception_illegal();
\r
2493 M68KMAKE_OP(bfclr, 32, ., d)
\r
2495 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2497 uint word2 = OPER_I_16();
\r
2498 uint offset = (word2>>6)&31;
\r
2499 uint width = word2;
\r
2505 offset = REG_D[offset&7];
\r
2507 width = REG_D[width&7];
\r
2511 width = ((width-1) & 31) + 1;
\r
2514 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2515 mask = ROR_32(mask, offset);
\r
2517 FLAG_N = NFLAG_32(*data<<offset);
\r
2518 FLAG_Z = *data & mask;
\r
2519 FLAG_V = VFLAG_CLEAR;
\r
2520 FLAG_C = CFLAG_CLEAR;
\r
2526 m68ki_exception_illegal();
\r
2530 M68KMAKE_OP(bfclr, 32, ., .)
\r
2532 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2534 uint word2 = OPER_I_16();
\r
2535 sint offset = (word2>>6)&31;
\r
2536 uint width = word2;
\r
2540 uint data_byte = 0;
\r
2541 uint mask_byte = 0;
\r
2542 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2546 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2548 width = REG_D[width&7];
\r
2550 /* Offset is signed so we have to use ugly math =( */
\r
2558 width = ((width-1) & 31) + 1;
\r
2560 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2561 mask_long = mask_base >> offset;
\r
2563 data_long = m68ki_read_32(ea);
\r
2564 FLAG_N = NFLAG_32(data_long << offset);
\r
2565 FLAG_Z = data_long & mask_long;
\r
2566 FLAG_V = VFLAG_CLEAR;
\r
2567 FLAG_C = CFLAG_CLEAR;
\r
2569 m68ki_write_32(ea, data_long & ~mask_long);
\r
2571 if((width + offset) > 32)
\r
2573 mask_byte = MASK_OUT_ABOVE_8(mask_base);
\r
2574 data_byte = m68ki_read_8(ea+4);
\r
2575 FLAG_Z |= (data_byte & mask_byte);
\r
2576 m68ki_write_8(ea+4, data_byte & ~mask_byte);
\r
2580 m68ki_exception_illegal();
\r
2584 M68KMAKE_OP(bfexts, 32, ., d)
\r
2586 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2588 uint word2 = OPER_I_16();
\r
2589 uint offset = (word2>>6)&31;
\r
2590 uint width = word2;
\r
2595 offset = REG_D[offset&7];
\r
2597 width = REG_D[width&7];
\r
2600 width = ((width-1) & 31) + 1;
\r
2602 data = ROL_32(data, offset);
\r
2603 FLAG_N = NFLAG_32(data);
\r
2604 data = MAKE_INT_32(data) >> (32 - width);
\r
2607 FLAG_V = VFLAG_CLEAR;
\r
2608 FLAG_C = CFLAG_CLEAR;
\r
2610 REG_D[(word2>>12)&7] = data;
\r
2614 m68ki_exception_illegal();
\r
2618 M68KMAKE_OP(bfexts, 32, ., .)
\r
2620 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2622 uint word2 = OPER_I_16();
\r
2623 sint offset = (word2>>6)&31;
\r
2624 uint width = word2;
\r
2626 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2630 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2632 width = REG_D[width&7];
\r
2634 /* Offset is signed so we have to use ugly math =( */
\r
2642 width = ((width-1) & 31) + 1;
\r
2644 data = m68ki_read_32(ea);
\r
2646 data = MASK_OUT_ABOVE_32(data<<offset);
\r
2648 if((offset+width) > 32)
\r
2649 data |= (m68ki_read_8(ea+4) << offset) >> 8;
\r
2651 FLAG_N = NFLAG_32(data);
\r
2652 data = MAKE_INT_32(data) >> (32 - width);
\r
2655 FLAG_V = VFLAG_CLEAR;
\r
2656 FLAG_C = CFLAG_CLEAR;
\r
2658 REG_D[(word2 >> 12) & 7] = data;
\r
2662 m68ki_exception_illegal();
\r
2666 M68KMAKE_OP(bfextu, 32, ., d)
\r
2668 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2670 uint word2 = OPER_I_16();
\r
2671 uint offset = (word2>>6)&31;
\r
2672 uint width = word2;
\r
2677 offset = REG_D[offset&7];
\r
2679 width = REG_D[width&7];
\r
2682 width = ((width-1) & 31) + 1;
\r
2684 data = ROL_32(data, offset);
\r
2685 FLAG_N = NFLAG_32(data);
\r
2686 data >>= 32 - width;
\r
2689 FLAG_V = VFLAG_CLEAR;
\r
2690 FLAG_C = CFLAG_CLEAR;
\r
2692 REG_D[(word2>>12)&7] = data;
\r
2696 m68ki_exception_illegal();
\r
2700 M68KMAKE_OP(bfextu, 32, ., .)
\r
2702 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2704 uint word2 = OPER_I_16();
\r
2705 sint offset = (word2>>6)&31;
\r
2706 uint width = word2;
\r
2708 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2712 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2714 width = REG_D[width&7];
\r
2716 /* Offset is signed so we have to use ugly math =( */
\r
2724 width = ((width-1) & 31) + 1;
\r
2726 data = m68ki_read_32(ea);
\r
2727 data = MASK_OUT_ABOVE_32(data<<offset);
\r
2729 if((offset+width) > 32)
\r
2730 data |= (m68ki_read_8(ea+4) << offset) >> 8;
\r
2732 FLAG_N = NFLAG_32(data);
\r
2733 data >>= (32 - width);
\r
2736 FLAG_V = VFLAG_CLEAR;
\r
2737 FLAG_C = CFLAG_CLEAR;
\r
2739 REG_D[(word2 >> 12) & 7] = data;
\r
2743 m68ki_exception_illegal();
\r
2747 M68KMAKE_OP(bfffo, 32, ., d)
\r
2749 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2751 uint word2 = OPER_I_16();
\r
2752 uint offset = (word2>>6)&31;
\r
2753 uint width = word2;
\r
2759 offset = REG_D[offset&7];
\r
2761 width = REG_D[width&7];
\r
2764 width = ((width-1) & 31) + 1;
\r
2766 data = ROL_32(data, offset);
\r
2767 FLAG_N = NFLAG_32(data);
\r
2768 data >>= 32 - width;
\r
2771 FLAG_V = VFLAG_CLEAR;
\r
2772 FLAG_C = CFLAG_CLEAR;
\r
2774 for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
\r
2777 REG_D[(word2>>12)&7] = offset;
\r
2781 m68ki_exception_illegal();
\r
2785 M68KMAKE_OP(bfffo, 32, ., .)
\r
2787 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2789 uint word2 = OPER_I_16();
\r
2790 sint offset = (word2>>6)&31;
\r
2791 sint local_offset;
\r
2792 uint width = word2;
\r
2795 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2799 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2801 width = REG_D[width&7];
\r
2803 /* Offset is signed so we have to use ugly math =( */
\r
2805 local_offset = offset % 8;
\r
2806 if(local_offset < 0)
\r
2808 local_offset += 8;
\r
2811 width = ((width-1) & 31) + 1;
\r
2813 data = m68ki_read_32(ea);
\r
2814 data = MASK_OUT_ABOVE_32(data<<local_offset);
\r
2816 if((local_offset+width) > 32)
\r
2817 data |= (m68ki_read_8(ea+4) << local_offset) >> 8;
\r
2819 FLAG_N = NFLAG_32(data);
\r
2820 data >>= (32 - width);
\r
2823 FLAG_V = VFLAG_CLEAR;
\r
2824 FLAG_C = CFLAG_CLEAR;
\r
2826 for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
\r
2829 REG_D[(word2>>12)&7] = offset;
\r
2833 m68ki_exception_illegal();
\r
2837 M68KMAKE_OP(bfins, 32, ., d)
\r
2839 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2841 uint word2 = OPER_I_16();
\r
2842 uint offset = (word2>>6)&31;
\r
2843 uint width = word2;
\r
2846 uint64 insert = REG_D[(word2>>12)&7];
\r
2850 offset = REG_D[offset&7];
\r
2852 width = REG_D[width&7];
\r
2856 width = ((width-1) & 31) + 1;
\r
2859 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2860 mask = ROR_32(mask, offset);
\r
2862 insert = MASK_OUT_ABOVE_32(insert << (32 - width));
\r
2863 FLAG_N = NFLAG_32(insert);
\r
2865 insert = ROR_32(insert, offset);
\r
2867 FLAG_V = VFLAG_CLEAR;
\r
2868 FLAG_C = CFLAG_CLEAR;
\r
2875 m68ki_exception_illegal();
\r
2879 M68KMAKE_OP(bfins, 32, ., .)
\r
2881 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2883 uint word2 = OPER_I_16();
\r
2884 sint offset = (word2>>6)&31;
\r
2885 uint width = word2;
\r
2886 uint insert_base = REG_D[(word2>>12)&7];
\r
2892 uint data_byte = 0;
\r
2893 uint mask_byte = 0;
\r
2894 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2898 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2900 width = REG_D[width&7];
\r
2902 /* Offset is signed so we have to use ugly math =( */
\r
2910 width = ((width-1) & 31) + 1;
\r
2912 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2913 mask_long = mask_base >> offset;
\r
2915 insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width));
\r
2916 FLAG_N = NFLAG_32(insert_base);
\r
2917 FLAG_Z = insert_base;
\r
2918 insert_long = insert_base >> offset;
\r
2920 data_long = m68ki_read_32(ea);
\r
2921 FLAG_V = VFLAG_CLEAR;
\r
2922 FLAG_C = CFLAG_CLEAR;
\r
2924 m68ki_write_32(ea, (data_long & ~mask_long) | insert_long);
\r
2926 if((width + offset) > 32)
\r
2928 mask_byte = MASK_OUT_ABOVE_8(mask_base);
\r
2929 insert_byte = MASK_OUT_ABOVE_8(insert_base);
\r
2930 data_byte = m68ki_read_8(ea+4);
\r
2931 FLAG_Z |= (data_byte & mask_byte);
\r
2932 m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte);
\r
2936 m68ki_exception_illegal();
\r
2940 M68KMAKE_OP(bfset, 32, ., d)
\r
2942 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2944 uint word2 = OPER_I_16();
\r
2945 uint offset = (word2>>6)&31;
\r
2946 uint width = word2;
\r
2952 offset = REG_D[offset&7];
\r
2954 width = REG_D[width&7];
\r
2958 width = ((width-1) & 31) + 1;
\r
2961 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2962 mask = ROR_32(mask, offset);
\r
2964 FLAG_N = NFLAG_32(*data<<offset);
\r
2965 FLAG_Z = *data & mask;
\r
2966 FLAG_V = VFLAG_CLEAR;
\r
2967 FLAG_C = CFLAG_CLEAR;
\r
2973 m68ki_exception_illegal();
\r
2977 M68KMAKE_OP(bfset, 32, ., .)
\r
2979 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2981 uint word2 = OPER_I_16();
\r
2982 sint offset = (word2>>6)&31;
\r
2983 uint width = word2;
\r
2987 uint data_byte = 0;
\r
2988 uint mask_byte = 0;
\r
2989 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2993 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2995 width = REG_D[width&7];
\r
2997 /* Offset is signed so we have to use ugly math =( */
\r
3005 width = ((width-1) & 31) + 1;
\r
3008 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
3009 mask_long = mask_base >> offset;
\r
3011 data_long = m68ki_read_32(ea);
\r
3012 FLAG_N = NFLAG_32(data_long << offset);
\r
3013 FLAG_Z = data_long & mask_long;
\r
3014 FLAG_V = VFLAG_CLEAR;
\r
3015 FLAG_C = CFLAG_CLEAR;
\r
3017 m68ki_write_32(ea, data_long | mask_long);
\r
3019 if((width + offset) > 32)
\r
3021 mask_byte = MASK_OUT_ABOVE_8(mask_base);
\r
3022 data_byte = m68ki_read_8(ea+4);
\r
3023 FLAG_Z |= (data_byte & mask_byte);
\r
3024 m68ki_write_8(ea+4, data_byte | mask_byte);
\r
3028 m68ki_exception_illegal();
\r
3032 M68KMAKE_OP(bftst, 32, ., d)
\r
3034 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3036 uint word2 = OPER_I_16();
\r
3037 uint offset = (word2>>6)&31;
\r
3038 uint width = word2;
\r
3044 offset = REG_D[offset&7];
\r
3046 width = REG_D[width&7];
\r
3050 width = ((width-1) & 31) + 1;
\r
3053 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
3054 mask = ROR_32(mask, offset);
\r
3056 FLAG_N = NFLAG_32(*data<<offset);
\r
3057 FLAG_Z = *data & mask;
\r
3058 FLAG_V = VFLAG_CLEAR;
\r
3059 FLAG_C = CFLAG_CLEAR;
\r
3063 m68ki_exception_illegal();
\r
3067 M68KMAKE_OP(bftst, 32, ., .)
\r
3069 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3071 uint word2 = OPER_I_16();
\r
3072 sint offset = (word2>>6)&31;
\r
3073 uint width = word2;
\r
3077 uint data_byte = 0;
\r
3078 uint mask_byte = 0;
\r
3079 uint ea = M68KMAKE_GET_EA_AY_8;
\r
3082 offset = MAKE_INT_32(REG_D[offset&7]);
\r
3084 width = REG_D[width&7];
\r
3086 /* Offset is signed so we have to use ugly math =( */
\r
3094 width = ((width-1) & 31) + 1;
\r
3097 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
3098 mask_long = mask_base >> offset;
\r
3100 data_long = m68ki_read_32(ea);
\r
3101 FLAG_N = ((data_long & (0x80000000 >> offset))<<offset)>>24;
\r
3102 FLAG_Z = data_long & mask_long;
\r
3103 FLAG_V = VFLAG_CLEAR;
\r
3104 FLAG_C = CFLAG_CLEAR;
\r
3106 if((width + offset) > 32)
\r
3108 mask_byte = MASK_OUT_ABOVE_8(mask_base);
\r
3109 data_byte = m68ki_read_8(ea+4);
\r
3110 FLAG_Z |= (data_byte & mask_byte);
\r
3114 m68ki_exception_illegal();
\r
3118 M68KMAKE_OP(bkpt, 0, ., .)
\r
3120 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
3122 m68ki_bkpt_ack(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE) ? REG_IR & 7 : 0); /* auto-disable (see m68kcpu.h) */
\r
3124 m68ki_exception_illegal();
\r
3128 M68KMAKE_OP(bra, 8, ., .)
\r
3130 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3131 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
\r
3132 if(REG_PC == REG_PPC)
\r
3137 M68KMAKE_OP(bra, 16, ., .)
\r
3139 uint offset = OPER_I_16();
\r
3141 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3142 m68ki_branch_16(offset);
\r
3143 if(REG_PC == REG_PPC)
\r
3148 M68KMAKE_OP(bra, 32, ., .)
\r
3150 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3152 uint offset = OPER_I_32();
\r
3154 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3155 m68ki_branch_32(offset);
\r
3156 if(REG_PC == REG_PPC)
\r
3162 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3163 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
\r
3164 if(REG_PC == REG_PPC)
\r
3170 M68KMAKE_OP(bset, 32, r, d)
\r
3172 uint* r_dst = &DY;
\r
3173 uint mask = 1 << (DX & 0x1f);
\r
3175 FLAG_Z = *r_dst & mask;
\r
3180 M68KMAKE_OP(bset, 8, r, .)
\r
3182 uint ea = M68KMAKE_GET_EA_AY_8;
\r
3183 uint src = m68ki_read_8(ea);
\r
3184 uint mask = 1 << (DX & 7);
\r
3186 FLAG_Z = src & mask;
\r
3187 m68ki_write_8(ea, src | mask);
\r
3191 M68KMAKE_OP(bset, 32, s, d)
\r
3193 uint* r_dst = &DY;
\r
3194 uint mask = 1 << (OPER_I_8() & 0x1f);
\r
3196 FLAG_Z = *r_dst & mask;
\r
3201 M68KMAKE_OP(bset, 8, s, .)
\r
3203 uint mask = 1 << (OPER_I_8() & 7);
\r
3204 uint ea = M68KMAKE_GET_EA_AY_8;
\r
3205 uint src = m68ki_read_8(ea);
\r
3207 FLAG_Z = src & mask;
\r
3208 m68ki_write_8(ea, src | mask);
\r
3212 M68KMAKE_OP(bsr, 8, ., .)
\r
3214 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3215 m68ki_push_32(REG_PC);
\r
3216 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
\r
3220 M68KMAKE_OP(bsr, 16, ., .)
\r
3222 uint offset = OPER_I_16();
\r
3223 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3224 m68ki_push_32(REG_PC);
\r
3226 m68ki_branch_16(offset);
\r
3230 M68KMAKE_OP(bsr, 32, ., .)
\r
3232 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3234 uint offset = OPER_I_32();
\r
3235 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3236 m68ki_push_32(REG_PC);
\r
3238 m68ki_branch_32(offset);
\r
3243 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3244 m68ki_push_32(REG_PC);
\r
3245 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
\r
3250 M68KMAKE_OP(btst, 32, r, d)
\r
3252 FLAG_Z = DY & (1 << (DX & 0x1f));
\r
3256 M68KMAKE_OP(btst, 8, r, .)
\r
3258 FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << (DX & 7));
\r
3262 M68KMAKE_OP(btst, 32, s, d)
\r
3264 FLAG_Z = DY & (1 << (OPER_I_8() & 0x1f));
\r
3268 M68KMAKE_OP(btst, 8, s, .)
\r
3270 uint bit = OPER_I_8() & 7;
\r
3272 FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << bit);
\r
3276 M68KMAKE_OP(callm, 32, ., .)
\r
3278 /* note: watch out for pcrelative modes */
\r
3279 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
3281 uint ea = M68KMAKE_GET_EA_AY_32;
\r
3283 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3285 (void)ea; /* just to avoid an 'unused variable' warning */
\r
3286 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
3287 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
3288 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
3291 m68ki_exception_illegal();
\r
3295 M68KMAKE_OP(cas, 8, ., .)
\r
3297 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3299 uint word2 = OPER_I_16();
\r
3300 uint ea = M68KMAKE_GET_EA_AY_8;
\r
3301 uint dest = m68ki_read_8(ea);
\r
3302 uint* compare = ®_D[word2 & 7];
\r
3303 uint res = dest - MASK_OUT_ABOVE_8(*compare);
\r
3305 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3306 FLAG_N = NFLAG_8(res);
\r
3307 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
3308 FLAG_V = VFLAG_SUB_8(*compare, dest, res);
\r
3309 FLAG_C = CFLAG_8(res);
\r
3312 *compare = MASK_OUT_BELOW_8(*compare) | dest;
\r
3316 m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));
\r
3320 m68ki_exception_illegal();
\r
3324 M68KMAKE_OP(cas, 16, ., .)
\r
3326 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3328 uint word2 = OPER_I_16();
\r
3329 uint ea = M68KMAKE_GET_EA_AY_16;
\r
3330 uint dest = m68ki_read_16(ea);
\r
3331 uint* compare = ®_D[word2 & 7];
\r
3332 uint res = dest - MASK_OUT_ABOVE_16(*compare);
\r
3334 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3335 FLAG_N = NFLAG_16(res);
\r
3336 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
3337 FLAG_V = VFLAG_SUB_16(*compare, dest, res);
\r
3338 FLAG_C = CFLAG_16(res);
\r
3341 *compare = MASK_OUT_BELOW_16(*compare) | dest;
\r
3345 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7]));
\r
3349 m68ki_exception_illegal();
\r
3353 M68KMAKE_OP(cas, 32, ., .)
\r
3355 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3357 uint word2 = OPER_I_16();
\r
3358 uint ea = M68KMAKE_GET_EA_AY_32;
\r
3359 uint dest = m68ki_read_32(ea);
\r
3360 uint* compare = ®_D[word2 & 7];
\r
3361 uint res = dest - *compare;
\r
3363 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3364 FLAG_N = NFLAG_32(res);
\r
3365 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
3366 FLAG_V = VFLAG_SUB_32(*compare, dest, res);
\r
3367 FLAG_C = CFLAG_SUB_32(*compare, dest, res);
\r
3374 m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]);
\r
3378 m68ki_exception_illegal();
\r
3382 M68KMAKE_OP(cas2, 16, ., .)
\r
3384 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3386 uint word2 = OPER_I_32();
\r
3387 uint* compare1 = ®_D[(word2 >> 16) & 7];
\r
3388 uint ea1 = REG_DA[(word2 >> 28) & 15];
\r
3389 uint dest1 = m68ki_read_16(ea1);
\r
3390 uint res1 = dest1 - MASK_OUT_ABOVE_16(*compare1);
\r
3391 uint* compare2 = ®_D[word2 & 7];
\r
3392 uint ea2 = REG_DA[(word2 >> 12) & 15];
\r
3393 uint dest2 = m68ki_read_16(ea2);
\r
3396 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3397 FLAG_N = NFLAG_16(res1);
\r
3398 FLAG_Z = MASK_OUT_ABOVE_16(res1);
\r
3399 FLAG_V = VFLAG_SUB_16(*compare1, dest1, res1);
\r
3400 FLAG_C = CFLAG_16(res1);
\r
3404 res2 = dest2 - MASK_OUT_ABOVE_16(*compare2);
\r
3406 FLAG_N = NFLAG_16(res2);
\r
3407 FLAG_Z = MASK_OUT_ABOVE_16(res2);
\r
3408 FLAG_V = VFLAG_SUB_16(*compare2, dest2, res2);
\r
3409 FLAG_C = CFLAG_16(res2);
\r
3414 m68ki_write_16(ea1, REG_D[(word2 >> 22) & 7]);
\r
3415 m68ki_write_16(ea2, REG_D[(word2 >> 6) & 7]);
\r
3419 *compare1 = BIT_1F(word2) ? MAKE_INT_16(dest1) : MASK_OUT_BELOW_16(*compare1) | dest1;
\r
3420 *compare2 = BIT_F(word2) ? MAKE_INT_16(dest2) : MASK_OUT_BELOW_16(*compare2) | dest2;
\r
3423 m68ki_exception_illegal();
\r
3427 M68KMAKE_OP(cas2, 32, ., .)
\r
3429 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3431 uint word2 = OPER_I_32();
\r
3432 uint* compare1 = ®_D[(word2 >> 16) & 7];
\r
3433 uint ea1 = REG_DA[(word2 >> 28) & 15];
\r
3434 uint dest1 = m68ki_read_32(ea1);
\r
3435 uint res1 = dest1 - *compare1;
\r
3436 uint* compare2 = ®_D[word2 & 7];
\r
3437 uint ea2 = REG_DA[(word2 >> 12) & 15];
\r
3438 uint dest2 = m68ki_read_32(ea2);
\r
3441 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3442 FLAG_N = NFLAG_32(res1);
\r
3443 FLAG_Z = MASK_OUT_ABOVE_32(res1);
\r
3444 FLAG_V = VFLAG_SUB_32(*compare1, dest1, res1);
\r
3445 FLAG_C = CFLAG_SUB_32(*compare1, dest1, res1);
\r
3449 res2 = dest2 - *compare2;
\r
3451 FLAG_N = NFLAG_32(res2);
\r
3452 FLAG_Z = MASK_OUT_ABOVE_32(res2);
\r
3453 FLAG_V = VFLAG_SUB_32(*compare2, dest2, res2);
\r
3454 FLAG_C = CFLAG_SUB_32(*compare2, dest2, res2);
\r
3459 m68ki_write_32(ea1, REG_D[(word2 >> 22) & 7]);
\r
3460 m68ki_write_32(ea2, REG_D[(word2 >> 6) & 7]);
\r
3464 *compare1 = dest1;
\r
3465 *compare2 = dest2;
\r
3468 m68ki_exception_illegal();
\r
3472 M68KMAKE_OP(chk, 16, ., d)
\r
3474 sint src = MAKE_INT_16(DX);
\r
3475 sint bound = MAKE_INT_16(DY);
\r
3477 FLAG_Z = ZFLAG_16(src); /* Undocumented */
\r
3478 FLAG_V = VFLAG_CLEAR; /* Undocumented */
\r
3479 FLAG_C = CFLAG_CLEAR; /* Undocumented */
\r
3481 if(src >= 0 && src <= bound)
\r
3485 FLAG_N = (src < 0)<<7;
\r
3486 m68ki_exception_trap(EXCEPTION_CHK);
\r
3490 M68KMAKE_OP(chk, 16, ., .)
\r
3492 sint src = MAKE_INT_16(DX);
\r
3493 sint bound = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
\r
3495 FLAG_Z = ZFLAG_16(src); /* Undocumented */
\r
3496 FLAG_V = VFLAG_CLEAR; /* Undocumented */
\r
3497 FLAG_C = CFLAG_CLEAR; /* Undocumented */
\r
3499 if(src >= 0 && src <= bound)
\r
3503 FLAG_N = (src < 0)<<7;
\r
3504 m68ki_exception_trap(EXCEPTION_CHK);
\r
3508 M68KMAKE_OP(chk, 32, ., d)
\r
3510 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3512 sint src = MAKE_INT_32(DX);
\r
3513 sint bound = MAKE_INT_32(DY);
\r
3515 FLAG_Z = ZFLAG_32(src); /* Undocumented */
\r
3516 FLAG_V = VFLAG_CLEAR; /* Undocumented */
\r
3517 FLAG_C = CFLAG_CLEAR; /* Undocumented */
\r
3519 if(src >= 0 && src <= bound)
\r
3523 FLAG_N = (src < 0)<<7;
\r
3524 m68ki_exception_trap(EXCEPTION_CHK);
\r
3527 m68ki_exception_illegal();
\r
3531 M68KMAKE_OP(chk, 32, ., .)
\r
3533 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3535 sint src = MAKE_INT_32(DX);
\r
3536 sint bound = MAKE_INT_32(M68KMAKE_GET_OPER_AY_32);
\r
3538 FLAG_Z = ZFLAG_32(src); /* Undocumented */
\r
3539 FLAG_V = VFLAG_CLEAR; /* Undocumented */
\r
3540 FLAG_C = CFLAG_CLEAR; /* Undocumented */
\r
3542 if(src >= 0 && src <= bound)
\r
3546 FLAG_N = (src < 0)<<7;
\r
3547 m68ki_exception_trap(EXCEPTION_CHK);
\r
3550 m68ki_exception_illegal();
\r
3554 M68KMAKE_OP(chk2cmp2, 8, ., pcdi)
\r
3556 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3558 uint word2 = OPER_I_16();
\r
3559 uint compare = REG_DA[(word2 >> 12) & 15]&0xff;
\r
3560 uint ea = EA_PCDI_8();
\r
3561 uint lower_bound = m68ki_read_pcrel_8(ea);
\r
3562 uint upper_bound = m68ki_read_pcrel_8(ea + 1);
\r
3565 FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);
\r
3567 FLAG_C = compare - lower_bound;
\r
3568 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3572 m68ki_exception_trap(EXCEPTION_CHK);
\r
3576 FLAG_C = upper_bound - compare;
\r
3577 if(COND_CS() && BIT_B(word2))
\r
3578 m68ki_exception_trap(EXCEPTION_CHK);
\r
3581 m68ki_exception_illegal();
\r
3585 M68KMAKE_OP(chk2cmp2, 8, ., pcix)
\r
3587 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3589 uint word2 = OPER_I_16();
\r
3590 uint compare = REG_DA[(word2 >> 12) & 15]&0xff;
\r
3591 uint ea = EA_PCIX_8();
\r
3592 uint lower_bound = m68ki_read_pcrel_8(ea);
\r
3593 uint upper_bound = m68ki_read_pcrel_8(ea + 1);
\r
3596 FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);
\r
3598 FLAG_C = compare - lower_bound;
\r
3599 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3603 m68ki_exception_trap(EXCEPTION_CHK);
\r
3607 FLAG_C = upper_bound - compare;
\r
3608 if(COND_CS() && BIT_B(word2))
\r
3609 m68ki_exception_trap(EXCEPTION_CHK);
\r
3612 m68ki_exception_illegal();
\r
3616 M68KMAKE_OP(chk2cmp2, 8, ., .)
\r
3618 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3620 uint word2 = OPER_I_16();
\r
3621 uint compare = REG_DA[(word2 >> 12) & 15]&0xff;
\r
3622 uint ea = M68KMAKE_GET_EA_AY_8;
\r
3623 uint lower_bound = m68ki_read_8(ea);
\r
3624 uint upper_bound = m68ki_read_8(ea + 1);
\r
3627 FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);
\r
3629 FLAG_C = compare - lower_bound;
\r
3630 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3634 m68ki_exception_trap(EXCEPTION_CHK);
\r
3638 FLAG_C = upper_bound - compare;
\r
3639 if(COND_CS() && BIT_B(word2))
\r
3640 m68ki_exception_trap(EXCEPTION_CHK);
\r
3643 m68ki_exception_illegal();
\r
3647 M68KMAKE_OP(chk2cmp2, 16, ., pcdi)
\r
3649 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3651 uint word2 = OPER_I_16();
\r
3652 uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;
\r
3653 uint ea = EA_PCDI_16();
\r
3654 uint lower_bound = m68ki_read_pcrel_16(ea);
\r
3655 uint upper_bound = m68ki_read_pcrel_16(ea + 2);
\r
3658 FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);
\r
3660 FLAG_C = compare - lower_bound;
\r
3661 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3662 FLAG_C = CFLAG_16(FLAG_C);
\r
3666 m68ki_exception_trap(EXCEPTION_CHK);
\r
3671 FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);
\r
3673 FLAG_C = upper_bound - compare;
\r
3674 FLAG_C = CFLAG_16(FLAG_C);
\r
3675 if(COND_CS() && BIT_B(word2))
\r
3676 m68ki_exception_trap(EXCEPTION_CHK);
\r
3679 m68ki_exception_illegal();
\r
3683 M68KMAKE_OP(chk2cmp2, 16, ., pcix)
\r
3685 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3687 uint word2 = OPER_I_16();
\r
3688 uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;
\r
3689 uint ea = EA_PCIX_16();
\r
3690 uint lower_bound = m68ki_read_pcrel_16(ea);
\r
3691 uint upper_bound = m68ki_read_pcrel_16(ea + 2);
\r
3694 FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);
\r
3696 FLAG_C = compare - lower_bound;
\r
3697 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3698 FLAG_C = CFLAG_16(FLAG_C);
\r
3702 m68ki_exception_trap(EXCEPTION_CHK);
\r
3707 FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);
\r
3709 FLAG_C = upper_bound - compare;
\r
3710 FLAG_C = CFLAG_16(FLAG_C);
\r
3711 if(COND_CS() && BIT_B(word2))
\r
3712 m68ki_exception_trap(EXCEPTION_CHK);
\r
3715 m68ki_exception_illegal();
\r
3719 M68KMAKE_OP(chk2cmp2, 16, ., .)
\r
3721 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3723 uint word2 = OPER_I_16();
\r
3724 uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;
\r
3725 uint ea = M68KMAKE_GET_EA_AY_16;
\r
3726 uint lower_bound = m68ki_read_16(ea);
\r
3727 uint upper_bound = m68ki_read_16(ea + 2);
\r
3730 FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);
\r
3732 FLAG_C = compare - lower_bound;
\r
3734 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3735 FLAG_C = CFLAG_16(FLAG_C);
\r
3739 m68ki_exception_trap(EXCEPTION_CHK);
\r
3743 FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);
\r
3745 FLAG_C = upper_bound - compare;
\r
3747 FLAG_C = CFLAG_16(FLAG_C);
\r
3748 if(COND_CS() && BIT_B(word2))
\r
3749 m68ki_exception_trap(EXCEPTION_CHK);
\r
3752 m68ki_exception_illegal();
\r
3756 M68KMAKE_OP(chk2cmp2, 32, ., pcdi)
\r
3758 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3760 uint word2 = OPER_I_16();
\r
3761 uint compare = REG_DA[(word2 >> 12) & 15];
\r
3762 uint ea = EA_PCDI_32();
\r
3763 uint lower_bound = m68ki_read_pcrel_32(ea);
\r
3764 uint upper_bound = m68ki_read_pcrel_32(ea + 4);
\r
3766 FLAG_C = compare - lower_bound;
\r
3767 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3768 FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
\r
3772 m68ki_exception_trap(EXCEPTION_CHK);
\r
3776 FLAG_C = upper_bound - compare;
\r
3777 FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
\r
3778 if(COND_CS() && BIT_B(word2))
\r
3779 m68ki_exception_trap(EXCEPTION_CHK);
\r
3782 m68ki_exception_illegal();
\r
3786 M68KMAKE_OP(chk2cmp2, 32, ., pcix)
\r
3788 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3790 uint word2 = OPER_I_16();
\r
3791 uint compare = REG_DA[(word2 >> 12) & 15];
\r
3792 uint ea = EA_PCIX_32();
\r
3793 uint lower_bound = m68ki_read_pcrel_32(ea);
\r
3794 uint upper_bound = m68ki_read_pcrel_32(ea + 4);
\r
3796 FLAG_C = compare - lower_bound;
\r
3797 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3798 FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
\r
3802 m68ki_exception_trap(EXCEPTION_CHK);
\r
3806 FLAG_C = upper_bound - compare;
\r
3807 FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
\r
3808 if(COND_CS() && BIT_B(word2))
\r
3809 m68ki_exception_trap(EXCEPTION_CHK);
\r
3812 m68ki_exception_illegal();
\r
3816 M68KMAKE_OP(chk2cmp2, 32, ., .)
\r
3818 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3820 uint word2 = OPER_I_16();
\r
3821 uint compare = REG_DA[(word2 >> 12) & 15];
\r
3822 uint ea = M68KMAKE_GET_EA_AY_32;
\r
3823 uint lower_bound = m68ki_read_32(ea);
\r
3824 uint upper_bound = m68ki_read_32(ea + 4);
\r
3826 FLAG_C = compare - lower_bound;
\r
3827 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3828 FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
\r
3832 m68ki_exception_trap(EXCEPTION_CHK);
\r
3836 FLAG_C = upper_bound - compare;
\r
3837 FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
\r
3838 if(COND_CS() && BIT_B(word2))
\r
3839 m68ki_exception_trap(EXCEPTION_CHK);
\r
3842 m68ki_exception_illegal();
\r
3846 M68KMAKE_OP(clr, 8, ., d)
\r
3850 FLAG_N = NFLAG_CLEAR;
\r
3851 FLAG_V = VFLAG_CLEAR;
\r
3852 FLAG_C = CFLAG_CLEAR;
\r
3853 FLAG_Z = ZFLAG_SET;
\r
3857 M68KMAKE_OP(clr, 8, ., .)
\r
3859 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);
\r
3861 FLAG_N = NFLAG_CLEAR;
\r
3862 FLAG_V = VFLAG_CLEAR;
\r
3863 FLAG_C = CFLAG_CLEAR;
\r
3864 FLAG_Z = ZFLAG_SET;
\r
3868 M68KMAKE_OP(clr, 16, ., d)
\r
3872 FLAG_N = NFLAG_CLEAR;
\r
3873 FLAG_V = VFLAG_CLEAR;
\r
3874 FLAG_C = CFLAG_CLEAR;
\r
3875 FLAG_Z = ZFLAG_SET;
\r
3879 M68KMAKE_OP(clr, 16, ., .)
\r
3881 m68ki_write_16(M68KMAKE_GET_EA_AY_16, 0);
\r
3883 FLAG_N = NFLAG_CLEAR;
\r
3884 FLAG_V = VFLAG_CLEAR;
\r
3885 FLAG_C = CFLAG_CLEAR;
\r
3886 FLAG_Z = ZFLAG_SET;
\r
3890 M68KMAKE_OP(clr, 32, ., d)
\r
3894 FLAG_N = NFLAG_CLEAR;
\r
3895 FLAG_V = VFLAG_CLEAR;
\r
3896 FLAG_C = CFLAG_CLEAR;
\r
3897 FLAG_Z = ZFLAG_SET;
\r
3901 M68KMAKE_OP(clr, 32, ., .)
\r
3903 m68ki_write_32(M68KMAKE_GET_EA_AY_32, 0);
\r
3905 FLAG_N = NFLAG_CLEAR;
\r
3906 FLAG_V = VFLAG_CLEAR;
\r
3907 FLAG_C = CFLAG_CLEAR;
\r
3908 FLAG_Z = ZFLAG_SET;
\r
3912 M68KMAKE_OP(cmp, 8, ., d)
\r
3914 uint src = MASK_OUT_ABOVE_8(DY);
\r
3915 uint dst = MASK_OUT_ABOVE_8(DX);
\r
3916 uint res = dst - src;
\r
3918 FLAG_N = NFLAG_8(res);
\r
3919 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
3920 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
3921 FLAG_C = CFLAG_8(res);
\r
3925 M68KMAKE_OP(cmp, 8, ., .)
\r
3927 uint src = M68KMAKE_GET_OPER_AY_8;
\r
3928 uint dst = MASK_OUT_ABOVE_8(DX);
\r
3929 uint res = dst - src;
\r
3931 FLAG_N = NFLAG_8(res);
\r
3932 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
3933 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
3934 FLAG_C = CFLAG_8(res);
\r
3938 M68KMAKE_OP(cmp, 16, ., d)
\r
3940 uint src = MASK_OUT_ABOVE_16(DY);
\r
3941 uint dst = MASK_OUT_ABOVE_16(DX);
\r
3942 uint res = dst - src;
\r
3944 FLAG_N = NFLAG_16(res);
\r
3945 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
3946 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
3947 FLAG_C = CFLAG_16(res);
\r
3951 M68KMAKE_OP(cmp, 16, ., a)
\r
3953 uint src = MASK_OUT_ABOVE_16(AY);
\r
3954 uint dst = MASK_OUT_ABOVE_16(DX);
\r
3955 uint res = dst - src;
\r
3957 FLAG_N = NFLAG_16(res);
\r
3958 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
3959 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
3960 FLAG_C = CFLAG_16(res);
\r
3964 M68KMAKE_OP(cmp, 16, ., .)
\r
3966 uint src = M68KMAKE_GET_OPER_AY_16;
\r
3967 uint dst = MASK_OUT_ABOVE_16(DX);
\r
3968 uint res = dst - src;
\r
3970 FLAG_N = NFLAG_16(res);
\r
3971 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
3972 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
3973 FLAG_C = CFLAG_16(res);
\r
3977 M68KMAKE_OP(cmp, 32, ., d)
\r
3981 uint res = dst - src;
\r
3983 FLAG_N = NFLAG_32(res);
\r
3984 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
3985 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
3986 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
3990 M68KMAKE_OP(cmp, 32, ., a)
\r
3994 uint res = dst - src;
\r
3996 FLAG_N = NFLAG_32(res);
\r
3997 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
3998 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
3999 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4003 M68KMAKE_OP(cmp, 32, ., .)
\r
4005 uint src = M68KMAKE_GET_OPER_AY_32;
\r
4007 uint res = dst - src;
\r
4009 FLAG_N = NFLAG_32(res);
\r
4010 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4011 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4012 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4016 M68KMAKE_OP(cmpa, 16, ., d)
\r
4018 uint src = MAKE_INT_16(DY);
\r
4020 uint res = dst - src;
\r
4022 FLAG_N = NFLAG_32(res);
\r
4023 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4024 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4025 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4029 M68KMAKE_OP(cmpa, 16, ., a)
\r
4031 uint src = MAKE_INT_16(AY);
\r
4033 uint res = dst - src;
\r
4035 FLAG_N = NFLAG_32(res);
\r
4036 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4037 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4038 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4042 M68KMAKE_OP(cmpa, 16, ., .)
\r
4044 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
\r
4046 uint res = dst - src;
\r
4048 FLAG_N = NFLAG_32(res);
\r
4049 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4050 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4051 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4055 M68KMAKE_OP(cmpa, 32, ., d)
\r
4059 uint res = dst - src;
\r
4061 FLAG_N = NFLAG_32(res);
\r
4062 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4063 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4064 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4068 M68KMAKE_OP(cmpa, 32, ., a)
\r
4072 uint res = dst - src;
\r
4074 FLAG_N = NFLAG_32(res);
\r
4075 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4076 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4077 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4081 M68KMAKE_OP(cmpa, 32, ., .)
\r
4083 uint src = M68KMAKE_GET_OPER_AY_32;
\r
4085 uint res = dst - src;
\r
4087 FLAG_N = NFLAG_32(res);
\r
4088 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4089 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4090 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4094 M68KMAKE_OP(cmpi, 8, ., d)
\r
4096 uint src = OPER_I_8();
\r
4097 uint dst = MASK_OUT_ABOVE_8(DY);
\r
4098 uint res = dst - src;
\r
4100 FLAG_N = NFLAG_8(res);
\r
4101 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4102 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4103 FLAG_C = CFLAG_8(res);
\r
4107 M68KMAKE_OP(cmpi, 8, ., .)
\r
4109 uint src = OPER_I_8();
\r
4110 uint dst = M68KMAKE_GET_OPER_AY_8;
\r
4111 uint res = dst - src;
\r
4113 FLAG_N = NFLAG_8(res);
\r
4114 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4115 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4116 FLAG_C = CFLAG_8(res);
\r
4120 M68KMAKE_OP(cmpi, 8, ., pcdi)
\r
4122 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4124 uint src = OPER_I_8();
\r
4125 uint dst = OPER_PCDI_8();
\r
4126 uint res = dst - src;
\r
4128 FLAG_N = NFLAG_8(res);
\r
4129 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4130 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4131 FLAG_C = CFLAG_8(res);
\r
4134 m68ki_exception_illegal();
\r
4138 M68KMAKE_OP(cmpi, 8, ., pcix)
\r
4140 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4142 uint src = OPER_I_8();
\r
4143 uint dst = OPER_PCIX_8();
\r
4144 uint res = dst - src;
\r
4146 FLAG_N = NFLAG_8(res);
\r
4147 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4148 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4149 FLAG_C = CFLAG_8(res);
\r
4152 m68ki_exception_illegal();
\r
4156 M68KMAKE_OP(cmpi, 16, ., d)
\r
4158 uint src = OPER_I_16();
\r
4159 uint dst = MASK_OUT_ABOVE_16(DY);
\r
4160 uint res = dst - src;
\r
4162 FLAG_N = NFLAG_16(res);
\r
4163 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
4164 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
4165 FLAG_C = CFLAG_16(res);
\r
4169 M68KMAKE_OP(cmpi, 16, ., .)
\r
4171 uint src = OPER_I_16();
\r
4172 uint dst = M68KMAKE_GET_OPER_AY_16;
\r
4173 uint res = dst - src;
\r
4175 FLAG_N = NFLAG_16(res);
\r
4176 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
4177 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
4178 FLAG_C = CFLAG_16(res);
\r
4182 M68KMAKE_OP(cmpi, 16, ., pcdi)
\r
4184 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4186 uint src = OPER_I_16();
\r
4187 uint dst = OPER_PCDI_16();
\r
4188 uint res = dst - src;
\r
4190 FLAG_N = NFLAG_16(res);
\r
4191 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
4192 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
4193 FLAG_C = CFLAG_16(res);
\r
4196 m68ki_exception_illegal();
\r
4200 M68KMAKE_OP(cmpi, 16, ., pcix)
\r
4202 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4204 uint src = OPER_I_16();
\r
4205 uint dst = OPER_PCIX_16();
\r
4206 uint res = dst - src;
\r
4208 FLAG_N = NFLAG_16(res);
\r
4209 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
4210 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
4211 FLAG_C = CFLAG_16(res);
\r
4214 m68ki_exception_illegal();
\r
4218 M68KMAKE_OP(cmpi, 32, ., d)
\r
4220 uint src = OPER_I_32();
\r
4222 uint res = dst - src;
\r
4224 m68ki_cmpild_callback(src, REG_IR & 7); /* auto-disable (see m68kcpu.h) */
\r
4226 FLAG_N = NFLAG_32(res);
\r
4227 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4228 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4229 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4233 M68KMAKE_OP(cmpi, 32, ., .)
\r
4235 uint src = OPER_I_32();
\r
4236 uint dst = M68KMAKE_GET_OPER_AY_32;
\r
4237 uint res = dst - src;
\r
4239 FLAG_N = NFLAG_32(res);
\r
4240 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4241 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4242 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4246 M68KMAKE_OP(cmpi, 32, ., pcdi)
\r
4248 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4250 uint src = OPER_I_32();
\r
4251 uint dst = OPER_PCDI_32();
\r
4252 uint res = dst - src;
\r
4254 FLAG_N = NFLAG_32(res);
\r
4255 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4256 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4257 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4260 m68ki_exception_illegal();
\r
4264 M68KMAKE_OP(cmpi, 32, ., pcix)
\r
4266 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4268 uint src = OPER_I_32();
\r
4269 uint dst = OPER_PCIX_32();
\r
4270 uint res = dst - src;
\r
4272 FLAG_N = NFLAG_32(res);
\r
4273 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4274 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4275 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4278 m68ki_exception_illegal();
\r
4282 M68KMAKE_OP(cmpm, 8, ., ax7)
\r
4284 uint src = OPER_AY_PI_8();
\r
4285 uint dst = OPER_A7_PI_8();
\r
4286 uint res = dst - src;
\r
4288 FLAG_N = NFLAG_8(res);
\r
4289 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4290 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4291 FLAG_C = CFLAG_8(res);
\r
4295 M68KMAKE_OP(cmpm, 8, ., ay7)
\r
4297 uint src = OPER_A7_PI_8();
\r
4298 uint dst = OPER_AX_PI_8();
\r
4299 uint res = dst - src;
\r
4301 FLAG_N = NFLAG_8(res);
\r
4302 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4303 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4304 FLAG_C = CFLAG_8(res);
\r
4308 M68KMAKE_OP(cmpm, 8, ., axy7)
\r
4310 uint src = OPER_A7_PI_8();
\r
4311 uint dst = OPER_A7_PI_8();
\r
4312 uint res = dst - src;
\r
4314 FLAG_N = NFLAG_8(res);
\r
4315 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4316 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4317 FLAG_C = CFLAG_8(res);
\r
4321 M68KMAKE_OP(cmpm, 8, ., .)
\r
4323 uint src = OPER_AY_PI_8();
\r
4324 uint dst = OPER_AX_PI_8();
\r
4325 uint res = dst - src;
\r
4327 FLAG_N = NFLAG_8(res);
\r
4328 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4329 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4330 FLAG_C = CFLAG_8(res);
\r
4334 M68KMAKE_OP(cmpm, 16, ., .)
\r
4336 uint src = OPER_AY_PI_16();
\r
4337 uint dst = OPER_AX_PI_16();
\r
4338 uint res = dst - src;
\r
4340 FLAG_N = NFLAG_16(res);
\r
4341 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
4342 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
4343 FLAG_C = CFLAG_16(res);
\r
4347 M68KMAKE_OP(cmpm, 32, ., .)
\r
4349 uint src = OPER_AY_PI_32();
\r
4350 uint dst = OPER_AX_PI_32();
\r
4351 uint res = dst - src;
\r
4353 FLAG_N = NFLAG_32(res);
\r
4354 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4355 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4356 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4360 M68KMAKE_OP(cpbcc, 32, ., .)
\r
4362 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4364 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
4365 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
4366 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
4369 m68ki_exception_1111();
\r
4373 M68KMAKE_OP(cpdbcc, 32, ., .)
\r
4375 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4377 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
4378 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
4379 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
4382 m68ki_exception_1111();
\r
4386 M68KMAKE_OP(cpgen, 32, ., .)
\r
4388 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4390 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
4391 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
4392 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
4395 m68ki_exception_1111();
\r
4399 M68KMAKE_OP(cpscc, 32, ., .)
\r
4401 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4403 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
4404 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
4405 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
4408 m68ki_exception_1111();
\r
4412 M68KMAKE_OP(cptrapcc, 32, ., .)
\r
4414 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4416 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
4417 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
4418 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
4421 m68ki_exception_1111();
\r
4425 M68KMAKE_OP(dbt, 16, ., .)
\r
4431 M68KMAKE_OP(dbf, 16, ., .)
\r
4433 uint* r_dst = &DY;
\r
4434 uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
\r
4436 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
4439 uint offset = OPER_I_16();
\r
4441 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
4442 m68ki_branch_16(offset);
\r
4443 USE_CYCLES(CYC_DBCC_F_NOEXP);
\r
4447 USE_CYCLES(CYC_DBCC_F_EXP);
\r
4451 M68KMAKE_OP(dbcc, 16, ., .)
\r
4453 if(M68KMAKE_NOT_CC)
\r
4455 uint* r_dst = &DY;
\r
4456 uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
\r
4458 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
4461 uint offset = OPER_I_16();
\r
4463 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
4464 m68ki_branch_16(offset);
\r
4465 USE_CYCLES(CYC_DBCC_F_NOEXP);
\r
4469 USE_CYCLES(CYC_DBCC_F_EXP);
\r
4476 M68KMAKE_OP(divs, 16, ., d)
\r
4478 uint* r_dst = &DX;
\r
4479 sint src = MAKE_INT_16(DY);
\r
4485 if((uint32)*r_dst == 0x80000000 && src == -1)
\r
4488 FLAG_N = NFLAG_CLEAR;
\r
4489 FLAG_V = VFLAG_CLEAR;
\r
4490 FLAG_C = CFLAG_CLEAR;
\r
4495 quotient = MAKE_INT_32(*r_dst) / src;
\r
4496 remainder = MAKE_INT_32(*r_dst) % src;
\r
4498 if(quotient == MAKE_INT_16(quotient))
\r
4500 FLAG_Z = quotient;
\r
4501 FLAG_N = NFLAG_16(quotient);
\r
4502 FLAG_V = VFLAG_CLEAR;
\r
4503 FLAG_C = CFLAG_CLEAR;
\r
4504 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
\r
4507 FLAG_V = VFLAG_SET;
\r
4510 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4514 M68KMAKE_OP(divs, 16, ., .)
\r
4516 uint* r_dst = &DX;
\r
4517 sint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
\r
4523 if((uint32)*r_dst == 0x80000000 && src == -1)
\r
4526 FLAG_N = NFLAG_CLEAR;
\r
4527 FLAG_V = VFLAG_CLEAR;
\r
4528 FLAG_C = CFLAG_CLEAR;
\r
4533 quotient = MAKE_INT_32(*r_dst) / src;
\r
4534 remainder = MAKE_INT_32(*r_dst) % src;
\r
4536 if(quotient == MAKE_INT_16(quotient))
\r
4538 FLAG_Z = quotient;
\r
4539 FLAG_N = NFLAG_16(quotient);
\r
4540 FLAG_V = VFLAG_CLEAR;
\r
4541 FLAG_C = CFLAG_CLEAR;
\r
4542 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
\r
4545 FLAG_V = VFLAG_SET;
\r
4548 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4552 M68KMAKE_OP(divu, 16, ., d)
\r
4554 uint* r_dst = &DX;
\r
4555 uint src = MASK_OUT_ABOVE_16(DY);
\r
4559 uint quotient = *r_dst / src;
\r
4560 uint remainder = *r_dst % src;
\r
4562 if(quotient < 0x10000)
\r
4564 FLAG_Z = quotient;
\r
4565 FLAG_N = NFLAG_16(quotient);
\r
4566 FLAG_V = VFLAG_CLEAR;
\r
4567 FLAG_C = CFLAG_CLEAR;
\r
4568 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
\r
4571 FLAG_V = VFLAG_SET;
\r
4574 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4578 M68KMAKE_OP(divu, 16, ., .)
\r
4580 uint* r_dst = &DX;
\r
4581 uint src = M68KMAKE_GET_OPER_AY_16;
\r
4585 uint quotient = *r_dst / src;
\r
4586 uint remainder = *r_dst % src;
\r
4588 if(quotient < 0x10000)
\r
4590 FLAG_Z = quotient;
\r
4591 FLAG_N = NFLAG_16(quotient);
\r
4592 FLAG_V = VFLAG_CLEAR;
\r
4593 FLAG_C = CFLAG_CLEAR;
\r
4594 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
\r
4597 FLAG_V = VFLAG_SET;
\r
4600 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4604 M68KMAKE_OP(divl, 32, ., d)
\r
4606 #if M68K_USE_64_BIT
\r
4608 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4610 uint word2 = OPER_I_16();
\r
4611 uint64 divisor = DY;
\r
4612 uint64 dividend = 0;
\r
4613 uint64 quotient = 0;
\r
4614 uint64 remainder = 0;
\r
4618 if(BIT_A(word2)) /* 64 bit */
\r
4620 dividend = REG_D[word2 & 7];
\r
4622 dividend |= REG_D[(word2 >> 12) & 7];
\r
4624 if(BIT_B(word2)) /* signed */
\r
4626 quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
\r
4627 remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
\r
4628 if((sint64)quotient != (sint64)((sint32)quotient))
\r
4630 FLAG_V = VFLAG_SET;
\r
4634 else /* unsigned */
\r
4636 quotient = dividend / divisor;
\r
4637 if(quotient > 0xffffffff)
\r
4639 FLAG_V = VFLAG_SET;
\r
4642 remainder = dividend % divisor;
\r
4647 dividend = REG_D[(word2 >> 12) & 7];
\r
4648 if(BIT_B(word2)) /* signed */
\r
4650 quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
\r
4651 remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
\r
4653 else /* unsigned */
\r
4655 quotient = dividend / divisor;
\r
4656 remainder = dividend % divisor;
\r
4660 REG_D[word2 & 7] = remainder;
\r
4661 REG_D[(word2 >> 12) & 7] = quotient;
\r
4663 FLAG_N = NFLAG_32(quotient);
\r
4664 FLAG_Z = quotient;
\r
4665 FLAG_V = VFLAG_CLEAR;
\r
4666 FLAG_C = CFLAG_CLEAR;
\r
4669 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4672 m68ki_exception_illegal();
\r
4676 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4678 uint word2 = OPER_I_16();
\r
4679 uint divisor = DY;
\r
4680 uint dividend_hi = REG_D[word2 & 7];
\r
4681 uint dividend_lo = REG_D[(word2 >> 12) & 7];
\r
4682 uint quotient = 0;
\r
4683 uint remainder = 0;
\r
4684 uint dividend_neg = 0;
\r
4685 uint divisor_neg = 0;
\r
4691 /* quad / long : long quotient, long remainder */
\r
4694 if(BIT_B(word2)) /* signed */
\r
4696 /* special case in signed divide */
\r
4697 if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
\r
4699 REG_D[word2 & 7] = 0;
\r
4700 REG_D[(word2 >> 12) & 7] = 0x80000000;
\r
4702 FLAG_N = NFLAG_SET;
\r
4703 FLAG_Z = ZFLAG_CLEAR;
\r
4704 FLAG_V = VFLAG_CLEAR;
\r
4705 FLAG_C = CFLAG_CLEAR;
\r
4708 if(GET_MSB_32(dividend_hi))
\r
4711 dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
\r
4712 dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
\r
4714 if(GET_MSB_32(divisor))
\r
4717 divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
\r
4722 /* if the upper long is greater than the divisor, we're overflowing. */
\r
4723 if(dividend_hi >= divisor)
\r
4725 FLAG_V = VFLAG_SET;
\r
4729 for(i = 31; i >= 0; i--)
\r
4732 remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
\r
4733 if(remainder >= divisor)
\r
4735 remainder -= divisor;
\r
4739 for(i = 31; i >= 0; i--)
\r
4742 overflow = GET_MSB_32(remainder);
\r
4743 remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
\r
4744 if(remainder >= divisor || overflow)
\r
4746 remainder -= divisor;
\r
4751 if(BIT_B(word2)) /* signed */
\r
4753 if(quotient > 0x7fffffff)
\r
4755 FLAG_V = VFLAG_SET;
\r
4760 remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
\r
4761 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
\r
4764 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
\r
4767 REG_D[word2 & 7] = remainder;
\r
4768 REG_D[(word2 >> 12) & 7] = quotient;
\r
4770 FLAG_N = NFLAG_32(quotient);
\r
4771 FLAG_Z = quotient;
\r
4772 FLAG_V = VFLAG_CLEAR;
\r
4773 FLAG_C = CFLAG_CLEAR;
\r
4777 /* long / long: long quotient, maybe long remainder */
\r
4778 if(BIT_B(word2)) /* signed */
\r
4780 /* Special case in divide */
\r
4781 if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
\r
4783 FLAG_N = NFLAG_SET;
\r
4784 FLAG_Z = ZFLAG_CLEAR;
\r
4785 FLAG_V = VFLAG_CLEAR;
\r
4786 FLAG_C = CFLAG_CLEAR;
\r
4787 REG_D[(word2 >> 12) & 7] = 0x80000000;
\r
4788 REG_D[word2 & 7] = 0;
\r
4791 REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
\r
4792 quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
\r
4796 REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
\r
4797 quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
\r
4800 FLAG_N = NFLAG_32(quotient);
\r
4801 FLAG_Z = quotient;
\r
4802 FLAG_V = VFLAG_CLEAR;
\r
4803 FLAG_C = CFLAG_CLEAR;
\r
4806 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4809 m68ki_exception_illegal();
\r
4815 M68KMAKE_OP(divl, 32, ., .)
\r
4817 #if M68K_USE_64_BIT
\r
4819 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4821 uint word2 = OPER_I_16();
\r
4822 uint64 divisor = M68KMAKE_GET_OPER_AY_32;
\r
4823 uint64 dividend = 0;
\r
4824 uint64 quotient = 0;
\r
4825 uint64 remainder = 0;
\r
4829 if(BIT_A(word2)) /* 64 bit */
\r
4831 dividend = REG_D[word2 & 7];
\r
4833 dividend |= REG_D[(word2 >> 12) & 7];
\r
4835 if(BIT_B(word2)) /* signed */
\r
4837 quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
\r
4838 remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
\r
4839 if((sint64)quotient != (sint64)((sint32)quotient))
\r
4841 FLAG_V = VFLAG_SET;
\r
4845 else /* unsigned */
\r
4847 quotient = dividend / divisor;
\r
4848 if(quotient > 0xffffffff)
\r
4850 FLAG_V = VFLAG_SET;
\r
4853 remainder = dividend % divisor;
\r
4858 dividend = REG_D[(word2 >> 12) & 7];
\r
4859 if(BIT_B(word2)) /* signed */
\r
4861 quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
\r
4862 remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
\r
4864 else /* unsigned */
\r
4866 quotient = dividend / divisor;
\r
4867 remainder = dividend % divisor;
\r
4871 REG_D[word2 & 7] = remainder;
\r
4872 REG_D[(word2 >> 12) & 7] = quotient;
\r
4874 FLAG_N = NFLAG_32(quotient);
\r
4875 FLAG_Z = quotient;
\r
4876 FLAG_V = VFLAG_CLEAR;
\r
4877 FLAG_C = CFLAG_CLEAR;
\r
4880 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4883 m68ki_exception_illegal();
\r
4887 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4889 uint word2 = OPER_I_16();
\r
4890 uint divisor = M68KMAKE_GET_OPER_AY_32;
\r
4891 uint dividend_hi = REG_D[word2 & 7];
\r
4892 uint dividend_lo = REG_D[(word2 >> 12) & 7];
\r
4893 uint quotient = 0;
\r
4894 uint remainder = 0;
\r
4895 uint dividend_neg = 0;
\r
4896 uint divisor_neg = 0;
\r
4902 /* quad / long : long quotient, long remainder */
\r
4905 if(BIT_B(word2)) /* signed */
\r
4907 /* special case in signed divide */
\r
4908 if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
\r
4910 REG_D[word2 & 7] = 0;
\r
4911 REG_D[(word2 >> 12) & 7] = 0x80000000;
\r
4913 FLAG_N = NFLAG_SET;
\r
4914 FLAG_Z = ZFLAG_CLEAR;
\r
4915 FLAG_V = VFLAG_CLEAR;
\r
4916 FLAG_C = CFLAG_CLEAR;
\r
4919 if(GET_MSB_32(dividend_hi))
\r
4922 dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
\r
4923 dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
\r
4925 if(GET_MSB_32(divisor))
\r
4928 divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
\r
4933 /* if the upper long is greater than the divisor, we're overflowing. */
\r
4934 if(dividend_hi >= divisor)
\r
4936 FLAG_V = VFLAG_SET;
\r
4940 for(i = 31; i >= 0; i--)
\r
4943 remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
\r
4944 if(remainder >= divisor)
\r
4946 remainder -= divisor;
\r
4950 for(i = 31; i >= 0; i--)
\r
4953 overflow = GET_MSB_32(remainder);
\r
4954 remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
\r
4955 if(remainder >= divisor || overflow)
\r
4957 remainder -= divisor;
\r
4962 if(BIT_B(word2)) /* signed */
\r
4964 if(quotient > 0x7fffffff)
\r
4966 FLAG_V = VFLAG_SET;
\r
4971 remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
\r
4972 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
\r
4975 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
\r
4978 REG_D[word2 & 7] = remainder;
\r
4979 REG_D[(word2 >> 12) & 7] = quotient;
\r
4981 FLAG_N = NFLAG_32(quotient);
\r
4982 FLAG_Z = quotient;
\r
4983 FLAG_V = VFLAG_CLEAR;
\r
4984 FLAG_C = CFLAG_CLEAR;
\r
4988 /* long / long: long quotient, maybe long remainder */
\r
4989 if(BIT_B(word2)) /* signed */
\r
4991 /* Special case in divide */
\r
4992 if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
\r
4994 FLAG_N = NFLAG_SET;
\r
4995 FLAG_Z = ZFLAG_CLEAR;
\r
4996 FLAG_V = VFLAG_CLEAR;
\r
4997 FLAG_C = CFLAG_CLEAR;
\r
4998 REG_D[(word2 >> 12) & 7] = 0x80000000;
\r
4999 REG_D[word2 & 7] = 0;
\r
5002 REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
\r
5003 quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
\r
5007 REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
\r
5008 quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
\r
5011 FLAG_N = NFLAG_32(quotient);
\r
5012 FLAG_Z = quotient;
\r
5013 FLAG_V = VFLAG_CLEAR;
\r
5014 FLAG_C = CFLAG_CLEAR;
\r
5017 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
5020 m68ki_exception_illegal();
\r
5026 M68KMAKE_OP(eor, 8, ., d)
\r
5028 uint res = MASK_OUT_ABOVE_8(DY ^= MASK_OUT_ABOVE_8(DX));
\r
5030 FLAG_N = NFLAG_8(res);
\r
5032 FLAG_C = CFLAG_CLEAR;
\r
5033 FLAG_V = VFLAG_CLEAR;
\r
5037 M68KMAKE_OP(eor, 8, ., .)
\r
5039 uint ea = M68KMAKE_GET_EA_AY_8;
\r
5040 uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
\r
5042 m68ki_write_8(ea, res);
\r
5044 FLAG_N = NFLAG_8(res);
\r
5046 FLAG_C = CFLAG_CLEAR;
\r
5047 FLAG_V = VFLAG_CLEAR;
\r
5051 M68KMAKE_OP(eor, 16, ., d)
\r
5053 uint res = MASK_OUT_ABOVE_16(DY ^= MASK_OUT_ABOVE_16(DX));
\r
5055 FLAG_N = NFLAG_16(res);
\r
5057 FLAG_C = CFLAG_CLEAR;
\r
5058 FLAG_V = VFLAG_CLEAR;
\r
5062 M68KMAKE_OP(eor, 16, ., .)
\r
5064 uint ea = M68KMAKE_GET_EA_AY_16;
\r
5065 uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
\r
5067 m68ki_write_16(ea, res);
\r
5069 FLAG_N = NFLAG_16(res);
\r
5071 FLAG_C = CFLAG_CLEAR;
\r
5072 FLAG_V = VFLAG_CLEAR;
\r
5076 M68KMAKE_OP(eor, 32, ., d)
\r
5078 uint res = DY ^= DX;
\r
5080 FLAG_N = NFLAG_32(res);
\r
5082 FLAG_C = CFLAG_CLEAR;
\r
5083 FLAG_V = VFLAG_CLEAR;
\r
5087 M68KMAKE_OP(eor, 32, ., .)
\r
5089 uint ea = M68KMAKE_GET_EA_AY_32;
\r
5090 uint res = DX ^ m68ki_read_32(ea);
\r
5092 m68ki_write_32(ea, res);
\r
5094 FLAG_N = NFLAG_32(res);
\r
5096 FLAG_C = CFLAG_CLEAR;
\r
5097 FLAG_V = VFLAG_CLEAR;
\r
5101 M68KMAKE_OP(eori, 8, ., d)
\r
5103 uint res = MASK_OUT_ABOVE_8(DY ^= OPER_I_8());
\r
5105 FLAG_N = NFLAG_8(res);
\r
5107 FLAG_C = CFLAG_CLEAR;
\r
5108 FLAG_V = VFLAG_CLEAR;
\r
5112 M68KMAKE_OP(eori, 8, ., .)
\r
5114 uint src = OPER_I_8();
\r
5115 uint ea = M68KMAKE_GET_EA_AY_8;
\r
5116 uint res = src ^ m68ki_read_8(ea);
\r
5118 m68ki_write_8(ea, res);
\r
5120 FLAG_N = NFLAG_8(res);
\r
5122 FLAG_C = CFLAG_CLEAR;
\r
5123 FLAG_V = VFLAG_CLEAR;
\r
5127 M68KMAKE_OP(eori, 16, ., d)
\r
5129 uint res = MASK_OUT_ABOVE_16(DY ^= OPER_I_16());
\r
5131 FLAG_N = NFLAG_16(res);
\r
5133 FLAG_C = CFLAG_CLEAR;
\r
5134 FLAG_V = VFLAG_CLEAR;
\r
5138 M68KMAKE_OP(eori, 16, ., .)
\r
5140 uint src = OPER_I_16();
\r
5141 uint ea = M68KMAKE_GET_EA_AY_16;
\r
5142 uint res = src ^ m68ki_read_16(ea);
\r
5144 m68ki_write_16(ea, res);
\r
5146 FLAG_N = NFLAG_16(res);
\r
5148 FLAG_C = CFLAG_CLEAR;
\r
5149 FLAG_V = VFLAG_CLEAR;
\r
5153 M68KMAKE_OP(eori, 32, ., d)
\r
5155 uint res = DY ^= OPER_I_32();
\r
5157 FLAG_N = NFLAG_32(res);
\r
5159 FLAG_C = CFLAG_CLEAR;
\r
5160 FLAG_V = VFLAG_CLEAR;
\r
5164 M68KMAKE_OP(eori, 32, ., .)
\r
5166 uint src = OPER_I_32();
\r
5167 uint ea = M68KMAKE_GET_EA_AY_32;
\r
5168 uint res = src ^ m68ki_read_32(ea);
\r
5170 m68ki_write_32(ea, res);
\r
5172 FLAG_N = NFLAG_32(res);
\r
5174 FLAG_C = CFLAG_CLEAR;
\r
5175 FLAG_V = VFLAG_CLEAR;
\r
5179 M68KMAKE_OP(eori, 16, toc, .)
\r
5181 m68ki_set_ccr(m68ki_get_ccr() ^ OPER_I_16());
\r
5185 M68KMAKE_OP(eori, 16, tos, .)
\r
5189 uint src = OPER_I_16();
\r
5190 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
5191 m68ki_set_sr(m68ki_get_sr() ^ src);
\r
5194 m68ki_exception_privilege_violation();
\r
5198 M68KMAKE_OP(exg, 32, dd, .)
\r
5200 uint* reg_a = &DX;
\r
5201 uint* reg_b = &DY;
\r
5202 uint tmp = *reg_a;
\r
5208 M68KMAKE_OP(exg, 32, aa, .)
\r
5210 uint* reg_a = &AX;
\r
5211 uint* reg_b = &AY;
\r
5212 uint tmp = *reg_a;
\r
5218 M68KMAKE_OP(exg, 32, da, .)
\r
5220 uint* reg_a = &DX;
\r
5221 uint* reg_b = &AY;
\r
5222 uint tmp = *reg_a;
\r
5228 M68KMAKE_OP(ext, 16, ., .)
\r
5230 uint* r_dst = &DY;
\r
5232 *r_dst = MASK_OUT_BELOW_16(*r_dst) | MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xff00 : 0);
\r
5234 FLAG_N = NFLAG_16(*r_dst);
\r
5235 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
\r
5236 FLAG_V = VFLAG_CLEAR;
\r
5237 FLAG_C = CFLAG_CLEAR;
\r
5241 M68KMAKE_OP(ext, 32, ., .)
\r
5243 uint* r_dst = &DY;
\r
5245 *r_dst = MASK_OUT_ABOVE_16(*r_dst) | (GET_MSB_16(*r_dst) ? 0xffff0000 : 0);
\r
5247 FLAG_N = NFLAG_32(*r_dst);
\r
5249 FLAG_V = VFLAG_CLEAR;
\r
5250 FLAG_C = CFLAG_CLEAR;
\r
5254 M68KMAKE_OP(extb, 32, ., .)
\r
5256 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
5258 uint* r_dst = &DY;
\r
5260 *r_dst = MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xffffff00 : 0);
\r
5262 FLAG_N = NFLAG_32(*r_dst);
\r
5264 FLAG_V = VFLAG_CLEAR;
\r
5265 FLAG_C = CFLAG_CLEAR;
\r
5268 m68ki_exception_illegal();
\r
5272 M68KMAKE_OP(illegal, 0, ., .)
\r
5274 m68ki_exception_illegal();
\r
5277 M68KMAKE_OP(jmp, 32, ., .)
\r
5279 m68ki_jump(M68KMAKE_GET_EA_AY_32);
\r
5280 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
5281 if(REG_PC == REG_PPC)
\r
5286 M68KMAKE_OP(jsr, 32, ., .)
\r
5288 uint ea = M68KMAKE_GET_EA_AY_32;
\r
5289 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
5290 m68ki_push_32(REG_PC);
\r
5295 M68KMAKE_OP(lea, 32, ., .)
\r
5297 AX = M68KMAKE_GET_EA_AY_32;
\r
5301 M68KMAKE_OP(link, 16, ., a7)
\r
5304 m68ki_write_32(REG_A[7], REG_A[7]);
\r
5305 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
\r
5309 M68KMAKE_OP(link, 16, ., .)
\r
5311 uint* r_dst = &AY;
\r
5313 m68ki_push_32(*r_dst);
\r
5314 *r_dst = REG_A[7];
\r
5315 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
\r
5319 M68KMAKE_OP(link, 32, ., a7)
\r
5321 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
5324 m68ki_write_32(REG_A[7], REG_A[7]);
\r
5325 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());
\r
5328 m68ki_exception_illegal();
\r
5332 M68KMAKE_OP(link, 32, ., .)
\r
5334 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
5336 uint* r_dst = &AY;
\r
5338 m68ki_push_32(*r_dst);
\r
5339 *r_dst = REG_A[7];
\r
5340 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());
\r
5343 m68ki_exception_illegal();
\r
5347 M68KMAKE_OP(lsr, 8, s, .)
\r
5349 uint* r_dst = &DY;
\r
5350 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
5351 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
5352 uint res = src >> shift;
\r
5355 USE_CYCLES(shift<<CYC_SHIFT);
\r
5357 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
5359 FLAG_N = NFLAG_CLEAR;
\r
5361 FLAG_X = FLAG_C = src << (9-shift);
\r
5362 FLAG_V = VFLAG_CLEAR;
\r
5366 M68KMAKE_OP(lsr, 16, s, .)
\r
5368 uint* r_dst = &DY;
\r
5369 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
5370 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
5371 uint res = src >> shift;
\r
5374 USE_CYCLES(shift<<CYC_SHIFT);
\r
5376 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
5378 FLAG_N = NFLAG_CLEAR;
\r
5380 FLAG_X = FLAG_C = src << (9-shift);
\r
5381 FLAG_V = VFLAG_CLEAR;
\r
5385 M68KMAKE_OP(lsr, 32, s, .)
\r
5387 uint* r_dst = &DY;
\r
5388 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
5389 uint src = *r_dst;
\r
5390 uint res = src >> shift;
\r
5393 USE_CYCLES(shift<<CYC_SHIFT);
\r
5397 FLAG_N = NFLAG_CLEAR;
\r
5399 FLAG_X = FLAG_C = src << (9-shift);
\r
5400 FLAG_V = VFLAG_CLEAR;
\r
5404 M68KMAKE_OP(lsr, 8, r, .)
\r
5406 uint* r_dst = &DY;
\r
5407 uint shift = DX & 0x3f;
\r
5408 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
5409 uint res = src >> shift;
\r
5413 USE_CYCLES(shift<<CYC_SHIFT);
\r
5417 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
5418 FLAG_X = FLAG_C = src << (9-shift);
\r
5419 FLAG_N = NFLAG_CLEAR;
\r
5421 FLAG_V = VFLAG_CLEAR;
\r
5425 *r_dst &= 0xffffff00;
\r
5426 FLAG_X = XFLAG_CLEAR;
\r
5427 FLAG_C = CFLAG_CLEAR;
\r
5428 FLAG_N = NFLAG_CLEAR;
\r
5429 FLAG_Z = ZFLAG_SET;
\r
5430 FLAG_V = VFLAG_CLEAR;
\r
5434 FLAG_C = CFLAG_CLEAR;
\r
5435 FLAG_N = NFLAG_8(src);
\r
5437 FLAG_V = VFLAG_CLEAR;
\r
5441 M68KMAKE_OP(lsr, 16, r, .)
\r
5443 uint* r_dst = &DY;
\r
5444 uint shift = DX & 0x3f;
\r
5445 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
5446 uint res = src >> shift;
\r
5450 USE_CYCLES(shift<<CYC_SHIFT);
\r
5454 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
5455 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
\r
5456 FLAG_N = NFLAG_CLEAR;
\r
5458 FLAG_V = VFLAG_CLEAR;
\r
5462 *r_dst &= 0xffff0000;
\r
5463 FLAG_X = XFLAG_CLEAR;
\r
5464 FLAG_C = CFLAG_CLEAR;
\r
5465 FLAG_N = NFLAG_CLEAR;
\r
5466 FLAG_Z = ZFLAG_SET;
\r
5467 FLAG_V = VFLAG_CLEAR;
\r
5471 FLAG_C = CFLAG_CLEAR;
\r
5472 FLAG_N = NFLAG_16(src);
\r
5474 FLAG_V = VFLAG_CLEAR;
\r
5478 M68KMAKE_OP(lsr, 32, r, .)
\r
5480 uint* r_dst = &DY;
\r
5481 uint shift = DX & 0x3f;
\r
5482 uint src = *r_dst;
\r
5483 uint res = src >> shift;
\r
5487 USE_CYCLES(shift<<CYC_SHIFT);
\r
5492 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
\r
5493 FLAG_N = NFLAG_CLEAR;
\r
5495 FLAG_V = VFLAG_CLEAR;
\r
5500 FLAG_X = FLAG_C = (shift == 32 ? GET_MSB_32(src)>>23 : 0);
\r
5501 FLAG_N = NFLAG_CLEAR;
\r
5502 FLAG_Z = ZFLAG_SET;
\r
5503 FLAG_V = VFLAG_CLEAR;
\r
5507 FLAG_C = CFLAG_CLEAR;
\r
5508 FLAG_N = NFLAG_32(src);
\r
5510 FLAG_V = VFLAG_CLEAR;
\r
5514 M68KMAKE_OP(lsr, 16, ., .)
\r
5516 uint ea = M68KMAKE_GET_EA_AY_16;
\r
5517 uint src = m68ki_read_16(ea);
\r
5518 uint res = src >> 1;
\r
5520 m68ki_write_16(ea, res);
\r
5522 FLAG_N = NFLAG_CLEAR;
\r
5524 FLAG_C = FLAG_X = src << 8;
\r
5525 FLAG_V = VFLAG_CLEAR;
\r
5529 M68KMAKE_OP(lsl, 8, s, .)
\r
5531 uint* r_dst = &DY;
\r
5532 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
5533 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
5534 uint res = MASK_OUT_ABOVE_8(src << shift);
\r
5537 USE_CYCLES(shift<<CYC_SHIFT);
\r
5539 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
5541 FLAG_N = NFLAG_8(res);
\r
5543 FLAG_X = FLAG_C = src << shift;
\r
5544 FLAG_V = VFLAG_CLEAR;
\r
5548 M68KMAKE_OP(lsl, 16, s, .)
\r
5550 uint* r_dst = &DY;
\r
5551 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
5552 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
5553 uint res = MASK_OUT_ABOVE_16(src << shift);
\r
5556 USE_CYCLES(shift<<CYC_SHIFT);
\r
5558 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
5560 FLAG_N = NFLAG_16(res);
\r
5562 FLAG_X = FLAG_C = src >> (8-shift);
\r
5563 FLAG_V = VFLAG_CLEAR;
\r
5567 M68KMAKE_OP(lsl, 32, s, .)
\r
5569 uint* r_dst = &DY;
\r
5570 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
5571 uint src = *r_dst;
\r
5572 uint res = MASK_OUT_ABOVE_32(src << shift);
\r
5575 USE_CYCLES(shift<<CYC_SHIFT);
\r
5579 FLAG_N = NFLAG_32(res);
\r
5581 FLAG_X = FLAG_C = src >> (24-shift);
\r
5582 FLAG_V = VFLAG_CLEAR;
\r
5586 M68KMAKE_OP(lsl, 8, r, .)
\r
5588 uint* r_dst = &DY;
\r
5589 uint shift = DX & 0x3f;
\r
5590 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
5591 uint res = MASK_OUT_ABOVE_8(src << shift);
\r
5595 USE_CYCLES(shift<<CYC_SHIFT);
\r
5599 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
5600 FLAG_X = FLAG_C = src << shift;
\r
5601 FLAG_N = NFLAG_8(res);
\r
5603 FLAG_V = VFLAG_CLEAR;
\r
5607 *r_dst &= 0xffffff00;
\r
5608 FLAG_X = XFLAG_CLEAR;
\r
5609 FLAG_C = CFLAG_CLEAR;
\r
5610 FLAG_N = NFLAG_CLEAR;
\r
5611 FLAG_Z = ZFLAG_SET;
\r
5612 FLAG_V = VFLAG_CLEAR;
\r
5616 FLAG_C = CFLAG_CLEAR;
\r
5617 FLAG_N = NFLAG_8(src);
\r
5619 FLAG_V = VFLAG_CLEAR;
\r
5623 M68KMAKE_OP(lsl, 16, r, .)
\r
5625 uint* r_dst = &DY;
\r
5626 uint shift = DX & 0x3f;
\r
5627 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
5628 uint res = MASK_OUT_ABOVE_16(src << shift);
\r
5632 USE_CYCLES(shift<<CYC_SHIFT);
\r
5636 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
5637 FLAG_X = FLAG_C = (src << shift) >> 8;
\r
5638 FLAG_N = NFLAG_16(res);
\r
5640 FLAG_V = VFLAG_CLEAR;
\r
5644 *r_dst &= 0xffff0000;
\r
5645 FLAG_X = XFLAG_CLEAR;
\r
5646 FLAG_C = CFLAG_CLEAR;
\r
5647 FLAG_N = NFLAG_CLEAR;
\r
5648 FLAG_Z = ZFLAG_SET;
\r
5649 FLAG_V = VFLAG_CLEAR;
\r
5653 FLAG_C = CFLAG_CLEAR;
\r
5654 FLAG_N = NFLAG_16(src);
\r
5656 FLAG_V = VFLAG_CLEAR;
\r
5660 M68KMAKE_OP(lsl, 32, r, .)
\r
5662 uint* r_dst = &DY;
\r
5663 uint shift = DX & 0x3f;
\r
5664 uint src = *r_dst;
\r
5665 uint res = MASK_OUT_ABOVE_32(src << shift);
\r
5669 USE_CYCLES(shift<<CYC_SHIFT);
\r
5674 FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;
\r
5675 FLAG_N = NFLAG_32(res);
\r
5677 FLAG_V = VFLAG_CLEAR;
\r
5682 FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;
\r
5683 FLAG_N = NFLAG_CLEAR;
\r
5684 FLAG_Z = ZFLAG_SET;
\r
5685 FLAG_V = VFLAG_CLEAR;
\r
5689 FLAG_C = CFLAG_CLEAR;
\r
5690 FLAG_N = NFLAG_32(src);
\r
5692 FLAG_V = VFLAG_CLEAR;
\r
5696 M68KMAKE_OP(lsl, 16, ., .)
\r
5698 uint ea = M68KMAKE_GET_EA_AY_16;
\r
5699 uint src = m68ki_read_16(ea);
\r
5700 uint res = MASK_OUT_ABOVE_16(src << 1);
\r
5702 m68ki_write_16(ea, res);
\r
5704 FLAG_N = NFLAG_16(res);
\r
5706 FLAG_X = FLAG_C = src >> 7;
\r
5707 FLAG_V = VFLAG_CLEAR;
\r
5711 M68KMAKE_OP(move, 8, d, d)
\r
5713 uint res = MASK_OUT_ABOVE_8(DY);
\r
5714 uint* r_dst = &DX;
\r
5716 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
5718 FLAG_N = NFLAG_8(res);
\r
5720 FLAG_V = VFLAG_CLEAR;
\r
5721 FLAG_C = CFLAG_CLEAR;
\r
5725 M68KMAKE_OP(move, 8, d, .)
\r
5727 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5728 uint* r_dst = &DX;
\r
5730 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
5732 FLAG_N = NFLAG_8(res);
\r
5734 FLAG_V = VFLAG_CLEAR;
\r
5735 FLAG_C = CFLAG_CLEAR;
\r
5739 M68KMAKE_OP(move, 8, ai, d)
\r
5741 uint res = MASK_OUT_ABOVE_8(DY);
\r
5742 uint ea = EA_AX_AI_8();
\r
5744 m68ki_write_8(ea, res);
\r
5746 FLAG_N = NFLAG_8(res);
\r
5748 FLAG_V = VFLAG_CLEAR;
\r
5749 FLAG_C = CFLAG_CLEAR;
\r
5753 M68KMAKE_OP(move, 8, ai, .)
\r
5755 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5756 uint ea = EA_AX_AI_8();
\r
5758 m68ki_write_8(ea, res);
\r
5760 FLAG_N = NFLAG_8(res);
\r
5762 FLAG_V = VFLAG_CLEAR;
\r
5763 FLAG_C = CFLAG_CLEAR;
\r
5767 M68KMAKE_OP(move, 8, pi7, d)
\r
5769 uint res = MASK_OUT_ABOVE_8(DY);
\r
5770 uint ea = EA_A7_PI_8();
\r
5772 m68ki_write_8(ea, res);
\r
5774 FLAG_N = NFLAG_8(res);
\r
5776 FLAG_V = VFLAG_CLEAR;
\r
5777 FLAG_C = CFLAG_CLEAR;
\r
5781 M68KMAKE_OP(move, 8, pi, d)
\r
5783 uint res = MASK_OUT_ABOVE_8(DY);
\r
5784 uint ea = EA_AX_PI_8();
\r
5786 m68ki_write_8(ea, res);
\r
5788 FLAG_N = NFLAG_8(res);
\r
5790 FLAG_V = VFLAG_CLEAR;
\r
5791 FLAG_C = CFLAG_CLEAR;
\r
5795 M68KMAKE_OP(move, 8, pi7, .)
\r
5797 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5798 uint ea = EA_A7_PI_8();
\r
5800 m68ki_write_8(ea, res);
\r
5802 FLAG_N = NFLAG_8(res);
\r
5804 FLAG_V = VFLAG_CLEAR;
\r
5805 FLAG_C = CFLAG_CLEAR;
\r
5809 M68KMAKE_OP(move, 8, pi, .)
\r
5811 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5812 uint ea = EA_AX_PI_8();
\r
5814 m68ki_write_8(ea, res);
\r
5816 FLAG_N = NFLAG_8(res);
\r
5818 FLAG_V = VFLAG_CLEAR;
\r
5819 FLAG_C = CFLAG_CLEAR;
\r
5823 M68KMAKE_OP(move, 8, pd7, d)
\r
5825 uint res = MASK_OUT_ABOVE_8(DY);
\r
5826 uint ea = EA_A7_PD_8();
\r
5828 m68ki_write_8(ea, res);
\r
5830 FLAG_N = NFLAG_8(res);
\r
5832 FLAG_V = VFLAG_CLEAR;
\r
5833 FLAG_C = CFLAG_CLEAR;
\r
5837 M68KMAKE_OP(move, 8, pd, d)
\r
5839 uint res = MASK_OUT_ABOVE_8(DY);
\r
5840 uint ea = EA_AX_PD_8();
\r
5842 m68ki_write_8(ea, res);
\r
5844 FLAG_N = NFLAG_8(res);
\r
5846 FLAG_V = VFLAG_CLEAR;
\r
5847 FLAG_C = CFLAG_CLEAR;
\r
5851 M68KMAKE_OP(move, 8, pd7, .)
\r
5853 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5854 uint ea = EA_A7_PD_8();
\r
5856 m68ki_write_8(ea, res);
\r
5858 FLAG_N = NFLAG_8(res);
\r
5860 FLAG_V = VFLAG_CLEAR;
\r
5861 FLAG_C = CFLAG_CLEAR;
\r
5865 M68KMAKE_OP(move, 8, pd, .)
\r
5867 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5868 uint ea = EA_AX_PD_8();
\r
5870 m68ki_write_8(ea, res);
\r
5872 FLAG_N = NFLAG_8(res);
\r
5874 FLAG_V = VFLAG_CLEAR;
\r
5875 FLAG_C = CFLAG_CLEAR;
\r
5879 M68KMAKE_OP(move, 8, di, d)
\r
5881 uint res = MASK_OUT_ABOVE_8(DY);
\r
5882 uint ea = EA_AX_DI_8();
\r
5884 m68ki_write_8(ea, res);
\r
5886 FLAG_N = NFLAG_8(res);
\r
5888 FLAG_V = VFLAG_CLEAR;
\r
5889 FLAG_C = CFLAG_CLEAR;
\r
5893 M68KMAKE_OP(move, 8, di, .)
\r
5895 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5896 uint ea = EA_AX_DI_8();
\r
5898 m68ki_write_8(ea, res);
\r
5900 FLAG_N = NFLAG_8(res);
\r
5902 FLAG_V = VFLAG_CLEAR;
\r
5903 FLAG_C = CFLAG_CLEAR;
\r
5907 M68KMAKE_OP(move, 8, ix, d)
\r
5909 uint res = MASK_OUT_ABOVE_8(DY);
\r
5910 uint ea = EA_AX_IX_8();
\r
5912 m68ki_write_8(ea, res);
\r
5914 FLAG_N = NFLAG_8(res);
\r
5916 FLAG_V = VFLAG_CLEAR;
\r
5917 FLAG_C = CFLAG_CLEAR;
\r
5921 M68KMAKE_OP(move, 8, ix, .)
\r
5923 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5924 uint ea = EA_AX_IX_8();
\r
5926 m68ki_write_8(ea, res);
\r
5928 FLAG_N = NFLAG_8(res);
\r
5930 FLAG_V = VFLAG_CLEAR;
\r
5931 FLAG_C = CFLAG_CLEAR;
\r
5935 M68KMAKE_OP(move, 8, aw, d)
\r
5937 uint res = MASK_OUT_ABOVE_8(DY);
\r
5938 uint ea = EA_AW_8();
\r
5940 m68ki_write_8(ea, res);
\r
5942 FLAG_N = NFLAG_8(res);
\r
5944 FLAG_V = VFLAG_CLEAR;
\r
5945 FLAG_C = CFLAG_CLEAR;
\r
5949 M68KMAKE_OP(move, 8, aw, .)
\r
5951 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5952 uint ea = EA_AW_8();
\r
5954 m68ki_write_8(ea, res);
\r
5956 FLAG_N = NFLAG_8(res);
\r
5958 FLAG_V = VFLAG_CLEAR;
\r
5959 FLAG_C = CFLAG_CLEAR;
\r
5963 M68KMAKE_OP(move, 8, al, d)
\r
5965 uint res = MASK_OUT_ABOVE_8(DY);
\r
5966 uint ea = EA_AL_8();
\r
5968 m68ki_write_8(ea, res);
\r
5970 FLAG_N = NFLAG_8(res);
\r
5972 FLAG_V = VFLAG_CLEAR;
\r
5973 FLAG_C = CFLAG_CLEAR;
\r
5977 M68KMAKE_OP(move, 8, al, .)
\r
5979 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5980 uint ea = EA_AL_8();
\r
5982 m68ki_write_8(ea, res);
\r
5984 FLAG_N = NFLAG_8(res);
\r
5986 FLAG_V = VFLAG_CLEAR;
\r
5987 FLAG_C = CFLAG_CLEAR;
\r
5991 M68KMAKE_OP(move, 16, d, d)
\r
5993 uint res = MASK_OUT_ABOVE_16(DY);
\r
5994 uint* r_dst = &DX;
\r
5996 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
5998 FLAG_N = NFLAG_16(res);
\r
6000 FLAG_V = VFLAG_CLEAR;
\r
6001 FLAG_C = CFLAG_CLEAR;
\r
6005 M68KMAKE_OP(move, 16, d, a)
\r
6007 uint res = MASK_OUT_ABOVE_16(AY);
\r
6008 uint* r_dst = &DX;
\r
6010 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
6012 FLAG_N = NFLAG_16(res);
\r
6014 FLAG_V = VFLAG_CLEAR;
\r
6015 FLAG_C = CFLAG_CLEAR;
\r
6019 M68KMAKE_OP(move, 16, d, .)
\r
6021 uint res = M68KMAKE_GET_OPER_AY_16;
\r
6022 uint* r_dst = &DX;
\r
6024 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
6026 FLAG_N = NFLAG_16(res);
\r
6028 FLAG_V = VFLAG_CLEAR;
\r
6029 FLAG_C = CFLAG_CLEAR;
\r
6033 M68KMAKE_OP(move, 16, ai, d)
\r
6035 uint res = MASK_OUT_ABOVE_16(DY);
\r
6036 uint ea = EA_AX_AI_16();
\r
6038 m68ki_write_16(ea, res);
\r
6040 FLAG_N = NFLAG_16(res);
\r
6042 FLAG_V = VFLAG_CLEAR;
\r
6043 FLAG_C = CFLAG_CLEAR;
\r
6047 M68KMAKE_OP(move, 16, ai, a)
\r
6049 uint res = MASK_OUT_ABOVE_16(AY);
\r
6050 uint ea = EA_AX_AI_16();
\r
6052 m68ki_write_16(ea, res);
\r
6054 FLAG_N = NFLAG_16(res);
\r
6056 FLAG_V = VFLAG_CLEAR;
\r
6057 FLAG_C = CFLAG_CLEAR;
\r
6061 M68KMAKE_OP(move, 16, ai, .)
\r
6063 uint res = M68KMAKE_GET_OPER_AY_16;
\r
6064 uint ea = EA_AX_AI_16();
\r
6066 m68ki_write_16(ea, res);
\r
6068 FLAG_N = NFLAG_16(res);
\r
6070 FLAG_V = VFLAG_CLEAR;
\r
6071 FLAG_C = CFLAG_CLEAR;
\r
6075 M68KMAKE_OP(move, 16, pi, d)
\r
6077 uint res = MASK_OUT_ABOVE_16(DY);
\r
6078 uint ea = EA_AX_PI_16();
\r
6080 m68ki_write_16(ea, res);
\r
6082 FLAG_N = NFLAG_16(res);
\r
6084 FLAG_V = VFLAG_CLEAR;
\r
6085 FLAG_C = CFLAG_CLEAR;
\r
6089 M68KMAKE_OP(move, 16, pi, a)
\r
6091 uint res = MASK_OUT_ABOVE_16(AY);
\r
6092 uint ea = EA_AX_PI_16();
\r
6094 m68ki_write_16(ea, res);
\r
6096 FLAG_N = NFLAG_16(res);
\r
6098 FLAG_V = VFLAG_CLEAR;
\r
6099 FLAG_C = CFLAG_CLEAR;
\r
6103 M68KMAKE_OP(move, 16, pi, .)
\r
6105 uint res = M68KMAKE_GET_OPER_AY_16;
\r
6106 uint ea = EA_AX_PI_16();
\r
6108 m68ki_write_16(ea, res);
\r
6110 FLAG_N = NFLAG_16(res);
\r
6112 FLAG_V = VFLAG_CLEAR;
\r
6113 FLAG_C = CFLAG_CLEAR;
\r
6117 M68KMAKE_OP(move, 16, pd, d)
\r
6119 uint res = MASK_OUT_ABOVE_16(DY);
\r
6120 uint ea = EA_AX_PD_16();
\r
6122 m68ki_write_16(ea, res);
\r
6124 FLAG_N = NFLAG_16(res);
\r
6126 FLAG_V = VFLAG_CLEAR;
\r
6127 FLAG_C = CFLAG_CLEAR;
\r
6131 M68KMAKE_OP(move, 16, pd, a)
\r
6133 uint res = MASK_OUT_ABOVE_16(AY);
\r
6134 uint ea = EA_AX_PD_16();
\r
6136 m68ki_write_16(ea, res);
\r
6138 FLAG_N = NFLAG_16(res);
\r
6140 FLAG_V = VFLAG_CLEAR;
\r
6141 FLAG_C = CFLAG_CLEAR;
\r
6145 M68KMAKE_OP(move, 16, pd, .)
\r
6147 uint res = M68KMAKE_GET_OPER_AY_16;
\r
6148 uint ea = EA_AX_PD_16();
\r
6150 m68ki_write_16(ea, res);
\r
6152 FLAG_N = NFLAG_16(res);
\r
6154 FLAG_V = VFLAG_CLEAR;
\r
6155 FLAG_C = CFLAG_CLEAR;
\r
6159 M68KMAKE_OP(move, 16, di, d)
\r
6161 uint res = MASK_OUT_ABOVE_16(DY);
\r
6162 uint ea = EA_AX_DI_16();
\r
6164 m68ki_write_16(ea, res);
\r
6166 FLAG_N = NFLAG_16(res);
\r
6168 FLAG_V = VFLAG_CLEAR;
\r
6169 FLAG_C = CFLAG_CLEAR;
\r
6173 M68KMAKE_OP(move, 16, di, a)
\r
6175 uint res = MASK_OUT_ABOVE_16(AY);
\r
6176 uint ea = EA_AX_DI_16();
\r
6178 m68ki_write_16(ea, res);
\r
6180 FLAG_N = NFLAG_16(res);
\r
6182 FLAG_V = VFLAG_CLEAR;
\r
6183 FLAG_C = CFLAG_CLEAR;
\r
6187 M68KMAKE_OP(move, 16, di, .)
\r
6189 uint res = M68KMAKE_GET_OPER_AY_16;
\r
6190 uint ea = EA_AX_DI_16();
\r
6192 m68ki_write_16(ea, res);
\r
6194 FLAG_N = NFLAG_16(res);
\r
6196 FLAG_V = VFLAG_CLEAR;
\r
6197 FLAG_C = CFLAG_CLEAR;
\r
6201 M68KMAKE_OP(move, 16, ix, d)
\r
6203 uint res = MASK_OUT_ABOVE_16(DY);
\r
6204 uint ea = EA_AX_IX_16();
\r
6206 m68ki_write_16(ea, res);
\r
6208 FLAG_N = NFLAG_16(res);
\r
6210 FLAG_V = VFLAG_CLEAR;
\r
6211 FLAG_C = CFLAG_CLEAR;
\r
6215 M68KMAKE_OP(move, 16, ix, a)
\r
6217 uint res = MASK_OUT_ABOVE_16(AY);
\r
6218 uint ea = EA_AX_IX_16();
\r
6220 m68ki_write_16(ea, res);
\r
6222 FLAG_N = NFLAG_16(res);
\r
6224 FLAG_V = VFLAG_CLEAR;
\r
6225 FLAG_C = CFLAG_CLEAR;
\r
6229 M68KMAKE_OP(move, 16, ix, .)
\r
6231 uint res = M68KMAKE_GET_OPER_AY_16;
\r
6232 uint ea = EA_AX_IX_16();
\r
6234 m68ki_write_16(ea, res);
\r
6236 FLAG_N = NFLAG_16(res);
\r
6238 FLAG_V = VFLAG_CLEAR;
\r
6239 FLAG_C = CFLAG_CLEAR;
\r
6243 M68KMAKE_OP(move, 16, aw, d)
\r
6245 uint res = MASK_OUT_ABOVE_16(DY);
\r
6246 uint ea = EA_AW_16();
\r
6248 m68ki_write_16(ea, res);
\r
6250 FLAG_N = NFLAG_16(res);
\r
6252 FLAG_V = VFLAG_CLEAR;
\r
6253 FLAG_C = CFLAG_CLEAR;
\r
6257 M68KMAKE_OP(move, 16, aw, a)
\r
6259 uint res = MASK_OUT_ABOVE_16(AY);
\r
6260 uint ea = EA_AW_16();
\r
6262 m68ki_write_16(ea, res);
\r
6264 FLAG_N = NFLAG_16(res);
\r
6266 FLAG_V = VFLAG_CLEAR;
\r
6267 FLAG_C = CFLAG_CLEAR;
\r
6271 M68KMAKE_OP(move, 16, aw, .)
\r
6273 uint res = M68KMAKE_GET_OPER_AY_16;
\r
6274 uint ea = EA_AW_16();
\r
6276 m68ki_write_16(ea, res);
\r
6278 FLAG_N = NFLAG_16(res);
\r
6280 FLAG_V = VFLAG_CLEAR;
\r
6281 FLAG_C = CFLAG_CLEAR;
\r
6285 M68KMAKE_OP(move, 16, al, d)
\r
6287 uint res = MASK_OUT_ABOVE_16(DY);
\r
6288 uint ea = EA_AL_16();
\r
6290 m68ki_write_16(ea, res);
\r
6292 FLAG_N = NFLAG_16(res);
\r
6294 FLAG_V = VFLAG_CLEAR;
\r
6295 FLAG_C = CFLAG_CLEAR;
\r
6299 M68KMAKE_OP(move, 16, al, a)
\r
6301 uint res = MASK_OUT_ABOVE_16(AY);
\r
6302 uint ea = EA_AL_16();
\r
6304 m68ki_write_16(ea, res);
\r
6306 FLAG_N = NFLAG_16(res);
\r
6308 FLAG_V = VFLAG_CLEAR;
\r
6309 FLAG_C = CFLAG_CLEAR;
\r
6313 M68KMAKE_OP(move, 16, al, .)
\r
6315 uint res = M68KMAKE_GET_OPER_AY_16;
\r
6316 uint ea = EA_AL_16();
\r
6318 m68ki_write_16(ea, res);
\r
6320 FLAG_N = NFLAG_16(res);
\r
6322 FLAG_V = VFLAG_CLEAR;
\r
6323 FLAG_C = CFLAG_CLEAR;
\r
6327 M68KMAKE_OP(move, 32, d, d)
\r
6330 uint* r_dst = &DX;
\r
6334 FLAG_N = NFLAG_32(res);
\r
6336 FLAG_V = VFLAG_CLEAR;
\r
6337 FLAG_C = CFLAG_CLEAR;
\r
6341 M68KMAKE_OP(move, 32, d, a)
\r
6344 uint* r_dst = &DX;
\r
6348 FLAG_N = NFLAG_32(res);
\r
6350 FLAG_V = VFLAG_CLEAR;
\r
6351 FLAG_C = CFLAG_CLEAR;
\r
6355 M68KMAKE_OP(move, 32, d, .)
\r
6357 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6358 uint* r_dst = &DX;
\r
6362 FLAG_N = NFLAG_32(res);
\r
6364 FLAG_V = VFLAG_CLEAR;
\r
6365 FLAG_C = CFLAG_CLEAR;
\r
6369 M68KMAKE_OP(move, 32, ai, d)
\r
6372 uint ea = EA_AX_AI_32();
\r
6374 m68ki_write_32(ea, res);
\r
6376 FLAG_N = NFLAG_32(res);
\r
6378 FLAG_V = VFLAG_CLEAR;
\r
6379 FLAG_C = CFLAG_CLEAR;
\r
6383 M68KMAKE_OP(move, 32, ai, a)
\r
6386 uint ea = EA_AX_AI_32();
\r
6388 m68ki_write_32(ea, res);
\r
6390 FLAG_N = NFLAG_32(res);
\r
6392 FLAG_V = VFLAG_CLEAR;
\r
6393 FLAG_C = CFLAG_CLEAR;
\r
6397 M68KMAKE_OP(move, 32, ai, .)
\r
6399 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6400 uint ea = EA_AX_AI_32();
\r
6402 m68ki_write_32(ea, res);
\r
6404 FLAG_N = NFLAG_32(res);
\r
6406 FLAG_V = VFLAG_CLEAR;
\r
6407 FLAG_C = CFLAG_CLEAR;
\r
6411 M68KMAKE_OP(move, 32, pi, d)
\r
6414 uint ea = EA_AX_PI_32();
\r
6416 m68ki_write_32(ea, res);
\r
6418 FLAG_N = NFLAG_32(res);
\r
6420 FLAG_V = VFLAG_CLEAR;
\r
6421 FLAG_C = CFLAG_CLEAR;
\r
6425 M68KMAKE_OP(move, 32, pi, a)
\r
6428 uint ea = EA_AX_PI_32();
\r
6430 m68ki_write_32(ea, res);
\r
6432 FLAG_N = NFLAG_32(res);
\r
6434 FLAG_V = VFLAG_CLEAR;
\r
6435 FLAG_C = CFLAG_CLEAR;
\r
6439 M68KMAKE_OP(move, 32, pi, .)
\r
6441 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6442 uint ea = EA_AX_PI_32();
\r
6444 m68ki_write_32(ea, res);
\r
6446 FLAG_N = NFLAG_32(res);
\r
6448 FLAG_V = VFLAG_CLEAR;
\r
6449 FLAG_C = CFLAG_CLEAR;
\r
6453 M68KMAKE_OP(move, 32, pd, d)
\r
6456 uint ea = EA_AX_PD_32();
\r
6458 m68ki_write_16(ea+2, res & 0xFFFF );
\r
6459 m68ki_write_16(ea, (res >> 16) & 0xFFFF );
\r
6461 FLAG_N = NFLAG_32(res);
\r
6463 FLAG_V = VFLAG_CLEAR;
\r
6464 FLAG_C = CFLAG_CLEAR;
\r
6468 M68KMAKE_OP(move, 32, pd, a)
\r
6471 uint ea = EA_AX_PD_32();
\r
6473 m68ki_write_16(ea+2, res & 0xFFFF );
\r
6474 m68ki_write_16(ea, (res >> 16) & 0xFFFF );
\r
6476 FLAG_N = NFLAG_32(res);
\r
6478 FLAG_V = VFLAG_CLEAR;
\r
6479 FLAG_C = CFLAG_CLEAR;
\r
6483 M68KMAKE_OP(move, 32, pd, .)
\r
6485 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6486 uint ea = EA_AX_PD_32();
\r
6488 m68ki_write_16(ea+2, res & 0xFFFF );
\r
6489 m68ki_write_16(ea, (res >> 16) & 0xFFFF );
\r
6491 FLAG_N = NFLAG_32(res);
\r
6493 FLAG_V = VFLAG_CLEAR;
\r
6494 FLAG_C = CFLAG_CLEAR;
\r
6498 M68KMAKE_OP(move, 32, di, d)
\r
6501 uint ea = EA_AX_DI_32();
\r
6503 m68ki_write_32(ea, res);
\r
6505 FLAG_N = NFLAG_32(res);
\r
6507 FLAG_V = VFLAG_CLEAR;
\r
6508 FLAG_C = CFLAG_CLEAR;
\r
6512 M68KMAKE_OP(move, 32, di, a)
\r
6515 uint ea = EA_AX_DI_32();
\r
6517 m68ki_write_32(ea, res);
\r
6519 FLAG_N = NFLAG_32(res);
\r
6521 FLAG_V = VFLAG_CLEAR;
\r
6522 FLAG_C = CFLAG_CLEAR;
\r
6526 M68KMAKE_OP(move, 32, di, .)
\r
6528 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6529 uint ea = EA_AX_DI_32();
\r
6531 m68ki_write_32(ea, res);
\r
6533 FLAG_N = NFLAG_32(res);
\r
6535 FLAG_V = VFLAG_CLEAR;
\r
6536 FLAG_C = CFLAG_CLEAR;
\r
6540 M68KMAKE_OP(move, 32, ix, d)
\r
6543 uint ea = EA_AX_IX_32();
\r
6545 m68ki_write_32(ea, res);
\r
6547 FLAG_N = NFLAG_32(res);
\r
6549 FLAG_V = VFLAG_CLEAR;
\r
6550 FLAG_C = CFLAG_CLEAR;
\r
6554 M68KMAKE_OP(move, 32, ix, a)
\r
6557 uint ea = EA_AX_IX_32();
\r
6559 m68ki_write_32(ea, res);
\r
6561 FLAG_N = NFLAG_32(res);
\r
6563 FLAG_V = VFLAG_CLEAR;
\r
6564 FLAG_C = CFLAG_CLEAR;
\r
6568 M68KMAKE_OP(move, 32, ix, .)
\r
6570 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6571 uint ea = EA_AX_IX_32();
\r
6573 m68ki_write_32(ea, res);
\r
6575 FLAG_N = NFLAG_32(res);
\r
6577 FLAG_V = VFLAG_CLEAR;
\r
6578 FLAG_C = CFLAG_CLEAR;
\r
6582 M68KMAKE_OP(move, 32, aw, d)
\r
6585 uint ea = EA_AW_32();
\r
6587 m68ki_write_32(ea, res);
\r
6589 FLAG_N = NFLAG_32(res);
\r
6591 FLAG_V = VFLAG_CLEAR;
\r
6592 FLAG_C = CFLAG_CLEAR;
\r
6596 M68KMAKE_OP(move, 32, aw, a)
\r
6599 uint ea = EA_AW_32();
\r
6601 m68ki_write_32(ea, res);
\r
6603 FLAG_N = NFLAG_32(res);
\r
6605 FLAG_V = VFLAG_CLEAR;
\r
6606 FLAG_C = CFLAG_CLEAR;
\r
6610 M68KMAKE_OP(move, 32, aw, .)
\r
6612 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6613 uint ea = EA_AW_32();
\r
6615 m68ki_write_32(ea, res);
\r
6617 FLAG_N = NFLAG_32(res);
\r
6619 FLAG_V = VFLAG_CLEAR;
\r
6620 FLAG_C = CFLAG_CLEAR;
\r
6624 M68KMAKE_OP(move, 32, al, d)
\r
6627 uint ea = EA_AL_32();
\r
6629 m68ki_write_32(ea, res);
\r
6631 FLAG_N = NFLAG_32(res);
\r
6633 FLAG_V = VFLAG_CLEAR;
\r
6634 FLAG_C = CFLAG_CLEAR;
\r
6638 M68KMAKE_OP(move, 32, al, a)
\r
6641 uint ea = EA_AL_32();
\r
6643 m68ki_write_32(ea, res);
\r
6645 FLAG_N = NFLAG_32(res);
\r
6647 FLAG_V = VFLAG_CLEAR;
\r
6648 FLAG_C = CFLAG_CLEAR;
\r
6652 M68KMAKE_OP(move, 32, al, .)
\r
6654 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6655 uint ea = EA_AL_32();
\r
6657 m68ki_write_32(ea, res);
\r
6659 FLAG_N = NFLAG_32(res);
\r
6661 FLAG_V = VFLAG_CLEAR;
\r
6662 FLAG_C = CFLAG_CLEAR;
\r
6666 M68KMAKE_OP(movea, 16, ., d)
\r
6668 AX = MAKE_INT_16(DY);
\r
6672 M68KMAKE_OP(movea, 16, ., a)
\r
6674 AX = MAKE_INT_16(AY);
\r
6678 M68KMAKE_OP(movea, 16, ., .)
\r
6680 AX = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
\r
6684 M68KMAKE_OP(movea, 32, ., d)
\r
6690 M68KMAKE_OP(movea, 32, ., a)
\r
6696 M68KMAKE_OP(movea, 32, ., .)
\r
6698 AX = M68KMAKE_GET_OPER_AY_32;
\r
6702 M68KMAKE_OP(move, 16, frc, d)
\r
6704 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
6706 DY = MASK_OUT_BELOW_16(DY) | m68ki_get_ccr();
\r
6709 m68ki_exception_illegal();
\r
6713 M68KMAKE_OP(move, 16, frc, .)
\r
6715 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
6717 m68ki_write_16(M68KMAKE_GET_EA_AY_16, m68ki_get_ccr());
\r
6720 m68ki_exception_illegal();
\r
6724 M68KMAKE_OP(move, 16, toc, d)
\r
6726 m68ki_set_ccr(DY);
\r
6730 M68KMAKE_OP(move, 16, toc, .)
\r
6732 m68ki_set_ccr(M68KMAKE_GET_OPER_AY_16);
\r
6736 M68KMAKE_OP(move, 16, frs, d)
\r
6738 if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */
\r
6740 DY = MASK_OUT_BELOW_16(DY) | m68ki_get_sr();
\r
6743 m68ki_exception_privilege_violation();
\r
6747 M68KMAKE_OP(move, 16, frs, .)
\r
6749 if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */
\r
6751 uint ea = M68KMAKE_GET_EA_AY_16;
\r
6752 m68ki_write_16(ea, m68ki_get_sr());
\r
6755 m68ki_exception_privilege_violation();
\r
6759 M68KMAKE_OP(move, 16, tos, d)
\r
6766 m68ki_exception_privilege_violation();
\r
6770 M68KMAKE_OP(move, 16, tos, .)
\r
6774 uint new_sr = M68KMAKE_GET_OPER_AY_16;
\r
6775 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
6776 m68ki_set_sr(new_sr);
\r
6779 m68ki_exception_privilege_violation();
\r
6783 M68KMAKE_OP(move, 32, fru, .)
\r
6790 m68ki_exception_privilege_violation();
\r
6794 M68KMAKE_OP(move, 32, tou, .)
\r
6798 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
6802 m68ki_exception_privilege_violation();
\r
6806 M68KMAKE_OP(movec, 32, cr, .)
\r
6808 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
6812 uint word2 = OPER_I_16();
\r
6814 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
6815 switch (word2 & 0xfff)
\r
6817 case 0x000: /* SFC */
\r
6818 REG_DA[(word2 >> 12) & 15] = REG_SFC;
\r
6820 case 0x001: /* DFC */
\r
6821 REG_DA[(word2 >> 12) & 15] = REG_DFC;
\r
6823 case 0x002: /* CACR */
\r
6824 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6826 REG_DA[(word2 >> 12) & 15] = REG_CACR;
\r
6830 case 0x800: /* USP */
\r
6831 REG_DA[(word2 >> 12) & 15] = REG_USP;
\r
6833 case 0x801: /* VBR */
\r
6834 REG_DA[(word2 >> 12) & 15] = REG_VBR;
\r
6836 case 0x802: /* CAAR */
\r
6837 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6839 REG_DA[(word2 >> 12) & 15] = REG_CAAR;
\r
6842 m68ki_exception_illegal();
\r
6844 case 0x803: /* MSP */
\r
6845 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6847 REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_SP : REG_MSP;
\r
6850 m68ki_exception_illegal();
\r
6852 case 0x804: /* ISP */
\r
6853 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6855 REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_ISP : REG_SP;
\r
6858 m68ki_exception_illegal();
\r
6860 case 0x003: /* TC */
\r
6861 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6866 m68ki_exception_illegal();
\r
6868 case 0x004: /* ITT0 */
\r
6869 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6874 m68ki_exception_illegal();
\r
6876 case 0x005: /* ITT1 */
\r
6877 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6882 m68ki_exception_illegal();
\r
6884 case 0x006: /* DTT0 */
\r
6885 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6890 m68ki_exception_illegal();
\r
6892 case 0x007: /* DTT1 */
\r
6893 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6898 m68ki_exception_illegal();
\r
6900 case 0x805: /* MMUSR */
\r
6901 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6906 m68ki_exception_illegal();
\r
6908 case 0x806: /* URP */
\r
6909 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6914 m68ki_exception_illegal();
\r
6916 case 0x807: /* SRP */
\r
6917 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6922 m68ki_exception_illegal();
\r
6925 m68ki_exception_illegal();
\r
6929 m68ki_exception_privilege_violation();
\r
6932 m68ki_exception_illegal();
\r
6936 M68KMAKE_OP(movec, 32, rc, .)
\r
6938 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
6942 uint word2 = OPER_I_16();
\r
6944 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
6945 switch (word2 & 0xfff)
\r
6947 case 0x000: /* SFC */
\r
6948 REG_SFC = REG_DA[(word2 >> 12) & 15] & 7;
\r
6950 case 0x001: /* DFC */
\r
6951 REG_DFC = REG_DA[(word2 >> 12) & 15] & 7;
\r
6953 case 0x002: /* CACR */
\r
6954 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6956 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6958 REG_CACR = REG_DA[(word2 >> 12) & 15];
\r
6962 /* non 68040 can only set the lower 4 bits (C,CE,F,E) */
\r
6963 REG_CACR = REG_DA[(word2 >> 12) & 15] & 0x0f;
\r
6967 m68ki_exception_illegal();
\r
6969 case 0x800: /* USP */
\r
6970 REG_USP = REG_DA[(word2 >> 12) & 15];
\r
6972 case 0x801: /* VBR */
\r
6973 REG_VBR = REG_DA[(word2 >> 12) & 15];
\r
6975 case 0x802: /* CAAR */
\r
6976 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6978 REG_CAAR = REG_DA[(word2 >> 12) & 15];
\r
6981 m68ki_exception_illegal();
\r
6983 case 0x803: /* MSP */
\r
6984 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6986 /* we are in supervisor mode so just check for M flag */
\r
6989 REG_MSP = REG_DA[(word2 >> 12) & 15];
\r
6992 REG_SP = REG_DA[(word2 >> 12) & 15];
\r
6995 m68ki_exception_illegal();
\r
6997 case 0x804: /* ISP */
\r
6998 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
7002 REG_SP = REG_DA[(word2 >> 12) & 15];
\r
7005 REG_ISP = REG_DA[(word2 >> 12) & 15];
\r
7008 m68ki_exception_illegal();
\r
7010 case 0x003: /* TC */
\r
7011 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7016 m68ki_exception_illegal();
\r
7018 case 0x004: /* ITT0 */
\r
7019 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7024 m68ki_exception_illegal();
\r
7026 case 0x005: /* ITT1 */
\r
7027 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7032 m68ki_exception_illegal();
\r
7034 case 0x006: /* DTT0 */
\r
7035 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7040 m68ki_exception_illegal();
\r
7042 case 0x007: /* DTT1 */
\r
7043 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7048 m68ki_exception_illegal();
\r
7050 case 0x805: /* MMUSR */
\r
7051 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7056 m68ki_exception_illegal();
\r
7058 case 0x806: /* URP */
\r
7059 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7064 m68ki_exception_illegal();
\r
7066 case 0x807: /* SRP */
\r
7067 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7072 m68ki_exception_illegal();
\r
7075 m68ki_exception_illegal();
\r
7079 m68ki_exception_privilege_violation();
\r
7082 m68ki_exception_illegal();
\r
7086 M68KMAKE_OP(movem, 16, re, pd)
\r
7089 uint register_list = OPER_I_16();
\r
7093 for(; i < 16; i++)
\r
7094 if(register_list & (1 << i))
\r
7097 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[15-i]));
\r
7102 USE_CYCLES(count<<CYC_MOVEM_W);
\r
7106 M68KMAKE_OP(movem, 16, re, .)
\r
7109 uint register_list = OPER_I_16();
\r
7110 uint ea = M68KMAKE_GET_EA_AY_16;
\r
7113 for(; i < 16; i++)
\r
7114 if(register_list & (1 << i))
\r
7116 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));
\r
7121 USE_CYCLES(count<<CYC_MOVEM_W);
\r
7125 M68KMAKE_OP(movem, 32, re, pd)
\r
7128 uint register_list = OPER_I_16();
\r
7132 for(; i < 16; i++)
\r
7133 if(register_list & (1 << i))
\r
7136 m68ki_write_32(ea, REG_DA[15-i] ); // notaz Cyclone hack
\r
7137 //m68ki_write_16(ea+2, REG_DA[15-i] & 0xFFFF );
\r
7138 //m68ki_write_16(ea, (REG_DA[15-i] >> 16) & 0xFFFF );
\r
7143 USE_CYCLES(count<<CYC_MOVEM_L);
\r
7147 M68KMAKE_OP(movem, 32, re, .)
\r
7150 uint register_list = OPER_I_16();
\r
7151 uint ea = M68KMAKE_GET_EA_AY_32;
\r
7154 for(; i < 16; i++)
\r
7155 if(register_list & (1 << i))
\r
7157 m68ki_write_32(ea, REG_DA[i]);
\r
7162 USE_CYCLES(count<<CYC_MOVEM_L);
\r
7166 M68KMAKE_OP(movem, 16, er, pi)
\r
7169 uint register_list = OPER_I_16();
\r
7173 for(; i < 16; i++)
\r
7174 if(register_list & (1 << i))
\r
7176 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
\r
7182 USE_CYCLES(count<<CYC_MOVEM_W);
\r
7186 M68KMAKE_OP(movem, 16, er, pcdi)
\r
7189 uint register_list = OPER_I_16();
\r
7190 uint ea = EA_PCDI_16();
\r
7193 for(; i < 16; i++)
\r
7194 if(register_list & (1 << i))
\r
7196 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));
\r
7201 USE_CYCLES(count<<CYC_MOVEM_W);
\r
7205 M68KMAKE_OP(movem, 16, er, pcix)
\r
7208 uint register_list = OPER_I_16();
\r
7209 uint ea = EA_PCIX_16();
\r
7212 for(; i < 16; i++)
\r
7213 if(register_list & (1 << i))
\r
7215 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));
\r
7220 USE_CYCLES(count<<CYC_MOVEM_W);
\r
7224 M68KMAKE_OP(movem, 16, er, .)
\r
7227 uint register_list = OPER_I_16();
\r
7228 uint ea = M68KMAKE_GET_EA_AY_16;
\r
7231 for(; i < 16; i++)
\r
7232 if(register_list & (1 << i))
\r
7234 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
\r
7239 USE_CYCLES(count<<CYC_MOVEM_W);
\r
7243 M68KMAKE_OP(movem, 32, er, pi)
\r
7246 uint register_list = OPER_I_16();
\r
7250 for(; i < 16; i++)
\r
7251 if(register_list & (1 << i))
\r
7253 REG_DA[i] = m68ki_read_32(ea);
\r
7259 USE_CYCLES(count<<CYC_MOVEM_L);
\r
7263 M68KMAKE_OP(movem, 32, er, pcdi)
\r
7266 uint register_list = OPER_I_16();
\r
7267 uint ea = EA_PCDI_32();
\r
7270 for(; i < 16; i++)
\r
7271 if(register_list & (1 << i))
\r
7273 REG_DA[i] = m68ki_read_pcrel_32(ea);
\r
7278 USE_CYCLES(count<<CYC_MOVEM_L);
\r
7282 M68KMAKE_OP(movem, 32, er, pcix)
\r
7285 uint register_list = OPER_I_16();
\r
7286 uint ea = EA_PCIX_32();
\r
7289 for(; i < 16; i++)
\r
7290 if(register_list & (1 << i))
\r
7292 REG_DA[i] = m68ki_read_pcrel_32(ea);
\r
7297 USE_CYCLES(count<<CYC_MOVEM_L);
\r
7301 M68KMAKE_OP(movem, 32, er, .)
\r
7304 uint register_list = OPER_I_16();
\r
7305 uint ea = M68KMAKE_GET_EA_AY_32;
\r
7308 for(; i < 16; i++)
\r
7309 if(register_list & (1 << i))
\r
7311 REG_DA[i] = m68ki_read_32(ea);
\r
7316 USE_CYCLES(count<<CYC_MOVEM_L);
\r
7320 M68KMAKE_OP(movep, 16, re, .)
\r
7322 uint ea = EA_AY_DI_16();
\r
7325 m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 8));
\r
7326 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));
\r
7330 M68KMAKE_OP(movep, 32, re, .)
\r
7332 uint ea = EA_AY_DI_32();
\r
7335 m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 24));
\r
7336 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 16));
\r
7337 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 8));
\r
7338 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));
\r
7342 M68KMAKE_OP(movep, 16, er, .)
\r
7344 uint ea = EA_AY_DI_16();
\r
7345 uint* r_dst = &DX;
\r
7347 *r_dst = MASK_OUT_BELOW_16(*r_dst) | ((m68ki_read_8(ea) << 8) + m68ki_read_8(ea + 2));
\r
7351 M68KMAKE_OP(movep, 32, er, .)
\r
7353 uint ea = EA_AY_DI_32();
\r
7355 DX = (m68ki_read_8(ea) << 24) + (m68ki_read_8(ea + 2) << 16)
\r
7356 + (m68ki_read_8(ea + 4) << 8) + m68ki_read_8(ea + 6);
\r
7360 M68KMAKE_OP(moves, 8, ., .)
\r
7362 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
7366 uint word2 = OPER_I_16();
\r
7367 uint ea = M68KMAKE_GET_EA_AY_8;
\r
7369 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
7370 if(BIT_B(word2)) /* Register to memory */
\r
7372 m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));
\r
7375 if(BIT_F(word2)) /* Memory to address register */
\r
7377 REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC));
\r
7378 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
7382 /* Memory to data register */
\r
7383 REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC);
\r
7384 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
7388 m68ki_exception_privilege_violation();
\r
7391 m68ki_exception_illegal();
\r
7395 M68KMAKE_OP(moves, 16, ., .)
\r
7397 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
7401 uint word2 = OPER_I_16();
\r
7402 uint ea = M68KMAKE_GET_EA_AY_16;
\r
7404 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
7405 if(BIT_B(word2)) /* Register to memory */
\r
7407 m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15]));
\r
7410 if(BIT_F(word2)) /* Memory to address register */
\r
7412 REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC));
\r
7413 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
7417 /* Memory to data register */
\r
7418 REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC);
\r
7419 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
7423 m68ki_exception_privilege_violation();
\r
7426 m68ki_exception_illegal();
\r
7430 M68KMAKE_OP(moves, 32, ., .)
\r
7432 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
7436 uint word2 = OPER_I_16();
\r
7437 uint ea = M68KMAKE_GET_EA_AY_32;
\r
7439 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
7440 if(BIT_B(word2)) /* Register to memory */
\r
7442 m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]);
\r
7443 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
7447 /* Memory to register */
\r
7448 REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC);
\r
7449 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
7453 m68ki_exception_privilege_violation();
\r
7456 m68ki_exception_illegal();
\r
7460 M68KMAKE_OP(moveq, 32, ., .)
\r
7462 uint res = DX = MAKE_INT_8(MASK_OUT_ABOVE_8(REG_IR));
\r
7464 FLAG_N = NFLAG_32(res);
\r
7466 FLAG_V = VFLAG_CLEAR;
\r
7467 FLAG_C = CFLAG_CLEAR;
\r
7471 M68KMAKE_OP(move16, 32, ., .)
\r
7473 UINT16 w2 = OPER_I_16();
\r
7474 int ax = REG_IR & 7;
\r
7475 int ay = (w2 >> 12) & 7;
\r
7477 m68ki_write_32(REG_A[ay], m68ki_read_32(REG_A[ax]));
\r
7478 m68ki_write_32(REG_A[ay]+4, m68ki_read_32(REG_A[ax]+4));
\r
7479 m68ki_write_32(REG_A[ay]+8, m68ki_read_32(REG_A[ax]+8));
\r
7480 m68ki_write_32(REG_A[ay]+12, m68ki_read_32(REG_A[ax]+12));
\r
7487 M68KMAKE_OP(muls, 16, ., d)
\r
7489 uint* r_dst = &DX;
\r
7490 uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(DY) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
\r
7495 FLAG_N = NFLAG_32(res);
\r
7496 FLAG_V = VFLAG_CLEAR;
\r
7497 FLAG_C = CFLAG_CLEAR;
\r
7501 M68KMAKE_OP(muls, 16, ., .)
\r
7503 uint* r_dst = &DX;
\r
7504 uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(M68KMAKE_GET_OPER_AY_16) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
\r
7509 FLAG_N = NFLAG_32(res);
\r
7510 FLAG_V = VFLAG_CLEAR;
\r
7511 FLAG_C = CFLAG_CLEAR;
\r
7515 M68KMAKE_OP(mulu, 16, ., d)
\r
7517 uint* r_dst = &DX;
\r
7518 uint res = MASK_OUT_ABOVE_16(DY) * MASK_OUT_ABOVE_16(*r_dst);
\r
7523 FLAG_N = NFLAG_32(res);
\r
7524 FLAG_V = VFLAG_CLEAR;
\r
7525 FLAG_C = CFLAG_CLEAR;
\r
7529 M68KMAKE_OP(mulu, 16, ., .)
\r
7531 uint* r_dst = &DX;
\r
7532 uint res = M68KMAKE_GET_OPER_AY_16 * MASK_OUT_ABOVE_16(*r_dst);
\r
7537 FLAG_N = NFLAG_32(res);
\r
7538 FLAG_V = VFLAG_CLEAR;
\r
7539 FLAG_C = CFLAG_CLEAR;
\r
7543 M68KMAKE_OP(mull, 32, ., d)
\r
7545 #if M68K_USE_64_BIT
\r
7547 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
7549 uint word2 = OPER_I_16();
\r
7551 uint64 dst = REG_D[(word2 >> 12) & 7];
\r
7554 FLAG_C = CFLAG_CLEAR;
\r
7556 if(BIT_B(word2)) /* signed */
\r
7558 res = (sint64)((sint32)src) * (sint64)((sint32)dst);
\r
7561 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
7562 FLAG_N = NFLAG_32(res);
\r
7563 FLAG_V = ((sint64)res != (sint32)res)<<7;
\r
7564 REG_D[(word2 >> 12) & 7] = FLAG_Z;
\r
7567 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
\r
7568 FLAG_N = NFLAG_64(res);
\r
7569 FLAG_V = VFLAG_CLEAR;
\r
7570 REG_D[word2 & 7] = (res >> 32);
\r
7571 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
\r
7578 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
7579 FLAG_N = NFLAG_32(res);
\r
7580 FLAG_V = (res > 0xffffffff)<<7;
\r
7581 REG_D[(word2 >> 12) & 7] = FLAG_Z;
\r
7584 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
\r
7585 FLAG_N = NFLAG_64(res);
\r
7586 FLAG_V = VFLAG_CLEAR;
\r
7587 REG_D[word2 & 7] = (res >> 32);
\r
7588 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
\r
7591 m68ki_exception_illegal();
\r
7595 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
7597 uint word2 = OPER_I_16();
\r
7599 uint dst = REG_D[(word2 >> 12) & 7];
\r
7600 uint neg = GET_MSB_32(src ^ dst);
\r
7612 FLAG_C = CFLAG_CLEAR;
\r
7614 if(BIT_B(word2)) /* signed */
\r
7616 if(GET_MSB_32(src))
\r
7617 src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
\r
7618 if(GET_MSB_32(dst))
\r
7619 dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
\r
7622 src1 = MASK_OUT_ABOVE_16(src);
\r
7624 dst1 = MASK_OUT_ABOVE_16(dst);
\r
7633 lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
\r
7634 hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
\r
7636 if(BIT_B(word2) && neg)
\r
7638 hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
\r
7639 lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
\r
7644 REG_D[word2 & 7] = hi;
\r
7645 REG_D[(word2 >> 12) & 7] = lo;
\r
7646 FLAG_N = NFLAG_32(hi);
\r
7648 FLAG_V = VFLAG_CLEAR;
\r
7652 REG_D[(word2 >> 12) & 7] = lo;
\r
7653 FLAG_N = NFLAG_32(lo);
\r
7656 FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
\r
7658 FLAG_V = (hi != 0) << 7;
\r
7661 m68ki_exception_illegal();
\r
7667 M68KMAKE_OP(mull, 32, ., .)
\r
7669 #if M68K_USE_64_BIT
\r
7671 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
7673 uint word2 = OPER_I_16();
\r
7674 uint64 src = M68KMAKE_GET_OPER_AY_32;
\r
7675 uint64 dst = REG_D[(word2 >> 12) & 7];
\r
7678 FLAG_C = CFLAG_CLEAR;
\r
7680 if(BIT_B(word2)) /* signed */
\r
7682 res = (sint64)((sint32)src) * (sint64)((sint32)dst);
\r
7685 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
7686 FLAG_N = NFLAG_32(res);
\r
7687 FLAG_V = ((sint64)res != (sint32)res)<<7;
\r
7688 REG_D[(word2 >> 12) & 7] = FLAG_Z;
\r
7691 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
\r
7692 FLAG_N = NFLAG_64(res);
\r
7693 FLAG_V = VFLAG_CLEAR;
\r
7694 REG_D[word2 & 7] = (res >> 32);
\r
7695 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
\r
7702 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
7703 FLAG_N = NFLAG_32(res);
\r
7704 FLAG_V = (res > 0xffffffff)<<7;
\r
7705 REG_D[(word2 >> 12) & 7] = FLAG_Z;
\r
7708 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
\r
7709 FLAG_N = NFLAG_64(res);
\r
7710 FLAG_V = VFLAG_CLEAR;
\r
7711 REG_D[word2 & 7] = (res >> 32);
\r
7712 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
\r
7715 m68ki_exception_illegal();
\r
7719 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
7721 uint word2 = OPER_I_16();
\r
7722 uint src = M68KMAKE_GET_OPER_AY_32;
\r
7723 uint dst = REG_D[(word2 >> 12) & 7];
\r
7724 uint neg = GET_MSB_32(src ^ dst);
\r
7736 FLAG_C = CFLAG_CLEAR;
\r
7738 if(BIT_B(word2)) /* signed */
\r
7740 if(GET_MSB_32(src))
\r
7741 src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
\r
7742 if(GET_MSB_32(dst))
\r
7743 dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
\r
7746 src1 = MASK_OUT_ABOVE_16(src);
\r
7748 dst1 = MASK_OUT_ABOVE_16(dst);
\r
7757 lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
\r
7758 hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
\r
7760 if(BIT_B(word2) && neg)
\r
7762 hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
\r
7763 lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
\r
7768 REG_D[word2 & 7] = hi;
\r
7769 REG_D[(word2 >> 12) & 7] = lo;
\r
7770 FLAG_N = NFLAG_32(hi);
\r
7772 FLAG_V = VFLAG_CLEAR;
\r
7776 REG_D[(word2 >> 12) & 7] = lo;
\r
7777 FLAG_N = NFLAG_32(lo);
\r
7780 FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
\r
7782 FLAG_V = (hi != 0) << 7;
\r
7785 m68ki_exception_illegal();
\r
7791 M68KMAKE_OP(nbcd, 8, ., d)
\r
7793 uint* r_dst = &DY;
\r
7794 uint dst = *r_dst;
\r
7795 uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());
\r
7799 FLAG_V = ~res; /* Undefined V behavior */
\r
7801 if((res & 0x0f) == 0xa)
\r
7802 res = (res & 0xf0) + 0x10;
\r
7804 res = MASK_OUT_ABOVE_8(res);
\r
7806 FLAG_V &= res; /* Undefined V behavior part II */
\r
7808 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
7811 FLAG_C = CFLAG_SET;
\r
7812 FLAG_X = XFLAG_SET;
\r
7816 FLAG_V = VFLAG_CLEAR;
\r
7817 FLAG_C = CFLAG_CLEAR;
\r
7818 FLAG_X = XFLAG_CLEAR;
\r
7820 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
7824 M68KMAKE_OP(nbcd, 8, ., .)
\r
7826 uint ea = M68KMAKE_GET_EA_AY_8;
\r
7827 uint dst = m68ki_read_8(ea);
\r
7828 uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());
\r
7832 FLAG_V = ~res; /* Undefined V behavior */
\r
7834 if((res & 0x0f) == 0xa)
\r
7835 res = (res & 0xf0) + 0x10;
\r
7837 res = MASK_OUT_ABOVE_8(res);
\r
7839 FLAG_V &= res; /* Undefined V behavior part II */
\r
7841 m68ki_write_8(ea, MASK_OUT_ABOVE_8(res));
\r
7844 FLAG_C = CFLAG_SET;
\r
7845 FLAG_X = XFLAG_SET;
\r
7849 FLAG_V = VFLAG_CLEAR;
\r
7850 FLAG_C = CFLAG_CLEAR;
\r
7851 FLAG_X = XFLAG_CLEAR;
\r
7853 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
7857 M68KMAKE_OP(neg, 8, ., d)
\r
7859 uint* r_dst = &DY;
\r
7860 uint res = 0 - MASK_OUT_ABOVE_8(*r_dst);
\r
7862 FLAG_N = NFLAG_8(res);
\r
7863 FLAG_C = FLAG_X = CFLAG_8(res);
\r
7864 FLAG_V = *r_dst & res;
\r
7865 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
7867 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
7871 M68KMAKE_OP(neg, 8, ., .)
\r
7873 uint ea = M68KMAKE_GET_EA_AY_8;
\r
7874 uint src = m68ki_read_8(ea);
\r
7875 uint res = 0 - src;
\r
7877 FLAG_N = NFLAG_8(res);
\r
7878 FLAG_C = FLAG_X = CFLAG_8(res);
\r
7879 FLAG_V = src & res;
\r
7880 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
7882 m68ki_write_8(ea, FLAG_Z);
\r
7886 M68KMAKE_OP(neg, 16, ., d)
\r
7888 uint* r_dst = &DY;
\r
7889 uint res = 0 - MASK_OUT_ABOVE_16(*r_dst);
\r
7891 FLAG_N = NFLAG_16(res);
\r
7892 FLAG_C = FLAG_X = CFLAG_16(res);
\r
7893 FLAG_V = (*r_dst & res)>>8;
\r
7894 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
7896 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
7900 M68KMAKE_OP(neg, 16, ., .)
\r
7902 uint ea = M68KMAKE_GET_EA_AY_16;
\r
7903 uint src = m68ki_read_16(ea);
\r
7904 uint res = 0 - src;
\r
7906 FLAG_N = NFLAG_16(res);
\r
7907 FLAG_C = FLAG_X = CFLAG_16(res);
\r
7908 FLAG_V = (src & res)>>8;
\r
7909 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
7911 m68ki_write_16(ea, FLAG_Z);
\r
7915 M68KMAKE_OP(neg, 32, ., d)
\r
7917 uint* r_dst = &DY;
\r
7918 uint res = 0 - *r_dst;
\r
7920 FLAG_N = NFLAG_32(res);
\r
7921 FLAG_C = FLAG_X = CFLAG_SUB_32(*r_dst, 0, res);
\r
7922 FLAG_V = (*r_dst & res)>>24;
\r
7923 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
7929 M68KMAKE_OP(neg, 32, ., .)
\r
7931 uint ea = M68KMAKE_GET_EA_AY_32;
\r
7932 uint src = m68ki_read_32(ea);
\r
7933 uint res = 0 - src;
\r
7935 FLAG_N = NFLAG_32(res);
\r
7936 FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
\r
7937 FLAG_V = (src & res)>>24;
\r
7938 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
7940 m68ki_write_32(ea, FLAG_Z);
\r
7944 M68KMAKE_OP(negx, 8, ., d)
\r
7946 uint* r_dst = &DY;
\r
7947 uint res = 0 - MASK_OUT_ABOVE_8(*r_dst) - XFLAG_AS_1();
\r
7949 FLAG_N = NFLAG_8(res);
\r
7950 FLAG_X = FLAG_C = CFLAG_8(res);
\r
7951 FLAG_V = *r_dst & res;
\r
7953 res = MASK_OUT_ABOVE_8(res);
\r
7956 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
7960 M68KMAKE_OP(negx, 8, ., .)
\r
7962 uint ea = M68KMAKE_GET_EA_AY_8;
\r
7963 uint src = m68ki_read_8(ea);
\r
7964 uint res = 0 - src - XFLAG_AS_1();
\r
7966 FLAG_N = NFLAG_8(res);
\r
7967 FLAG_X = FLAG_C = CFLAG_8(res);
\r
7968 FLAG_V = src & res;
\r
7970 res = MASK_OUT_ABOVE_8(res);
\r
7973 m68ki_write_8(ea, res);
\r
7977 M68KMAKE_OP(negx, 16, ., d)
\r
7979 uint* r_dst = &DY;
\r
7980 uint res = 0 - MASK_OUT_ABOVE_16(*r_dst) - XFLAG_AS_1();
\r
7982 FLAG_N = NFLAG_16(res);
\r
7983 FLAG_X = FLAG_C = CFLAG_16(res);
\r
7984 FLAG_V = (*r_dst & res)>>8;
\r
7986 res = MASK_OUT_ABOVE_16(res);
\r
7989 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
7993 M68KMAKE_OP(negx, 16, ., .)
\r
7995 uint ea = M68KMAKE_GET_EA_AY_16;
\r
7996 uint src = m68ki_read_16(ea);
\r
7997 uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
\r
7999 FLAG_N = NFLAG_16(res);
\r
8000 FLAG_X = FLAG_C = CFLAG_16(res);
\r
8001 FLAG_V = (src & res)>>8;
\r
8003 res = MASK_OUT_ABOVE_16(res);
\r
8006 m68ki_write_16(ea, res);
\r
8010 M68KMAKE_OP(negx, 32, ., d)
\r
8012 uint* r_dst = &DY;
\r
8013 uint res = 0 - MASK_OUT_ABOVE_32(*r_dst) - XFLAG_AS_1();
\r
8015 FLAG_N = NFLAG_32(res);
\r
8016 FLAG_X = FLAG_C = CFLAG_SUB_32(*r_dst, 0, res);
\r
8017 FLAG_V = (*r_dst & res)>>24;
\r
8019 res = MASK_OUT_ABOVE_32(res);
\r
8026 M68KMAKE_OP(negx, 32, ., .)
\r
8028 uint ea = M68KMAKE_GET_EA_AY_32;
\r
8029 uint src = m68ki_read_32(ea);
\r
8030 uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
\r
8032 FLAG_N = NFLAG_32(res);
\r
8033 FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
\r
8034 FLAG_V = (src & res)>>24;
\r
8036 res = MASK_OUT_ABOVE_32(res);
\r
8039 m68ki_write_32(ea, res);
\r
8043 M68KMAKE_OP(nop, 0, ., .)
\r
8045 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
8049 M68KMAKE_OP(not, 8, ., d)
\r
8051 uint* r_dst = &DY;
\r
8052 uint res = MASK_OUT_ABOVE_8(~*r_dst);
\r
8054 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8056 FLAG_N = NFLAG_8(res);
\r
8058 FLAG_C = CFLAG_CLEAR;
\r
8059 FLAG_V = VFLAG_CLEAR;
\r
8063 M68KMAKE_OP(not, 8, ., .)
\r
8065 uint ea = M68KMAKE_GET_EA_AY_8;
\r
8066 uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
\r
8068 m68ki_write_8(ea, res);
\r
8070 FLAG_N = NFLAG_8(res);
\r
8072 FLAG_C = CFLAG_CLEAR;
\r
8073 FLAG_V = VFLAG_CLEAR;
\r
8077 M68KMAKE_OP(not, 16, ., d)
\r
8079 uint* r_dst = &DY;
\r
8080 uint res = MASK_OUT_ABOVE_16(~*r_dst);
\r
8082 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8084 FLAG_N = NFLAG_16(res);
\r
8086 FLAG_C = CFLAG_CLEAR;
\r
8087 FLAG_V = VFLAG_CLEAR;
\r
8091 M68KMAKE_OP(not, 16, ., .)
\r
8093 uint ea = M68KMAKE_GET_EA_AY_16;
\r
8094 uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
\r
8096 m68ki_write_16(ea, res);
\r
8098 FLAG_N = NFLAG_16(res);
\r
8100 FLAG_C = CFLAG_CLEAR;
\r
8101 FLAG_V = VFLAG_CLEAR;
\r
8105 M68KMAKE_OP(not, 32, ., d)
\r
8107 uint* r_dst = &DY;
\r
8108 uint res = *r_dst = MASK_OUT_ABOVE_32(~*r_dst);
\r
8110 FLAG_N = NFLAG_32(res);
\r
8112 FLAG_C = CFLAG_CLEAR;
\r
8113 FLAG_V = VFLAG_CLEAR;
\r
8117 M68KMAKE_OP(not, 32, ., .)
\r
8119 uint ea = M68KMAKE_GET_EA_AY_32;
\r
8120 uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
\r
8122 m68ki_write_32(ea, res);
\r
8124 FLAG_N = NFLAG_32(res);
\r
8126 FLAG_C = CFLAG_CLEAR;
\r
8127 FLAG_V = VFLAG_CLEAR;
\r
8131 M68KMAKE_OP(or, 8, er, d)
\r
8133 uint res = MASK_OUT_ABOVE_8((DX |= MASK_OUT_ABOVE_8(DY)));
\r
8135 FLAG_N = NFLAG_8(res);
\r
8137 FLAG_C = CFLAG_CLEAR;
\r
8138 FLAG_V = VFLAG_CLEAR;
\r
8142 M68KMAKE_OP(or, 8, er, .)
\r
8144 uint res = MASK_OUT_ABOVE_8((DX |= M68KMAKE_GET_OPER_AY_8));
\r
8146 FLAG_N = NFLAG_8(res);
\r
8148 FLAG_C = CFLAG_CLEAR;
\r
8149 FLAG_V = VFLAG_CLEAR;
\r
8153 M68KMAKE_OP(or, 16, er, d)
\r
8155 uint res = MASK_OUT_ABOVE_16((DX |= MASK_OUT_ABOVE_16(DY)));
\r
8157 FLAG_N = NFLAG_16(res);
\r
8159 FLAG_C = CFLAG_CLEAR;
\r
8160 FLAG_V = VFLAG_CLEAR;
\r
8164 M68KMAKE_OP(or, 16, er, .)
\r
8166 uint res = MASK_OUT_ABOVE_16((DX |= M68KMAKE_GET_OPER_AY_16));
\r
8168 FLAG_N = NFLAG_16(res);
\r
8170 FLAG_C = CFLAG_CLEAR;
\r
8171 FLAG_V = VFLAG_CLEAR;
\r
8175 M68KMAKE_OP(or, 32, er, d)
\r
8177 uint res = DX |= DY;
\r
8179 FLAG_N = NFLAG_32(res);
\r
8181 FLAG_C = CFLAG_CLEAR;
\r
8182 FLAG_V = VFLAG_CLEAR;
\r
8186 M68KMAKE_OP(or, 32, er, .)
\r
8188 uint res = DX |= M68KMAKE_GET_OPER_AY_32;
\r
8190 FLAG_N = NFLAG_32(res);
\r
8192 FLAG_C = CFLAG_CLEAR;
\r
8193 FLAG_V = VFLAG_CLEAR;
\r
8197 M68KMAKE_OP(or, 8, re, .)
\r
8199 uint ea = M68KMAKE_GET_EA_AY_8;
\r
8200 uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
\r
8202 m68ki_write_8(ea, res);
\r
8204 FLAG_N = NFLAG_8(res);
\r
8206 FLAG_C = CFLAG_CLEAR;
\r
8207 FLAG_V = VFLAG_CLEAR;
\r
8211 M68KMAKE_OP(or, 16, re, .)
\r
8213 uint ea = M68KMAKE_GET_EA_AY_16;
\r
8214 uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
\r
8216 m68ki_write_16(ea, res);
\r
8218 FLAG_N = NFLAG_16(res);
\r
8220 FLAG_C = CFLAG_CLEAR;
\r
8221 FLAG_V = VFLAG_CLEAR;
\r
8225 M68KMAKE_OP(or, 32, re, .)
\r
8227 uint ea = M68KMAKE_GET_EA_AY_32;
\r
8228 uint res = DX | m68ki_read_32(ea);
\r
8230 m68ki_write_32(ea, res);
\r
8232 FLAG_N = NFLAG_32(res);
\r
8234 FLAG_C = CFLAG_CLEAR;
\r
8235 FLAG_V = VFLAG_CLEAR;
\r
8239 M68KMAKE_OP(ori, 8, ., d)
\r
8241 uint res = MASK_OUT_ABOVE_8((DY |= OPER_I_8()));
\r
8243 FLAG_N = NFLAG_8(res);
\r
8245 FLAG_C = CFLAG_CLEAR;
\r
8246 FLAG_V = VFLAG_CLEAR;
\r
8250 M68KMAKE_OP(ori, 8, ., .)
\r
8252 uint src = OPER_I_8();
\r
8253 uint ea = M68KMAKE_GET_EA_AY_8;
\r
8254 uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
\r
8256 m68ki_write_8(ea, res);
\r
8258 FLAG_N = NFLAG_8(res);
\r
8260 FLAG_C = CFLAG_CLEAR;
\r
8261 FLAG_V = VFLAG_CLEAR;
\r
8265 M68KMAKE_OP(ori, 16, ., d)
\r
8267 uint res = MASK_OUT_ABOVE_16(DY |= OPER_I_16());
\r
8269 FLAG_N = NFLAG_16(res);
\r
8271 FLAG_C = CFLAG_CLEAR;
\r
8272 FLAG_V = VFLAG_CLEAR;
\r
8276 M68KMAKE_OP(ori, 16, ., .)
\r
8278 uint src = OPER_I_16();
\r
8279 uint ea = M68KMAKE_GET_EA_AY_16;
\r
8280 uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
\r
8282 m68ki_write_16(ea, res);
\r
8284 FLAG_N = NFLAG_16(res);
\r
8286 FLAG_C = CFLAG_CLEAR;
\r
8287 FLAG_V = VFLAG_CLEAR;
\r
8291 M68KMAKE_OP(ori, 32, ., d)
\r
8293 uint res = DY |= OPER_I_32();
\r
8295 FLAG_N = NFLAG_32(res);
\r
8297 FLAG_C = CFLAG_CLEAR;
\r
8298 FLAG_V = VFLAG_CLEAR;
\r
8302 M68KMAKE_OP(ori, 32, ., .)
\r
8304 uint src = OPER_I_32();
\r
8305 uint ea = M68KMAKE_GET_EA_AY_32;
\r
8306 uint res = src | m68ki_read_32(ea);
\r
8308 m68ki_write_32(ea, res);
\r
8310 FLAG_N = NFLAG_32(res);
\r
8312 FLAG_C = CFLAG_CLEAR;
\r
8313 FLAG_V = VFLAG_CLEAR;
\r
8317 M68KMAKE_OP(ori, 16, toc, .)
\r
8319 m68ki_set_ccr(m68ki_get_ccr() | OPER_I_16());
\r
8323 M68KMAKE_OP(ori, 16, tos, .)
\r
8327 uint src = OPER_I_16();
\r
8328 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
8329 m68ki_set_sr(m68ki_get_sr() | src);
\r
8332 m68ki_exception_privilege_violation();
\r
8336 M68KMAKE_OP(pack, 16, rr, .)
\r
8338 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
8340 /* Note: DX and DY are reversed in Motorola's docs */
\r
8341 uint src = DY + OPER_I_16();
\r
8342 uint* r_dst = &DX;
\r
8344 *r_dst = MASK_OUT_BELOW_8(*r_dst) | ((src >> 4) & 0x00f0) | (src & 0x000f);
\r
8347 m68ki_exception_illegal();
\r
8351 M68KMAKE_OP(pack, 16, mm, ax7)
\r
8353 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
8355 /* Note: AX and AY are reversed in Motorola's docs */
\r
8356 uint ea_src = EA_AY_PD_8();
\r
8357 uint src = m68ki_read_8(ea_src);
\r
8358 ea_src = EA_AY_PD_8();
\r
8359 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
\r
8361 m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
\r
8364 m68ki_exception_illegal();
\r
8368 M68KMAKE_OP(pack, 16, mm, ay7)
\r
8370 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
8372 /* Note: AX and AY are reversed in Motorola's docs */
\r
8373 uint ea_src = EA_A7_PD_8();
\r
8374 uint src = m68ki_read_8(ea_src);
\r
8375 ea_src = EA_A7_PD_8();
\r
8376 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
\r
8378 m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
\r
8381 m68ki_exception_illegal();
\r
8385 M68KMAKE_OP(pack, 16, mm, axy7)
\r
8387 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
8389 uint ea_src = EA_A7_PD_8();
\r
8390 uint src = m68ki_read_8(ea_src);
\r
8391 ea_src = EA_A7_PD_8();
\r
8392 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
\r
8394 m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
\r
8397 m68ki_exception_illegal();
\r
8401 M68KMAKE_OP(pack, 16, mm, .)
\r
8403 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
8405 /* Note: AX and AY are reversed in Motorola's docs */
\r
8406 uint ea_src = EA_AY_PD_8();
\r
8407 uint src = m68ki_read_8(ea_src);
\r
8408 ea_src = EA_AY_PD_8();
\r
8409 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
\r
8411 m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
\r
8414 m68ki_exception_illegal();
\r
8418 M68KMAKE_OP(pea, 32, ., .)
\r
8420 uint ea = M68KMAKE_GET_EA_AY_32;
\r
8422 m68ki_push_32(ea);
\r
8426 M68KMAKE_OP(pflush, 32, ., .)
\r
8428 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
8430 // Nothing to do, unless address translation cache is emulated
\r
8433 m68ki_exception_illegal();
\r
8437 M68KMAKE_OP(reset, 0, ., .)
\r
8441 m68ki_output_reset(); /* auto-disable (see m68kcpu.h) */
\r
8442 USE_CYCLES(CYC_RESET);
\r
8445 m68ki_exception_privilege_violation();
\r
8449 M68KMAKE_OP(ror, 8, s, .)
\r
8451 uint* r_dst = &DY;
\r
8452 uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8453 uint shift = orig_shift & 7;
\r
8454 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
8455 uint res = ROR_8(src, shift);
\r
8457 if(orig_shift != 0)
\r
8458 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8460 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8462 FLAG_N = NFLAG_8(res);
\r
8464 FLAG_C = src << (9-orig_shift);
\r
8465 FLAG_V = VFLAG_CLEAR;
\r
8469 M68KMAKE_OP(ror, 16, s, .)
\r
8471 uint* r_dst = &DY;
\r
8472 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8473 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
8474 uint res = ROR_16(src, shift);
\r
8477 USE_CYCLES(shift<<CYC_SHIFT);
\r
8479 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8481 FLAG_N = NFLAG_16(res);
\r
8483 FLAG_C = src << (9-shift);
\r
8484 FLAG_V = VFLAG_CLEAR;
\r
8488 M68KMAKE_OP(ror, 32, s, .)
\r
8490 uint* r_dst = &DY;
\r
8491 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8492 uint64 src = *r_dst;
\r
8493 uint res = ROR_32(src, shift);
\r
8496 USE_CYCLES(shift<<CYC_SHIFT);
\r
8500 FLAG_N = NFLAG_32(res);
\r
8502 FLAG_C = src << (9-shift);
\r
8503 FLAG_V = VFLAG_CLEAR;
\r
8507 M68KMAKE_OP(ror, 8, r, .)
\r
8509 uint* r_dst = &DY;
\r
8510 uint orig_shift = DX & 0x3f;
\r
8511 uint shift = orig_shift & 7;
\r
8512 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
8513 uint res = ROR_8(src, shift);
\r
8515 if(orig_shift != 0)
\r
8517 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8519 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8520 FLAG_C = src << (8-((shift-1)&7));
\r
8521 FLAG_N = NFLAG_8(res);
\r
8523 FLAG_V = VFLAG_CLEAR;
\r
8527 FLAG_C = CFLAG_CLEAR;
\r
8528 FLAG_N = NFLAG_8(src);
\r
8530 FLAG_V = VFLAG_CLEAR;
\r
8534 M68KMAKE_OP(ror, 16, r, .)
\r
8536 uint* r_dst = &DY;
\r
8537 uint orig_shift = DX & 0x3f;
\r
8538 uint shift = orig_shift & 15;
\r
8539 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
8540 uint res = ROR_16(src, shift);
\r
8542 if(orig_shift != 0)
\r
8544 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8546 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8547 FLAG_C = (src >> ((shift - 1) & 15)) << 8;
\r
8548 FLAG_N = NFLAG_16(res);
\r
8550 FLAG_V = VFLAG_CLEAR;
\r
8554 FLAG_C = CFLAG_CLEAR;
\r
8555 FLAG_N = NFLAG_16(src);
\r
8557 FLAG_V = VFLAG_CLEAR;
\r
8561 M68KMAKE_OP(ror, 32, r, .)
\r
8563 uint* r_dst = &DY;
\r
8564 uint orig_shift = DX & 0x3f;
\r
8565 uint shift = orig_shift & 31;
\r
8566 uint64 src = *r_dst;
\r
8567 uint res = ROR_32(src, shift);
\r
8569 if(orig_shift != 0)
\r
8571 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8574 FLAG_C = (src >> ((shift - 1) & 31)) << 8;
\r
8575 FLAG_N = NFLAG_32(res);
\r
8577 FLAG_V = VFLAG_CLEAR;
\r
8581 FLAG_C = CFLAG_CLEAR;
\r
8582 FLAG_N = NFLAG_32(src);
\r
8584 FLAG_V = VFLAG_CLEAR;
\r
8588 M68KMAKE_OP(ror, 16, ., .)
\r
8590 uint ea = M68KMAKE_GET_EA_AY_16;
\r
8591 uint src = m68ki_read_16(ea);
\r
8592 uint res = ROR_16(src, 1);
\r
8594 m68ki_write_16(ea, res);
\r
8596 FLAG_N = NFLAG_16(res);
\r
8598 FLAG_C = src << 8;
\r
8599 FLAG_V = VFLAG_CLEAR;
\r
8603 M68KMAKE_OP(rol, 8, s, .)
\r
8605 uint* r_dst = &DY;
\r
8606 uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8607 uint shift = orig_shift & 7;
\r
8608 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
8609 uint res = ROL_8(src, shift);
\r
8611 if(orig_shift != 0)
\r
8612 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8614 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8616 FLAG_N = NFLAG_8(res);
\r
8618 FLAG_C = src << orig_shift;
\r
8619 FLAG_V = VFLAG_CLEAR;
\r
8623 M68KMAKE_OP(rol, 16, s, .)
\r
8625 uint* r_dst = &DY;
\r
8626 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8627 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
8628 uint res = ROL_16(src, shift);
\r
8631 USE_CYCLES(shift<<CYC_SHIFT);
\r
8633 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8635 FLAG_N = NFLAG_16(res);
\r
8637 FLAG_C = src >> (8-shift);
\r
8638 FLAG_V = VFLAG_CLEAR;
\r
8642 M68KMAKE_OP(rol, 32, s, .)
\r
8644 uint* r_dst = &DY;
\r
8645 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8646 uint64 src = *r_dst;
\r
8647 uint res = ROL_32(src, shift);
\r
8650 USE_CYCLES(shift<<CYC_SHIFT);
\r
8654 FLAG_N = NFLAG_32(res);
\r
8656 FLAG_C = src >> (24-shift);
\r
8657 FLAG_V = VFLAG_CLEAR;
\r
8661 M68KMAKE_OP(rol, 8, r, .)
\r
8663 uint* r_dst = &DY;
\r
8664 uint orig_shift = DX & 0x3f;
\r
8665 uint shift = orig_shift & 7;
\r
8666 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
8667 uint res = ROL_8(src, shift);
\r
8669 if(orig_shift != 0)
\r
8671 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8675 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8676 FLAG_C = src << shift;
\r
8677 FLAG_N = NFLAG_8(res);
\r
8679 FLAG_V = VFLAG_CLEAR;
\r
8682 FLAG_C = (src & 1)<<8;
\r
8683 FLAG_N = NFLAG_8(src);
\r
8685 FLAG_V = VFLAG_CLEAR;
\r
8689 FLAG_C = CFLAG_CLEAR;
\r
8690 FLAG_N = NFLAG_8(src);
\r
8692 FLAG_V = VFLAG_CLEAR;
\r
8696 M68KMAKE_OP(rol, 16, r, .)
\r
8698 uint* r_dst = &DY;
\r
8699 uint orig_shift = DX & 0x3f;
\r
8700 uint shift = orig_shift & 15;
\r
8701 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
8702 uint res = MASK_OUT_ABOVE_16(ROL_16(src, shift));
\r
8704 if(orig_shift != 0)
\r
8706 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8710 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8711 FLAG_C = (src << shift) >> 8;
\r
8712 FLAG_N = NFLAG_16(res);
\r
8714 FLAG_V = VFLAG_CLEAR;
\r
8717 FLAG_C = (src & 1)<<8;
\r
8718 FLAG_N = NFLAG_16(src);
\r
8720 FLAG_V = VFLAG_CLEAR;
\r
8724 FLAG_C = CFLAG_CLEAR;
\r
8725 FLAG_N = NFLAG_16(src);
\r
8727 FLAG_V = VFLAG_CLEAR;
\r
8731 M68KMAKE_OP(rol, 32, r, .)
\r
8733 uint* r_dst = &DY;
\r
8734 uint orig_shift = DX & 0x3f;
\r
8735 uint shift = orig_shift & 31;
\r
8736 uint64 src = *r_dst;
\r
8737 uint res = ROL_32(src, shift);
\r
8739 if(orig_shift != 0)
\r
8741 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8745 FLAG_C = (src >> ((32 - shift) & 0x1f)) << 8;
\r
8746 FLAG_N = NFLAG_32(res);
\r
8748 FLAG_V = VFLAG_CLEAR;
\r
8752 FLAG_C = CFLAG_CLEAR;
\r
8753 FLAG_N = NFLAG_32(src);
\r
8755 FLAG_V = VFLAG_CLEAR;
\r
8759 M68KMAKE_OP(rol, 16, ., .)
\r
8761 uint ea = M68KMAKE_GET_EA_AY_16;
\r
8762 uint src = m68ki_read_16(ea);
\r
8763 uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
\r
8765 m68ki_write_16(ea, res);
\r
8767 FLAG_N = NFLAG_16(res);
\r
8769 FLAG_C = src >> 7;
\r
8770 FLAG_V = VFLAG_CLEAR;
\r
8774 M68KMAKE_OP(roxr, 8, s, .)
\r
8776 uint* r_dst = &DY;
\r
8777 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8778 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
8779 uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);
\r
8782 USE_CYCLES(shift<<CYC_SHIFT);
\r
8784 FLAG_C = FLAG_X = res;
\r
8785 res = MASK_OUT_ABOVE_8(res);
\r
8787 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8789 FLAG_N = NFLAG_8(res);
\r
8791 FLAG_V = VFLAG_CLEAR;
\r
8795 M68KMAKE_OP(roxr, 16, s, .)
\r
8797 uint* r_dst = &DY;
\r
8798 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8799 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
8800 uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);
\r
8803 USE_CYCLES(shift<<CYC_SHIFT);
\r
8805 FLAG_C = FLAG_X = res >> 8;
\r
8806 res = MASK_OUT_ABOVE_16(res);
\r
8808 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8810 FLAG_N = NFLAG_16(res);
\r
8812 FLAG_V = VFLAG_CLEAR;
\r
8816 M68KMAKE_OP(roxr, 32, s, .)
\r
8818 #if M68K_USE_64_BIT
\r
8820 uint* r_dst = &DY;
\r
8821 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8822 uint64 src = *r_dst;
\r
8823 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
\r
8826 USE_CYCLES(shift<<CYC_SHIFT);
\r
8828 res = ROR_33_64(res, shift);
\r
8830 FLAG_C = FLAG_X = res >> 24;
\r
8831 res = MASK_OUT_ABOVE_32(res);
\r
8835 FLAG_N = NFLAG_32(res);
\r
8837 FLAG_V = VFLAG_CLEAR;
\r
8841 uint* r_dst = &DY;
\r
8842 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8843 uint src = *r_dst;
\r
8844 uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));
\r
8845 uint new_x_flag = src & (1 << (shift - 1));
\r
8848 USE_CYCLES(shift<<CYC_SHIFT);
\r
8852 FLAG_C = FLAG_X = (new_x_flag != 0)<<8;
\r
8853 FLAG_N = NFLAG_32(res);
\r
8855 FLAG_V = VFLAG_CLEAR;
\r
8861 M68KMAKE_OP(roxr, 8, r, .)
\r
8863 uint* r_dst = &DY;
\r
8864 uint orig_shift = DX & 0x3f;
\r
8866 if(orig_shift != 0)
\r
8868 uint shift = orig_shift % 9;
\r
8869 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
8870 uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);
\r
8872 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8874 FLAG_C = FLAG_X = res;
\r
8875 res = MASK_OUT_ABOVE_8(res);
\r
8877 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8878 FLAG_N = NFLAG_8(res);
\r
8880 FLAG_V = VFLAG_CLEAR;
\r
8885 FLAG_N = NFLAG_8(*r_dst);
\r
8886 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
\r
8887 FLAG_V = VFLAG_CLEAR;
\r
8891 M68KMAKE_OP(roxr, 16, r, .)
\r
8893 uint* r_dst = &DY;
\r
8894 uint orig_shift = DX & 0x3f;
\r
8896 if(orig_shift != 0)
\r
8898 uint shift = orig_shift % 17;
\r
8899 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
8900 uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);
\r
8902 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8904 FLAG_C = FLAG_X = res >> 8;
\r
8905 res = MASK_OUT_ABOVE_16(res);
\r
8907 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8908 FLAG_N = NFLAG_16(res);
\r
8910 FLAG_V = VFLAG_CLEAR;
\r
8915 FLAG_N = NFLAG_16(*r_dst);
\r
8916 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
\r
8917 FLAG_V = VFLAG_CLEAR;
\r
8921 M68KMAKE_OP(roxr, 32, r, .)
\r
8923 #if M68K_USE_64_BIT
\r
8925 uint* r_dst = &DY;
\r
8926 uint orig_shift = DX & 0x3f;
\r
8928 if(orig_shift != 0)
\r
8930 uint shift = orig_shift % 33;
\r
8931 uint64 src = *r_dst;
\r
8932 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
\r
8934 res = ROR_33_64(res, shift);
\r
8936 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8938 FLAG_C = FLAG_X = res >> 24;
\r
8939 res = MASK_OUT_ABOVE_32(res);
\r
8942 FLAG_N = NFLAG_32(res);
\r
8944 FLAG_V = VFLAG_CLEAR;
\r
8949 FLAG_N = NFLAG_32(*r_dst);
\r
8951 FLAG_V = VFLAG_CLEAR;
\r
8955 uint* r_dst = &DY;
\r
8956 uint orig_shift = DX & 0x3f;
\r
8957 uint shift = orig_shift % 33;
\r
8958 uint src = *r_dst;
\r
8959 uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));
\r
8960 uint new_x_flag = src & (1 << (shift - 1));
\r
8962 if(orig_shift != 0)
\r
8963 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8968 FLAG_X = (new_x_flag != 0)<<8;
\r
8973 FLAG_N = NFLAG_32(res);
\r
8975 FLAG_V = VFLAG_CLEAR;
\r
8981 M68KMAKE_OP(roxr, 16, ., .)
\r
8983 uint ea = M68KMAKE_GET_EA_AY_16;
\r
8984 uint src = m68ki_read_16(ea);
\r
8985 uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
\r
8987 FLAG_C = FLAG_X = res >> 8;
\r
8988 res = MASK_OUT_ABOVE_16(res);
\r
8990 m68ki_write_16(ea, res);
\r
8992 FLAG_N = NFLAG_16(res);
\r
8994 FLAG_V = VFLAG_CLEAR;
\r
8998 M68KMAKE_OP(roxl, 8, s, .)
\r
9000 uint* r_dst = &DY;
\r
9001 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9002 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
9003 uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);
\r
9006 USE_CYCLES(shift<<CYC_SHIFT);
\r
9008 FLAG_C = FLAG_X = res;
\r
9009 res = MASK_OUT_ABOVE_8(res);
\r
9011 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
9013 FLAG_N = NFLAG_8(res);
\r
9015 FLAG_V = VFLAG_CLEAR;
\r
9019 M68KMAKE_OP(roxl, 16, s, .)
\r
9021 uint* r_dst = &DY;
\r
9022 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9023 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
9024 uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);
\r
9027 USE_CYCLES(shift<<CYC_SHIFT);
\r
9029 FLAG_C = FLAG_X = res >> 8;
\r
9030 res = MASK_OUT_ABOVE_16(res);
\r
9032 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
9034 FLAG_N = NFLAG_16(res);
\r
9036 FLAG_V = VFLAG_CLEAR;
\r
9040 M68KMAKE_OP(roxl, 32, s, .)
\r
9042 #if M68K_USE_64_BIT
\r
9044 uint* r_dst = &DY;
\r
9045 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9046 uint64 src = *r_dst;
\r
9047 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
\r
9050 USE_CYCLES(shift<<CYC_SHIFT);
\r
9052 res = ROL_33_64(res, shift);
\r
9054 FLAG_C = FLAG_X = res >> 24;
\r
9055 res = MASK_OUT_ABOVE_32(res);
\r
9059 FLAG_N = NFLAG_32(res);
\r
9061 FLAG_V = VFLAG_CLEAR;
\r
9065 uint* r_dst = &DY;
\r
9066 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9067 uint src = *r_dst;
\r
9068 uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));
\r
9069 uint new_x_flag = src & (1 << (32 - shift));
\r
9072 USE_CYCLES(shift<<CYC_SHIFT);
\r
9076 FLAG_C = FLAG_X = (new_x_flag != 0)<<8;
\r
9077 FLAG_N = NFLAG_32(res);
\r
9079 FLAG_V = VFLAG_CLEAR;
\r
9085 M68KMAKE_OP(roxl, 8, r, .)
\r
9087 uint* r_dst = &DY;
\r
9088 uint orig_shift = DX & 0x3f;
\r
9091 if(orig_shift != 0)
\r
9093 uint shift = orig_shift % 9;
\r
9094 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
9095 uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);
\r
9097 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
9099 FLAG_C = FLAG_X = res;
\r
9100 res = MASK_OUT_ABOVE_8(res);
\r
9102 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
9103 FLAG_N = NFLAG_8(res);
\r
9105 FLAG_V = VFLAG_CLEAR;
\r
9110 FLAG_N = NFLAG_8(*r_dst);
\r
9111 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
\r
9112 FLAG_V = VFLAG_CLEAR;
\r
9116 M68KMAKE_OP(roxl, 16, r, .)
\r
9118 uint* r_dst = &DY;
\r
9119 uint orig_shift = DX & 0x3f;
\r
9121 if(orig_shift != 0)
\r
9123 uint shift = orig_shift % 17;
\r
9124 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
9125 uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);
\r
9127 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
9129 FLAG_C = FLAG_X = res >> 8;
\r
9130 res = MASK_OUT_ABOVE_16(res);
\r
9132 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
9133 FLAG_N = NFLAG_16(res);
\r
9135 FLAG_V = VFLAG_CLEAR;
\r
9140 FLAG_N = NFLAG_16(*r_dst);
\r
9141 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
\r
9142 FLAG_V = VFLAG_CLEAR;
\r
9146 M68KMAKE_OP(roxl, 32, r, .)
\r
9148 #if M68K_USE_64_BIT
\r
9150 uint* r_dst = &DY;
\r
9151 uint orig_shift = DX & 0x3f;
\r
9153 if(orig_shift != 0)
\r
9155 uint shift = orig_shift % 33;
\r
9156 uint64 src = *r_dst;
\r
9157 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
\r
9159 res = ROL_33_64(res, shift);
\r
9161 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
9163 FLAG_C = FLAG_X = res >> 24;
\r
9164 res = MASK_OUT_ABOVE_32(res);
\r
9167 FLAG_N = NFLAG_32(res);
\r
9169 FLAG_V = VFLAG_CLEAR;
\r
9174 FLAG_N = NFLAG_32(*r_dst);
\r
9176 FLAG_V = VFLAG_CLEAR;
\r
9180 uint* r_dst = &DY;
\r
9181 uint orig_shift = DX & 0x3f;
\r
9182 uint shift = orig_shift % 33;
\r
9183 uint src = *r_dst;
\r
9184 uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));
\r
9185 uint new_x_flag = src & (1 << (32 - shift));
\r
9187 if(orig_shift != 0)
\r
9188 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
9193 FLAG_X = (new_x_flag != 0)<<8;
\r
9198 FLAG_N = NFLAG_32(res);
\r
9200 FLAG_V = VFLAG_CLEAR;
\r
9206 M68KMAKE_OP(roxl, 16, ., .)
\r
9208 uint ea = M68KMAKE_GET_EA_AY_16;
\r
9209 uint src = m68ki_read_16(ea);
\r
9210 uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
\r
9212 FLAG_C = FLAG_X = res >> 8;
\r
9213 res = MASK_OUT_ABOVE_16(res);
\r
9215 m68ki_write_16(ea, res);
\r
9217 FLAG_N = NFLAG_16(res);
\r
9219 FLAG_V = VFLAG_CLEAR;
\r
9223 M68KMAKE_OP(rtd, 32, ., .)
\r
9225 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
9227 uint new_pc = m68ki_pull_32();
\r
9229 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
9230 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
\r
9231 m68ki_jump(new_pc);
\r
9234 m68ki_exception_illegal();
\r
9238 M68KMAKE_OP(rte, 32, ., .)
\r
9246 m68ki_rte_callback(); /* auto-disable (see m68kcpu.h) */
\r
9247 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
9249 if(CPU_TYPE_IS_000(CPU_TYPE))
\r
9251 new_sr = m68ki_pull_16();
\r
9252 new_pc = m68ki_pull_32();
\r
9253 m68ki_jump(new_pc);
\r
9254 m68ki_set_sr(new_sr);
\r
9256 CPU_INSTR_MODE = INSTRUCTION_YES;
\r
9257 CPU_RUN_MODE = RUN_MODE_NORMAL;
\r
9262 if(CPU_TYPE_IS_010(CPU_TYPE))
\r
9264 format_word = m68ki_read_16(REG_A[7]+6) >> 12;
\r
9265 if(format_word == 0)
\r
9267 new_sr = m68ki_pull_16();
\r
9268 new_pc = m68ki_pull_32();
\r
9269 m68ki_fake_pull_16(); /* format word */
\r
9270 m68ki_jump(new_pc);
\r
9271 m68ki_set_sr(new_sr);
\r
9272 CPU_INSTR_MODE = INSTRUCTION_YES;
\r
9273 CPU_RUN_MODE = RUN_MODE_NORMAL;
\r
9276 CPU_INSTR_MODE = INSTRUCTION_YES;
\r
9277 CPU_RUN_MODE = RUN_MODE_NORMAL;
\r
9278 /* Not handling bus fault (9) */
\r
9279 m68ki_exception_format_error();
\r
9283 /* Otherwise it's 020 */
\r
9285 format_word = m68ki_read_16(REG_A[7]+6) >> 12;
\r
9286 switch(format_word)
\r
9288 case 0: /* Normal */
\r
9289 new_sr = m68ki_pull_16();
\r
9290 new_pc = m68ki_pull_32();
\r
9291 m68ki_fake_pull_16(); /* format word */
\r
9292 m68ki_jump(new_pc);
\r
9293 m68ki_set_sr(new_sr);
\r
9294 CPU_INSTR_MODE = INSTRUCTION_YES;
\r
9295 CPU_RUN_MODE = RUN_MODE_NORMAL;
\r
9297 case 1: /* Throwaway */
\r
9298 new_sr = m68ki_pull_16();
\r
9299 m68ki_fake_pull_32(); /* program counter */
\r
9300 m68ki_fake_pull_16(); /* format word */
\r
9301 m68ki_set_sr_noint(new_sr);
\r
9303 case 2: /* Trap */
\r
9304 new_sr = m68ki_pull_16();
\r
9305 new_pc = m68ki_pull_32();
\r
9306 m68ki_fake_pull_16(); /* format word */
\r
9307 m68ki_fake_pull_32(); /* address */
\r
9308 m68ki_jump(new_pc);
\r
9309 m68ki_set_sr(new_sr);
\r
9310 CPU_INSTR_MODE = INSTRUCTION_YES;
\r
9311 CPU_RUN_MODE = RUN_MODE_NORMAL;
\r
9314 /* Not handling long or short bus fault */
\r
9315 CPU_INSTR_MODE = INSTRUCTION_YES;
\r
9316 CPU_RUN_MODE = RUN_MODE_NORMAL;
\r
9317 m68ki_exception_format_error();
\r
9320 m68ki_exception_privilege_violation();
\r
9324 M68KMAKE_OP(rtm, 32, ., .)
\r
9326 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
9328 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
9329 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
9330 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
9331 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
9334 m68ki_exception_illegal();
\r
9338 M68KMAKE_OP(rtr, 32, ., .)
\r
9340 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
9341 m68ki_set_ccr(m68ki_pull_16());
\r
9342 m68ki_jump(m68ki_pull_32());
\r
9346 M68KMAKE_OP(rts, 32, ., .)
\r
9348 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
9349 m68ki_jump(m68ki_pull_32());
\r
9353 M68KMAKE_OP(sbcd, 8, rr, .)
\r
9355 uint* r_dst = &DX;
\r
9357 uint dst = *r_dst;
\r
9358 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
\r
9360 // FLAG_V = ~res; /* Undefined V behavior */
\r
9361 FLAG_V = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to assume cleared. */
\r
9365 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
\r
9369 FLAG_X = FLAG_C = CFLAG_SET;
\r
9370 FLAG_N = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */
\r
9373 FLAG_N = FLAG_X = FLAG_C = 0;
\r
9375 res = MASK_OUT_ABOVE_8(res);
\r
9377 // FLAG_V &= res; /* Undefined V behavior part II */
\r
9378 // FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
9381 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
9385 M68KMAKE_OP(sbcd, 8, mm, ax7)
\r
9387 uint src = OPER_AY_PD_8();
\r
9388 uint ea = EA_A7_PD_8();
\r
9389 uint dst = m68ki_read_8(ea);
\r
9390 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
\r
9392 // FLAG_V = ~res; /* Undefined V behavior */
\r
9393 FLAG_V = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to return zero. */
\r
9397 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
\r
9401 FLAG_X = FLAG_C = CFLAG_SET;
\r
9402 FLAG_N = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */
\r
9405 FLAG_N = FLAG_X = FLAG_C = 0;
\r
9407 res = MASK_OUT_ABOVE_8(res);
\r
9409 // FLAG_V &= res; /* Undefined V behavior part II */
\r
9410 // FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
9413 m68ki_write_8(ea, res);
\r
9417 M68KMAKE_OP(sbcd, 8, mm, ay7)
\r
9419 uint src = OPER_A7_PD_8();
\r
9420 uint ea = EA_AX_PD_8();
\r
9421 uint dst = m68ki_read_8(ea);
\r
9422 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
\r
9424 // FLAG_V = ~res; /* Undefined V behavior */
\r
9425 FLAG_V = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to return zero. */
\r
9429 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
\r
9433 FLAG_X = FLAG_C = CFLAG_SET;
\r
9434 FLAG_N = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */
\r
9437 FLAG_N = FLAG_X = FLAG_C = 0;
\r
9439 res = MASK_OUT_ABOVE_8(res);
\r
9441 // FLAG_V &= res; /* Undefined V behavior part II */
\r
9442 // FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
9445 m68ki_write_8(ea, res);
\r
9449 M68KMAKE_OP(sbcd, 8, mm, axy7)
\r
9451 uint src = OPER_A7_PD_8();
\r
9452 uint ea = EA_A7_PD_8();
\r
9453 uint dst = m68ki_read_8(ea);
\r
9454 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
\r
9456 // FLAG_V = ~res; /* Undefined V behavior */
\r
9457 FLAG_V = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to return zero. */
\r
9461 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
\r
9465 FLAG_X = FLAG_C = CFLAG_SET;
\r
9466 FLAG_N = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */
\r
9469 FLAG_N = FLAG_X = FLAG_C = 0;
\r
9471 res = MASK_OUT_ABOVE_8(res);
\r
9473 // FLAG_V &= res; /* Undefined V behavior part II */
\r
9474 // FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
9477 m68ki_write_8(ea, res);
\r
9481 M68KMAKE_OP(sbcd, 8, mm, .)
\r
9483 uint src = OPER_AY_PD_8();
\r
9484 uint ea = EA_AX_PD_8();
\r
9485 uint dst = m68ki_read_8(ea);
\r
9486 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
\r
9488 // FLAG_V = ~res; /* Undefined V behavior */
\r
9489 FLAG_V = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to return zero. */
\r
9493 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
\r
9497 FLAG_X = FLAG_C = CFLAG_SET;
\r
9498 FLAG_N = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */
\r
9501 FLAG_N = FLAG_X = FLAG_C = 0;
\r
9503 res = MASK_OUT_ABOVE_8(res);
\r
9505 // FLAG_V &= res; /* Undefined V behavior part II */
\r
9506 // FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
9509 m68ki_write_8(ea, res);
\r
9513 M68KMAKE_OP(st, 8, ., d)
\r
9519 M68KMAKE_OP(st, 8, ., .)
\r
9521 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0xff);
\r
9525 M68KMAKE_OP(sf, 8, ., d)
\r
9531 M68KMAKE_OP(sf, 8, ., .)
\r
9533 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);
\r
9537 M68KMAKE_OP(scc, 8, ., d)
\r
9542 USE_CYCLES(CYC_SCC_R_TRUE);
\r
9549 M68KMAKE_OP(scc, 8, ., .)
\r
9551 m68ki_write_8(M68KMAKE_GET_EA_AY_8, M68KMAKE_CC ? 0xff : 0);
\r
9555 M68KMAKE_OP(stop, 0, ., .)
\r
9559 uint new_sr = OPER_I_16();
\r
9560 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
9561 CPU_STOPPED |= STOP_LEVEL_STOP;
\r
9562 m68ki_set_sr(new_sr);
\r
9563 m68ki_remaining_cycles = 0;
\r
9566 m68ki_exception_privilege_violation();
\r
9570 M68KMAKE_OP(sub, 8, er, d)
\r
9572 uint* r_dst = &DX;
\r
9573 uint src = MASK_OUT_ABOVE_8(DY);
\r
9574 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
9575 uint res = dst - src;
\r
9577 FLAG_N = NFLAG_8(res);
\r
9578 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9579 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9580 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
9582 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
9586 M68KMAKE_OP(sub, 8, er, .)
\r
9588 uint* r_dst = &DX;
\r
9589 uint src = M68KMAKE_GET_OPER_AY_8;
\r
9590 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
9591 uint res = dst - src;
\r
9593 FLAG_N = NFLAG_8(res);
\r
9594 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9595 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9596 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
9598 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
9602 M68KMAKE_OP(sub, 16, er, d)
\r
9604 uint* r_dst = &DX;
\r
9605 uint src = MASK_OUT_ABOVE_16(DY);
\r
9606 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
9607 uint res = dst - src;
\r
9609 FLAG_N = NFLAG_16(res);
\r
9610 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9611 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9612 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9614 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
9618 M68KMAKE_OP(sub, 16, er, a)
\r
9620 uint* r_dst = &DX;
\r
9621 uint src = MASK_OUT_ABOVE_16(AY);
\r
9622 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
9623 uint res = dst - src;
\r
9625 FLAG_N = NFLAG_16(res);
\r
9626 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9627 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9628 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9630 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
9634 M68KMAKE_OP(sub, 16, er, .)
\r
9636 uint* r_dst = &DX;
\r
9637 uint src = M68KMAKE_GET_OPER_AY_16;
\r
9638 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
9639 uint res = dst - src;
\r
9641 FLAG_N = NFLAG_16(res);
\r
9642 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9643 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9644 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9646 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
9650 M68KMAKE_OP(sub, 32, er, d)
\r
9652 uint* r_dst = &DX;
\r
9654 uint dst = *r_dst;
\r
9655 uint res = dst - src;
\r
9657 FLAG_N = NFLAG_32(res);
\r
9658 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9659 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9660 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9666 M68KMAKE_OP(sub, 32, er, a)
\r
9668 uint* r_dst = &DX;
\r
9670 uint dst = *r_dst;
\r
9671 uint res = dst - src;
\r
9673 FLAG_N = NFLAG_32(res);
\r
9674 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9675 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9676 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9682 M68KMAKE_OP(sub, 32, er, .)
\r
9684 uint* r_dst = &DX;
\r
9685 uint src = M68KMAKE_GET_OPER_AY_32;
\r
9686 uint dst = *r_dst;
\r
9687 uint res = dst - src;
\r
9689 FLAG_N = NFLAG_32(res);
\r
9690 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9691 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9692 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9698 M68KMAKE_OP(sub, 8, re, .)
\r
9700 uint ea = M68KMAKE_GET_EA_AY_8;
\r
9701 uint src = MASK_OUT_ABOVE_8(DX);
\r
9702 uint dst = m68ki_read_8(ea);
\r
9703 uint res = dst - src;
\r
9705 FLAG_N = NFLAG_8(res);
\r
9706 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
9707 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9708 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9710 m68ki_write_8(ea, FLAG_Z);
\r
9714 M68KMAKE_OP(sub, 16, re, .)
\r
9716 uint ea = M68KMAKE_GET_EA_AY_16;
\r
9717 uint src = MASK_OUT_ABOVE_16(DX);
\r
9718 uint dst = m68ki_read_16(ea);
\r
9719 uint res = dst - src;
\r
9721 FLAG_N = NFLAG_16(res);
\r
9722 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9723 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9724 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9726 m68ki_write_16(ea, FLAG_Z);
\r
9730 M68KMAKE_OP(sub, 32, re, .)
\r
9732 uint ea = M68KMAKE_GET_EA_AY_32;
\r
9734 uint dst = m68ki_read_32(ea);
\r
9735 uint res = dst - src;
\r
9737 FLAG_N = NFLAG_32(res);
\r
9738 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9739 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9740 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9742 m68ki_write_32(ea, FLAG_Z);
\r
9746 M68KMAKE_OP(suba, 16, ., d)
\r
9748 uint* r_dst = &AX;
\r
9750 *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(DY));
\r
9754 M68KMAKE_OP(suba, 16, ., a)
\r
9756 uint* r_dst = &AX;
\r
9758 *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(AY));
\r
9762 M68KMAKE_OP(suba, 16, ., .)
\r
9764 uint* r_dst = &AX;
\r
9765 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
\r
9767 *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
\r
9771 M68KMAKE_OP(suba, 32, ., d)
\r
9773 uint* r_dst = &AX;
\r
9775 *r_dst = MASK_OUT_ABOVE_32(*r_dst - DY);
\r
9779 M68KMAKE_OP(suba, 32, ., a)
\r
9781 uint* r_dst = &AX;
\r
9783 *r_dst = MASK_OUT_ABOVE_32(*r_dst - AY);
\r
9787 M68KMAKE_OP(suba, 32, ., .)
\r
9789 uint* r_dst = &AX;
\r
9790 uint src = M68KMAKE_GET_OPER_AY_32; // notaz
\r
9792 *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
\r
9796 M68KMAKE_OP(subi, 8, ., d)
\r
9798 uint* r_dst = &DY;
\r
9799 uint src = OPER_I_8();
\r
9800 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
9801 uint res = dst - src;
\r
9803 FLAG_N = NFLAG_8(res);
\r
9804 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
9805 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9806 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9808 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
9812 M68KMAKE_OP(subi, 8, ., .)
\r
9814 uint src = OPER_I_8();
\r
9815 uint ea = M68KMAKE_GET_EA_AY_8;
\r
9816 uint dst = m68ki_read_8(ea);
\r
9817 uint res = dst - src;
\r
9819 FLAG_N = NFLAG_8(res);
\r
9820 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
9821 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9822 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9824 m68ki_write_8(ea, FLAG_Z);
\r
9828 M68KMAKE_OP(subi, 16, ., d)
\r
9830 uint* r_dst = &DY;
\r
9831 uint src = OPER_I_16();
\r
9832 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
9833 uint res = dst - src;
\r
9835 FLAG_N = NFLAG_16(res);
\r
9836 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9837 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9838 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9840 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
9844 M68KMAKE_OP(subi, 16, ., .)
\r
9846 uint src = OPER_I_16();
\r
9847 uint ea = M68KMAKE_GET_EA_AY_16;
\r
9848 uint dst = m68ki_read_16(ea);
\r
9849 uint res = dst - src;
\r
9851 FLAG_N = NFLAG_16(res);
\r
9852 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9853 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9854 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9856 m68ki_write_16(ea, FLAG_Z);
\r
9860 M68KMAKE_OP(subi, 32, ., d)
\r
9862 uint* r_dst = &DY;
\r
9863 uint src = OPER_I_32();
\r
9864 uint dst = *r_dst;
\r
9865 uint res = dst - src;
\r
9867 FLAG_N = NFLAG_32(res);
\r
9868 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9869 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9870 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9876 M68KMAKE_OP(subi, 32, ., .)
\r
9878 uint src = OPER_I_32();
\r
9879 uint ea = M68KMAKE_GET_EA_AY_32;
\r
9880 uint dst = m68ki_read_32(ea);
\r
9881 uint res = dst - src;
\r
9883 FLAG_N = NFLAG_32(res);
\r
9884 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9885 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9886 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9888 m68ki_write_32(ea, FLAG_Z);
\r
9892 M68KMAKE_OP(subq, 8, ., d)
\r
9894 uint* r_dst = &DY;
\r
9895 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9896 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
9897 uint res = dst - src;
\r
9899 FLAG_N = NFLAG_8(res);
\r
9900 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
9901 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9902 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9904 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
9908 M68KMAKE_OP(subq, 8, ., .)
\r
9910 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9911 uint ea = M68KMAKE_GET_EA_AY_8;
\r
9912 uint dst = m68ki_read_8(ea);
\r
9913 uint res = dst - src;
\r
9915 FLAG_N = NFLAG_8(res);
\r
9916 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
9917 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9918 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9920 m68ki_write_8(ea, FLAG_Z);
\r
9924 M68KMAKE_OP(subq, 16, ., d)
\r
9926 uint* r_dst = &DY;
\r
9927 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9928 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
9929 uint res = dst - src;
\r
9931 FLAG_N = NFLAG_16(res);
\r
9932 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9933 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9934 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9936 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
9940 M68KMAKE_OP(subq, 16, ., a)
\r
9942 uint* r_dst = &AY;
\r
9944 *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));
\r
9948 M68KMAKE_OP(subq, 16, ., .)
\r
9950 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9951 uint ea = M68KMAKE_GET_EA_AY_16;
\r
9952 uint dst = m68ki_read_16(ea);
\r
9953 uint res = dst - src;
\r
9955 FLAG_N = NFLAG_16(res);
\r
9956 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9957 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9958 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9960 m68ki_write_16(ea, FLAG_Z);
\r
9964 M68KMAKE_OP(subq, 32, ., d)
\r
9966 uint* r_dst = &DY;
\r
9967 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9968 uint dst = *r_dst;
\r
9969 uint res = dst - src;
\r
9971 FLAG_N = NFLAG_32(res);
\r
9972 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9973 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9974 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9980 M68KMAKE_OP(subq, 32, ., a)
\r
9982 uint* r_dst = &AY;
\r
9984 *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));
\r
9988 M68KMAKE_OP(subq, 32, ., .)
\r
9990 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9991 uint ea = M68KMAKE_GET_EA_AY_32;
\r
9992 uint dst = m68ki_read_32(ea);
\r
9993 uint res = dst - src;
\r
9995 FLAG_N = NFLAG_32(res);
\r
9996 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9997 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9998 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
10000 m68ki_write_32(ea, FLAG_Z);
\r
10004 M68KMAKE_OP(subx, 8, rr, .)
\r
10006 uint* r_dst = &DX;
\r
10007 uint src = MASK_OUT_ABOVE_8(DY);
\r
10008 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
10009 uint res = dst - src - XFLAG_AS_1();
\r
10011 FLAG_N = NFLAG_8(res);
\r
10012 FLAG_X = FLAG_C = CFLAG_8(res);
\r
10013 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
10015 res = MASK_OUT_ABOVE_8(res);
\r
10018 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
10022 M68KMAKE_OP(subx, 16, rr, .)
\r
10024 uint* r_dst = &DX;
\r
10025 uint src = MASK_OUT_ABOVE_16(DY);
\r
10026 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
10027 uint res = dst - src - XFLAG_AS_1();
\r
10029 FLAG_N = NFLAG_16(res);
\r
10030 FLAG_X = FLAG_C = CFLAG_16(res);
\r
10031 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
10033 res = MASK_OUT_ABOVE_16(res);
\r
10036 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
10040 M68KMAKE_OP(subx, 32, rr, .)
\r
10042 uint* r_dst = &DX;
\r
10044 uint dst = *r_dst;
\r
10045 uint res = dst - src - XFLAG_AS_1();
\r
10047 FLAG_N = NFLAG_32(res);
\r
10048 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
10049 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
10051 res = MASK_OUT_ABOVE_32(res);
\r
10058 M68KMAKE_OP(subx, 8, mm, ax7)
\r
10060 uint src = OPER_AY_PD_8();
\r
10061 uint ea = EA_A7_PD_8();
\r
10062 uint dst = m68ki_read_8(ea);
\r
10063 uint res = dst - src - XFLAG_AS_1();
\r
10065 FLAG_N = NFLAG_8(res);
\r
10066 FLAG_X = FLAG_C = CFLAG_8(res);
\r
10067 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
10069 res = MASK_OUT_ABOVE_8(res);
\r
10072 m68ki_write_8(ea, res);
\r
10076 M68KMAKE_OP(subx, 8, mm, ay7)
\r
10078 uint src = OPER_A7_PD_8();
\r
10079 uint ea = EA_AX_PD_8();
\r
10080 uint dst = m68ki_read_8(ea);
\r
10081 uint res = dst - src - XFLAG_AS_1();
\r
10083 FLAG_N = NFLAG_8(res);
\r
10084 FLAG_X = FLAG_C = CFLAG_8(res);
\r
10085 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
10087 res = MASK_OUT_ABOVE_8(res);
\r
10090 m68ki_write_8(ea, res);
\r
10094 M68KMAKE_OP(subx, 8, mm, axy7)
\r
10096 uint src = OPER_A7_PD_8();
\r
10097 uint ea = EA_A7_PD_8();
\r
10098 uint dst = m68ki_read_8(ea);
\r
10099 uint res = dst - src - XFLAG_AS_1();
\r
10101 FLAG_N = NFLAG_8(res);
\r
10102 FLAG_X = FLAG_C = CFLAG_8(res);
\r
10103 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
10105 res = MASK_OUT_ABOVE_8(res);
\r
10108 m68ki_write_8(ea, res);
\r
10112 M68KMAKE_OP(subx, 8, mm, .)
\r
10114 uint src = OPER_AY_PD_8();
\r
10115 uint ea = EA_AX_PD_8();
\r
10116 uint dst = m68ki_read_8(ea);
\r
10117 uint res = dst - src - XFLAG_AS_1();
\r
10119 FLAG_N = NFLAG_8(res);
\r
10120 FLAG_X = FLAG_C = CFLAG_8(res);
\r
10121 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
10123 res = MASK_OUT_ABOVE_8(res);
\r
10126 m68ki_write_8(ea, res);
\r
10130 M68KMAKE_OP(subx, 16, mm, .)
\r
10132 uint src = OPER_AY_PD_16();
\r
10133 uint ea = EA_AX_PD_16();
\r
10134 uint dst = m68ki_read_16(ea);
\r
10135 uint res = dst - src - XFLAG_AS_1();
\r
10137 FLAG_N = NFLAG_16(res);
\r
10138 FLAG_X = FLAG_C = CFLAG_16(res);
\r
10139 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
10141 res = MASK_OUT_ABOVE_16(res);
\r
10144 m68ki_write_16(ea, res);
\r
10148 M68KMAKE_OP(subx, 32, mm, .)
\r
10150 uint src = OPER_AY_PD_32();
\r
10151 uint ea = EA_AX_PD_32();
\r
10152 uint dst = m68ki_read_32(ea);
\r
10153 uint res = dst - src - XFLAG_AS_1();
\r
10155 FLAG_N = NFLAG_32(res);
\r
10156 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
10157 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
10159 res = MASK_OUT_ABOVE_32(res);
\r
10162 m68ki_write_32(ea, res);
\r
10166 M68KMAKE_OP(swap, 32, ., .)
\r
10168 uint* r_dst = &DY;
\r
10170 FLAG_Z = MASK_OUT_ABOVE_32(*r_dst<<16);
\r
10171 *r_dst = (*r_dst>>16) | FLAG_Z;
\r
10174 FLAG_N = NFLAG_32(*r_dst);
\r
10175 FLAG_C = CFLAG_CLEAR;
\r
10176 FLAG_V = VFLAG_CLEAR;
\r
10180 M68KMAKE_OP(tas, 8, ., d)
\r
10182 uint* r_dst = &DY;
\r
10184 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
\r
10185 FLAG_N = NFLAG_8(*r_dst);
\r
10186 FLAG_V = VFLAG_CLEAR;
\r
10187 FLAG_C = CFLAG_CLEAR;
\r
10192 M68KMAKE_OP(tas, 8, ., .)
\r
10194 uint ea = M68KMAKE_GET_EA_AY_8;
\r
10195 uint dst = m68ki_read_8(ea);
\r
10196 uint allow_writeback;
\r
10199 FLAG_N = NFLAG_8(dst);
\r
10200 FLAG_V = VFLAG_CLEAR;
\r
10201 FLAG_C = CFLAG_CLEAR;
\r
10203 /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback
\r
10204 disabled in order to function properly. Some Amiga software may also rely
\r
10205 on this, but only when accessing specific addresses so additional functionality
\r
10206 will be needed. */
\r
10207 allow_writeback = m68ki_tas_callback();
\r
10209 if (allow_writeback==1) m68ki_write_8(ea, dst | 0x80);
\r
10213 M68KMAKE_OP(trap, 0, ., .)
\r
10215 /* Trap#n stacks exception frame type 0 */
\r
10216 m68ki_exception_trapN(EXCEPTION_TRAP_BASE + (REG_IR & 0xf)); /* HJB 990403 */
\r
10220 M68KMAKE_OP(trapt, 0, ., .)
\r
10222 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10224 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
10227 m68ki_exception_illegal();
\r
10231 M68KMAKE_OP(trapt, 16, ., .)
\r
10233 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10235 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
10238 m68ki_exception_illegal();
\r
10242 M68KMAKE_OP(trapt, 32, ., .)
\r
10244 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10246 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
10249 m68ki_exception_illegal();
\r
10253 M68KMAKE_OP(trapf, 0, ., .)
\r
10255 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10259 m68ki_exception_illegal();
\r
10263 M68KMAKE_OP(trapf, 16, ., .)
\r
10265 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10270 m68ki_exception_illegal();
\r
10274 M68KMAKE_OP(trapf, 32, ., .)
\r
10276 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10281 m68ki_exception_illegal();
\r
10285 M68KMAKE_OP(trapcc, 0, ., .)
\r
10287 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10290 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
10293 m68ki_exception_illegal();
\r
10297 M68KMAKE_OP(trapcc, 16, ., .)
\r
10299 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10303 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
10309 m68ki_exception_illegal();
\r
10313 M68KMAKE_OP(trapcc, 32, ., .)
\r
10315 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10319 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
10325 m68ki_exception_illegal();
\r
10329 M68KMAKE_OP(trapv, 0, ., .)
\r
10335 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
10339 M68KMAKE_OP(tst, 8, ., d)
\r
10341 uint res = MASK_OUT_ABOVE_8(DY);
\r
10343 FLAG_N = NFLAG_8(res);
\r
10345 FLAG_V = VFLAG_CLEAR;
\r
10346 FLAG_C = CFLAG_CLEAR;
\r
10350 M68KMAKE_OP(tst, 8, ., .)
\r
10352 uint res = M68KMAKE_GET_OPER_AY_8;
\r
10354 FLAG_N = NFLAG_8(res);
\r
10356 FLAG_V = VFLAG_CLEAR;
\r
10357 FLAG_C = CFLAG_CLEAR;
\r
10361 M68KMAKE_OP(tst, 8, ., pcdi)
\r
10363 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10365 uint res = OPER_PCDI_8();
\r
10367 FLAG_N = NFLAG_8(res);
\r
10369 FLAG_V = VFLAG_CLEAR;
\r
10370 FLAG_C = CFLAG_CLEAR;
\r
10373 m68ki_exception_illegal();
\r
10377 M68KMAKE_OP(tst, 8, ., pcix)
\r
10379 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10381 uint res = OPER_PCIX_8();
\r
10383 FLAG_N = NFLAG_8(res);
\r
10385 FLAG_V = VFLAG_CLEAR;
\r
10386 FLAG_C = CFLAG_CLEAR;
\r
10389 m68ki_exception_illegal();
\r
10393 M68KMAKE_OP(tst, 8, ., i)
\r
10395 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10397 uint res = OPER_I_8();
\r
10399 FLAG_N = NFLAG_8(res);
\r
10401 FLAG_V = VFLAG_CLEAR;
\r
10402 FLAG_C = CFLAG_CLEAR;
\r
10405 m68ki_exception_illegal();
\r
10409 M68KMAKE_OP(tst, 16, ., d)
\r
10411 uint res = MASK_OUT_ABOVE_16(DY);
\r
10413 FLAG_N = NFLAG_16(res);
\r
10415 FLAG_V = VFLAG_CLEAR;
\r
10416 FLAG_C = CFLAG_CLEAR;
\r
10420 M68KMAKE_OP(tst, 16, ., a)
\r
10422 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10424 uint res = MAKE_INT_16(AY);
\r
10426 FLAG_N = NFLAG_16(res);
\r
10428 FLAG_V = VFLAG_CLEAR;
\r
10429 FLAG_C = CFLAG_CLEAR;
\r
10432 m68ki_exception_illegal();
\r
10436 M68KMAKE_OP(tst, 16, ., .)
\r
10438 uint res = M68KMAKE_GET_OPER_AY_16;
\r
10440 FLAG_N = NFLAG_16(res);
\r
10442 FLAG_V = VFLAG_CLEAR;
\r
10443 FLAG_C = CFLAG_CLEAR;
\r
10447 M68KMAKE_OP(tst, 16, ., pcdi)
\r
10449 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10451 uint res = OPER_PCDI_16();
\r
10453 FLAG_N = NFLAG_16(res);
\r
10455 FLAG_V = VFLAG_CLEAR;
\r
10456 FLAG_C = CFLAG_CLEAR;
\r
10459 m68ki_exception_illegal();
\r
10463 M68KMAKE_OP(tst, 16, ., pcix)
\r
10465 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10467 uint res = OPER_PCIX_16();
\r
10469 FLAG_N = NFLAG_16(res);
\r
10471 FLAG_V = VFLAG_CLEAR;
\r
10472 FLAG_C = CFLAG_CLEAR;
\r
10475 m68ki_exception_illegal();
\r
10479 M68KMAKE_OP(tst, 16, ., i)
\r
10481 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10483 uint res = OPER_I_16();
\r
10485 FLAG_N = NFLAG_16(res);
\r
10487 FLAG_V = VFLAG_CLEAR;
\r
10488 FLAG_C = CFLAG_CLEAR;
\r
10491 m68ki_exception_illegal();
\r
10495 M68KMAKE_OP(tst, 32, ., d)
\r
10499 FLAG_N = NFLAG_32(res);
\r
10501 FLAG_V = VFLAG_CLEAR;
\r
10502 FLAG_C = CFLAG_CLEAR;
\r
10506 M68KMAKE_OP(tst, 32, ., a)
\r
10508 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10512 FLAG_N = NFLAG_32(res);
\r
10514 FLAG_V = VFLAG_CLEAR;
\r
10515 FLAG_C = CFLAG_CLEAR;
\r
10518 m68ki_exception_illegal();
\r
10522 M68KMAKE_OP(tst, 32, ., .)
\r
10524 uint res = M68KMAKE_GET_OPER_AY_32;
\r
10526 FLAG_N = NFLAG_32(res);
\r
10528 FLAG_V = VFLAG_CLEAR;
\r
10529 FLAG_C = CFLAG_CLEAR;
\r
10533 M68KMAKE_OP(tst, 32, ., pcdi)
\r
10535 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10537 uint res = OPER_PCDI_32();
\r
10539 FLAG_N = NFLAG_32(res);
\r
10541 FLAG_V = VFLAG_CLEAR;
\r
10542 FLAG_C = CFLAG_CLEAR;
\r
10545 m68ki_exception_illegal();
\r
10549 M68KMAKE_OP(tst, 32, ., pcix)
\r
10551 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10553 uint res = OPER_PCIX_32();
\r
10555 FLAG_N = NFLAG_32(res);
\r
10557 FLAG_V = VFLAG_CLEAR;
\r
10558 FLAG_C = CFLAG_CLEAR;
\r
10561 m68ki_exception_illegal();
\r
10565 M68KMAKE_OP(tst, 32, ., i)
\r
10567 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10569 uint res = OPER_I_32();
\r
10571 FLAG_N = NFLAG_32(res);
\r
10573 FLAG_V = VFLAG_CLEAR;
\r
10574 FLAG_C = CFLAG_CLEAR;
\r
10577 m68ki_exception_illegal();
\r
10581 M68KMAKE_OP(unlk, 32, ., a7)
\r
10583 REG_A[7] = m68ki_read_32(REG_A[7]);
\r
10587 M68KMAKE_OP(unlk, 32, ., .)
\r
10589 uint* r_dst = &AY;
\r
10591 REG_A[7] = *r_dst;
\r
10592 *r_dst = m68ki_pull_32();
\r
10596 M68KMAKE_OP(unpk, 16, rr, .)
\r
10598 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10600 /* Note: DX and DY are reversed in Motorola's docs */
\r
10602 uint* r_dst = &DX;
\r
10604 *r_dst = MASK_OUT_BELOW_16(*r_dst) | (((((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16()) & 0xffff);
\r
10607 m68ki_exception_illegal();
\r
10611 M68KMAKE_OP(unpk, 16, mm, ax7)
\r
10613 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10615 /* Note: AX and AY are reversed in Motorola's docs */
\r
10616 uint src = OPER_AY_PD_8();
\r
10619 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
\r
10620 ea_dst = EA_A7_PD_8();
\r
10621 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
\r
10622 ea_dst = EA_A7_PD_8();
\r
10623 m68ki_write_8(ea_dst, src & 0xff);
\r
10626 m68ki_exception_illegal();
\r
10630 M68KMAKE_OP(unpk, 16, mm, ay7)
\r
10632 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10634 /* Note: AX and AY are reversed in Motorola's docs */
\r
10635 uint src = OPER_A7_PD_8();
\r
10638 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
\r
10639 ea_dst = EA_AX_PD_8();
\r
10640 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
\r
10641 ea_dst = EA_AX_PD_8();
\r
10642 m68ki_write_8(ea_dst, src & 0xff);
\r
10645 m68ki_exception_illegal();
\r
10649 M68KMAKE_OP(unpk, 16, mm, axy7)
\r
10651 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10653 uint src = OPER_A7_PD_8();
\r
10656 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
\r
10657 ea_dst = EA_A7_PD_8();
\r
10658 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
\r
10659 ea_dst = EA_A7_PD_8();
\r
10660 m68ki_write_8(ea_dst, src & 0xff);
\r
10663 m68ki_exception_illegal();
\r
10667 M68KMAKE_OP(unpk, 16, mm, .)
\r
10669 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10671 /* Note: AX and AY are reversed in Motorola's docs */
\r
10672 uint src = OPER_AY_PD_8();
\r
10675 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
\r
10676 ea_dst = EA_AX_PD_8();
\r
10677 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
\r
10678 ea_dst = EA_AX_PD_8();
\r
10679 m68ki_write_8(ea_dst, src & 0xff);
\r
10682 m68ki_exception_illegal();
\r
10687 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
\r