6 /* ======================================================================== */
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7 /* ========================= LICENSING & COPYRIGHT ======================== */
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8 /* ======================================================================== */
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13 * A portable Motorola M680x0 processor emulation engine.
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14 * Copyright 1998-2007 Karl Stenerud. All rights reserved.
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16 * This code may be freely used for non-commercial purposes as long as this
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17 * copyright notice remains unaltered in the source code and any binary files
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18 * containing this code in compiled form.
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20 * All other lisencing terms must be negotiated with the author
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23 * The latest version of this code can be obtained at:
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24 * http://kstenerud.cjb.net
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27 /* Special thanks to Bart Trzynadlowski for his insight into the
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28 * undocumented features of this chip:
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30 * http://dynarec.com/~bart/files/68knotes.txt
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34 /* Input file for m68kmake
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35 * -----------------------
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37 * All sections begin with 80 X's in a row followed by an end-of-line
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39 * After this, m68kmake will expect to find one of the following section
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41 * M68KMAKE_PROTOTYPE_HEADER - header for opcode handler prototypes
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42 * M68KMAKE_PROTOTYPE_FOOTER - footer for opcode handler prototypes
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43 * M68KMAKE_TABLE_HEADER - header for opcode handler jumptable
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44 * M68KMAKE_TABLE_FOOTER - footer for opcode handler jumptable
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45 * M68KMAKE_TABLE_BODY - the table itself
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46 * M68KMAKE_OPCODE_HANDLER_HEADER - header for opcode handler implementation
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47 * M68KMAKE_OPCODE_HANDLER_FOOTER - footer for opcode handler implementation
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48 * M68KMAKE_OPCODE_HANDLER_BODY - body section for opcode handler implementation
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50 * NOTE: M68KMAKE_OPCODE_HANDLER_BODY must be last in the file and
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51 * M68KMAKE_TABLE_BODY must be second last in the file.
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53 * The M68KMAKE_OPHANDLER_BODY section contains the opcode handler
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54 * primitives themselves. Each opcode handler begins with:
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55 * M68KMAKE_OP(A, B, C, D)
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57 * where A is the opcode handler name, B is the size of the operation,
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58 * C denotes any special processing mode, and D denotes a specific
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60 * For C and D where nothing is specified, use "."
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63 * M68KMAKE_OP(abcd, 8, rr, .) abcd, size 8, register to register, default EA
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64 * M68KMAKE_OP(abcd, 8, mm, ax7) abcd, size 8, memory to memory, register X is A7
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65 * M68KMAKE_OP(tst, 16, ., pcix) tst, size 16, PCIX addressing
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67 * All opcode handler primitives end with a closing curly brace "}" at column 1
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69 * NOTE: Do not place a M68KMAKE_OP() directive inside the opcode handler,
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70 * and do not put a closing curly brace at column 1 unless it is
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71 * marking the end of the handler!
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73 * Inside the handler, m68kmake will recognize M68KMAKE_GET_OPER_xx_xx,
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74 * M68KMAKE_GET_EA_xx_xx, and M68KMAKE_CC directives, and create multiple
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75 * opcode handlers to handle variations in the opcode handler.
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76 * Note: M68KMAKE_CC will only be interpreted in condition code opcodes.
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77 * As well, M68KMAKE_GET_EA_xx_xx and M68KMAKE_GET_OPER_xx_xx will only
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78 * be interpreted on instructions where the corresponding table entry
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79 * specifies multiple effective addressing modes.
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81 * clr 32 . . 0100001010...... A+-DXWL... U U U 12 6 4
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83 * This table entry says that the clr.l opcde has 7 variations (A+-DXWL).
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84 * It is run in user or supervisor mode for all CPUs, and uses 12 cycles for
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85 * 68000, 6 cycles for 68010, and 4 cycles for 68020.
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88 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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89 M68KMAKE_PROTOTYPE_HEADER
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91 #ifndef M68KOPS__HEADER
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92 #define M68KOPS__HEADER
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94 /* ======================================================================== */
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95 /* ============================ OPCODE HANDLERS =========================== */
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96 /* ======================================================================== */
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100 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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101 M68KMAKE_PROTOTYPE_FOOTER
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104 /* Build the opcode handler table */
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105 void m68ki_build_opcode_table(void);
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107 extern void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */
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108 extern unsigned char m68ki_cycles[][0x10000];
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111 /* ======================================================================== */
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112 /* ============================== END OF FILE ============================= */
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113 /* ======================================================================== */
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115 #endif /* M68KOPS__HEADER */
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119 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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120 M68KMAKE_TABLE_HEADER
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122 /* ======================================================================== */
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123 /* ========================= OPCODE TABLE BUILDER ========================= */
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124 /* ======================================================================== */
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126 #include "m68kops.h"
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128 #define NUM_CPU_TYPES 4
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130 void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */
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131 unsigned char m68ki_cycles[NUM_CPU_TYPES][0x10000]; /* Cycles used by CPU type */
\r
133 /* This is used to generate the opcode handler jump table */
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136 void (*opcode_handler)(void); /* handler function */
\r
137 unsigned int mask; /* mask on opcode */
\r
138 unsigned int match; /* what to match after masking */
\r
139 unsigned char cycles[NUM_CPU_TYPES]; /* cycles each cpu type takes */
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140 } opcode_handler_struct;
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143 /* Opcode handler table */
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144 static opcode_handler_struct m68k_opcode_handler_table[] =
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146 /* function mask match 000 010 020 040 */
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150 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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151 M68KMAKE_TABLE_FOOTER
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153 {0, 0, 0, {0, 0, 0, 0}}
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157 /* Build the opcode handler jump table */
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158 void m68ki_build_opcode_table(void)
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160 opcode_handler_struct *ostruct;
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166 for(i = 0; i < 0x10000; i++)
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168 /* default to illegal */
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169 m68ki_instruction_jump_table[i] = m68k_op_illegal;
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170 for(k=0;k<NUM_CPU_TYPES;k++)
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171 m68ki_cycles[k][i] = 0;
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174 ostruct = m68k_opcode_handler_table;
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175 while(ostruct->mask != 0xff00)
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177 for(i = 0;i < 0x10000;i++)
\r
179 if((i & ostruct->mask) == ostruct->match)
\r
181 m68ki_instruction_jump_table[i] = ostruct->opcode_handler;
\r
182 for(k=0;k<NUM_CPU_TYPES;k++)
\r
183 m68ki_cycles[k][i] = ostruct->cycles[k];
\r
188 while(ostruct->mask == 0xff00)
\r
190 for(i = 0;i <= 0xff;i++)
\r
192 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
\r
193 for(k=0;k<NUM_CPU_TYPES;k++)
\r
194 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
\r
198 while(ostruct->mask == 0xf1f8)
\r
200 for(i = 0;i < 8;i++)
\r
202 for(j = 0;j < 8;j++)
\r
204 instr = ostruct->match | (i << 9) | j;
\r
205 m68ki_instruction_jump_table[instr] = ostruct->opcode_handler;
\r
206 for(k=0;k<NUM_CPU_TYPES;k++)
\r
207 m68ki_cycles[k][instr] = ostruct->cycles[k];
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212 while(ostruct->mask == 0xfff0)
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214 for(i = 0;i <= 0x0f;i++)
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216 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
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217 for(k=0;k<NUM_CPU_TYPES;k++)
\r
218 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
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222 while(ostruct->mask == 0xf1ff)
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224 for(i = 0;i <= 0x07;i++)
\r
226 m68ki_instruction_jump_table[ostruct->match | (i << 9)] = ostruct->opcode_handler;
\r
227 for(k=0;k<NUM_CPU_TYPES;k++)
\r
228 m68ki_cycles[k][ostruct->match | (i << 9)] = ostruct->cycles[k];
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232 while(ostruct->mask == 0xfff8)
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234 for(i = 0;i <= 0x07;i++)
\r
236 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
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237 for(k=0;k<NUM_CPU_TYPES;k++)
\r
238 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
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242 while(ostruct->mask == 0xffff)
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244 m68ki_instruction_jump_table[ostruct->match] = ostruct->opcode_handler;
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245 for(k=0;k<NUM_CPU_TYPES;k++)
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246 m68ki_cycles[k][ostruct->match] = ostruct->cycles[k];
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252 /* ======================================================================== */
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253 /* ============================== END OF FILE ============================= */
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254 /* ======================================================================== */
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258 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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259 M68KMAKE_OPCODE_HANDLER_HEADER
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260 #include <stdlib.h>
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262 #include "m68kcpu.h"
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263 extern void m68040_fpu_op0(void);
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264 extern void m68040_fpu_op1(void);
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266 /* Count non-0 bits */
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267 INLINE int m68ki_bit_count(uint32 arg)
\r
269 arg = arg - ((arg>>1)&0x55555555);
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270 arg = (arg&0x33333333) + ((arg>>2)&0x33333333);
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271 return (((arg + (arg>>4))&0x0f0f0f0f) * 0x01010101) >> 24;
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274 INLINE int m68ki_mulu_cycles(uint32 arg)
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276 if (CPU_TYPE_IS_000(CPU_TYPE))
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277 return m68ki_bit_count(arg) * 2;
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278 else if (CPU_TYPE_IS_010(CPU_TYPE))
\r
279 return m68ki_bit_count(arg); /* guesswork */
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281 return m68ki_bit_count(arg) / 2; /* guesswork */
\r
284 INLINE int m68ki_muls_cycles(sint32 arg)
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286 if (CPU_TYPE_IS_000(CPU_TYPE))
\r
287 return m68ki_bit_count(arg ^ (arg<<1)) * 2;
\r
288 else if (CPU_TYPE_IS_010(CPU_TYPE))
\r
289 return m68ki_bit_count(arg ^ (arg<<1)); /* guesswork */
\r
291 return m68ki_bit_count(arg ^ (arg<<1)) / 2; /* guesswork */
\r
294 INLINE int m68ki_divu_cycles(uint32 arg)
\r
296 /* approximation only. Doesn't factor in shorter cycles by carry */
\r
297 if (CPU_TYPE_IS_000(CPU_TYPE))
\r
298 return 128 - m68ki_bit_count(arg) * 2;
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299 else if (CPU_TYPE_IS_010(CPU_TYPE))
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300 return 96; /* guesswork */
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302 return 32; /* guesswork */
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305 INLINE int m68ki_divs_cycles(uint32 scyc, sint32 arg)
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307 /* approximation only. Doesn't factor in shorter cycles by carry */
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308 if (CPU_TYPE_IS_000(CPU_TYPE))
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309 return 128 - m68ki_bit_count(abs(arg)) * 2 + scyc*2 + 8;
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310 else if (CPU_TYPE_IS_010(CPU_TYPE))
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311 return 96 + scyc*2 + 8; /* guesswork */
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313 return 32 + scyc + 4; /* guesswork */
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316 /* ======================================================================== */
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317 /* ========================= INSTRUCTION HANDLERS ========================= */
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318 /* ======================================================================== */
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322 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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323 M68KMAKE_OPCODE_HANDLER_FOOTER
\r
325 /* ======================================================================== */
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326 /* ============================== END OF FILE ============================= */
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327 /* ======================================================================== */
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331 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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332 M68KMAKE_TABLE_BODY
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334 The following table is arranged as follows:
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336 name: Opcode mnemonic
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338 size: Operation size
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340 spec proc: Special processing mode:
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343 r: register operand
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344 rr: register to register
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345 mm: memory to memory
\r
346 er: effective address to register
\r
347 re: register to effective address
\r
348 dd: data register to data register
\r
349 da: data register to address register
\r
350 aa: address register to address register
\r
351 cr: control register to register
\r
352 rc: register to control register
\r
353 toc: to condition code register
\r
354 tos: to status register
\r
355 tou: to user stack pointer
\r
356 frc: from condition code register
\r
357 frs: from status register
\r
358 fru: from user stack pointer
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359 * for move.x, the special processing mode is a specific
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360 destination effective addressing mode.
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362 spec ea: Specific effective addressing mode:
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366 a: address register
\r
367 ai: address register indirect
\r
368 pi: address register indirect with postincrement
\r
369 pd: address register indirect with predecrement
\r
370 di: address register indirect with displacement
\r
371 ix: address register indirect with index
\r
372 aw: absolute word address
\r
373 al: absolute long address
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374 pcdi: program counter relative with displacement
\r
375 pcix: program counter relative with index
\r
376 a7: register specified in instruction is A7
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377 ax7: register field X of instruction is A7
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378 ay7: register field Y of instruction is A7
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379 axy7: register fields X and Y of instruction are A7
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381 bit pattern: Pattern to recognize this opcode. "." means don't care.
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383 allowed ea: List of allowed addressing modes:
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385 A: address register indirect
\r
386 +: ARI (address register indirect) with postincrement
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387 -: ARI with predecrement
\r
388 D: ARI with displacement
\r
390 W: absolute word address
\r
391 L: absolute long address
\r
392 d: program counter indirect with displacement
\r
393 x: program counter indirect with index
\r
395 mode: CPU operating mode for each cpu type. U = user or supervisor,
\r
396 S = supervisor only, "." = opcode not present.
\r
398 cpu cycles: Base number of cycles required to execute this opcode on the
\r
399 specified CPU type.
\r
400 Use "." if CPU does not have this opcode.
\r
404 spec spec allowed ea mode cpu cycles
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405 name size proc ea bit pattern A+-DXWLdxI 0 1 2 4 000 010 020 040 comments
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406 ====== ==== ==== ==== ================ ========== = = = = === === === === =============
\r
407 M68KMAKE_TABLE_START
\r
408 1010 0 . . 1010............ .......... U U U U 4 4 4 4
\r
409 1111 0 . . 1111............ .......... U U U U 4 4 4 4
\r
410 040fpu0 32 . . 11110010........ .......... . . . U . . . 0
\r
411 040fpu1 32 . . 11110011........ .......... . . . U . . . 0
\r
412 abcd 8 rr . 1100...100000... .......... U U U U 6 6 4 4
\r
413 abcd 8 mm ax7 1100111100001... .......... U U U U 18 18 16 16
\r
414 abcd 8 mm ay7 1100...100001111 .......... U U U U 18 18 16 16
\r
415 abcd 8 mm axy7 1100111100001111 .......... U U U U 18 18 16 16
\r
416 abcd 8 mm . 1100...100001... .......... U U U U 18 18 16 16
\r
417 add 8 er d 1101...000000... .......... U U U U 4 4 2 2
\r
418 add 8 er . 1101...000...... A+-DXWLdxI U U U U 4 4 2 2
\r
419 add 16 er d 1101...001000... .......... U U U U 4 4 2 2
\r
420 add 16 er a 1101...001001... .......... U U U U 4 4 2 2
\r
421 add 16 er . 1101...001...... A+-DXWLdxI U U U U 4 4 2 2
\r
422 add 32 er d 1101...010000... .......... U U U U 6 6 2 2
\r
423 add 32 er a 1101...010001... .......... U U U U 6 6 2 2
\r
424 add 32 er . 1101...010...... A+-DXWLdxI U U U U 6 6 2 2
\r
425 add 8 re . 1101...100...... A+-DXWL... U U U U 8 8 4 4
\r
426 add 16 re . 1101...101...... A+-DXWL... U U U U 8 8 4 4
\r
427 add 32 re . 1101...110...... A+-DXWL... U U U U 12 12 4 4
\r
428 adda 16 . d 1101...011000... .......... U U U U 8 8 2 2
\r
429 adda 16 . a 1101...011001... .......... U U U U 8 8 2 2
\r
430 adda 16 . . 1101...011...... A+-DXWLdxI U U U U 8 8 2 2
\r
431 adda 32 . d 1101...111000... .......... U U U U 6 6 2 2
\r
432 adda 32 . a 1101...111001... .......... U U U U 6 6 2 2
\r
433 adda 32 . . 1101...111...... A+-DXWLdxI U U U U 6 6 2 2
\r
434 addi 8 . d 0000011000000... .......... U U U U 8 8 2 2
\r
435 addi 8 . . 0000011000...... A+-DXWL... U U U U 12 12 4 4
\r
436 addi 16 . d 0000011001000... .......... U U U U 8 8 2 2
\r
437 addi 16 . . 0000011001...... A+-DXWL... U U U U 12 12 4 4
\r
438 addi 32 . d 0000011010000... .......... U U U U 16 14 2 2
\r
439 addi 32 . . 0000011010...... A+-DXWL... U U U U 20 20 4 4
\r
440 addq 8 . d 0101...000000... .......... U U U U 4 4 2 2
\r
441 addq 8 . . 0101...000...... A+-DXWL... U U U U 8 8 4 4
\r
442 addq 16 . d 0101...001000... .......... U U U U 4 4 2 2
\r
443 addq 16 . a 0101...001001... .......... U U U U 8 8 2 2
\r
444 addq 16 . . 0101...001...... A+-DXWL... U U U U 8 8 4 4
\r
445 addq 32 . d 0101...010000... .......... U U U U 8 8 2 2
\r
446 addq 32 . a 0101...010001... .......... U U U U 8 8 2 2
\r
447 addq 32 . . 0101...010...... A+-DXWL... U U U U 12 12 4 4
\r
448 addx 8 rr . 1101...100000... .......... U U U U 4 4 2 2
\r
449 addx 16 rr . 1101...101000... .......... U U U U 4 4 2 2
\r
450 addx 32 rr . 1101...110000... .......... U U U U 8 6 2 2
\r
451 addx 8 mm ax7 1101111100001... .......... U U U U 18 18 12 12
\r
452 addx 8 mm ay7 1101...100001111 .......... U U U U 18 18 12 12
\r
453 addx 8 mm axy7 1101111100001111 .......... U U U U 18 18 12 12
\r
454 addx 8 mm . 1101...100001... .......... U U U U 18 18 12 12
\r
455 addx 16 mm . 1101...101001... .......... U U U U 18 18 12 12
\r
456 addx 32 mm . 1101...110001... .......... U U U U 30 30 12 12
\r
457 and 8 er d 1100...000000... .......... U U U U 4 4 2 2
\r
458 and 8 er . 1100...000...... A+-DXWLdxI U U U U 4 4 2 2
\r
459 and 16 er d 1100...001000... .......... U U U U 4 4 2 2
\r
460 and 16 er . 1100...001...... A+-DXWLdxI U U U U 4 4 2 2
\r
461 and 32 er d 1100...010000... .......... U U U U 6 6 2 2
\r
462 and 32 er . 1100...010...... A+-DXWLdxI U U U U 6 6 2 2
\r
463 and 8 re . 1100...100...... A+-DXWL... U U U U 8 8 4 4
\r
464 and 16 re . 1100...101...... A+-DXWL... U U U U 8 8 4 4
\r
465 and 32 re . 1100...110...... A+-DXWL... U U U U 12 12 4 4
\r
466 andi 16 toc . 0000001000111100 .......... U U U U 20 16 12 12
\r
467 andi 16 tos . 0000001001111100 .......... S S S S 20 16 12 12
\r
468 andi 8 . d 0000001000000... .......... U U U U 8 8 2 2
\r
469 andi 8 . . 0000001000...... A+-DXWL... U U U U 12 12 4 4
\r
470 andi 16 . d 0000001001000... .......... U U U U 8 8 2 2
\r
471 andi 16 . . 0000001001...... A+-DXWL... U U U U 12 12 4 4
\r
472 andi 32 . d 0000001010000... .......... U U U U 16 14 2 2
\r
473 andi 32 . . 0000001010...... A+-DXWL... U U U U 20 20 4 4
\r
474 asr 8 s . 1110...000000... .......... U U U U 6 6 6 6
\r
475 asr 16 s . 1110...001000... .......... U U U U 6 6 6 6
\r
476 asr 32 s . 1110...010000... .......... U U U U 8 8 6 6
\r
477 asr 8 r . 1110...000100... .......... U U U U 6 6 6 6
\r
478 asr 16 r . 1110...001100... .......... U U U U 6 6 6 6
\r
479 asr 32 r . 1110...010100... .......... U U U U 8 8 6 6
\r
480 asr 16 . . 1110000011...... A+-DXWL... U U U U 8 8 5 5
\r
481 asl 8 s . 1110...100000... .......... U U U U 6 6 8 8
\r
482 asl 16 s . 1110...101000... .......... U U U U 6 6 8 8
\r
483 asl 32 s . 1110...110000... .......... U U U U 8 8 8 8
\r
484 asl 8 r . 1110...100100... .......... U U U U 6 6 8 8
\r
485 asl 16 r . 1110...101100... .......... U U U U 6 6 8 8
\r
486 asl 32 r . 1110...110100... .......... U U U U 8 8 8 8
\r
487 asl 16 . . 1110000111...... A+-DXWL... U U U U 8 8 6 6
\r
488 bcc 8 . . 0110............ .......... U U U U 10 10 6 6
\r
489 bcc 16 . . 0110....00000000 .......... U U U U 10 10 6 6
\r
490 bcc 32 . . 0110....11111111 .......... U U U U 10 10 6 6
\r
491 bchg 8 r . 0000...101...... A+-DXWL... U U U U 8 8 4 4
\r
492 bchg 32 r d 0000...101000... .......... U U U U 6 6 4 4
\r
493 bchg 8 s . 0000100001...... A+-DXWL... U U U U 12 12 4 4
\r
494 bchg 32 s d 0000100001000... .......... U U U U 10 10 4 4
\r
495 bclr 8 r . 0000...110...... A+-DXWL... U U U U 8 8 4 4
\r
496 bclr 32 r d 0000...110000... .......... U U U U 8 8 4 4
\r
497 bclr 8 s . 0000100010...... A+-DXWL... U U U U 12 12 4 4
\r
498 bclr 32 s d 0000100010000... .......... U U U U 12 12 4 4
\r
499 bfchg 32 . d 1110101011000... .......... . . U U . . 12 12 timing not quite correct
\r
500 bfchg 32 . . 1110101011...... A..DXWL... . . U U . . 20 20
\r
501 bfclr 32 . d 1110110011000... .......... . . U U . . 12 12
\r
502 bfclr 32 . . 1110110011...... A..DXWL... . . U U . . 20 20
\r
503 bfexts 32 . d 1110101111000... .......... . . U U . . 8 8
\r
504 bfexts 32 . . 1110101111...... A..DXWLdx. . . U U . . 15 15
\r
505 bfextu 32 . d 1110100111000... .......... . . U U . . 8 8
\r
506 bfextu 32 . . 1110100111...... A..DXWLdx. . . U U . . 15 15
\r
507 bfffo 32 . d 1110110111000... .......... . . U U . . 18 18
\r
508 bfffo 32 . . 1110110111...... A..DXWLdx. . . U U . . 28 28
\r
509 bfins 32 . d 1110111111000... .......... . . U U . . 10 10
\r
510 bfins 32 . . 1110111111...... A..DXWL... . . U U . . 17 17
\r
511 bfset 32 . d 1110111011000... .......... . . U U . . 12 12
\r
512 bfset 32 . . 1110111011...... A..DXWL... . . U U . . 20 20
\r
513 bftst 32 . d 1110100011000... .......... . . U U . . 6 6
\r
514 bftst 32 . . 1110100011...... A..DXWLdx. . . U U . . 13 13
\r
515 bkpt 0 . . 0100100001001... .......... . U U U . 10 10 10
\r
516 bra 8 . . 01100000........ .......... U U U U 10 10 10 10
\r
517 bra 16 . . 0110000000000000 .......... U U U U 10 10 10 10
\r
518 bra 32 . . 0110000011111111 .......... U U U U 10 10 10 10
\r
519 bset 32 r d 0000...111000... .......... U U U U 6 6 4 4
\r
520 bset 8 r . 0000...111...... A+-DXWL... U U U U 8 8 4 4
\r
521 bset 8 s . 0000100011...... A+-DXWL... U U U U 12 12 4 4
\r
522 bset 32 s d 0000100011000... .......... U U U U 10 10 4 4
\r
523 bsr 8 . . 01100001........ .......... U U U U 18 18 7 7
\r
524 bsr 16 . . 0110000100000000 .......... U U U U 18 18 7 7
\r
525 bsr 32 . . 0110000111111111 .......... U U U U 18 18 7 7
\r
526 btst 8 r . 0000...100...... A+-DXWLdxI U U U U 4 4 4 4
\r
527 btst 32 r d 0000...100000... .......... U U U U 6 6 4 4
\r
528 btst 8 s . 0000100000...... A+-DXWLdx. U U U U 8 8 4 4
\r
529 btst 32 s d 0000100000000... .......... U U U U 10 10 4 4
\r
530 callm 32 . . 0000011011...... A..DXWLdx. . . U U . . 60 60 not properly emulated
\r
531 cas 8 . . 0000101011...... A+-DXWL... . . U U . . 12 12
\r
532 cas 16 . . 0000110011...... A+-DXWL... . . U U . . 12 12
\r
533 cas 32 . . 0000111011...... A+-DXWL... . . U U . . 12 12
\r
534 cas2 16 . . 0000110011111100 .......... . . U U . . 12 12
\r
535 cas2 32 . . 0000111011111100 .......... . . U U . . 12 12
\r
536 chk 16 . d 0100...110000... .......... U U U U 4 2 2 2
\r
537 chk 16 . . 0100...110...... A+-DXWLdxI U U U U 4 2 2 2
\r
538 chk 32 . d 0100...100000... .......... . . U U . . 8 8
\r
539 chk 32 . . 0100...100...... A+-DXWLdxI . . U U . . 8 8
\r
540 chk2cmp2 8 . pcdi 0000000011111010 .......... . . U U . . 23 23
\r
541 chk2cmp2 8 . pcix 0000000011111011 .......... . . U U . . 23 23
\r
542 chk2cmp2 8 . . 0000000011...... A..DXWL... . . U U . . 18 18
\r
543 chk2cmp2 16 . pcdi 0000001011111010 .......... . . U U . . 23 23
\r
544 chk2cmp2 16 . pcix 0000001011111011 .......... . . U U . . 23 23
\r
545 chk2cmp2 16 . . 0000001011...... A..DXWL... . . U U . . 18 18
\r
546 chk2cmp2 32 . pcdi 0000010011111010 .......... . . U U . . 23 23
\r
547 chk2cmp2 32 . pcix 0000010011111011 .......... . . U U . . 23 23
\r
548 chk2cmp2 32 . . 0000010011...... A..DXWL... . . U U . . 18 18
\r
549 clr 8 . d 0100001000000... .......... U U U U 4 4 2 2
\r
550 clr 8 . . 0100001000...... A+-DXWL... U U U U 8 4 4 4
\r
551 clr 16 . d 0100001001000... .......... U U U U 4 4 2 2
\r
552 clr 16 . . 0100001001...... A+-DXWL... U U U U 8 4 4 4
\r
553 clr 32 . d 0100001010000... .......... U U U U 6 6 2 2
\r
554 clr 32 . . 0100001010...... A+-DXWL... U U U U 12 6 4 4
\r
555 cmp 8 . d 1011...000000... .......... U U U U 4 4 2 2
\r
556 cmp 8 . . 1011...000...... A+-DXWLdxI U U U U 4 4 2 2
\r
557 cmp 16 . d 1011...001000... .......... U U U U 4 4 2 2
\r
558 cmp 16 . a 1011...001001... .......... U U U U 4 4 2 2
\r
559 cmp 16 . . 1011...001...... A+-DXWLdxI U U U U 4 4 2 2
\r
560 cmp 32 . d 1011...010000... .......... U U U U 6 6 2 2
\r
561 cmp 32 . a 1011...010001... .......... U U U U 6 6 2 2
\r
562 cmp 32 . . 1011...010...... A+-DXWLdxI U U U U 6 6 2 2
\r
563 cmpa 16 . d 1011...011000... .......... U U U U 6 6 4 4
\r
564 cmpa 16 . a 1011...011001... .......... U U U U 6 6 4 4
\r
565 cmpa 16 . . 1011...011...... A+-DXWLdxI U U U U 6 6 4 4
\r
566 cmpa 32 . d 1011...111000... .......... U U U U 6 6 4 4
\r
567 cmpa 32 . a 1011...111001... .......... U U U U 6 6 4 4
\r
568 cmpa 32 . . 1011...111...... A+-DXWLdxI U U U U 6 6 4 4
\r
569 cmpi 8 . d 0000110000000... .......... U U U U 8 8 2 2
\r
570 cmpi 8 . . 0000110000...... A+-DXWL... U U U U 8 8 2 2
\r
571 cmpi 8 . pcdi 0000110000111010 .......... . . U U . . 7 7
\r
572 cmpi 8 . pcix 0000110000111011 .......... . . U U . . 9 9
\r
573 cmpi 16 . d 0000110001000... .......... U U U U 8 8 2 2
\r
574 cmpi 16 . . 0000110001...... A+-DXWL... U U U U 8 8 2 2
\r
575 cmpi 16 . pcdi 0000110001111010 .......... . . U U . . 7 7
\r
576 cmpi 16 . pcix 0000110001111011 .......... . . U U . . 9 9
\r
577 cmpi 32 . d 0000110010000... .......... U U U U 14 12 2 2
\r
578 cmpi 32 . . 0000110010...... A+-DXWL... U U U U 12 12 2 2
\r
579 cmpi 32 . pcdi 0000110010111010 .......... . . U U . . 7 7
\r
580 cmpi 32 . pcix 0000110010111011 .......... . . U U . . 9 9
\r
581 cmpm 8 . ax7 1011111100001... .......... U U U U 12 12 9 9
\r
582 cmpm 8 . ay7 1011...100001111 .......... U U U U 12 12 9 9
\r
583 cmpm 8 . axy7 1011111100001111 .......... U U U U 12 12 9 9
\r
584 cmpm 8 . . 1011...100001... .......... U U U U 12 12 9 9
\r
585 cmpm 16 . . 1011...101001... .......... U U U U 12 12 9 9
\r
586 cmpm 32 . . 1011...110001... .......... U U U U 20 20 9 9
\r
587 cpbcc 32 . . 1111...01....... .......... . . U . . . 4 . unemulated
\r
588 cpdbcc 32 . . 1111...001001... .......... . . U . . . 4 . unemulated
\r
589 cpgen 32 . . 1111...000...... .......... . . U . . . 4 . unemulated
\r
590 cpscc 32 . . 1111...001...... .......... . . U . . . 4 . unemulated
\r
591 cptrapcc 32 . . 1111...001111... .......... . . U . . . 4 . unemulated
\r
592 dbt 16 . . 0101000011001... .......... U U U U 12 12 6 6
\r
593 dbf 16 . . 0101000111001... .......... U U U U 12 12 6 6
\r
594 dbcc 16 . . 0101....11001... .......... U U U U 12 12 6 6
\r
595 divs 16 . d 1000...111000... .......... U U U U 16 16 16 16 cycles depending on operands
\r
596 divs 16 . . 1000...111...... A+-DXWLdxI U U U U 16 16 16 16 cycles depending on operands
\r
597 divu 16 . d 1000...011000... .......... U U U U 10 10 10 10 cycles depending on operands
\r
598 divu 16 . . 1000...011...... A+-DXWLdxI U U U U 10 10 10 10 cycles depending on operands
\r
599 divl 32 . d 0100110001000... .......... . . U U . . 84 84
\r
600 divl 32 . . 0100110001...... A+-DXWLdxI . . U U . . 84 84
\r
601 eor 8 . d 1011...100000... .......... U U U U 4 4 2 2
\r
602 eor 8 . . 1011...100...... A+-DXWL... U U U U 8 8 4 4
\r
603 eor 16 . d 1011...101000... .......... U U U U 4 4 2 2
\r
604 eor 16 . . 1011...101...... A+-DXWL... U U U U 8 8 4 4
\r
605 eor 32 . d 1011...110000... .......... U U U U 8 6 2 2
\r
606 eor 32 . . 1011...110...... A+-DXWL... U U U U 12 12 4 4
\r
607 eori 16 toc . 0000101000111100 .......... U U U U 20 16 12 12
\r
608 eori 16 tos . 0000101001111100 .......... S S S S 20 16 12 12
\r
609 eori 8 . d 0000101000000... .......... U U U U 8 8 2 2
\r
610 eori 8 . . 0000101000...... A+-DXWL... U U U U 12 12 4 4
\r
611 eori 16 . d 0000101001000... .......... U U U U 8 8 2 2
\r
612 eori 16 . . 0000101001...... A+-DXWL... U U U U 12 12 4 4
\r
613 eori 32 . d 0000101010000... .......... U U U U 16 14 2 2
\r
614 eori 32 . . 0000101010...... A+-DXWL... U U U U 20 20 4 4
\r
615 exg 32 dd . 1100...101000... .......... U U U U 6 6 2 2
\r
616 exg 32 aa . 1100...101001... .......... U U U U 6 6 2 2
\r
617 exg 32 da . 1100...110001... .......... U U U U 6 6 2 2
\r
618 ext 16 . . 0100100010000... .......... U U U U 4 4 4 4
\r
619 ext 32 . . 0100100011000... .......... U U U U 4 4 4 4
\r
620 extb 32 . . 0100100111000... .......... . . U U . . 4 4
\r
621 illegal 0 . . 0100101011111100 .......... U U U U 4 4 4 4
\r
622 jmp 32 . . 0100111011...... A..DXWLdx. U U U U 4 4 0 0
\r
623 jsr 32 . . 0100111010...... A..DXWLdx. U U U U 12 12 0 0
\r
624 lea 32 . . 0100...111...... A..DXWLdx. U U U U 0 0 2 2
\r
625 link 16 . a7 0100111001010111 .......... U U U U 16 16 5 5
\r
626 link 16 . . 0100111001010... .......... U U U U 16 16 5 5
\r
627 link 32 . a7 0100100000001111 .......... . . U U . . 6 6
\r
628 link 32 . . 0100100000001... .......... . . U U . . 6 6
\r
629 lsr 8 s . 1110...000001... .......... U U U U 6 6 4 4
\r
630 lsr 16 s . 1110...001001... .......... U U U U 6 6 4 4
\r
631 lsr 32 s . 1110...010001... .......... U U U U 8 8 4 4
\r
632 lsr 8 r . 1110...000101... .......... U U U U 6 6 6 6
\r
633 lsr 16 r . 1110...001101... .......... U U U U 6 6 6 6
\r
634 lsr 32 r . 1110...010101... .......... U U U U 8 8 6 6
\r
635 lsr 16 . . 1110001011...... A+-DXWL... U U U U 8 8 5 5
\r
636 lsl 8 s . 1110...100001... .......... U U U U 6 6 4 4
\r
637 lsl 16 s . 1110...101001... .......... U U U U 6 6 4 4
\r
638 lsl 32 s . 1110...110001... .......... U U U U 8 8 4 4
\r
639 lsl 8 r . 1110...100101... .......... U U U U 6 6 6 6
\r
640 lsl 16 r . 1110...101101... .......... U U U U 6 6 6 6
\r
641 lsl 32 r . 1110...110101... .......... U U U U 8 8 6 6
\r
642 lsl 16 . . 1110001111...... A+-DXWL... U U U U 8 8 5 5
\r
643 move 8 d d 0001...000000... .......... U U U U 4 4 2 2
\r
644 move 8 d . 0001...000...... A+-DXWLdxI U U U U 4 4 2 2
\r
645 move 8 ai d 0001...010000... .......... U U U U 8 8 4 4
\r
646 move 8 ai . 0001...010...... A+-DXWLdxI U U U U 8 8 4 4
\r
647 move 8 pi d 0001...011000... .......... U U U U 8 8 4 4
\r
648 move 8 pi . 0001...011...... A+-DXWLdxI U U U U 8 8 4 4
\r
649 move 8 pi7 d 0001111011000... .......... U U U U 8 8 4 4
\r
650 move 8 pi7 . 0001111011...... A+-DXWLdxI U U U U 8 8 4 4
\r
651 move 8 pd d 0001...100000... .......... U U U U 8 8 5 5
\r
652 move 8 pd . 0001...100...... A+-DXWLdxI U U U U 8 8 5 5
\r
653 move 8 pd7 d 0001111100000... .......... U U U U 8 8 5 5
\r
654 move 8 pd7 . 0001111100...... A+-DXWLdxI U U U U 8 8 5 5
\r
655 move 8 di d 0001...101000... .......... U U U U 12 12 5 5
\r
656 move 8 di . 0001...101...... A+-DXWLdxI U U U U 12 12 5 5
\r
657 move 8 ix d 0001...110000... .......... U U U U 14 14 7 7
\r
658 move 8 ix . 0001...110...... A+-DXWLdxI U U U U 14 14 7 7
\r
659 move 8 aw d 0001000111000... .......... U U U U 12 12 4 4
\r
660 move 8 aw . 0001000111...... A+-DXWLdxI U U U U 12 12 4 4
\r
661 move 8 al d 0001001111000... .......... U U U U 16 16 6 6
\r
662 move 8 al . 0001001111...... A+-DXWLdxI U U U U 16 16 6 6
\r
663 move 16 d d 0011...000000... .......... U U U U 4 4 2 2
\r
664 move 16 d a 0011...000001... .......... U U U U 4 4 2 2
\r
665 move 16 d . 0011...000...... A+-DXWLdxI U U U U 4 4 2 2
\r
666 move 16 ai d 0011...010000... .......... U U U U 8 8 4 4
\r
667 move 16 ai a 0011...010001... .......... U U U U 8 8 4 4
\r
668 move 16 ai . 0011...010...... A+-DXWLdxI U U U U 8 8 4 4
\r
669 move 16 pi d 0011...011000... .......... U U U U 8 8 4 4
\r
670 move 16 pi a 0011...011001... .......... U U U U 8 8 4 4
\r
671 move 16 pi . 0011...011...... A+-DXWLdxI U U U U 8 8 4 4
\r
672 move 16 pd d 0011...100000... .......... U U U U 8 8 5 5
\r
673 move 16 pd a 0011...100001... .......... U U U U 8 8 5 5
\r
674 move 16 pd . 0011...100...... A+-DXWLdxI U U U U 8 8 5 5
\r
675 move 16 di d 0011...101000... .......... U U U U 12 12 5 5
\r
676 move 16 di a 0011...101001... .......... U U U U 12 12 5 5
\r
677 move 16 di . 0011...101...... A+-DXWLdxI U U U U 12 12 5 5
\r
678 move 16 ix d 0011...110000... .......... U U U U 14 14 7 7
\r
679 move 16 ix a 0011...110001... .......... U U U U 14 14 7 7
\r
680 move 16 ix . 0011...110...... A+-DXWLdxI U U U U 14 14 7 7
\r
681 move 16 aw d 0011000111000... .......... U U U U 12 12 4 4
\r
682 move 16 aw a 0011000111001... .......... U U U U 12 12 4 4
\r
683 move 16 aw . 0011000111...... A+-DXWLdxI U U U U 12 12 4 4
\r
684 move 16 al d 0011001111000... .......... U U U U 16 16 6 6
\r
685 move 16 al a 0011001111001... .......... U U U U 16 16 6 6
\r
686 move 16 al . 0011001111...... A+-DXWLdxI U U U U 16 16 6 6
\r
687 move 32 d d 0010...000000... .......... U U U U 4 4 2 2
\r
688 move 32 d a 0010...000001... .......... U U U U 4 4 2 2
\r
689 move 32 d . 0010...000...... A+-DXWLdxI U U U U 4 4 2 2
\r
690 move 32 ai d 0010...010000... .......... U U U U 12 12 4 4
\r
691 move 32 ai a 0010...010001... .......... U U U U 12 12 4 4
\r
692 move 32 ai . 0010...010...... A+-DXWLdxI U U U U 12 12 4 4
\r
693 move 32 pi d 0010...011000... .......... U U U U 12 12 4 4
\r
694 move 32 pi a 0010...011001... .......... U U U U 12 12 4 4
\r
695 move 32 pi . 0010...011...... A+-DXWLdxI U U U U 12 12 4 4
\r
696 move 32 pd d 0010...100000... .......... U U U U 12 14 5 5
\r
697 move 32 pd a 0010...100001... .......... U U U U 12 14 5 5
\r
698 move 32 pd . 0010...100...... A+-DXWLdxI U U U U 12 14 5 5
\r
699 move 32 di d 0010...101000... .......... U U U U 16 16 5 5
\r
700 move 32 di a 0010...101001... .......... U U U U 16 16 5 5
\r
701 move 32 di . 0010...101...... A+-DXWLdxI U U U U 16 16 5 5
\r
702 move 32 ix d 0010...110000... .......... U U U U 18 18 7 7
\r
703 move 32 ix a 0010...110001... .......... U U U U 18 18 7 7
\r
704 move 32 ix . 0010...110...... A+-DXWLdxI U U U U 18 18 7 7
\r
705 move 32 aw d 0010000111000... .......... U U U U 16 16 4 4
\r
706 move 32 aw a 0010000111001... .......... U U U U 16 16 4 4
\r
707 move 32 aw . 0010000111...... A+-DXWLdxI U U U U 16 16 4 4
\r
708 move 32 al d 0010001111000... .......... U U U U 20 20 6 6
\r
709 move 32 al a 0010001111001... .......... U U U U 20 20 6 6
\r
710 move 32 al . 0010001111...... A+-DXWLdxI U U U U 20 20 6 6
\r
711 movea 16 . d 0011...001000... .......... U U U U 4 4 2 2
\r
712 movea 16 . a 0011...001001... .......... U U U U 4 4 2 2
\r
713 movea 16 . . 0011...001...... A+-DXWLdxI U U U U 4 4 2 2
\r
714 movea 32 . d 0010...001000... .......... U U U U 4 4 2 2
\r
715 movea 32 . a 0010...001001... .......... U U U U 4 4 2 2
\r
716 movea 32 . . 0010...001...... A+-DXWLdxI U U U U 4 4 2 2
\r
717 move 16 frc d 0100001011000... .......... . U U U . 4 4 4
\r
718 move 16 frc . 0100001011...... A+-DXWL... . U U U . 8 4 4
\r
719 move 16 toc d 0100010011000... .......... U U U U 12 12 4 4
\r
720 move 16 toc . 0100010011...... A+-DXWLdxI U U U U 12 12 4 4
\r
721 move 16 frs d 0100000011000... .......... U S S S 6 4 8 8 U only for 000
\r
722 move 16 frs . 0100000011...... A+-DXWL... U S S S 8 8 8 8 U only for 000
\r
723 move 16 tos d 0100011011000... .......... S S S S 12 12 8 8
\r
724 move 16 tos . 0100011011...... A+-DXWLdxI S S S S 12 12 8 8
\r
725 move 32 fru . 0100111001101... .......... S S S S 4 6 2 2
\r
726 move 32 tou . 0100111001100... .......... S S S S 4 6 2 2
\r
727 movec 32 cr . 0100111001111010 .......... . S S S . 12 6 6
\r
728 movec 32 rc . 0100111001111011 .......... . S S S . 10 12 12
\r
729 movem 16 re pd 0100100010100... .......... U U U U 8 8 4 4
\r
730 movem 16 re . 0100100010...... A..DXWL... U U U U 8 8 4 4
\r
731 movem 32 re pd 0100100011100... .......... U U U U 8 8 4 4
\r
732 movem 32 re . 0100100011...... A..DXWL... U U U U 8 8 4 4
\r
733 movem 16 er pi 0100110010011... .......... U U U U 12 12 8 8
\r
734 movem 16 er pcdi 0100110010111010 .......... U U U U 16 16 9 9
\r
735 movem 16 er pcix 0100110010111011 .......... U U U U 18 18 11 11
\r
736 movem 16 er . 0100110010...... A..DXWL... U U U U 12 12 8 8
\r
737 movem 32 er pi 0100110011011... .......... U U U U 12 12 8 8
\r
738 movem 32 er pcdi 0100110011111010 .......... U U U U 16 16 9 9
\r
739 movem 32 er pcix 0100110011111011 .......... U U U U 18 18 11 11
\r
740 movem 32 er . 0100110011...... A..DXWL... U U U U 12 12 8 8
\r
741 movep 16 er . 0000...100001... .......... U U U U 16 16 12 12
\r
742 movep 32 er . 0000...101001... .......... U U U U 24 24 18 18
\r
743 movep 16 re . 0000...110001... .......... U U U U 16 16 11 11
\r
744 movep 32 re . 0000...111001... .......... U U U U 24 24 17 17
\r
745 moveq 32 . . 0111...0........ .......... U U U U 4 4 2 2
\r
746 moves 8 . . 0000111000...... A+-DXWL... . S S S . 14 5 5
\r
747 moves 16 . . 0000111001...... A+-DXWL... . S S S . 14 5 5
\r
748 moves 32 . . 0000111010...... A+-DXWL... . S S S . 16 5 5
\r
749 move16 32 . . 1111011000100... .......... . . . U . . . 4 TODO: correct timing
\r
750 muls 16 . d 1100...111000... .......... U U U U 38 28 20 20 cycles depending on operands
\r
751 muls 16 . . 1100...111...... A+-DXWLdxI U U U U 38 28 20 20 cycles depending on operands
\r
752 mulu 16 . d 1100...011000... .......... U U U U 38 26 20 20 cycles depending on operands
\r
753 mulu 16 . . 1100...011...... A+-DXWLdxI U U U U 38 26 20 20 cycles depending on operands
\r
754 mull 32 . d 0100110000000... .......... . . U U . . 43 43
\r
755 mull 32 . . 0100110000...... A+-DXWLdxI . . U U . . 43 43
\r
756 nbcd 8 . d 0100100000000... .......... U U U U 6 6 6 6
\r
757 nbcd 8 . . 0100100000...... A+-DXWL... U U U U 8 8 6 6
\r
758 neg 8 . d 0100010000000... .......... U U U U 4 4 2 2
\r
759 neg 8 . . 0100010000...... A+-DXWL... U U U U 8 8 4 4
\r
760 neg 16 . d 0100010001000... .......... U U U U 4 4 2 2
\r
761 neg 16 . . 0100010001...... A+-DXWL... U U U U 8 8 4 4
\r
762 neg 32 . d 0100010010000... .......... U U U U 6 6 2 2
\r
763 neg 32 . . 0100010010...... A+-DXWL... U U U U 12 12 4 4
\r
764 negx 8 . d 0100000000000... .......... U U U U 4 4 2 2
\r
765 negx 8 . . 0100000000...... A+-DXWL... U U U U 8 8 4 4
\r
766 negx 16 . d 0100000001000... .......... U U U U 4 4 2 2
\r
767 negx 16 . . 0100000001...... A+-DXWL... U U U U 8 8 4 4
\r
768 negx 32 . d 0100000010000... .......... U U U U 6 6 2 2
\r
769 negx 32 . . 0100000010...... A+-DXWL... U U U U 12 12 4 4
\r
770 nop 0 . . 0100111001110001 .......... U U U U 4 4 2 2
\r
771 not 8 . d 0100011000000... .......... U U U U 4 4 2 2
\r
772 not 8 . . 0100011000...... A+-DXWL... U U U U 8 8 4 4
\r
773 not 16 . d 0100011001000... .......... U U U U 4 4 2 2
\r
774 not 16 . . 0100011001...... A+-DXWL... U U U U 8 8 4 4
\r
775 not 32 . d 0100011010000... .......... U U U U 6 6 2 2
\r
776 not 32 . . 0100011010...... A+-DXWL... U U U U 12 12 4 4
\r
777 or 8 er d 1000...000000... .......... U U U U 4 4 2 2
\r
778 or 8 er . 1000...000...... A+-DXWLdxI U U U U 4 4 2 2
\r
779 or 16 er d 1000...001000... .......... U U U U 4 4 2 2
\r
780 or 16 er . 1000...001...... A+-DXWLdxI U U U U 4 4 2 2
\r
781 or 32 er d 1000...010000... .......... U U U U 6 6 2 2
\r
782 or 32 er . 1000...010...... A+-DXWLdxI U U U U 6 6 2 2
\r
783 or 8 re . 1000...100...... A+-DXWL... U U U U 8 8 4 4
\r
784 or 16 re . 1000...101...... A+-DXWL... U U U U 8 8 4 4
\r
785 or 32 re . 1000...110...... A+-DXWL... U U U U 12 12 4 4
\r
786 ori 16 toc . 0000000000111100 .......... U U U U 20 16 12 12
\r
787 ori 16 tos . 0000000001111100 .......... S S S S 20 16 12 12
\r
788 ori 8 . d 0000000000000... .......... U U U U 8 8 2 2
\r
789 ori 8 . . 0000000000...... A+-DXWL... U U U U 12 12 4 4
\r
790 ori 16 . d 0000000001000... .......... U U U U 8 8 2 2
\r
791 ori 16 . . 0000000001...... A+-DXWL... U U U U 12 12 4 4
\r
792 ori 32 . d 0000000010000... .......... U U U U 16 14 2 2
\r
793 ori 32 . . 0000000010...... A+-DXWL... U U U U 20 20 4 4
\r
794 pack 16 rr . 1000...101000... .......... . . U U . . 6 6
\r
795 pack 16 mm ax7 1000111101001... .......... . . U U . . 13 13
\r
796 pack 16 mm ay7 1000...101001111 .......... . . U U . . 13 13
\r
797 pack 16 mm axy7 1000111101001111 .......... . . U U . . 13 13
\r
798 pack 16 mm . 1000...101001... .......... . . U U . . 13 13
\r
799 pea 32 . . 0100100001...... A..DXWLdx. U U U U 6 6 5 5
\r
800 pflush 32 . . 1111010100011000 .......... . . . S . . . 4 TODO: correct timing
\r
801 reset 0 . . 0100111001110000 .......... S S S S 0 0 0 0
\r
802 ror 8 s . 1110...000011... .......... U U U U 6 6 8 8
\r
803 ror 16 s . 1110...001011... .......... U U U U 6 6 8 8
\r
804 ror 32 s . 1110...010011... .......... U U U U 8 8 8 8
\r
805 ror 8 r . 1110...000111... .......... U U U U 6 6 8 8
\r
806 ror 16 r . 1110...001111... .......... U U U U 6 6 8 8
\r
807 ror 32 r . 1110...010111... .......... U U U U 8 8 8 8
\r
808 ror 16 . . 1110011011...... A+-DXWL... U U U U 8 8 7 7
\r
809 rol 8 s . 1110...100011... .......... U U U U 6 6 8 8
\r
810 rol 16 s . 1110...101011... .......... U U U U 6 6 8 8
\r
811 rol 32 s . 1110...110011... .......... U U U U 8 8 8 8
\r
812 rol 8 r . 1110...100111... .......... U U U U 6 6 8 8
\r
813 rol 16 r . 1110...101111... .......... U U U U 6 6 8 8
\r
814 rol 32 r . 1110...110111... .......... U U U U 8 8 8 8
\r
815 rol 16 . . 1110011111...... A+-DXWL... U U U U 8 8 7 7
\r
816 roxr 8 s . 1110...000010... .......... U U U U 6 6 12 12
\r
817 roxr 16 s . 1110...001010... .......... U U U U 6 6 12 12
\r
818 roxr 32 s . 1110...010010... .......... U U U U 8 8 12 12
\r
819 roxr 8 r . 1110...000110... .......... U U U U 6 6 12 12
\r
820 roxr 16 r . 1110...001110... .......... U U U U 6 6 12 12
\r
821 roxr 32 r . 1110...010110... .......... U U U U 8 8 12 12
\r
822 roxr 16 . . 1110010011...... A+-DXWL... U U U U 8 8 5 5
\r
823 roxl 8 s . 1110...100010... .......... U U U U 6 6 12 12
\r
824 roxl 16 s . 1110...101010... .......... U U U U 6 6 12 12
\r
825 roxl 32 s . 1110...110010... .......... U U U U 8 8 12 12
\r
826 roxl 8 r . 1110...100110... .......... U U U U 6 6 12 12
\r
827 roxl 16 r . 1110...101110... .......... U U U U 6 6 12 12
\r
828 roxl 32 r . 1110...110110... .......... U U U U 8 8 12 12
\r
829 roxl 16 . . 1110010111...... A+-DXWL... U U U U 8 8 5 5
\r
830 rtd 32 . . 0100111001110100 .......... . U U U . 16 10 10
\r
831 rte 32 . . 0100111001110011 .......... S S S S 20 24 20 20 bus fault not emulated
\r
832 rtm 32 . . 000001101100.... .......... . . U U . . 19 19 not properly emulated
\r
833 rtr 32 . . 0100111001110111 .......... U U U U 20 20 14 14
\r
834 rts 32 . . 0100111001110101 .......... U U U U 16 16 10 10
\r
835 sbcd 8 rr . 1000...100000... .......... U U U U 6 6 4 4
\r
836 sbcd 8 mm ax7 1000111100001... .......... U U U U 18 18 16 16
\r
837 sbcd 8 mm ay7 1000...100001111 .......... U U U U 18 18 16 16
\r
838 sbcd 8 mm axy7 1000111100001111 .......... U U U U 18 18 16 16
\r
839 sbcd 8 mm . 1000...100001... .......... U U U U 18 18 16 16
\r
840 st 8 . d 0101000011000... .......... U U U U 6 4 4 4
\r
841 st 8 . . 0101000011...... A+-DXWL... U U U U 8 8 6 6
\r
842 sf 8 . d 0101000111000... .......... U U U U 4 4 4 4
\r
843 sf 8 . . 0101000111...... A+-DXWL... U U U U 8 8 6 6
\r
844 scc 8 . d 0101....11000... .......... U U U U 4 4 4 4
\r
845 scc 8 . . 0101....11...... A+-DXWL... U U U U 8 8 6 6
\r
846 stop 0 . . 0100111001110010 .......... S S S S 4 4 8 8
\r
847 sub 8 er d 1001...000000... .......... U U U U 4 4 2 2
\r
848 sub 8 er . 1001...000...... A+-DXWLdxI U U U U 4 4 2 2
\r
849 sub 16 er d 1001...001000... .......... U U U U 4 4 2 2
\r
850 sub 16 er a 1001...001001... .......... U U U U 4 4 2 2
\r
851 sub 16 er . 1001...001...... A+-DXWLdxI U U U U 4 4 2 2
\r
852 sub 32 er d 1001...010000... .......... U U U U 6 6 2 2
\r
853 sub 32 er a 1001...010001... .......... U U U U 6 6 2 2
\r
854 sub 32 er . 1001...010...... A+-DXWLdxI U U U U 6 6 2 2
\r
855 sub 8 re . 1001...100...... A+-DXWL... U U U U 8 8 4 4
\r
856 sub 16 re . 1001...101...... A+-DXWL... U U U U 8 8 4 4
\r
857 sub 32 re . 1001...110...... A+-DXWL... U U U U 12 12 4 4
\r
858 suba 16 . d 1001...011000... .......... U U U U 8 8 2 2
\r
859 suba 16 . a 1001...011001... .......... U U U U 8 8 2 2
\r
860 suba 16 . . 1001...011...... A+-DXWLdxI U U U U 8 8 2 2
\r
861 suba 32 . d 1001...111000... .......... U U U U 6 6 2 2
\r
862 suba 32 . a 1001...111001... .......... U U U U 6 6 2 2
\r
863 suba 32 . . 1001...111...... A+-DXWLdxI U U U U 6 6 2 2
\r
864 subi 8 . d 0000010000000... .......... U U U U 8 8 2 2
\r
865 subi 8 . . 0000010000...... A+-DXWL... U U U U 12 12 4 4
\r
866 subi 16 . d 0000010001000... .......... U U U U 8 8 2 2
\r
867 subi 16 . . 0000010001...... A+-DXWL... U U U U 12 12 4 4
\r
868 subi 32 . d 0000010010000... .......... U U U U 16 14 2 2
\r
869 subi 32 . . 0000010010...... A+-DXWL... U U U U 20 20 4 4
\r
870 subq 8 . d 0101...100000... .......... U U U U 4 4 2 2
\r
871 subq 8 . . 0101...100...... A+-DXWL... U U U U 8 8 4 4
\r
872 subq 16 . d 0101...101000... .......... U U U U 4 4 2 2
\r
873 subq 16 . a 0101...101001... .......... U U U U 8 4 2 2
\r
874 subq 16 . . 0101...101...... A+-DXWL... U U U U 8 8 4 4
\r
875 subq 32 . d 0101...110000... .......... U U U U 8 8 2 2
\r
876 subq 32 . a 0101...110001... .......... U U U U 8 8 2 2
\r
877 subq 32 . . 0101...110...... A+-DXWL... U U U U 12 12 4 4
\r
878 subx 8 rr . 1001...100000... .......... U U U U 4 4 2 2
\r
879 subx 16 rr . 1001...101000... .......... U U U U 4 4 2 2
\r
880 subx 32 rr . 1001...110000... .......... U U U U 8 6 2 2
\r
881 subx 8 mm ax7 1001111100001... .......... U U U U 18 18 12 12
\r
882 subx 8 mm ay7 1001...100001111 .......... U U U U 18 18 12 12
\r
883 subx 8 mm axy7 1001111100001111 .......... U U U U 18 18 12 12
\r
884 subx 8 mm . 1001...100001... .......... U U U U 18 18 12 12
\r
885 subx 16 mm . 1001...101001... .......... U U U U 18 18 12 12
\r
886 subx 32 mm . 1001...110001... .......... U U U U 30 30 12 12
\r
887 swap 32 . . 0100100001000... .......... U U U U 4 4 4 4
\r
888 tas 8 . d 0100101011000... .......... U U U U 4 4 4 4
\r
889 tas 8 . . 0100101011...... A+-DXWL... U U U U 10 10 8 8
\r
890 trap 0 . . 010011100100.... .......... U U U U 4 4 4 4
\r
891 trapt 0 . . 0101000011111100 .......... . . U U . . 4 4
\r
892 trapt 16 . . 0101000011111010 .......... . . U U . . 6 6
\r
893 trapt 32 . . 0101000011111011 .......... . . U U . . 8 8
\r
894 trapf 0 . . 0101000111111100 .......... . . U U . . 4 4
\r
895 trapf 16 . . 0101000111111010 .......... . . U U . . 6 6
\r
896 trapf 32 . . 0101000111111011 .......... . . U U . . 8 8
\r
897 trapcc 0 . . 0101....11111100 .......... . . U U . . 4 4
\r
898 trapcc 16 . . 0101....11111010 .......... . . U U . . 6 6
\r
899 trapcc 32 . . 0101....11111011 .......... . . U U . . 8 8
\r
900 trapv 0 . . 0100111001110110 .......... U U U U 4 4 4 4
\r
901 tst 8 . d 0100101000000... .......... U U U U 4 4 2 2
\r
902 tst 8 . . 0100101000...... A+-DXWL... U U U U 4 4 2 2
\r
903 tst 8 . pcdi 0100101000111010 .......... . . U U . . 7 7
\r
904 tst 8 . pcix 0100101000111011 .......... . . U U . . 9 9
\r
905 tst 8 . i 0100101000111100 .......... . . U U . . 6 6
\r
906 tst 16 . d 0100101001000... .......... U U U U 4 4 2 2
\r
907 tst 16 . a 0100101001001... .......... . . U U . . 2 2
\r
908 tst 16 . . 0100101001...... A+-DXWL... U U U U 4 4 2 2
\r
909 tst 16 . pcdi 0100101001111010 .......... . . U U . . 7 7
\r
910 tst 16 . pcix 0100101001111011 .......... . . U U . . 9 9
\r
911 tst 16 . i 0100101001111100 .......... . . U U . . 6 6
\r
912 tst 32 . d 0100101010000... .......... U U U U 4 4 2 2
\r
913 tst 32 . a 0100101010001... .......... . . U U . . 2 2
\r
914 tst 32 . . 0100101010...... A+-DXWL... U U U U 4 4 2 2
\r
915 tst 32 . pcdi 0100101010111010 .......... . . U U . . 7 7
\r
916 tst 32 . pcix 0100101010111011 .......... . . U U . . 9 9
\r
917 tst 32 . i 0100101010111100 .......... . . U U . . 6 6
\r
918 unlk 32 . a7 0100111001011111 .......... U U U U 12 12 6 6
\r
919 unlk 32 . . 0100111001011... .......... U U U U 12 12 6 6
\r
920 unpk 16 rr . 1000...110000... .......... . . U U . . 8 8
\r
921 unpk 16 mm ax7 1000111110001... .......... . . U U . . 13 13
\r
922 unpk 16 mm ay7 1000...110001111 .......... . . U U . . 13 13
\r
923 unpk 16 mm axy7 1000111110001111 .......... . . U U . . 13 13
\r
924 unpk 16 mm . 1000...110001... .......... . . U U . . 13 13
\r
928 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
\r
929 M68KMAKE_OPCODE_HANDLER_BODY
\r
931 M68KMAKE_OP(1010, 0, ., .)
\r
933 m68ki_exception_1010();
\r
937 M68KMAKE_OP(1111, 0, ., .)
\r
939 m68ki_exception_1111();
\r
943 M68KMAKE_OP(040fpu0, 32, ., .)
\r
945 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
950 m68ki_exception_1111();
\r
954 M68KMAKE_OP(040fpu1, 32, ., .)
\r
956 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
961 m68ki_exception_1111();
\r
966 M68KMAKE_OP(abcd, 8, rr, .)
\r
971 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
\r
976 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
\r
977 FLAG_V = ~res; /* Undefined V behavior */
\r
980 FLAG_X = FLAG_C = (res > 0x9f) << 8;
\r
984 FLAG_V &= res; /* Undefined V behavior part II */
\r
985 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
987 res = MASK_OUT_ABOVE_8(res);
\r
990 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
994 M68KMAKE_OP(abcd, 8, mm, ax7)
\r
996 uint src = OPER_AY_PD_8();
\r
997 uint ea = EA_A7_PD_8();
\r
998 uint dst = m68ki_read_8(ea);
\r
999 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
\r
1004 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
\r
1005 FLAG_V = ~res; /* Undefined V behavior */
\r
1008 FLAG_X = FLAG_C = (res > 0x9f) << 8;
\r
1012 FLAG_V &= res; /* Undefined V behavior part II */
\r
1013 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
1015 res = MASK_OUT_ABOVE_8(res);
\r
1018 m68ki_write_8(ea, res);
\r
1022 M68KMAKE_OP(abcd, 8, mm, ay7)
\r
1024 uint src = OPER_A7_PD_8();
\r
1025 uint ea = EA_AX_PD_8();
\r
1026 uint dst = m68ki_read_8(ea);
\r
1027 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
\r
1032 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
\r
1033 FLAG_V = ~res; /* Undefined V behavior */
\r
1036 FLAG_X = FLAG_C = (res > 0x9f) << 8;
\r
1040 FLAG_V &= res; /* Undefined V behavior part II */
\r
1041 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
1043 res = MASK_OUT_ABOVE_8(res);
\r
1046 m68ki_write_8(ea, res);
\r
1050 M68KMAKE_OP(abcd, 8, mm, axy7)
\r
1052 uint src = OPER_A7_PD_8();
\r
1053 uint ea = EA_A7_PD_8();
\r
1054 uint dst = m68ki_read_8(ea);
\r
1055 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
\r
1060 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
\r
1061 FLAG_V = ~res; /* Undefined V behavior */
\r
1064 FLAG_X = FLAG_C = (res > 0x9f) << 8;
\r
1068 FLAG_V &= res; /* Undefined V behavior part II */
\r
1069 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
1071 res = MASK_OUT_ABOVE_8(res);
\r
1074 m68ki_write_8(ea, res);
\r
1078 M68KMAKE_OP(abcd, 8, mm, .)
\r
1080 uint src = OPER_AY_PD_8();
\r
1081 uint ea = EA_AX_PD_8();
\r
1082 uint dst = m68ki_read_8(ea);
\r
1083 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
\r
1088 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
\r
1089 FLAG_V = ~res; /* Undefined V behavior */
\r
1092 FLAG_X = FLAG_C = (res > 0x9f) << 8;
\r
1096 FLAG_V &= res; /* Undefined V behavior part II */
\r
1097 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
1099 res = MASK_OUT_ABOVE_8(res);
\r
1102 m68ki_write_8(ea, res);
\r
1106 M68KMAKE_OP(add, 8, er, d)
\r
1108 uint* r_dst = &DX;
\r
1109 uint src = MASK_OUT_ABOVE_8(DY);
\r
1110 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
1111 uint res = src + dst;
\r
1113 FLAG_N = NFLAG_8(res);
\r
1114 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1115 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1116 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1118 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
1122 M68KMAKE_OP(add, 8, er, .)
\r
1124 uint* r_dst = &DX;
\r
1125 uint src = M68KMAKE_GET_OPER_AY_8;
\r
1126 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
1127 uint res = src + dst;
\r
1129 FLAG_N = NFLAG_8(res);
\r
1130 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1131 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1132 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1134 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
1138 M68KMAKE_OP(add, 16, er, d)
\r
1140 uint* r_dst = &DX;
\r
1141 uint src = MASK_OUT_ABOVE_16(DY);
\r
1142 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
1143 uint res = src + dst;
\r
1145 FLAG_N = NFLAG_16(res);
\r
1146 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1147 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1148 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1150 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
1154 M68KMAKE_OP(add, 16, er, a)
\r
1156 uint* r_dst = &DX;
\r
1157 uint src = MASK_OUT_ABOVE_16(AY);
\r
1158 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
1159 uint res = src + dst;
\r
1161 FLAG_N = NFLAG_16(res);
\r
1162 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1163 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1164 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1166 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
1170 M68KMAKE_OP(add, 16, er, .)
\r
1172 uint* r_dst = &DX;
\r
1173 uint src = M68KMAKE_GET_OPER_AY_16;
\r
1174 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
1175 uint res = src + dst;
\r
1177 FLAG_N = NFLAG_16(res);
\r
1178 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1179 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1180 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1182 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
1186 M68KMAKE_OP(add, 32, er, d)
\r
1188 uint* r_dst = &DX;
\r
1190 uint dst = *r_dst;
\r
1191 uint res = src + dst;
\r
1193 FLAG_N = NFLAG_32(res);
\r
1194 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1195 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1196 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1202 M68KMAKE_OP(add, 32, er, a)
\r
1204 uint* r_dst = &DX;
\r
1206 uint dst = *r_dst;
\r
1207 uint res = src + dst;
\r
1209 FLAG_N = NFLAG_32(res);
\r
1210 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1211 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1212 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1218 M68KMAKE_OP(add, 32, er, .)
\r
1220 uint* r_dst = &DX;
\r
1221 uint src = M68KMAKE_GET_OPER_AY_32;
\r
1222 uint dst = *r_dst;
\r
1223 uint res = src + dst;
\r
1225 FLAG_N = NFLAG_32(res);
\r
1226 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1227 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1228 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1234 M68KMAKE_OP(add, 8, re, .)
\r
1236 uint ea = M68KMAKE_GET_EA_AY_8;
\r
1237 uint src = MASK_OUT_ABOVE_8(DX);
\r
1238 uint dst = m68ki_read_8(ea);
\r
1239 uint res = src + dst;
\r
1241 FLAG_N = NFLAG_8(res);
\r
1242 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1243 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1244 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1246 m68ki_write_8(ea, FLAG_Z);
\r
1250 M68KMAKE_OP(add, 16, re, .)
\r
1252 uint ea = M68KMAKE_GET_EA_AY_16;
\r
1253 uint src = MASK_OUT_ABOVE_16(DX);
\r
1254 uint dst = m68ki_read_16(ea);
\r
1255 uint res = src + dst;
\r
1257 FLAG_N = NFLAG_16(res);
\r
1258 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1259 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1260 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1262 m68ki_write_16(ea, FLAG_Z);
\r
1266 M68KMAKE_OP(add, 32, re, .)
\r
1268 uint ea = M68KMAKE_GET_EA_AY_32;
\r
1270 uint dst = m68ki_read_32(ea);
\r
1271 uint res = src + dst;
\r
1273 FLAG_N = NFLAG_32(res);
\r
1274 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1275 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1276 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1278 m68ki_write_32(ea, FLAG_Z);
\r
1282 M68KMAKE_OP(adda, 16, ., d)
\r
1284 uint* r_dst = &AX;
\r
1286 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(DY));
\r
1290 M68KMAKE_OP(adda, 16, ., a)
\r
1292 uint* r_dst = &AX;
\r
1294 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(AY));
\r
1298 M68KMAKE_OP(adda, 16, ., .)
\r
1300 uint* r_dst = &AX;
\r
1301 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
\r
1303 *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
\r
1307 M68KMAKE_OP(adda, 32, ., d)
\r
1309 uint* r_dst = &AX;
\r
1311 *r_dst = MASK_OUT_ABOVE_32(*r_dst + DY);
\r
1315 M68KMAKE_OP(adda, 32, ., a)
\r
1317 uint* r_dst = &AX;
\r
1319 *r_dst = MASK_OUT_ABOVE_32(*r_dst + AY);
\r
1323 M68KMAKE_OP(adda, 32, ., .)
\r
1325 uint* r_dst = &AX;
\r
1326 uint src = M68KMAKE_GET_OPER_AY_32; // notaz
\r
1328 *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
\r
1332 M68KMAKE_OP(addi, 8, ., d)
\r
1334 uint* r_dst = &DY;
\r
1335 uint src = OPER_I_8();
\r
1336 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
1337 uint res = src + dst;
\r
1339 FLAG_N = NFLAG_8(res);
\r
1340 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1341 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1342 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1344 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
1348 M68KMAKE_OP(addi, 8, ., .)
\r
1350 uint src = OPER_I_8();
\r
1351 uint ea = M68KMAKE_GET_EA_AY_8;
\r
1352 uint dst = m68ki_read_8(ea);
\r
1353 uint res = src + dst;
\r
1355 FLAG_N = NFLAG_8(res);
\r
1356 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1357 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1358 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1360 m68ki_write_8(ea, FLAG_Z);
\r
1364 M68KMAKE_OP(addi, 16, ., d)
\r
1366 uint* r_dst = &DY;
\r
1367 uint src = OPER_I_16();
\r
1368 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
1369 uint res = src + dst;
\r
1371 FLAG_N = NFLAG_16(res);
\r
1372 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1373 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1374 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1376 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
1380 M68KMAKE_OP(addi, 16, ., .)
\r
1382 uint src = OPER_I_16();
\r
1383 uint ea = M68KMAKE_GET_EA_AY_16;
\r
1384 uint dst = m68ki_read_16(ea);
\r
1385 uint res = src + dst;
\r
1387 FLAG_N = NFLAG_16(res);
\r
1388 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1389 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1390 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1392 m68ki_write_16(ea, FLAG_Z);
\r
1396 M68KMAKE_OP(addi, 32, ., d)
\r
1398 uint* r_dst = &DY;
\r
1399 uint src = OPER_I_32();
\r
1400 uint dst = *r_dst;
\r
1401 uint res = src + dst;
\r
1403 FLAG_N = NFLAG_32(res);
\r
1404 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1405 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1406 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1412 M68KMAKE_OP(addi, 32, ., .)
\r
1414 uint src = OPER_I_32();
\r
1415 uint ea = M68KMAKE_GET_EA_AY_32;
\r
1416 uint dst = m68ki_read_32(ea);
\r
1417 uint res = src + dst;
\r
1419 FLAG_N = NFLAG_32(res);
\r
1420 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1421 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1422 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1424 m68ki_write_32(ea, FLAG_Z);
\r
1428 M68KMAKE_OP(addq, 8, ., d)
\r
1430 uint* r_dst = &DY;
\r
1431 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1432 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
1433 uint res = src + dst;
\r
1435 FLAG_N = NFLAG_8(res);
\r
1436 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1437 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1438 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1440 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
1444 M68KMAKE_OP(addq, 8, ., .)
\r
1446 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1447 uint ea = M68KMAKE_GET_EA_AY_8;
\r
1448 uint dst = m68ki_read_8(ea);
\r
1449 uint res = src + dst;
\r
1451 FLAG_N = NFLAG_8(res);
\r
1452 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1453 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1454 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1456 m68ki_write_8(ea, FLAG_Z);
\r
1460 M68KMAKE_OP(addq, 16, ., d)
\r
1462 uint* r_dst = &DY;
\r
1463 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1464 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
1465 uint res = src + dst;
\r
1467 FLAG_N = NFLAG_16(res);
\r
1468 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1469 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1470 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1472 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
1476 M68KMAKE_OP(addq, 16, ., a)
\r
1478 uint* r_dst = &AY;
\r
1480 *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);
\r
1484 M68KMAKE_OP(addq, 16, ., .)
\r
1486 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1487 uint ea = M68KMAKE_GET_EA_AY_16;
\r
1488 uint dst = m68ki_read_16(ea);
\r
1489 uint res = src + dst;
\r
1491 FLAG_N = NFLAG_16(res);
\r
1492 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1493 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1494 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1496 m68ki_write_16(ea, FLAG_Z);
\r
1500 M68KMAKE_OP(addq, 32, ., d)
\r
1502 uint* r_dst = &DY;
\r
1503 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1504 uint dst = *r_dst;
\r
1505 uint res = src + dst;
\r
1507 FLAG_N = NFLAG_32(res);
\r
1508 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1509 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1510 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1516 M68KMAKE_OP(addq, 32, ., a)
\r
1518 uint* r_dst = &AY;
\r
1520 *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);
\r
1524 M68KMAKE_OP(addq, 32, ., .)
\r
1526 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1527 uint ea = M68KMAKE_GET_EA_AY_32;
\r
1528 uint dst = m68ki_read_32(ea);
\r
1529 uint res = src + dst;
\r
1532 FLAG_N = NFLAG_32(res);
\r
1533 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1534 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1535 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1537 m68ki_write_32(ea, FLAG_Z);
\r
1541 M68KMAKE_OP(addx, 8, rr, .)
\r
1543 uint* r_dst = &DX;
\r
1544 uint src = MASK_OUT_ABOVE_8(DY);
\r
1545 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
1546 uint res = src + dst + XFLAG_AS_1();
\r
1548 FLAG_N = NFLAG_8(res);
\r
1549 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1550 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1552 res = MASK_OUT_ABOVE_8(res);
\r
1555 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
1559 M68KMAKE_OP(addx, 16, rr, .)
\r
1561 uint* r_dst = &DX;
\r
1562 uint src = MASK_OUT_ABOVE_16(DY);
\r
1563 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
1564 uint res = src + dst + XFLAG_AS_1();
\r
1566 FLAG_N = NFLAG_16(res);
\r
1567 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1568 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1570 res = MASK_OUT_ABOVE_16(res);
\r
1573 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
1577 M68KMAKE_OP(addx, 32, rr, .)
\r
1579 uint* r_dst = &DX;
\r
1581 uint dst = *r_dst;
\r
1582 uint res = src + dst + XFLAG_AS_1();
\r
1584 FLAG_N = NFLAG_32(res);
\r
1585 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1586 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1588 res = MASK_OUT_ABOVE_32(res);
\r
1595 M68KMAKE_OP(addx, 8, mm, ax7)
\r
1597 uint src = OPER_AY_PD_8();
\r
1598 uint ea = EA_A7_PD_8();
\r
1599 uint dst = m68ki_read_8(ea);
\r
1600 uint res = src + dst + XFLAG_AS_1();
\r
1602 FLAG_N = NFLAG_8(res);
\r
1603 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1604 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1606 res = MASK_OUT_ABOVE_8(res);
\r
1609 m68ki_write_8(ea, res);
\r
1613 M68KMAKE_OP(addx, 8, mm, ay7)
\r
1615 uint src = OPER_A7_PD_8();
\r
1616 uint ea = EA_AX_PD_8();
\r
1617 uint dst = m68ki_read_8(ea);
\r
1618 uint res = src + dst + XFLAG_AS_1();
\r
1620 FLAG_N = NFLAG_8(res);
\r
1621 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1622 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1624 res = MASK_OUT_ABOVE_8(res);
\r
1627 m68ki_write_8(ea, res);
\r
1631 M68KMAKE_OP(addx, 8, mm, axy7)
\r
1633 uint src = OPER_A7_PD_8();
\r
1634 uint ea = EA_A7_PD_8();
\r
1635 uint dst = m68ki_read_8(ea);
\r
1636 uint res = src + dst + XFLAG_AS_1();
\r
1638 FLAG_N = NFLAG_8(res);
\r
1639 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1640 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1642 res = MASK_OUT_ABOVE_8(res);
\r
1645 m68ki_write_8(ea, res);
\r
1649 M68KMAKE_OP(addx, 8, mm, .)
\r
1651 uint src = OPER_AY_PD_8();
\r
1652 uint ea = EA_AX_PD_8();
\r
1653 uint dst = m68ki_read_8(ea);
\r
1654 uint res = src + dst + XFLAG_AS_1();
\r
1656 FLAG_N = NFLAG_8(res);
\r
1657 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1658 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1660 res = MASK_OUT_ABOVE_8(res);
\r
1663 m68ki_write_8(ea, res);
\r
1667 M68KMAKE_OP(addx, 16, mm, .)
\r
1669 uint src = OPER_AY_PD_16();
\r
1670 uint ea = EA_AX_PD_16();
\r
1671 uint dst = m68ki_read_16(ea);
\r
1672 uint res = src + dst + XFLAG_AS_1();
\r
1674 FLAG_N = NFLAG_16(res);
\r
1675 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1676 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1678 res = MASK_OUT_ABOVE_16(res);
\r
1681 m68ki_write_16(ea, res);
\r
1685 M68KMAKE_OP(addx, 32, mm, .)
\r
1687 uint src = OPER_AY_PD_32();
\r
1688 uint ea = EA_AX_PD_32();
\r
1689 uint dst = m68ki_read_32(ea);
\r
1690 uint res = src + dst + XFLAG_AS_1();
\r
1692 FLAG_N = NFLAG_32(res);
\r
1693 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1694 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1696 res = MASK_OUT_ABOVE_32(res);
\r
1699 m68ki_write_32(ea, res);
\r
1703 M68KMAKE_OP(and, 8, er, d)
\r
1705 FLAG_Z = MASK_OUT_ABOVE_8(DX &= (DY | 0xffffff00));
\r
1707 FLAG_N = NFLAG_8(FLAG_Z);
\r
1708 FLAG_C = CFLAG_CLEAR;
\r
1709 FLAG_V = VFLAG_CLEAR;
\r
1713 M68KMAKE_OP(and, 8, er, .)
\r
1715 FLAG_Z = MASK_OUT_ABOVE_8(DX &= (M68KMAKE_GET_OPER_AY_8 | 0xffffff00));
\r
1717 FLAG_N = NFLAG_8(FLAG_Z);
\r
1718 FLAG_C = CFLAG_CLEAR;
\r
1719 FLAG_V = VFLAG_CLEAR;
\r
1723 M68KMAKE_OP(and, 16, er, d)
\r
1725 FLAG_Z = MASK_OUT_ABOVE_16(DX &= (DY | 0xffff0000));
\r
1727 FLAG_N = NFLAG_16(FLAG_Z);
\r
1728 FLAG_C = CFLAG_CLEAR;
\r
1729 FLAG_V = VFLAG_CLEAR;
\r
1733 M68KMAKE_OP(and, 16, er, .)
\r
1735 FLAG_Z = MASK_OUT_ABOVE_16(DX &= (M68KMAKE_GET_OPER_AY_16 | 0xffff0000));
\r
1737 FLAG_N = NFLAG_16(FLAG_Z);
\r
1738 FLAG_C = CFLAG_CLEAR;
\r
1739 FLAG_V = VFLAG_CLEAR;
\r
1743 M68KMAKE_OP(and, 32, er, d)
\r
1745 FLAG_Z = DX &= DY;
\r
1747 FLAG_N = NFLAG_32(FLAG_Z);
\r
1748 FLAG_C = CFLAG_CLEAR;
\r
1749 FLAG_V = VFLAG_CLEAR;
\r
1753 M68KMAKE_OP(and, 32, er, .)
\r
1755 FLAG_Z = DX &= M68KMAKE_GET_OPER_AY_32;
\r
1757 FLAG_N = NFLAG_32(FLAG_Z);
\r
1758 FLAG_C = CFLAG_CLEAR;
\r
1759 FLAG_V = VFLAG_CLEAR;
\r
1763 M68KMAKE_OP(and, 8, re, .)
\r
1765 uint ea = M68KMAKE_GET_EA_AY_8;
\r
1766 uint res = DX & m68ki_read_8(ea);
\r
1768 FLAG_N = NFLAG_8(res);
\r
1769 FLAG_C = CFLAG_CLEAR;
\r
1770 FLAG_V = VFLAG_CLEAR;
\r
1771 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1773 m68ki_write_8(ea, FLAG_Z);
\r
1777 M68KMAKE_OP(and, 16, re, .)
\r
1779 uint ea = M68KMAKE_GET_EA_AY_16;
\r
1780 uint res = DX & m68ki_read_16(ea);
\r
1782 FLAG_N = NFLAG_16(res);
\r
1783 FLAG_C = CFLAG_CLEAR;
\r
1784 FLAG_V = VFLAG_CLEAR;
\r
1785 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1787 m68ki_write_16(ea, FLAG_Z);
\r
1791 M68KMAKE_OP(and, 32, re, .)
\r
1793 uint ea = M68KMAKE_GET_EA_AY_32;
\r
1794 uint res = DX & m68ki_read_32(ea);
\r
1796 FLAG_N = NFLAG_32(res);
\r
1798 FLAG_C = CFLAG_CLEAR;
\r
1799 FLAG_V = VFLAG_CLEAR;
\r
1801 m68ki_write_32(ea, res);
\r
1805 M68KMAKE_OP(andi, 8, ., d)
\r
1807 FLAG_Z = MASK_OUT_ABOVE_8(DY &= (OPER_I_8() | 0xffffff00));
\r
1809 FLAG_N = NFLAG_8(FLAG_Z);
\r
1810 FLAG_C = CFLAG_CLEAR;
\r
1811 FLAG_V = VFLAG_CLEAR;
\r
1815 M68KMAKE_OP(andi, 8, ., .)
\r
1817 uint src = OPER_I_8();
\r
1818 uint ea = M68KMAKE_GET_EA_AY_8;
\r
1819 uint res = src & m68ki_read_8(ea);
\r
1821 FLAG_N = NFLAG_8(res);
\r
1823 FLAG_C = CFLAG_CLEAR;
\r
1824 FLAG_V = VFLAG_CLEAR;
\r
1826 m68ki_write_8(ea, res);
\r
1830 M68KMAKE_OP(andi, 16, ., d)
\r
1832 FLAG_Z = MASK_OUT_ABOVE_16(DY &= (OPER_I_16() | 0xffff0000));
\r
1834 FLAG_N = NFLAG_16(FLAG_Z);
\r
1835 FLAG_C = CFLAG_CLEAR;
\r
1836 FLAG_V = VFLAG_CLEAR;
\r
1840 M68KMAKE_OP(andi, 16, ., .)
\r
1842 uint src = OPER_I_16();
\r
1843 uint ea = M68KMAKE_GET_EA_AY_16;
\r
1844 uint res = src & m68ki_read_16(ea);
\r
1846 FLAG_N = NFLAG_16(res);
\r
1848 FLAG_C = CFLAG_CLEAR;
\r
1849 FLAG_V = VFLAG_CLEAR;
\r
1851 m68ki_write_16(ea, res);
\r
1855 M68KMAKE_OP(andi, 32, ., d)
\r
1857 FLAG_Z = DY &= (OPER_I_32());
\r
1859 FLAG_N = NFLAG_32(FLAG_Z);
\r
1860 FLAG_C = CFLAG_CLEAR;
\r
1861 FLAG_V = VFLAG_CLEAR;
\r
1865 M68KMAKE_OP(andi, 32, ., .)
\r
1867 uint src = OPER_I_32();
\r
1868 uint ea = M68KMAKE_GET_EA_AY_32;
\r
1869 uint res = src & m68ki_read_32(ea);
\r
1871 FLAG_N = NFLAG_32(res);
\r
1873 FLAG_C = CFLAG_CLEAR;
\r
1874 FLAG_V = VFLAG_CLEAR;
\r
1876 m68ki_write_32(ea, res);
\r
1880 M68KMAKE_OP(andi, 16, toc, .)
\r
1882 m68ki_set_ccr(m68ki_get_ccr() & OPER_I_16());
\r
1886 M68KMAKE_OP(andi, 16, tos, .)
\r
1890 uint src = OPER_I_16();
\r
1891 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
1892 m68ki_set_sr(m68ki_get_sr() & src);
\r
1895 m68ki_exception_privilege_violation();
\r
1899 M68KMAKE_OP(asr, 8, s, .)
\r
1901 uint* r_dst = &DY;
\r
1902 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1903 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
1904 uint res = src >> shift;
\r
1907 USE_CYCLES(shift<<CYC_SHIFT);
\r
1909 if(GET_MSB_8(src))
\r
1910 res |= m68ki_shift_8_table[shift];
\r
1912 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
1914 FLAG_N = NFLAG_8(res);
\r
1916 FLAG_V = VFLAG_CLEAR;
\r
1917 FLAG_X = FLAG_C = src << (9-shift);
\r
1921 M68KMAKE_OP(asr, 16, s, .)
\r
1923 uint* r_dst = &DY;
\r
1924 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1925 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
1926 uint res = src >> shift;
\r
1929 USE_CYCLES(shift<<CYC_SHIFT);
\r
1931 if(GET_MSB_16(src))
\r
1932 res |= m68ki_shift_16_table[shift];
\r
1934 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
1936 FLAG_N = NFLAG_16(res);
\r
1938 FLAG_V = VFLAG_CLEAR;
\r
1939 FLAG_X = FLAG_C = src << (9-shift);
\r
1943 M68KMAKE_OP(asr, 32, s, .)
\r
1945 uint* r_dst = &DY;
\r
1946 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1947 uint src = *r_dst;
\r
1948 uint res = src >> shift;
\r
1951 USE_CYCLES(shift<<CYC_SHIFT);
\r
1953 if(GET_MSB_32(src))
\r
1954 res |= m68ki_shift_32_table[shift];
\r
1958 FLAG_N = NFLAG_32(res);
\r
1960 FLAG_V = VFLAG_CLEAR;
\r
1961 FLAG_X = FLAG_C = src << (9-shift);
\r
1965 M68KMAKE_OP(asr, 8, r, .)
\r
1967 uint* r_dst = &DY;
\r
1968 uint shift = DX & 0x3f;
\r
1969 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
1970 uint res = src >> shift;
\r
1974 USE_CYCLES(shift<<CYC_SHIFT);
\r
1978 if(GET_MSB_8(src))
\r
1979 res |= m68ki_shift_8_table[shift];
\r
1981 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
1983 FLAG_X = FLAG_C = src << (9-shift);
\r
1984 FLAG_N = NFLAG_8(res);
\r
1986 FLAG_V = VFLAG_CLEAR;
\r
1990 if(GET_MSB_8(src))
\r
1993 FLAG_C = CFLAG_SET;
\r
1994 FLAG_X = XFLAG_SET;
\r
1995 FLAG_N = NFLAG_SET;
\r
1996 FLAG_Z = ZFLAG_CLEAR;
\r
1997 FLAG_V = VFLAG_CLEAR;
\r
2001 *r_dst &= 0xffffff00;
\r
2002 FLAG_C = CFLAG_CLEAR;
\r
2003 FLAG_X = XFLAG_CLEAR;
\r
2004 FLAG_N = NFLAG_CLEAR;
\r
2005 FLAG_Z = ZFLAG_SET;
\r
2006 FLAG_V = VFLAG_CLEAR;
\r
2010 FLAG_C = CFLAG_CLEAR;
\r
2011 FLAG_N = NFLAG_8(src);
\r
2013 FLAG_V = VFLAG_CLEAR;
\r
2017 M68KMAKE_OP(asr, 16, r, .)
\r
2019 uint* r_dst = &DY;
\r
2020 uint shift = DX & 0x3f;
\r
2021 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
2022 uint res = src >> shift;
\r
2026 USE_CYCLES(shift<<CYC_SHIFT);
\r
2030 if(GET_MSB_16(src))
\r
2031 res |= m68ki_shift_16_table[shift];
\r
2033 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
2035 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
\r
2036 FLAG_N = NFLAG_16(res);
\r
2038 FLAG_V = VFLAG_CLEAR;
\r
2042 if(GET_MSB_16(src))
\r
2045 FLAG_C = CFLAG_SET;
\r
2046 FLAG_X = XFLAG_SET;
\r
2047 FLAG_N = NFLAG_SET;
\r
2048 FLAG_Z = ZFLAG_CLEAR;
\r
2049 FLAG_V = VFLAG_CLEAR;
\r
2053 *r_dst &= 0xffff0000;
\r
2054 FLAG_C = CFLAG_CLEAR;
\r
2055 FLAG_X = XFLAG_CLEAR;
\r
2056 FLAG_N = NFLAG_CLEAR;
\r
2057 FLAG_Z = ZFLAG_SET;
\r
2058 FLAG_V = VFLAG_CLEAR;
\r
2062 FLAG_C = CFLAG_CLEAR;
\r
2063 FLAG_N = NFLAG_16(src);
\r
2065 FLAG_V = VFLAG_CLEAR;
\r
2069 M68KMAKE_OP(asr, 32, r, .)
\r
2071 uint* r_dst = &DY;
\r
2072 uint shift = DX & 0x3f;
\r
2073 uint src = *r_dst;
\r
2074 uint res = src >> shift;
\r
2078 USE_CYCLES(shift<<CYC_SHIFT);
\r
2082 if(GET_MSB_32(src))
\r
2083 res |= m68ki_shift_32_table[shift];
\r
2087 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
\r
2088 FLAG_N = NFLAG_32(res);
\r
2090 FLAG_V = VFLAG_CLEAR;
\r
2094 if(GET_MSB_32(src))
\r
2096 *r_dst = 0xffffffff;
\r
2097 FLAG_C = CFLAG_SET;
\r
2098 FLAG_X = XFLAG_SET;
\r
2099 FLAG_N = NFLAG_SET;
\r
2100 FLAG_Z = ZFLAG_CLEAR;
\r
2101 FLAG_V = VFLAG_CLEAR;
\r
2106 FLAG_C = CFLAG_CLEAR;
\r
2107 FLAG_X = XFLAG_CLEAR;
\r
2108 FLAG_N = NFLAG_CLEAR;
\r
2109 FLAG_Z = ZFLAG_SET;
\r
2110 FLAG_V = VFLAG_CLEAR;
\r
2114 FLAG_C = CFLAG_CLEAR;
\r
2115 FLAG_N = NFLAG_32(src);
\r
2117 FLAG_V = VFLAG_CLEAR;
\r
2121 M68KMAKE_OP(asr, 16, ., .)
\r
2123 uint ea = M68KMAKE_GET_EA_AY_16;
\r
2124 uint src = m68ki_read_16(ea);
\r
2125 uint res = src >> 1;
\r
2127 if(GET_MSB_16(src))
\r
2130 m68ki_write_16(ea, res);
\r
2132 FLAG_N = NFLAG_16(res);
\r
2134 FLAG_V = VFLAG_CLEAR;
\r
2135 FLAG_C = FLAG_X = src << 8;
\r
2139 M68KMAKE_OP(asl, 8, s, .)
\r
2141 uint* r_dst = &DY;
\r
2142 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
2143 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
2144 uint res = MASK_OUT_ABOVE_8(src << shift);
\r
2147 USE_CYCLES(shift<<CYC_SHIFT);
\r
2149 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
2151 FLAG_X = FLAG_C = src << shift;
\r
2152 FLAG_N = NFLAG_8(res);
\r
2154 src &= m68ki_shift_8_table[shift + 1];
\r
2155 FLAG_V = (!(src == 0 || (src == m68ki_shift_8_table[shift + 1] && shift < 8)))<<7;
\r
2159 M68KMAKE_OP(asl, 16, s, .)
\r
2161 uint* r_dst = &DY;
\r
2162 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
2163 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
2164 uint res = MASK_OUT_ABOVE_16(src << shift);
\r
2167 USE_CYCLES(shift<<CYC_SHIFT);
\r
2169 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
2171 FLAG_N = NFLAG_16(res);
\r
2173 FLAG_X = FLAG_C = src >> (8-shift);
\r
2174 src &= m68ki_shift_16_table[shift + 1];
\r
2175 FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
\r
2179 M68KMAKE_OP(asl, 32, s, .)
\r
2181 uint* r_dst = &DY;
\r
2182 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
2183 uint src = *r_dst;
\r
2184 uint res = MASK_OUT_ABOVE_32(src << shift);
\r
2187 USE_CYCLES(shift<<CYC_SHIFT);
\r
2191 FLAG_N = NFLAG_32(res);
\r
2193 FLAG_X = FLAG_C = src >> (24-shift);
\r
2194 src &= m68ki_shift_32_table[shift + 1];
\r
2195 FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
\r
2199 M68KMAKE_OP(asl, 8, r, .)
\r
2201 uint* r_dst = &DY;
\r
2202 uint shift = DX & 0x3f;
\r
2203 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
2204 uint res = MASK_OUT_ABOVE_8(src << shift);
\r
2208 USE_CYCLES(shift<<CYC_SHIFT);
\r
2212 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
2213 FLAG_X = FLAG_C = src << shift;
\r
2214 FLAG_N = NFLAG_8(res);
\r
2216 src &= m68ki_shift_8_table[shift + 1];
\r
2217 FLAG_V = (!(src == 0 || src == m68ki_shift_8_table[shift + 1]))<<7;
\r
2221 *r_dst &= 0xffffff00;
\r
2222 FLAG_X = FLAG_C = ((shift == 8 ? src & 1 : 0))<<8;
\r
2223 FLAG_N = NFLAG_CLEAR;
\r
2224 FLAG_Z = ZFLAG_SET;
\r
2225 FLAG_V = (!(src == 0))<<7;
\r
2229 FLAG_C = CFLAG_CLEAR;
\r
2230 FLAG_N = NFLAG_8(src);
\r
2232 FLAG_V = VFLAG_CLEAR;
\r
2236 M68KMAKE_OP(asl, 16, r, .)
\r
2238 uint* r_dst = &DY;
\r
2239 uint shift = DX & 0x3f;
\r
2240 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
2241 uint res = MASK_OUT_ABOVE_16(src << shift);
\r
2245 USE_CYCLES(shift<<CYC_SHIFT);
\r
2249 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
2250 FLAG_X = FLAG_C = (src << shift) >> 8;
\r
2251 FLAG_N = NFLAG_16(res);
\r
2253 src &= m68ki_shift_16_table[shift + 1];
\r
2254 FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
\r
2258 *r_dst &= 0xffff0000;
\r
2259 FLAG_X = FLAG_C = ((shift == 16 ? src & 1 : 0))<<8;
\r
2260 FLAG_N = NFLAG_CLEAR;
\r
2261 FLAG_Z = ZFLAG_SET;
\r
2262 FLAG_V = (!(src == 0))<<7;
\r
2266 FLAG_C = CFLAG_CLEAR;
\r
2267 FLAG_N = NFLAG_16(src);
\r
2269 FLAG_V = VFLAG_CLEAR;
\r
2273 M68KMAKE_OP(asl, 32, r, .)
\r
2275 uint* r_dst = &DY;
\r
2276 uint shift = DX & 0x3f;
\r
2277 uint src = *r_dst;
\r
2278 uint res = MASK_OUT_ABOVE_32(src << shift);
\r
2282 USE_CYCLES(shift<<CYC_SHIFT);
\r
2287 FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;
\r
2288 FLAG_N = NFLAG_32(res);
\r
2290 src &= m68ki_shift_32_table[shift + 1];
\r
2291 FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
\r
2296 FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;
\r
2297 FLAG_N = NFLAG_CLEAR;
\r
2298 FLAG_Z = ZFLAG_SET;
\r
2299 FLAG_V = (!(src == 0))<<7;
\r
2303 FLAG_C = CFLAG_CLEAR;
\r
2304 FLAG_N = NFLAG_32(src);
\r
2306 FLAG_V = VFLAG_CLEAR;
\r
2310 M68KMAKE_OP(asl, 16, ., .)
\r
2312 uint ea = M68KMAKE_GET_EA_AY_16;
\r
2313 uint src = m68ki_read_16(ea);
\r
2314 uint res = MASK_OUT_ABOVE_16(src << 1);
\r
2316 m68ki_write_16(ea, res);
\r
2318 FLAG_N = NFLAG_16(res);
\r
2320 FLAG_X = FLAG_C = src >> 7;
\r
2322 FLAG_V = (!(src == 0 || src == 0xc000))<<7;
\r
2326 M68KMAKE_OP(bcc, 8, ., .)
\r
2330 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
2331 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
\r
2334 USE_CYCLES(CYC_BCC_NOTAKE_B);
\r
2338 M68KMAKE_OP(bcc, 16, ., .)
\r
2342 uint offset = OPER_I_16();
\r
2344 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
2345 m68ki_branch_16(offset);
\r
2349 USE_CYCLES(CYC_BCC_NOTAKE_W);
\r
2353 M68KMAKE_OP(bcc, 32, ., .)
\r
2355 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2359 uint offset = OPER_I_32();
\r
2361 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
2362 m68ki_branch_32(offset);
\r
2372 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
2373 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
\r
2376 USE_CYCLES(CYC_BCC_NOTAKE_B);
\r
2381 M68KMAKE_OP(bchg, 32, r, d)
\r
2383 uint* r_dst = &DY;
\r
2384 uint mask = 1 << (DX & 0x1f);
\r
2386 if(CPU_TYPE_IS_010_LESS(CPU_TYPE) && mask >= 0x10000)
\r
2388 FLAG_Z = *r_dst & mask;
\r
2393 M68KMAKE_OP(bchg, 8, r, .)
\r
2395 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2396 uint src = m68ki_read_8(ea);
\r
2397 uint mask = 1 << (DX & 7);
\r
2399 FLAG_Z = src & mask;
\r
2400 m68ki_write_8(ea, src ^ mask);
\r
2404 M68KMAKE_OP(bchg, 32, s, d)
\r
2406 uint* r_dst = &DY;
\r
2407 uint mask = 1 << (OPER_I_8() & 0x1f);
\r
2409 if(CPU_TYPE_IS_010_LESS(CPU_TYPE) && mask >= 0x10000)
\r
2411 FLAG_Z = *r_dst & mask;
\r
2416 M68KMAKE_OP(bchg, 8, s, .)
\r
2418 uint mask = 1 << (OPER_I_8() & 7);
\r
2419 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2420 uint src = m68ki_read_8(ea);
\r
2422 FLAG_Z = src & mask;
\r
2423 m68ki_write_8(ea, src ^ mask);
\r
2427 M68KMAKE_OP(bclr, 32, r, d)
\r
2429 uint* r_dst = &DY;
\r
2430 uint mask = 1 << (DX & 0x1f);
\r
2432 if(CPU_TYPE_IS_010_LESS(CPU_TYPE) && mask >= 0x10000)
\r
2434 FLAG_Z = *r_dst & mask;
\r
2439 M68KMAKE_OP(bclr, 8, r, .)
\r
2441 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2442 uint src = m68ki_read_8(ea);
\r
2443 uint mask = 1 << (DX & 7);
\r
2445 FLAG_Z = src & mask;
\r
2446 m68ki_write_8(ea, src & ~mask);
\r
2450 M68KMAKE_OP(bclr, 32, s, d)
\r
2452 uint* r_dst = &DY;
\r
2453 uint mask = 1 << (OPER_I_8() & 0x1f);
\r
2455 if(CPU_TYPE_IS_010_LESS(CPU_TYPE) && mask >= 0x10000)
\r
2457 FLAG_Z = *r_dst & mask;
\r
2462 M68KMAKE_OP(bclr, 8, s, .)
\r
2464 uint mask = 1 << (OPER_I_8() & 7);
\r
2465 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2466 uint src = m68ki_read_8(ea);
\r
2468 FLAG_Z = src & mask;
\r
2469 m68ki_write_8(ea, src & ~mask);
\r
2473 M68KMAKE_OP(bfchg, 32, ., d)
\r
2475 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2477 uint word2 = OPER_I_16();
\r
2478 uint offset = (word2>>6)&31;
\r
2479 uint width = word2;
\r
2485 offset = REG_D[offset&7];
\r
2487 width = REG_D[width&7];
\r
2490 width = ((width-1) & 31) + 1;
\r
2492 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2493 mask = ROR_32(mask, offset);
\r
2495 FLAG_N = NFLAG_32(*data<<offset);
\r
2496 FLAG_Z = *data & mask;
\r
2497 FLAG_V = VFLAG_CLEAR;
\r
2498 FLAG_C = CFLAG_CLEAR;
\r
2504 m68ki_exception_illegal();
\r
2508 M68KMAKE_OP(bfchg, 32, ., .)
\r
2510 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2512 uint word2 = OPER_I_16();
\r
2513 sint offset = (word2>>6)&31;
\r
2514 uint width = word2;
\r
2518 uint data_byte = 0;
\r
2519 uint mask_byte = 0;
\r
2520 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2524 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2526 width = REG_D[width&7];
\r
2528 /* Offset is signed so we have to use ugly math =( */
\r
2536 width = ((width-1) & 31) + 1;
\r
2538 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2539 mask_long = mask_base >> offset;
\r
2541 data_long = m68ki_read_32(ea);
\r
2542 FLAG_N = NFLAG_32(data_long << offset);
\r
2543 FLAG_Z = data_long & mask_long;
\r
2544 FLAG_V = VFLAG_CLEAR;
\r
2545 FLAG_C = CFLAG_CLEAR;
\r
2547 m68ki_write_32(ea, data_long ^ mask_long);
\r
2549 if((width + offset) > 32)
\r
2551 mask_byte = MASK_OUT_ABOVE_8(mask_base);
\r
2552 data_byte = m68ki_read_8(ea+4);
\r
2553 FLAG_Z |= (data_byte & mask_byte);
\r
2554 m68ki_write_8(ea+4, data_byte ^ mask_byte);
\r
2558 m68ki_exception_illegal();
\r
2562 M68KMAKE_OP(bfclr, 32, ., d)
\r
2564 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2566 uint word2 = OPER_I_16();
\r
2567 uint offset = (word2>>6)&31;
\r
2568 uint width = word2;
\r
2574 offset = REG_D[offset&7];
\r
2576 width = REG_D[width&7];
\r
2580 width = ((width-1) & 31) + 1;
\r
2583 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2584 mask = ROR_32(mask, offset);
\r
2586 FLAG_N = NFLAG_32(*data<<offset);
\r
2587 FLAG_Z = *data & mask;
\r
2588 FLAG_V = VFLAG_CLEAR;
\r
2589 FLAG_C = CFLAG_CLEAR;
\r
2595 m68ki_exception_illegal();
\r
2599 M68KMAKE_OP(bfclr, 32, ., .)
\r
2601 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2603 uint word2 = OPER_I_16();
\r
2604 sint offset = (word2>>6)&31;
\r
2605 uint width = word2;
\r
2609 uint data_byte = 0;
\r
2610 uint mask_byte = 0;
\r
2611 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2615 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2617 width = REG_D[width&7];
\r
2619 /* Offset is signed so we have to use ugly math =( */
\r
2627 width = ((width-1) & 31) + 1;
\r
2629 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2630 mask_long = mask_base >> offset;
\r
2632 data_long = m68ki_read_32(ea);
\r
2633 FLAG_N = NFLAG_32(data_long << offset);
\r
2634 FLAG_Z = data_long & mask_long;
\r
2635 FLAG_V = VFLAG_CLEAR;
\r
2636 FLAG_C = CFLAG_CLEAR;
\r
2638 m68ki_write_32(ea, data_long & ~mask_long);
\r
2640 if((width + offset) > 32)
\r
2642 mask_byte = MASK_OUT_ABOVE_8(mask_base);
\r
2643 data_byte = m68ki_read_8(ea+4);
\r
2644 FLAG_Z |= (data_byte & mask_byte);
\r
2645 m68ki_write_8(ea+4, data_byte & ~mask_byte);
\r
2649 m68ki_exception_illegal();
\r
2653 M68KMAKE_OP(bfexts, 32, ., d)
\r
2655 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2657 uint word2 = OPER_I_16();
\r
2658 uint offset = (word2>>6)&31;
\r
2659 uint width = word2;
\r
2664 offset = REG_D[offset&7];
\r
2666 width = REG_D[width&7];
\r
2669 width = ((width-1) & 31) + 1;
\r
2671 data = ROL_32(data, offset);
\r
2672 FLAG_N = NFLAG_32(data);
\r
2673 data = MAKE_INT_32(data) >> (32 - width);
\r
2676 FLAG_V = VFLAG_CLEAR;
\r
2677 FLAG_C = CFLAG_CLEAR;
\r
2679 REG_D[(word2>>12)&7] = data;
\r
2683 m68ki_exception_illegal();
\r
2687 M68KMAKE_OP(bfexts, 32, ., .)
\r
2689 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2691 uint word2 = OPER_I_16();
\r
2692 sint offset = (word2>>6)&31;
\r
2693 uint width = word2;
\r
2695 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2699 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2701 width = REG_D[width&7];
\r
2703 /* Offset is signed so we have to use ugly math =( */
\r
2711 width = ((width-1) & 31) + 1;
\r
2713 data = m68ki_read_32(ea);
\r
2715 data = MASK_OUT_ABOVE_32(data<<offset);
\r
2717 if((offset+width) > 32)
\r
2718 data |= (m68ki_read_8(ea+4) << offset) >> 8;
\r
2720 FLAG_N = NFLAG_32(data);
\r
2721 data = MAKE_INT_32(data) >> (32 - width);
\r
2724 FLAG_V = VFLAG_CLEAR;
\r
2725 FLAG_C = CFLAG_CLEAR;
\r
2727 REG_D[(word2 >> 12) & 7] = data;
\r
2731 m68ki_exception_illegal();
\r
2735 M68KMAKE_OP(bfextu, 32, ., d)
\r
2737 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2739 uint word2 = OPER_I_16();
\r
2740 uint offset = (word2>>6)&31;
\r
2741 uint width = word2;
\r
2746 offset = REG_D[offset&7];
\r
2748 width = REG_D[width&7];
\r
2751 width = ((width-1) & 31) + 1;
\r
2753 data = ROL_32(data, offset);
\r
2754 FLAG_N = NFLAG_32(data);
\r
2755 data >>= 32 - width;
\r
2758 FLAG_V = VFLAG_CLEAR;
\r
2759 FLAG_C = CFLAG_CLEAR;
\r
2761 REG_D[(word2>>12)&7] = data;
\r
2765 m68ki_exception_illegal();
\r
2769 M68KMAKE_OP(bfextu, 32, ., .)
\r
2771 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2773 uint word2 = OPER_I_16();
\r
2774 sint offset = (word2>>6)&31;
\r
2775 uint width = word2;
\r
2777 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2781 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2783 width = REG_D[width&7];
\r
2785 /* Offset is signed so we have to use ugly math =( */
\r
2793 width = ((width-1) & 31) + 1;
\r
2795 data = m68ki_read_32(ea);
\r
2796 data = MASK_OUT_ABOVE_32(data<<offset);
\r
2798 if((offset+width) > 32)
\r
2799 data |= (m68ki_read_8(ea+4) << offset) >> 8;
\r
2801 FLAG_N = NFLAG_32(data);
\r
2802 data >>= (32 - width);
\r
2805 FLAG_V = VFLAG_CLEAR;
\r
2806 FLAG_C = CFLAG_CLEAR;
\r
2808 REG_D[(word2 >> 12) & 7] = data;
\r
2812 m68ki_exception_illegal();
\r
2816 M68KMAKE_OP(bfffo, 32, ., d)
\r
2818 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2820 uint word2 = OPER_I_16();
\r
2821 uint offset = (word2>>6)&31;
\r
2822 uint width = word2;
\r
2828 offset = REG_D[offset&7];
\r
2830 width = REG_D[width&7];
\r
2833 width = ((width-1) & 31) + 1;
\r
2835 data = ROL_32(data, offset);
\r
2836 FLAG_N = NFLAG_32(data);
\r
2837 data >>= 32 - width;
\r
2840 FLAG_V = VFLAG_CLEAR;
\r
2841 FLAG_C = CFLAG_CLEAR;
\r
2843 for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
\r
2846 REG_D[(word2>>12)&7] = offset;
\r
2850 m68ki_exception_illegal();
\r
2854 M68KMAKE_OP(bfffo, 32, ., .)
\r
2856 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2858 uint word2 = OPER_I_16();
\r
2859 sint offset = (word2>>6)&31;
\r
2860 sint local_offset;
\r
2861 uint width = word2;
\r
2864 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2868 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2870 width = REG_D[width&7];
\r
2872 /* Offset is signed so we have to use ugly math =( */
\r
2874 local_offset = offset % 8;
\r
2875 if(local_offset < 0)
\r
2877 local_offset += 8;
\r
2880 width = ((width-1) & 31) + 1;
\r
2882 data = m68ki_read_32(ea);
\r
2883 data = MASK_OUT_ABOVE_32(data<<local_offset);
\r
2885 if((local_offset+width) > 32)
\r
2886 data |= (m68ki_read_8(ea+4) << local_offset) >> 8;
\r
2888 FLAG_N = NFLAG_32(data);
\r
2889 data >>= (32 - width);
\r
2892 FLAG_V = VFLAG_CLEAR;
\r
2893 FLAG_C = CFLAG_CLEAR;
\r
2895 for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
\r
2898 REG_D[(word2>>12)&7] = offset;
\r
2902 m68ki_exception_illegal();
\r
2906 M68KMAKE_OP(bfins, 32, ., d)
\r
2908 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2910 uint word2 = OPER_I_16();
\r
2911 uint offset = (word2>>6)&31;
\r
2912 uint width = word2;
\r
2915 uint64 insert = REG_D[(word2>>12)&7];
\r
2919 offset = REG_D[offset&7];
\r
2921 width = REG_D[width&7];
\r
2925 width = ((width-1) & 31) + 1;
\r
2928 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2929 mask = ROR_32(mask, offset);
\r
2931 insert = MASK_OUT_ABOVE_32(insert << (32 - width));
\r
2932 FLAG_N = NFLAG_32(insert);
\r
2934 insert = ROR_32(insert, offset);
\r
2936 FLAG_V = VFLAG_CLEAR;
\r
2937 FLAG_C = CFLAG_CLEAR;
\r
2944 m68ki_exception_illegal();
\r
2948 M68KMAKE_OP(bfins, 32, ., .)
\r
2950 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2952 uint word2 = OPER_I_16();
\r
2953 sint offset = (word2>>6)&31;
\r
2954 uint width = word2;
\r
2955 uint insert_base = REG_D[(word2>>12)&7];
\r
2961 uint data_byte = 0;
\r
2962 uint mask_byte = 0;
\r
2963 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2967 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2969 width = REG_D[width&7];
\r
2971 /* Offset is signed so we have to use ugly math =( */
\r
2979 width = ((width-1) & 31) + 1;
\r
2981 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2982 mask_long = mask_base >> offset;
\r
2984 insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width));
\r
2985 FLAG_N = NFLAG_32(insert_base);
\r
2986 FLAG_Z = insert_base;
\r
2987 insert_long = insert_base >> offset;
\r
2989 data_long = m68ki_read_32(ea);
\r
2990 FLAG_V = VFLAG_CLEAR;
\r
2991 FLAG_C = CFLAG_CLEAR;
\r
2993 m68ki_write_32(ea, (data_long & ~mask_long) | insert_long);
\r
2995 if((width + offset) > 32)
\r
2997 mask_byte = MASK_OUT_ABOVE_8(mask_base);
\r
2998 insert_byte = MASK_OUT_ABOVE_8(insert_base);
\r
2999 data_byte = m68ki_read_8(ea+4);
\r
3000 FLAG_Z |= (data_byte & mask_byte);
\r
3001 m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte);
\r
3005 m68ki_exception_illegal();
\r
3009 M68KMAKE_OP(bfset, 32, ., d)
\r
3011 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3013 uint word2 = OPER_I_16();
\r
3014 uint offset = (word2>>6)&31;
\r
3015 uint width = word2;
\r
3021 offset = REG_D[offset&7];
\r
3023 width = REG_D[width&7];
\r
3027 width = ((width-1) & 31) + 1;
\r
3030 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
3031 mask = ROR_32(mask, offset);
\r
3033 FLAG_N = NFLAG_32(*data<<offset);
\r
3034 FLAG_Z = *data & mask;
\r
3035 FLAG_V = VFLAG_CLEAR;
\r
3036 FLAG_C = CFLAG_CLEAR;
\r
3042 m68ki_exception_illegal();
\r
3046 M68KMAKE_OP(bfset, 32, ., .)
\r
3048 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3050 uint word2 = OPER_I_16();
\r
3051 sint offset = (word2>>6)&31;
\r
3052 uint width = word2;
\r
3056 uint data_byte = 0;
\r
3057 uint mask_byte = 0;
\r
3058 uint ea = M68KMAKE_GET_EA_AY_8;
\r
3062 offset = MAKE_INT_32(REG_D[offset&7]);
\r
3064 width = REG_D[width&7];
\r
3066 /* Offset is signed so we have to use ugly math =( */
\r
3074 width = ((width-1) & 31) + 1;
\r
3077 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
3078 mask_long = mask_base >> offset;
\r
3080 data_long = m68ki_read_32(ea);
\r
3081 FLAG_N = NFLAG_32(data_long << offset);
\r
3082 FLAG_Z = data_long & mask_long;
\r
3083 FLAG_V = VFLAG_CLEAR;
\r
3084 FLAG_C = CFLAG_CLEAR;
\r
3086 m68ki_write_32(ea, data_long | mask_long);
\r
3088 if((width + offset) > 32)
\r
3090 mask_byte = MASK_OUT_ABOVE_8(mask_base);
\r
3091 data_byte = m68ki_read_8(ea+4);
\r
3092 FLAG_Z |= (data_byte & mask_byte);
\r
3093 m68ki_write_8(ea+4, data_byte | mask_byte);
\r
3097 m68ki_exception_illegal();
\r
3101 M68KMAKE_OP(bftst, 32, ., d)
\r
3103 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3105 uint word2 = OPER_I_16();
\r
3106 uint offset = (word2>>6)&31;
\r
3107 uint width = word2;
\r
3113 offset = REG_D[offset&7];
\r
3115 width = REG_D[width&7];
\r
3119 width = ((width-1) & 31) + 1;
\r
3122 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
3123 mask = ROR_32(mask, offset);
\r
3125 FLAG_N = NFLAG_32(*data<<offset);
\r
3126 FLAG_Z = *data & mask;
\r
3127 FLAG_V = VFLAG_CLEAR;
\r
3128 FLAG_C = CFLAG_CLEAR;
\r
3132 m68ki_exception_illegal();
\r
3136 M68KMAKE_OP(bftst, 32, ., .)
\r
3138 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3140 uint word2 = OPER_I_16();
\r
3141 sint offset = (word2>>6)&31;
\r
3142 uint width = word2;
\r
3146 uint data_byte = 0;
\r
3147 uint mask_byte = 0;
\r
3148 uint ea = M68KMAKE_GET_EA_AY_8;
\r
3151 offset = MAKE_INT_32(REG_D[offset&7]);
\r
3153 width = REG_D[width&7];
\r
3155 /* Offset is signed so we have to use ugly math =( */
\r
3163 width = ((width-1) & 31) + 1;
\r
3166 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
3167 mask_long = mask_base >> offset;
\r
3169 data_long = m68ki_read_32(ea);
\r
3170 FLAG_N = ((data_long & (0x80000000 >> offset))<<offset)>>24;
\r
3171 FLAG_Z = data_long & mask_long;
\r
3172 FLAG_V = VFLAG_CLEAR;
\r
3173 FLAG_C = CFLAG_CLEAR;
\r
3175 if((width + offset) > 32)
\r
3177 mask_byte = MASK_OUT_ABOVE_8(mask_base);
\r
3178 data_byte = m68ki_read_8(ea+4);
\r
3179 FLAG_Z |= (data_byte & mask_byte);
\r
3183 m68ki_exception_illegal();
\r
3187 M68KMAKE_OP(bkpt, 0, ., .)
\r
3189 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
3191 m68ki_bkpt_ack(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE) ? REG_IR & 7 : 0); /* auto-disable (see m68kcpu.h) */
\r
3193 m68ki_exception_illegal();
\r
3197 M68KMAKE_OP(bra, 8, ., .)
\r
3199 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3200 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
\r
3201 if(REG_PC == REG_PPC)
\r
3206 M68KMAKE_OP(bra, 16, ., .)
\r
3208 uint offset = OPER_I_16();
\r
3210 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3211 m68ki_branch_16(offset);
\r
3212 if(REG_PC == REG_PPC)
\r
3217 M68KMAKE_OP(bra, 32, ., .)
\r
3219 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3221 uint offset = OPER_I_32();
\r
3223 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3224 m68ki_branch_32(offset);
\r
3225 if(REG_PC == REG_PPC)
\r
3231 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3232 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
\r
3233 if(REG_PC == REG_PPC)
\r
3239 M68KMAKE_OP(bset, 32, r, d)
\r
3241 uint* r_dst = &DY;
\r
3242 uint mask = 1 << (DX & 0x1f);
\r
3244 if(CPU_TYPE_IS_010_LESS(CPU_TYPE) && mask >= 0x10000)
\r
3246 FLAG_Z = *r_dst & mask;
\r
3251 M68KMAKE_OP(bset, 8, r, .)
\r
3253 uint ea = M68KMAKE_GET_EA_AY_8;
\r
3254 uint src = m68ki_read_8(ea);
\r
3255 uint mask = 1 << (DX & 7);
\r
3257 FLAG_Z = src & mask;
\r
3258 m68ki_write_8(ea, src | mask);
\r
3262 M68KMAKE_OP(bset, 32, s, d)
\r
3264 uint* r_dst = &DY;
\r
3265 uint mask = 1 << (OPER_I_8() & 0x1f);
\r
3267 if(CPU_TYPE_IS_010_LESS(CPU_TYPE) && mask >= 0x10000)
\r
3269 FLAG_Z = *r_dst & mask;
\r
3274 M68KMAKE_OP(bset, 8, s, .)
\r
3276 uint mask = 1 << (OPER_I_8() & 7);
\r
3277 uint ea = M68KMAKE_GET_EA_AY_8;
\r
3278 uint src = m68ki_read_8(ea);
\r
3280 FLAG_Z = src & mask;
\r
3281 m68ki_write_8(ea, src | mask);
\r
3285 M68KMAKE_OP(bsr, 8, ., .)
\r
3287 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3288 m68ki_push_32(REG_PC);
\r
3289 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
\r
3293 M68KMAKE_OP(bsr, 16, ., .)
\r
3295 uint offset = OPER_I_16();
\r
3296 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3297 m68ki_push_32(REG_PC);
\r
3299 m68ki_branch_16(offset);
\r
3303 M68KMAKE_OP(bsr, 32, ., .)
\r
3305 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3307 uint offset = OPER_I_32();
\r
3308 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3309 m68ki_push_32(REG_PC);
\r
3311 m68ki_branch_32(offset);
\r
3316 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3317 m68ki_push_32(REG_PC);
\r
3318 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
\r
3323 M68KMAKE_OP(btst, 32, r, d)
\r
3325 FLAG_Z = DY & (1 << (DX & 0x1f));
\r
3329 M68KMAKE_OP(btst, 8, r, .)
\r
3331 FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << (DX & 7));
\r
3335 M68KMAKE_OP(btst, 32, s, d)
\r
3337 FLAG_Z = DY & (1 << (OPER_I_8() & 0x1f));
\r
3341 M68KMAKE_OP(btst, 8, s, .)
\r
3343 uint bit = OPER_I_8() & 7;
\r
3345 FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << bit);
\r
3349 M68KMAKE_OP(callm, 32, ., .)
\r
3351 /* note: watch out for pcrelative modes */
\r
3352 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
3354 uint ea = M68KMAKE_GET_EA_AY_32;
\r
3356 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3358 (void)ea; /* just to avoid an 'unused variable' warning */
\r
3359 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
3360 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
3361 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
3364 m68ki_exception_illegal();
\r
3368 M68KMAKE_OP(cas, 8, ., .)
\r
3370 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3372 uint word2 = OPER_I_16();
\r
3373 uint ea = M68KMAKE_GET_EA_AY_8;
\r
3374 uint dest = m68ki_read_8(ea);
\r
3375 uint* compare = ®_D[word2 & 7];
\r
3376 uint res = dest - MASK_OUT_ABOVE_8(*compare);
\r
3378 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3379 FLAG_N = NFLAG_8(res);
\r
3380 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
3381 FLAG_V = VFLAG_SUB_8(*compare, dest, res);
\r
3382 FLAG_C = CFLAG_8(res);
\r
3385 *compare = MASK_OUT_BELOW_8(*compare) | dest;
\r
3389 m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));
\r
3393 m68ki_exception_illegal();
\r
3397 M68KMAKE_OP(cas, 16, ., .)
\r
3399 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3401 uint word2 = OPER_I_16();
\r
3402 uint ea = M68KMAKE_GET_EA_AY_16;
\r
3403 uint dest = m68ki_read_16(ea);
\r
3404 uint* compare = ®_D[word2 & 7];
\r
3405 uint res = dest - MASK_OUT_ABOVE_16(*compare);
\r
3407 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3408 FLAG_N = NFLAG_16(res);
\r
3409 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
3410 FLAG_V = VFLAG_SUB_16(*compare, dest, res);
\r
3411 FLAG_C = CFLAG_16(res);
\r
3414 *compare = MASK_OUT_BELOW_16(*compare) | dest;
\r
3418 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7]));
\r
3422 m68ki_exception_illegal();
\r
3426 M68KMAKE_OP(cas, 32, ., .)
\r
3428 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3430 uint word2 = OPER_I_16();
\r
3431 uint ea = M68KMAKE_GET_EA_AY_32;
\r
3432 uint dest = m68ki_read_32(ea);
\r
3433 uint* compare = ®_D[word2 & 7];
\r
3434 uint res = dest - *compare;
\r
3436 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3437 FLAG_N = NFLAG_32(res);
\r
3438 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
3439 FLAG_V = VFLAG_SUB_32(*compare, dest, res);
\r
3440 FLAG_C = CFLAG_SUB_32(*compare, dest, res);
\r
3447 m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]);
\r
3451 m68ki_exception_illegal();
\r
3455 M68KMAKE_OP(cas2, 16, ., .)
\r
3457 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3459 uint word2 = OPER_I_32();
\r
3460 uint* compare1 = ®_D[(word2 >> 16) & 7];
\r
3461 uint ea1 = REG_DA[(word2 >> 28) & 15];
\r
3462 uint dest1 = m68ki_read_16(ea1);
\r
3463 uint res1 = dest1 - MASK_OUT_ABOVE_16(*compare1);
\r
3464 uint* compare2 = ®_D[word2 & 7];
\r
3465 uint ea2 = REG_DA[(word2 >> 12) & 15];
\r
3466 uint dest2 = m68ki_read_16(ea2);
\r
3469 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3470 FLAG_N = NFLAG_16(res1);
\r
3471 FLAG_Z = MASK_OUT_ABOVE_16(res1);
\r
3472 FLAG_V = VFLAG_SUB_16(*compare1, dest1, res1);
\r
3473 FLAG_C = CFLAG_16(res1);
\r
3477 res2 = dest2 - MASK_OUT_ABOVE_16(*compare2);
\r
3479 FLAG_N = NFLAG_16(res2);
\r
3480 FLAG_Z = MASK_OUT_ABOVE_16(res2);
\r
3481 FLAG_V = VFLAG_SUB_16(*compare2, dest2, res2);
\r
3482 FLAG_C = CFLAG_16(res2);
\r
3487 m68ki_write_16(ea1, REG_D[(word2 >> 22) & 7]);
\r
3488 m68ki_write_16(ea2, REG_D[(word2 >> 6) & 7]);
\r
3492 *compare1 = BIT_1F(word2) ? MAKE_INT_16(dest1) : MASK_OUT_BELOW_16(*compare1) | dest1;
\r
3493 *compare2 = BIT_F(word2) ? MAKE_INT_16(dest2) : MASK_OUT_BELOW_16(*compare2) | dest2;
\r
3496 m68ki_exception_illegal();
\r
3500 M68KMAKE_OP(cas2, 32, ., .)
\r
3502 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3504 uint word2 = OPER_I_32();
\r
3505 uint* compare1 = ®_D[(word2 >> 16) & 7];
\r
3506 uint ea1 = REG_DA[(word2 >> 28) & 15];
\r
3507 uint dest1 = m68ki_read_32(ea1);
\r
3508 uint res1 = dest1 - *compare1;
\r
3509 uint* compare2 = ®_D[word2 & 7];
\r
3510 uint ea2 = REG_DA[(word2 >> 12) & 15];
\r
3511 uint dest2 = m68ki_read_32(ea2);
\r
3514 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3515 FLAG_N = NFLAG_32(res1);
\r
3516 FLAG_Z = MASK_OUT_ABOVE_32(res1);
\r
3517 FLAG_V = VFLAG_SUB_32(*compare1, dest1, res1);
\r
3518 FLAG_C = CFLAG_SUB_32(*compare1, dest1, res1);
\r
3522 res2 = dest2 - *compare2;
\r
3524 FLAG_N = NFLAG_32(res2);
\r
3525 FLAG_Z = MASK_OUT_ABOVE_32(res2);
\r
3526 FLAG_V = VFLAG_SUB_32(*compare2, dest2, res2);
\r
3527 FLAG_C = CFLAG_SUB_32(*compare2, dest2, res2);
\r
3532 m68ki_write_32(ea1, REG_D[(word2 >> 22) & 7]);
\r
3533 m68ki_write_32(ea2, REG_D[(word2 >> 6) & 7]);
\r
3537 *compare1 = dest1;
\r
3538 *compare2 = dest2;
\r
3541 m68ki_exception_illegal();
\r
3545 M68KMAKE_OP(chk, 16, ., d)
\r
3547 sint src = MAKE_INT_16(DX);
\r
3548 sint bound = MAKE_INT_16(DY);
\r
3550 FLAG_Z = ZFLAG_16(src); /* Undocumented */
\r
3551 FLAG_V = VFLAG_CLEAR; /* Undocumented */
\r
3552 FLAG_C = CFLAG_CLEAR; /* Undocumented */
\r
3554 if(src >= 0 && src <= bound)
\r
3559 FLAG_N = (src < 0)<<7;
\r
3560 m68ki_exception_trap(EXCEPTION_CHK);
\r
3564 M68KMAKE_OP(chk, 16, ., .)
\r
3566 sint src = MAKE_INT_16(DX);
\r
3567 sint bound = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
\r
3569 FLAG_Z = ZFLAG_16(src); /* Undocumented */
\r
3570 FLAG_V = VFLAG_CLEAR; /* Undocumented */
\r
3571 FLAG_C = CFLAG_CLEAR; /* Undocumented */
\r
3573 if(src >= 0 && src <= bound)
\r
3578 FLAG_N = (src < 0)<<7;
\r
3579 m68ki_exception_trap(EXCEPTION_CHK);
\r
3583 M68KMAKE_OP(chk, 32, ., d)
\r
3585 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3587 sint src = MAKE_INT_32(DX);
\r
3588 sint bound = MAKE_INT_32(DY);
\r
3590 FLAG_Z = ZFLAG_32(src); /* Undocumented */
\r
3591 FLAG_V = VFLAG_CLEAR; /* Undocumented */
\r
3592 FLAG_C = CFLAG_CLEAR; /* Undocumented */
\r
3594 if(src >= 0 && src <= bound)
\r
3598 FLAG_N = (src < 0)<<7;
\r
3599 m68ki_exception_trap(EXCEPTION_CHK);
\r
3602 m68ki_exception_illegal();
\r
3606 M68KMAKE_OP(chk, 32, ., .)
\r
3608 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3610 sint src = MAKE_INT_32(DX);
\r
3611 sint bound = MAKE_INT_32(M68KMAKE_GET_OPER_AY_32);
\r
3613 FLAG_Z = ZFLAG_32(src); /* Undocumented */
\r
3614 FLAG_V = VFLAG_CLEAR; /* Undocumented */
\r
3615 FLAG_C = CFLAG_CLEAR; /* Undocumented */
\r
3617 if(src >= 0 && src <= bound)
\r
3621 FLAG_N = (src < 0)<<7;
\r
3622 m68ki_exception_trap(EXCEPTION_CHK);
\r
3625 m68ki_exception_illegal();
\r
3629 M68KMAKE_OP(chk2cmp2, 8, ., pcdi)
\r
3631 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3633 uint word2 = OPER_I_16();
\r
3634 uint compare = REG_DA[(word2 >> 12) & 15]&0xff;
\r
3635 uint ea = EA_PCDI_8();
\r
3636 uint lower_bound = m68ki_read_pcrel_8(ea);
\r
3637 uint upper_bound = m68ki_read_pcrel_8(ea + 1);
\r
3640 FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);
\r
3642 FLAG_C = compare - lower_bound;
\r
3643 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3647 m68ki_exception_trap(EXCEPTION_CHK);
\r
3651 FLAG_C = upper_bound - compare;
\r
3652 if(COND_CS() && BIT_B(word2))
\r
3653 m68ki_exception_trap(EXCEPTION_CHK);
\r
3656 m68ki_exception_illegal();
\r
3660 M68KMAKE_OP(chk2cmp2, 8, ., pcix)
\r
3662 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3664 uint word2 = OPER_I_16();
\r
3665 uint compare = REG_DA[(word2 >> 12) & 15]&0xff;
\r
3666 uint ea = EA_PCIX_8();
\r
3667 uint lower_bound = m68ki_read_pcrel_8(ea);
\r
3668 uint upper_bound = m68ki_read_pcrel_8(ea + 1);
\r
3671 FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);
\r
3673 FLAG_C = compare - lower_bound;
\r
3674 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3678 m68ki_exception_trap(EXCEPTION_CHK);
\r
3682 FLAG_C = upper_bound - compare;
\r
3683 if(COND_CS() && BIT_B(word2))
\r
3684 m68ki_exception_trap(EXCEPTION_CHK);
\r
3687 m68ki_exception_illegal();
\r
3691 M68KMAKE_OP(chk2cmp2, 8, ., .)
\r
3693 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3695 uint word2 = OPER_I_16();
\r
3696 uint compare = REG_DA[(word2 >> 12) & 15]&0xff;
\r
3697 uint ea = M68KMAKE_GET_EA_AY_8;
\r
3698 uint lower_bound = m68ki_read_8(ea);
\r
3699 uint upper_bound = m68ki_read_8(ea + 1);
\r
3702 FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);
\r
3704 FLAG_C = compare - lower_bound;
\r
3705 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3709 m68ki_exception_trap(EXCEPTION_CHK);
\r
3713 FLAG_C = upper_bound - compare;
\r
3714 if(COND_CS() && BIT_B(word2))
\r
3715 m68ki_exception_trap(EXCEPTION_CHK);
\r
3718 m68ki_exception_illegal();
\r
3722 M68KMAKE_OP(chk2cmp2, 16, ., pcdi)
\r
3724 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3726 uint word2 = OPER_I_16();
\r
3727 uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;
\r
3728 uint ea = EA_PCDI_16();
\r
3729 uint lower_bound = m68ki_read_pcrel_16(ea);
\r
3730 uint upper_bound = m68ki_read_pcrel_16(ea + 2);
\r
3733 FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);
\r
3735 FLAG_C = compare - lower_bound;
\r
3736 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3737 FLAG_C = CFLAG_16(FLAG_C);
\r
3741 m68ki_exception_trap(EXCEPTION_CHK);
\r
3746 FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);
\r
3748 FLAG_C = upper_bound - compare;
\r
3749 FLAG_C = CFLAG_16(FLAG_C);
\r
3750 if(COND_CS() && BIT_B(word2))
\r
3751 m68ki_exception_trap(EXCEPTION_CHK);
\r
3754 m68ki_exception_illegal();
\r
3758 M68KMAKE_OP(chk2cmp2, 16, ., pcix)
\r
3760 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3762 uint word2 = OPER_I_16();
\r
3763 uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;
\r
3764 uint ea = EA_PCIX_16();
\r
3765 uint lower_bound = m68ki_read_pcrel_16(ea);
\r
3766 uint upper_bound = m68ki_read_pcrel_16(ea + 2);
\r
3769 FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);
\r
3771 FLAG_C = compare - lower_bound;
\r
3772 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3773 FLAG_C = CFLAG_16(FLAG_C);
\r
3777 m68ki_exception_trap(EXCEPTION_CHK);
\r
3782 FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);
\r
3784 FLAG_C = upper_bound - compare;
\r
3785 FLAG_C = CFLAG_16(FLAG_C);
\r
3786 if(COND_CS() && BIT_B(word2))
\r
3787 m68ki_exception_trap(EXCEPTION_CHK);
\r
3790 m68ki_exception_illegal();
\r
3794 M68KMAKE_OP(chk2cmp2, 16, ., .)
\r
3796 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3798 uint word2 = OPER_I_16();
\r
3799 uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;
\r
3800 uint ea = M68KMAKE_GET_EA_AY_16;
\r
3801 uint lower_bound = m68ki_read_16(ea);
\r
3802 uint upper_bound = m68ki_read_16(ea + 2);
\r
3805 FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);
\r
3807 FLAG_C = compare - lower_bound;
\r
3809 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3810 FLAG_C = CFLAG_16(FLAG_C);
\r
3814 m68ki_exception_trap(EXCEPTION_CHK);
\r
3818 FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);
\r
3820 FLAG_C = upper_bound - compare;
\r
3822 FLAG_C = CFLAG_16(FLAG_C);
\r
3823 if(COND_CS() && BIT_B(word2))
\r
3824 m68ki_exception_trap(EXCEPTION_CHK);
\r
3827 m68ki_exception_illegal();
\r
3831 M68KMAKE_OP(chk2cmp2, 32, ., pcdi)
\r
3833 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3835 uint word2 = OPER_I_16();
\r
3836 uint compare = REG_DA[(word2 >> 12) & 15];
\r
3837 uint ea = EA_PCDI_32();
\r
3838 uint lower_bound = m68ki_read_pcrel_32(ea);
\r
3839 uint upper_bound = m68ki_read_pcrel_32(ea + 4);
\r
3841 FLAG_C = compare - lower_bound;
\r
3842 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3843 FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
\r
3847 m68ki_exception_trap(EXCEPTION_CHK);
\r
3851 FLAG_C = upper_bound - compare;
\r
3852 FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
\r
3853 if(COND_CS() && BIT_B(word2))
\r
3854 m68ki_exception_trap(EXCEPTION_CHK);
\r
3857 m68ki_exception_illegal();
\r
3861 M68KMAKE_OP(chk2cmp2, 32, ., pcix)
\r
3863 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3865 uint word2 = OPER_I_16();
\r
3866 uint compare = REG_DA[(word2 >> 12) & 15];
\r
3867 uint ea = EA_PCIX_32();
\r
3868 uint lower_bound = m68ki_read_pcrel_32(ea);
\r
3869 uint upper_bound = m68ki_read_pcrel_32(ea + 4);
\r
3871 FLAG_C = compare - lower_bound;
\r
3872 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3873 FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
\r
3877 m68ki_exception_trap(EXCEPTION_CHK);
\r
3881 FLAG_C = upper_bound - compare;
\r
3882 FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
\r
3883 if(COND_CS() && BIT_B(word2))
\r
3884 m68ki_exception_trap(EXCEPTION_CHK);
\r
3887 m68ki_exception_illegal();
\r
3891 M68KMAKE_OP(chk2cmp2, 32, ., .)
\r
3893 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3895 uint word2 = OPER_I_16();
\r
3896 uint compare = REG_DA[(word2 >> 12) & 15];
\r
3897 uint ea = M68KMAKE_GET_EA_AY_32;
\r
3898 uint lower_bound = m68ki_read_32(ea);
\r
3899 uint upper_bound = m68ki_read_32(ea + 4);
\r
3901 FLAG_C = compare - lower_bound;
\r
3902 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3903 FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
\r
3907 m68ki_exception_trap(EXCEPTION_CHK);
\r
3911 FLAG_C = upper_bound - compare;
\r
3912 FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
\r
3913 if(COND_CS() && BIT_B(word2))
\r
3914 m68ki_exception_trap(EXCEPTION_CHK);
\r
3917 m68ki_exception_illegal();
\r
3921 M68KMAKE_OP(clr, 8, ., d)
\r
3925 FLAG_N = NFLAG_CLEAR;
\r
3926 FLAG_V = VFLAG_CLEAR;
\r
3927 FLAG_C = CFLAG_CLEAR;
\r
3928 FLAG_Z = ZFLAG_SET;
\r
3932 M68KMAKE_OP(clr, 8, ., .)
\r
3934 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);
\r
3936 FLAG_N = NFLAG_CLEAR;
\r
3937 FLAG_V = VFLAG_CLEAR;
\r
3938 FLAG_C = CFLAG_CLEAR;
\r
3939 FLAG_Z = ZFLAG_SET;
\r
3943 M68KMAKE_OP(clr, 16, ., d)
\r
3947 FLAG_N = NFLAG_CLEAR;
\r
3948 FLAG_V = VFLAG_CLEAR;
\r
3949 FLAG_C = CFLAG_CLEAR;
\r
3950 FLAG_Z = ZFLAG_SET;
\r
3954 M68KMAKE_OP(clr, 16, ., .)
\r
3956 m68ki_write_16(M68KMAKE_GET_EA_AY_16, 0);
\r
3958 FLAG_N = NFLAG_CLEAR;
\r
3959 FLAG_V = VFLAG_CLEAR;
\r
3960 FLAG_C = CFLAG_CLEAR;
\r
3961 FLAG_Z = ZFLAG_SET;
\r
3965 M68KMAKE_OP(clr, 32, ., d)
\r
3969 FLAG_N = NFLAG_CLEAR;
\r
3970 FLAG_V = VFLAG_CLEAR;
\r
3971 FLAG_C = CFLAG_CLEAR;
\r
3972 FLAG_Z = ZFLAG_SET;
\r
3976 M68KMAKE_OP(clr, 32, ., .)
\r
3978 m68ki_write_32(M68KMAKE_GET_EA_AY_32, 0);
\r
3980 FLAG_N = NFLAG_CLEAR;
\r
3981 FLAG_V = VFLAG_CLEAR;
\r
3982 FLAG_C = CFLAG_CLEAR;
\r
3983 FLAG_Z = ZFLAG_SET;
\r
3987 M68KMAKE_OP(cmp, 8, ., d)
\r
3989 uint src = MASK_OUT_ABOVE_8(DY);
\r
3990 uint dst = MASK_OUT_ABOVE_8(DX);
\r
3991 uint res = dst - src;
\r
3993 FLAG_N = NFLAG_8(res);
\r
3994 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
3995 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
3996 FLAG_C = CFLAG_8(res);
\r
4000 M68KMAKE_OP(cmp, 8, ., .)
\r
4002 uint src = M68KMAKE_GET_OPER_AY_8;
\r
4003 uint dst = MASK_OUT_ABOVE_8(DX);
\r
4004 uint res = dst - src;
\r
4006 FLAG_N = NFLAG_8(res);
\r
4007 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4008 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4009 FLAG_C = CFLAG_8(res);
\r
4013 M68KMAKE_OP(cmp, 16, ., d)
\r
4015 uint src = MASK_OUT_ABOVE_16(DY);
\r
4016 uint dst = MASK_OUT_ABOVE_16(DX);
\r
4017 uint res = dst - src;
\r
4019 FLAG_N = NFLAG_16(res);
\r
4020 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
4021 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
4022 FLAG_C = CFLAG_16(res);
\r
4026 M68KMAKE_OP(cmp, 16, ., a)
\r
4028 uint src = MASK_OUT_ABOVE_16(AY);
\r
4029 uint dst = MASK_OUT_ABOVE_16(DX);
\r
4030 uint res = dst - src;
\r
4032 FLAG_N = NFLAG_16(res);
\r
4033 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
4034 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
4035 FLAG_C = CFLAG_16(res);
\r
4039 M68KMAKE_OP(cmp, 16, ., .)
\r
4041 uint src = M68KMAKE_GET_OPER_AY_16;
\r
4042 uint dst = MASK_OUT_ABOVE_16(DX);
\r
4043 uint res = dst - src;
\r
4045 FLAG_N = NFLAG_16(res);
\r
4046 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
4047 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
4048 FLAG_C = CFLAG_16(res);
\r
4052 M68KMAKE_OP(cmp, 32, ., d)
\r
4056 uint res = dst - src;
\r
4058 FLAG_N = NFLAG_32(res);
\r
4059 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4060 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4061 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4065 M68KMAKE_OP(cmp, 32, ., a)
\r
4069 uint res = dst - src;
\r
4071 FLAG_N = NFLAG_32(res);
\r
4072 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4073 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4074 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4078 M68KMAKE_OP(cmp, 32, ., .)
\r
4080 uint src = M68KMAKE_GET_OPER_AY_32;
\r
4082 uint res = dst - src;
\r
4084 FLAG_N = NFLAG_32(res);
\r
4085 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4086 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4087 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4091 M68KMAKE_OP(cmpa, 16, ., d)
\r
4093 uint src = MAKE_INT_16(DY);
\r
4095 uint res = dst - src;
\r
4097 FLAG_N = NFLAG_32(res);
\r
4098 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4099 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4100 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4104 M68KMAKE_OP(cmpa, 16, ., a)
\r
4106 uint src = MAKE_INT_16(AY);
\r
4108 uint res = dst - src;
\r
4110 FLAG_N = NFLAG_32(res);
\r
4111 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4112 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4113 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4117 M68KMAKE_OP(cmpa, 16, ., .)
\r
4119 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
\r
4121 uint res = dst - src;
\r
4123 FLAG_N = NFLAG_32(res);
\r
4124 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4125 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4126 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4130 M68KMAKE_OP(cmpa, 32, ., d)
\r
4134 uint res = dst - src;
\r
4136 FLAG_N = NFLAG_32(res);
\r
4137 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4138 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4139 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4143 M68KMAKE_OP(cmpa, 32, ., a)
\r
4147 uint res = dst - src;
\r
4149 FLAG_N = NFLAG_32(res);
\r
4150 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4151 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4152 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4156 M68KMAKE_OP(cmpa, 32, ., .)
\r
4158 uint src = M68KMAKE_GET_OPER_AY_32;
\r
4160 uint res = dst - src;
\r
4162 FLAG_N = NFLAG_32(res);
\r
4163 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4164 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4165 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4169 M68KMAKE_OP(cmpi, 8, ., d)
\r
4171 uint src = OPER_I_8();
\r
4172 uint dst = MASK_OUT_ABOVE_8(DY);
\r
4173 uint res = dst - src;
\r
4175 FLAG_N = NFLAG_8(res);
\r
4176 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4177 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4178 FLAG_C = CFLAG_8(res);
\r
4182 M68KMAKE_OP(cmpi, 8, ., .)
\r
4184 uint src = OPER_I_8();
\r
4185 uint dst = M68KMAKE_GET_OPER_AY_8;
\r
4186 uint res = dst - src;
\r
4188 FLAG_N = NFLAG_8(res);
\r
4189 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4190 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4191 FLAG_C = CFLAG_8(res);
\r
4195 M68KMAKE_OP(cmpi, 8, ., pcdi)
\r
4197 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4199 uint src = OPER_I_8();
\r
4200 uint dst = OPER_PCDI_8();
\r
4201 uint res = dst - src;
\r
4203 FLAG_N = NFLAG_8(res);
\r
4204 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4205 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4206 FLAG_C = CFLAG_8(res);
\r
4209 m68ki_exception_illegal();
\r
4213 M68KMAKE_OP(cmpi, 8, ., pcix)
\r
4215 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4217 uint src = OPER_I_8();
\r
4218 uint dst = OPER_PCIX_8();
\r
4219 uint res = dst - src;
\r
4221 FLAG_N = NFLAG_8(res);
\r
4222 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4223 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4224 FLAG_C = CFLAG_8(res);
\r
4227 m68ki_exception_illegal();
\r
4231 M68KMAKE_OP(cmpi, 16, ., d)
\r
4233 uint src = OPER_I_16();
\r
4234 uint dst = MASK_OUT_ABOVE_16(DY);
\r
4235 uint res = dst - src;
\r
4237 FLAG_N = NFLAG_16(res);
\r
4238 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
4239 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
4240 FLAG_C = CFLAG_16(res);
\r
4244 M68KMAKE_OP(cmpi, 16, ., .)
\r
4246 uint src = OPER_I_16();
\r
4247 uint dst = M68KMAKE_GET_OPER_AY_16;
\r
4248 uint res = dst - src;
\r
4250 FLAG_N = NFLAG_16(res);
\r
4251 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
4252 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
4253 FLAG_C = CFLAG_16(res);
\r
4257 M68KMAKE_OP(cmpi, 16, ., pcdi)
\r
4259 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4261 uint src = OPER_I_16();
\r
4262 uint dst = OPER_PCDI_16();
\r
4263 uint res = dst - src;
\r
4265 FLAG_N = NFLAG_16(res);
\r
4266 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
4267 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
4268 FLAG_C = CFLAG_16(res);
\r
4271 m68ki_exception_illegal();
\r
4275 M68KMAKE_OP(cmpi, 16, ., pcix)
\r
4277 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4279 uint src = OPER_I_16();
\r
4280 uint dst = OPER_PCIX_16();
\r
4281 uint res = dst - src;
\r
4283 FLAG_N = NFLAG_16(res);
\r
4284 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
4285 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
4286 FLAG_C = CFLAG_16(res);
\r
4289 m68ki_exception_illegal();
\r
4293 M68KMAKE_OP(cmpi, 32, ., d)
\r
4295 uint src = OPER_I_32();
\r
4297 uint res = dst - src;
\r
4299 m68ki_cmpild_callback(src, REG_IR & 7); /* auto-disable (see m68kcpu.h) */
\r
4301 FLAG_N = NFLAG_32(res);
\r
4302 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4303 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4304 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4308 M68KMAKE_OP(cmpi, 32, ., .)
\r
4310 uint src = OPER_I_32();
\r
4311 uint dst = M68KMAKE_GET_OPER_AY_32;
\r
4312 uint res = dst - src;
\r
4314 FLAG_N = NFLAG_32(res);
\r
4315 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4316 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4317 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4321 M68KMAKE_OP(cmpi, 32, ., pcdi)
\r
4323 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4325 uint src = OPER_I_32();
\r
4326 uint dst = OPER_PCDI_32();
\r
4327 uint res = dst - src;
\r
4329 FLAG_N = NFLAG_32(res);
\r
4330 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4331 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4332 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4335 m68ki_exception_illegal();
\r
4339 M68KMAKE_OP(cmpi, 32, ., pcix)
\r
4341 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4343 uint src = OPER_I_32();
\r
4344 uint dst = OPER_PCIX_32();
\r
4345 uint res = dst - src;
\r
4347 FLAG_N = NFLAG_32(res);
\r
4348 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4349 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4350 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4353 m68ki_exception_illegal();
\r
4357 M68KMAKE_OP(cmpm, 8, ., ax7)
\r
4359 uint src = OPER_AY_PI_8();
\r
4360 uint dst = OPER_A7_PI_8();
\r
4361 uint res = dst - src;
\r
4363 FLAG_N = NFLAG_8(res);
\r
4364 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4365 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4366 FLAG_C = CFLAG_8(res);
\r
4370 M68KMAKE_OP(cmpm, 8, ., ay7)
\r
4372 uint src = OPER_A7_PI_8();
\r
4373 uint dst = OPER_AX_PI_8();
\r
4374 uint res = dst - src;
\r
4376 FLAG_N = NFLAG_8(res);
\r
4377 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4378 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4379 FLAG_C = CFLAG_8(res);
\r
4383 M68KMAKE_OP(cmpm, 8, ., axy7)
\r
4385 uint src = OPER_A7_PI_8();
\r
4386 uint dst = OPER_A7_PI_8();
\r
4387 uint res = dst - src;
\r
4389 FLAG_N = NFLAG_8(res);
\r
4390 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4391 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4392 FLAG_C = CFLAG_8(res);
\r
4396 M68KMAKE_OP(cmpm, 8, ., .)
\r
4398 uint src = OPER_AY_PI_8();
\r
4399 uint dst = OPER_AX_PI_8();
\r
4400 uint res = dst - src;
\r
4402 FLAG_N = NFLAG_8(res);
\r
4403 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4404 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4405 FLAG_C = CFLAG_8(res);
\r
4409 M68KMAKE_OP(cmpm, 16, ., .)
\r
4411 uint src = OPER_AY_PI_16();
\r
4412 uint dst = OPER_AX_PI_16();
\r
4413 uint res = dst - src;
\r
4415 FLAG_N = NFLAG_16(res);
\r
4416 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
4417 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
4418 FLAG_C = CFLAG_16(res);
\r
4422 M68KMAKE_OP(cmpm, 32, ., .)
\r
4424 uint src = OPER_AY_PI_32();
\r
4425 uint dst = OPER_AX_PI_32();
\r
4426 uint res = dst - src;
\r
4428 FLAG_N = NFLAG_32(res);
\r
4429 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4430 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4431 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4435 M68KMAKE_OP(cpbcc, 32, ., .)
\r
4437 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4439 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
4440 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
4441 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
4444 m68ki_exception_1111();
\r
4448 M68KMAKE_OP(cpdbcc, 32, ., .)
\r
4450 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4452 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
4453 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
4454 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
4457 m68ki_exception_1111();
\r
4461 M68KMAKE_OP(cpgen, 32, ., .)
\r
4463 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4465 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
4466 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
4467 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
4470 m68ki_exception_1111();
\r
4474 M68KMAKE_OP(cpscc, 32, ., .)
\r
4476 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4478 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
4479 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
4480 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
4483 m68ki_exception_1111();
\r
4487 M68KMAKE_OP(cptrapcc, 32, ., .)
\r
4489 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4491 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
4492 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
4493 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
4496 m68ki_exception_1111();
\r
4500 M68KMAKE_OP(dbt, 16, ., .)
\r
4506 M68KMAKE_OP(dbf, 16, ., .)
\r
4508 uint* r_dst = &DY;
\r
4509 uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
\r
4511 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
4514 uint offset = OPER_I_16();
\r
4516 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
4517 m68ki_branch_16(offset);
\r
4518 USE_CYCLES(CYC_DBCC_F_NOEXP);
\r
4522 USE_CYCLES(CYC_DBCC_F_EXP);
\r
4526 M68KMAKE_OP(dbcc, 16, ., .)
\r
4528 if(M68KMAKE_NOT_CC)
\r
4530 uint* r_dst = &DY;
\r
4531 uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
\r
4533 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
4536 uint offset = OPER_I_16();
\r
4538 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
4539 m68ki_branch_16(offset);
\r
4540 USE_CYCLES(CYC_DBCC_F_NOEXP);
\r
4544 USE_CYCLES(CYC_DBCC_F_EXP);
\r
4551 M68KMAKE_OP(divs, 16, ., d)
\r
4553 uint* r_dst = &DX;
\r
4554 sint src = MAKE_INT_16(DY);
\r
4555 sint dst = MAKE_INT_32(*r_dst);
\r
4562 if((uint32)*r_dst == 0x80000000 && src == -1)
\r
4565 FLAG_N = NFLAG_CLEAR;
\r
4566 FLAG_V = VFLAG_CLEAR;
\r
4567 FLAG_C = CFLAG_CLEAR;
\r
4569 USE_CYCLES(m68ki_divs_cycles(2, 0));
\r
4573 if(abs(dst) >= abs(src<<16))
\r
4575 FLAG_V = VFLAG_SET;
\r
4576 USE_CYCLES(2*(dst < 0));
\r
4580 quotient = dst / src;
\r
4581 remainder = dst % src;
\r
4583 cycles = m68ki_divs_cycles(2*(dst < 0) + (quotient < 0), quotient);
\r
4584 if(quotient == MAKE_INT_16(quotient))
\r
4586 FLAG_Z = quotient;
\r
4587 FLAG_N = NFLAG_16(quotient);
\r
4588 FLAG_V = VFLAG_CLEAR;
\r
4589 FLAG_C = CFLAG_CLEAR;
\r
4590 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
\r
4591 USE_CYCLES(cycles);
\r
4594 FLAG_V = VFLAG_SET;
\r
4595 USE_CYCLES(cycles);
\r
4598 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4603 M68KMAKE_OP(divs, 16, ., .)
\r
4605 uint* r_dst = &DX;
\r
4606 sint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
\r
4607 sint dst = MAKE_INT_32(*r_dst);
\r
4614 if((uint32)*r_dst == 0x80000000 && src == -1)
\r
4617 FLAG_N = NFLAG_CLEAR;
\r
4618 FLAG_V = VFLAG_CLEAR;
\r
4619 FLAG_C = CFLAG_CLEAR;
\r
4621 USE_CYCLES(m68ki_divs_cycles(2, 0));
\r
4625 if(abs(dst) >= abs(src<<16))
\r
4627 FLAG_V = VFLAG_SET;
\r
4628 USE_CYCLES(2*(dst < 0));
\r
4632 quotient = dst / src;
\r
4633 remainder = dst % src;
\r
4635 cycles = m68ki_divs_cycles(2*(dst < 0) + (quotient < 0), quotient);
\r
4636 if(quotient == MAKE_INT_16(quotient))
\r
4638 FLAG_Z = quotient;
\r
4639 FLAG_N = NFLAG_16(quotient);
\r
4640 FLAG_V = VFLAG_CLEAR;
\r
4641 FLAG_C = CFLAG_CLEAR;
\r
4642 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
\r
4643 USE_CYCLES(cycles);
\r
4646 FLAG_V = VFLAG_SET;
\r
4647 USE_CYCLES(cycles);
\r
4650 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4655 M68KMAKE_OP(divu, 16, ., d)
\r
4657 uint* r_dst = &DX;
\r
4658 uint src = MASK_OUT_ABOVE_16(DY);
\r
4662 uint quotient = *r_dst / src;
\r
4663 uint remainder = *r_dst % src;
\r
4665 if(quotient < 0x10000)
\r
4667 FLAG_Z = quotient;
\r
4668 FLAG_N = NFLAG_16(quotient);
\r
4669 FLAG_V = VFLAG_CLEAR;
\r
4670 FLAG_C = CFLAG_CLEAR;
\r
4671 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
\r
4672 USE_CYCLES(m68ki_divu_cycles(quotient));
\r
4675 FLAG_V = VFLAG_SET;
\r
4678 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4683 M68KMAKE_OP(divu, 16, ., .)
\r
4685 uint* r_dst = &DX;
\r
4686 uint src = M68KMAKE_GET_OPER_AY_16;
\r
4690 uint quotient = *r_dst / src;
\r
4691 uint remainder = *r_dst % src;
\r
4693 if(quotient < 0x10000)
\r
4695 FLAG_Z = quotient;
\r
4696 FLAG_N = NFLAG_16(quotient);
\r
4697 FLAG_V = VFLAG_CLEAR;
\r
4698 FLAG_C = CFLAG_CLEAR;
\r
4699 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
\r
4700 USE_CYCLES(m68ki_divu_cycles(quotient));
\r
4703 FLAG_V = VFLAG_SET;
\r
4706 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4711 M68KMAKE_OP(divl, 32, ., d)
\r
4713 #if M68K_USE_64_BIT
\r
4715 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4717 uint word2 = OPER_I_16();
\r
4718 uint64 divisor = DY;
\r
4719 uint64 dividend = 0;
\r
4720 uint64 quotient = 0;
\r
4721 uint64 remainder = 0;
\r
4725 if(BIT_A(word2)) /* 64 bit */
\r
4727 dividend = REG_D[word2 & 7];
\r
4729 dividend |= REG_D[(word2 >> 12) & 7];
\r
4731 if(BIT_B(word2)) /* signed */
\r
4733 quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
\r
4734 remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
\r
4735 if((sint64)quotient != (sint64)((sint32)quotient))
\r
4737 FLAG_V = VFLAG_SET;
\r
4741 else /* unsigned */
\r
4743 quotient = dividend / divisor;
\r
4744 if(quotient > 0xffffffff)
\r
4746 FLAG_V = VFLAG_SET;
\r
4749 remainder = dividend % divisor;
\r
4754 dividend = REG_D[(word2 >> 12) & 7];
\r
4755 if(BIT_B(word2)) /* signed */
\r
4757 quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
\r
4758 remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
\r
4760 else /* unsigned */
\r
4762 quotient = dividend / divisor;
\r
4763 remainder = dividend % divisor;
\r
4767 REG_D[word2 & 7] = remainder;
\r
4768 REG_D[(word2 >> 12) & 7] = quotient;
\r
4770 FLAG_N = NFLAG_32(quotient);
\r
4771 FLAG_Z = quotient;
\r
4772 FLAG_V = VFLAG_CLEAR;
\r
4773 FLAG_C = CFLAG_CLEAR;
\r
4776 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4779 m68ki_exception_illegal();
\r
4783 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4785 uint word2 = OPER_I_16();
\r
4786 uint divisor = DY;
\r
4787 uint dividend_hi = REG_D[word2 & 7];
\r
4788 uint dividend_lo = REG_D[(word2 >> 12) & 7];
\r
4789 uint quotient = 0;
\r
4790 uint remainder = 0;
\r
4791 uint dividend_neg = 0;
\r
4792 uint divisor_neg = 0;
\r
4798 /* quad / long : long quotient, long remainder */
\r
4801 if(BIT_B(word2)) /* signed */
\r
4803 /* special case in signed divide */
\r
4804 if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
\r
4806 REG_D[word2 & 7] = 0;
\r
4807 REG_D[(word2 >> 12) & 7] = 0x80000000;
\r
4809 FLAG_N = NFLAG_SET;
\r
4810 FLAG_Z = ZFLAG_CLEAR;
\r
4811 FLAG_V = VFLAG_CLEAR;
\r
4812 FLAG_C = CFLAG_CLEAR;
\r
4815 if(GET_MSB_32(dividend_hi))
\r
4818 dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
\r
4819 dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
\r
4821 if(GET_MSB_32(divisor))
\r
4824 divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
\r
4829 /* if the upper long is greater than the divisor, we're overflowing. */
\r
4830 if(dividend_hi >= divisor)
\r
4832 FLAG_V = VFLAG_SET;
\r
4836 for(i = 31; i >= 0; i--)
\r
4839 remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
\r
4840 if(remainder >= divisor)
\r
4842 remainder -= divisor;
\r
4846 for(i = 31; i >= 0; i--)
\r
4849 overflow = GET_MSB_32(remainder);
\r
4850 remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
\r
4851 if(remainder >= divisor || overflow)
\r
4853 remainder -= divisor;
\r
4858 if(BIT_B(word2)) /* signed */
\r
4860 if(quotient > 0x7fffffff)
\r
4862 FLAG_V = VFLAG_SET;
\r
4867 remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
\r
4868 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
\r
4871 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
\r
4874 REG_D[word2 & 7] = remainder;
\r
4875 REG_D[(word2 >> 12) & 7] = quotient;
\r
4877 FLAG_N = NFLAG_32(quotient);
\r
4878 FLAG_Z = quotient;
\r
4879 FLAG_V = VFLAG_CLEAR;
\r
4880 FLAG_C = CFLAG_CLEAR;
\r
4884 /* long / long: long quotient, maybe long remainder */
\r
4885 if(BIT_B(word2)) /* signed */
\r
4887 /* Special case in divide */
\r
4888 if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
\r
4890 FLAG_N = NFLAG_SET;
\r
4891 FLAG_Z = ZFLAG_CLEAR;
\r
4892 FLAG_V = VFLAG_CLEAR;
\r
4893 FLAG_C = CFLAG_CLEAR;
\r
4894 REG_D[(word2 >> 12) & 7] = 0x80000000;
\r
4895 REG_D[word2 & 7] = 0;
\r
4898 REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
\r
4899 quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
\r
4903 REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
\r
4904 quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
\r
4907 FLAG_N = NFLAG_32(quotient);
\r
4908 FLAG_Z = quotient;
\r
4909 FLAG_V = VFLAG_CLEAR;
\r
4910 FLAG_C = CFLAG_CLEAR;
\r
4913 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4916 m68ki_exception_illegal();
\r
4922 M68KMAKE_OP(divl, 32, ., .)
\r
4924 #if M68K_USE_64_BIT
\r
4926 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4928 uint word2 = OPER_I_16();
\r
4929 uint64 divisor = M68KMAKE_GET_OPER_AY_32;
\r
4930 uint64 dividend = 0;
\r
4931 uint64 quotient = 0;
\r
4932 uint64 remainder = 0;
\r
4936 if(BIT_A(word2)) /* 64 bit */
\r
4938 dividend = REG_D[word2 & 7];
\r
4940 dividend |= REG_D[(word2 >> 12) & 7];
\r
4942 if(BIT_B(word2)) /* signed */
\r
4944 quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
\r
4945 remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
\r
4946 if((sint64)quotient != (sint64)((sint32)quotient))
\r
4948 FLAG_V = VFLAG_SET;
\r
4952 else /* unsigned */
\r
4954 quotient = dividend / divisor;
\r
4955 if(quotient > 0xffffffff)
\r
4957 FLAG_V = VFLAG_SET;
\r
4960 remainder = dividend % divisor;
\r
4965 dividend = REG_D[(word2 >> 12) & 7];
\r
4966 if(BIT_B(word2)) /* signed */
\r
4968 quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
\r
4969 remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
\r
4971 else /* unsigned */
\r
4973 quotient = dividend / divisor;
\r
4974 remainder = dividend % divisor;
\r
4978 REG_D[word2 & 7] = remainder;
\r
4979 REG_D[(word2 >> 12) & 7] = quotient;
\r
4981 FLAG_N = NFLAG_32(quotient);
\r
4982 FLAG_Z = quotient;
\r
4983 FLAG_V = VFLAG_CLEAR;
\r
4984 FLAG_C = CFLAG_CLEAR;
\r
4987 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4990 m68ki_exception_illegal();
\r
4994 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4996 uint word2 = OPER_I_16();
\r
4997 uint divisor = M68KMAKE_GET_OPER_AY_32;
\r
4998 uint dividend_hi = REG_D[word2 & 7];
\r
4999 uint dividend_lo = REG_D[(word2 >> 12) & 7];
\r
5000 uint quotient = 0;
\r
5001 uint remainder = 0;
\r
5002 uint dividend_neg = 0;
\r
5003 uint divisor_neg = 0;
\r
5009 /* quad / long : long quotient, long remainder */
\r
5012 if(BIT_B(word2)) /* signed */
\r
5014 /* special case in signed divide */
\r
5015 if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
\r
5017 REG_D[word2 & 7] = 0;
\r
5018 REG_D[(word2 >> 12) & 7] = 0x80000000;
\r
5020 FLAG_N = NFLAG_SET;
\r
5021 FLAG_Z = ZFLAG_CLEAR;
\r
5022 FLAG_V = VFLAG_CLEAR;
\r
5023 FLAG_C = CFLAG_CLEAR;
\r
5026 if(GET_MSB_32(dividend_hi))
\r
5029 dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
\r
5030 dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
\r
5032 if(GET_MSB_32(divisor))
\r
5035 divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
\r
5040 /* if the upper long is greater than the divisor, we're overflowing. */
\r
5041 if(dividend_hi >= divisor)
\r
5043 FLAG_V = VFLAG_SET;
\r
5047 for(i = 31; i >= 0; i--)
\r
5050 remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
\r
5051 if(remainder >= divisor)
\r
5053 remainder -= divisor;
\r
5057 for(i = 31; i >= 0; i--)
\r
5060 overflow = GET_MSB_32(remainder);
\r
5061 remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
\r
5062 if(remainder >= divisor || overflow)
\r
5064 remainder -= divisor;
\r
5069 if(BIT_B(word2)) /* signed */
\r
5071 if(quotient > 0x7fffffff)
\r
5073 FLAG_V = VFLAG_SET;
\r
5078 remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
\r
5079 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
\r
5082 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
\r
5085 REG_D[word2 & 7] = remainder;
\r
5086 REG_D[(word2 >> 12) & 7] = quotient;
\r
5088 FLAG_N = NFLAG_32(quotient);
\r
5089 FLAG_Z = quotient;
\r
5090 FLAG_V = VFLAG_CLEAR;
\r
5091 FLAG_C = CFLAG_CLEAR;
\r
5095 /* long / long: long quotient, maybe long remainder */
\r
5096 if(BIT_B(word2)) /* signed */
\r
5098 /* Special case in divide */
\r
5099 if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
\r
5101 FLAG_N = NFLAG_SET;
\r
5102 FLAG_Z = ZFLAG_CLEAR;
\r
5103 FLAG_V = VFLAG_CLEAR;
\r
5104 FLAG_C = CFLAG_CLEAR;
\r
5105 REG_D[(word2 >> 12) & 7] = 0x80000000;
\r
5106 REG_D[word2 & 7] = 0;
\r
5109 REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
\r
5110 quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
\r
5114 REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
\r
5115 quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
\r
5118 FLAG_N = NFLAG_32(quotient);
\r
5119 FLAG_Z = quotient;
\r
5120 FLAG_V = VFLAG_CLEAR;
\r
5121 FLAG_C = CFLAG_CLEAR;
\r
5124 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
5127 m68ki_exception_illegal();
\r
5133 M68KMAKE_OP(eor, 8, ., d)
\r
5135 uint res = MASK_OUT_ABOVE_8(DY ^= MASK_OUT_ABOVE_8(DX));
\r
5137 FLAG_N = NFLAG_8(res);
\r
5139 FLAG_C = CFLAG_CLEAR;
\r
5140 FLAG_V = VFLAG_CLEAR;
\r
5144 M68KMAKE_OP(eor, 8, ., .)
\r
5146 uint ea = M68KMAKE_GET_EA_AY_8;
\r
5147 uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
\r
5149 m68ki_write_8(ea, res);
\r
5151 FLAG_N = NFLAG_8(res);
\r
5153 FLAG_C = CFLAG_CLEAR;
\r
5154 FLAG_V = VFLAG_CLEAR;
\r
5158 M68KMAKE_OP(eor, 16, ., d)
\r
5160 uint res = MASK_OUT_ABOVE_16(DY ^= MASK_OUT_ABOVE_16(DX));
\r
5162 FLAG_N = NFLAG_16(res);
\r
5164 FLAG_C = CFLAG_CLEAR;
\r
5165 FLAG_V = VFLAG_CLEAR;
\r
5169 M68KMAKE_OP(eor, 16, ., .)
\r
5171 uint ea = M68KMAKE_GET_EA_AY_16;
\r
5172 uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
\r
5174 m68ki_write_16(ea, res);
\r
5176 FLAG_N = NFLAG_16(res);
\r
5178 FLAG_C = CFLAG_CLEAR;
\r
5179 FLAG_V = VFLAG_CLEAR;
\r
5183 M68KMAKE_OP(eor, 32, ., d)
\r
5185 uint res = DY ^= DX;
\r
5187 FLAG_N = NFLAG_32(res);
\r
5189 FLAG_C = CFLAG_CLEAR;
\r
5190 FLAG_V = VFLAG_CLEAR;
\r
5194 M68KMAKE_OP(eor, 32, ., .)
\r
5196 uint ea = M68KMAKE_GET_EA_AY_32;
\r
5197 uint res = DX ^ m68ki_read_32(ea);
\r
5199 m68ki_write_32(ea, res);
\r
5201 FLAG_N = NFLAG_32(res);
\r
5203 FLAG_C = CFLAG_CLEAR;
\r
5204 FLAG_V = VFLAG_CLEAR;
\r
5208 M68KMAKE_OP(eori, 8, ., d)
\r
5210 uint res = MASK_OUT_ABOVE_8(DY ^= OPER_I_8());
\r
5212 FLAG_N = NFLAG_8(res);
\r
5214 FLAG_C = CFLAG_CLEAR;
\r
5215 FLAG_V = VFLAG_CLEAR;
\r
5219 M68KMAKE_OP(eori, 8, ., .)
\r
5221 uint src = OPER_I_8();
\r
5222 uint ea = M68KMAKE_GET_EA_AY_8;
\r
5223 uint res = src ^ m68ki_read_8(ea);
\r
5225 m68ki_write_8(ea, res);
\r
5227 FLAG_N = NFLAG_8(res);
\r
5229 FLAG_C = CFLAG_CLEAR;
\r
5230 FLAG_V = VFLAG_CLEAR;
\r
5234 M68KMAKE_OP(eori, 16, ., d)
\r
5236 uint res = MASK_OUT_ABOVE_16(DY ^= OPER_I_16());
\r
5238 FLAG_N = NFLAG_16(res);
\r
5240 FLAG_C = CFLAG_CLEAR;
\r
5241 FLAG_V = VFLAG_CLEAR;
\r
5245 M68KMAKE_OP(eori, 16, ., .)
\r
5247 uint src = OPER_I_16();
\r
5248 uint ea = M68KMAKE_GET_EA_AY_16;
\r
5249 uint res = src ^ m68ki_read_16(ea);
\r
5251 m68ki_write_16(ea, res);
\r
5253 FLAG_N = NFLAG_16(res);
\r
5255 FLAG_C = CFLAG_CLEAR;
\r
5256 FLAG_V = VFLAG_CLEAR;
\r
5260 M68KMAKE_OP(eori, 32, ., d)
\r
5262 uint res = DY ^= OPER_I_32();
\r
5264 FLAG_N = NFLAG_32(res);
\r
5266 FLAG_C = CFLAG_CLEAR;
\r
5267 FLAG_V = VFLAG_CLEAR;
\r
5271 M68KMAKE_OP(eori, 32, ., .)
\r
5273 uint src = OPER_I_32();
\r
5274 uint ea = M68KMAKE_GET_EA_AY_32;
\r
5275 uint res = src ^ m68ki_read_32(ea);
\r
5277 m68ki_write_32(ea, res);
\r
5279 FLAG_N = NFLAG_32(res);
\r
5281 FLAG_C = CFLAG_CLEAR;
\r
5282 FLAG_V = VFLAG_CLEAR;
\r
5286 M68KMAKE_OP(eori, 16, toc, .)
\r
5288 m68ki_set_ccr(m68ki_get_ccr() ^ OPER_I_16());
\r
5292 M68KMAKE_OP(eori, 16, tos, .)
\r
5296 uint src = OPER_I_16();
\r
5297 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
5298 m68ki_set_sr(m68ki_get_sr() ^ src);
\r
5301 m68ki_exception_privilege_violation();
\r
5305 M68KMAKE_OP(exg, 32, dd, .)
\r
5307 uint* reg_a = &DX;
\r
5308 uint* reg_b = &DY;
\r
5309 uint tmp = *reg_a;
\r
5315 M68KMAKE_OP(exg, 32, aa, .)
\r
5317 uint* reg_a = &AX;
\r
5318 uint* reg_b = &AY;
\r
5319 uint tmp = *reg_a;
\r
5325 M68KMAKE_OP(exg, 32, da, .)
\r
5327 uint* reg_a = &DX;
\r
5328 uint* reg_b = &AY;
\r
5329 uint tmp = *reg_a;
\r
5335 M68KMAKE_OP(ext, 16, ., .)
\r
5337 uint* r_dst = &DY;
\r
5339 *r_dst = MASK_OUT_BELOW_16(*r_dst) | MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xff00 : 0);
\r
5341 FLAG_N = NFLAG_16(*r_dst);
\r
5342 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
\r
5343 FLAG_V = VFLAG_CLEAR;
\r
5344 FLAG_C = CFLAG_CLEAR;
\r
5348 M68KMAKE_OP(ext, 32, ., .)
\r
5350 uint* r_dst = &DY;
\r
5352 *r_dst = MASK_OUT_ABOVE_16(*r_dst) | (GET_MSB_16(*r_dst) ? 0xffff0000 : 0);
\r
5354 FLAG_N = NFLAG_32(*r_dst);
\r
5356 FLAG_V = VFLAG_CLEAR;
\r
5357 FLAG_C = CFLAG_CLEAR;
\r
5361 M68KMAKE_OP(extb, 32, ., .)
\r
5363 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
5365 uint* r_dst = &DY;
\r
5367 *r_dst = MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xffffff00 : 0);
\r
5369 FLAG_N = NFLAG_32(*r_dst);
\r
5371 FLAG_V = VFLAG_CLEAR;
\r
5372 FLAG_C = CFLAG_CLEAR;
\r
5375 m68ki_exception_illegal();
\r
5379 M68KMAKE_OP(illegal, 0, ., .)
\r
5381 m68ki_exception_illegal();
\r
5384 M68KMAKE_OP(jmp, 32, ., .)
\r
5386 m68ki_jump(M68KMAKE_GET_EA_AY_32);
\r
5387 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
5388 if(REG_PC == REG_PPC)
\r
5393 M68KMAKE_OP(jsr, 32, ., .)
\r
5395 uint ea = M68KMAKE_GET_EA_AY_32;
\r
5396 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
5397 m68ki_push_32(REG_PC);
\r
5402 M68KMAKE_OP(lea, 32, ., .)
\r
5404 AX = M68KMAKE_GET_EA_AY_32;
\r
5408 M68KMAKE_OP(link, 16, ., a7)
\r
5411 m68ki_write_32(REG_A[7], REG_A[7]);
\r
5412 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
\r
5416 M68KMAKE_OP(link, 16, ., .)
\r
5418 uint* r_dst = &AY;
\r
5420 m68ki_push_32(*r_dst);
\r
5421 *r_dst = REG_A[7];
\r
5422 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
\r
5426 M68KMAKE_OP(link, 32, ., a7)
\r
5428 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
5431 m68ki_write_32(REG_A[7], REG_A[7]);
\r
5432 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());
\r
5435 m68ki_exception_illegal();
\r
5439 M68KMAKE_OP(link, 32, ., .)
\r
5441 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
5443 uint* r_dst = &AY;
\r
5445 m68ki_push_32(*r_dst);
\r
5446 *r_dst = REG_A[7];
\r
5447 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());
\r
5450 m68ki_exception_illegal();
\r
5454 M68KMAKE_OP(lsr, 8, s, .)
\r
5456 uint* r_dst = &DY;
\r
5457 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
5458 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
5459 uint res = src >> shift;
\r
5462 USE_CYCLES(shift<<CYC_SHIFT);
\r
5464 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
5466 FLAG_N = NFLAG_CLEAR;
\r
5468 FLAG_X = FLAG_C = src << (9-shift);
\r
5469 FLAG_V = VFLAG_CLEAR;
\r
5473 M68KMAKE_OP(lsr, 16, s, .)
\r
5475 uint* r_dst = &DY;
\r
5476 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
5477 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
5478 uint res = src >> shift;
\r
5481 USE_CYCLES(shift<<CYC_SHIFT);
\r
5483 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
5485 FLAG_N = NFLAG_CLEAR;
\r
5487 FLAG_X = FLAG_C = src << (9-shift);
\r
5488 FLAG_V = VFLAG_CLEAR;
\r
5492 M68KMAKE_OP(lsr, 32, s, .)
\r
5494 uint* r_dst = &DY;
\r
5495 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
5496 uint src = *r_dst;
\r
5497 uint res = src >> shift;
\r
5500 USE_CYCLES(shift<<CYC_SHIFT);
\r
5504 FLAG_N = NFLAG_CLEAR;
\r
5506 FLAG_X = FLAG_C = src << (9-shift);
\r
5507 FLAG_V = VFLAG_CLEAR;
\r
5511 M68KMAKE_OP(lsr, 8, r, .)
\r
5513 uint* r_dst = &DY;
\r
5514 uint shift = DX & 0x3f;
\r
5515 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
5516 uint res = src >> shift;
\r
5520 USE_CYCLES(shift<<CYC_SHIFT);
\r
5524 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
5525 FLAG_X = FLAG_C = src << (9-shift);
\r
5526 FLAG_N = NFLAG_CLEAR;
\r
5528 FLAG_V = VFLAG_CLEAR;
\r
5532 *r_dst &= 0xffffff00;
\r
5533 FLAG_X = XFLAG_CLEAR;
\r
5534 FLAG_C = CFLAG_CLEAR;
\r
5535 FLAG_N = NFLAG_CLEAR;
\r
5536 FLAG_Z = ZFLAG_SET;
\r
5537 FLAG_V = VFLAG_CLEAR;
\r
5541 FLAG_C = CFLAG_CLEAR;
\r
5542 FLAG_N = NFLAG_8(src);
\r
5544 FLAG_V = VFLAG_CLEAR;
\r
5548 M68KMAKE_OP(lsr, 16, r, .)
\r
5550 uint* r_dst = &DY;
\r
5551 uint shift = DX & 0x3f;
\r
5552 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
5553 uint res = src >> shift;
\r
5557 USE_CYCLES(shift<<CYC_SHIFT);
\r
5561 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
5562 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
\r
5563 FLAG_N = NFLAG_CLEAR;
\r
5565 FLAG_V = VFLAG_CLEAR;
\r
5569 *r_dst &= 0xffff0000;
\r
5570 FLAG_X = XFLAG_CLEAR;
\r
5571 FLAG_C = CFLAG_CLEAR;
\r
5572 FLAG_N = NFLAG_CLEAR;
\r
5573 FLAG_Z = ZFLAG_SET;
\r
5574 FLAG_V = VFLAG_CLEAR;
\r
5578 FLAG_C = CFLAG_CLEAR;
\r
5579 FLAG_N = NFLAG_16(src);
\r
5581 FLAG_V = VFLAG_CLEAR;
\r
5585 M68KMAKE_OP(lsr, 32, r, .)
\r
5587 uint* r_dst = &DY;
\r
5588 uint shift = DX & 0x3f;
\r
5589 uint src = *r_dst;
\r
5590 uint res = src >> shift;
\r
5594 USE_CYCLES(shift<<CYC_SHIFT);
\r
5599 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
\r
5600 FLAG_N = NFLAG_CLEAR;
\r
5602 FLAG_V = VFLAG_CLEAR;
\r
5607 FLAG_X = FLAG_C = (shift == 32 ? GET_MSB_32(src)>>23 : 0);
\r
5608 FLAG_N = NFLAG_CLEAR;
\r
5609 FLAG_Z = ZFLAG_SET;
\r
5610 FLAG_V = VFLAG_CLEAR;
\r
5614 FLAG_C = CFLAG_CLEAR;
\r
5615 FLAG_N = NFLAG_32(src);
\r
5617 FLAG_V = VFLAG_CLEAR;
\r
5621 M68KMAKE_OP(lsr, 16, ., .)
\r
5623 uint ea = M68KMAKE_GET_EA_AY_16;
\r
5624 uint src = m68ki_read_16(ea);
\r
5625 uint res = src >> 1;
\r
5627 m68ki_write_16(ea, res);
\r
5629 FLAG_N = NFLAG_CLEAR;
\r
5631 FLAG_C = FLAG_X = src << 8;
\r
5632 FLAG_V = VFLAG_CLEAR;
\r
5636 M68KMAKE_OP(lsl, 8, s, .)
\r
5638 uint* r_dst = &DY;
\r
5639 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
5640 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
5641 uint res = MASK_OUT_ABOVE_8(src << shift);
\r
5644 USE_CYCLES(shift<<CYC_SHIFT);
\r
5646 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
5648 FLAG_N = NFLAG_8(res);
\r
5650 FLAG_X = FLAG_C = src << shift;
\r
5651 FLAG_V = VFLAG_CLEAR;
\r
5655 M68KMAKE_OP(lsl, 16, s, .)
\r
5657 uint* r_dst = &DY;
\r
5658 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
5659 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
5660 uint res = MASK_OUT_ABOVE_16(src << shift);
\r
5663 USE_CYCLES(shift<<CYC_SHIFT);
\r
5665 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
5667 FLAG_N = NFLAG_16(res);
\r
5669 FLAG_X = FLAG_C = src >> (8-shift);
\r
5670 FLAG_V = VFLAG_CLEAR;
\r
5674 M68KMAKE_OP(lsl, 32, s, .)
\r
5676 uint* r_dst = &DY;
\r
5677 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
5678 uint src = *r_dst;
\r
5679 uint res = MASK_OUT_ABOVE_32(src << shift);
\r
5682 USE_CYCLES(shift<<CYC_SHIFT);
\r
5686 FLAG_N = NFLAG_32(res);
\r
5688 FLAG_X = FLAG_C = src >> (24-shift);
\r
5689 FLAG_V = VFLAG_CLEAR;
\r
5693 M68KMAKE_OP(lsl, 8, r, .)
\r
5695 uint* r_dst = &DY;
\r
5696 uint shift = DX & 0x3f;
\r
5697 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
5698 uint res = MASK_OUT_ABOVE_8(src << shift);
\r
5702 USE_CYCLES(shift<<CYC_SHIFT);
\r
5706 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
5707 FLAG_X = FLAG_C = src << shift;
\r
5708 FLAG_N = NFLAG_8(res);
\r
5710 FLAG_V = VFLAG_CLEAR;
\r
5714 *r_dst &= 0xffffff00;
\r
5715 FLAG_X = XFLAG_CLEAR;
\r
5716 FLAG_C = CFLAG_CLEAR;
\r
5717 FLAG_N = NFLAG_CLEAR;
\r
5718 FLAG_Z = ZFLAG_SET;
\r
5719 FLAG_V = VFLAG_CLEAR;
\r
5723 FLAG_C = CFLAG_CLEAR;
\r
5724 FLAG_N = NFLAG_8(src);
\r
5726 FLAG_V = VFLAG_CLEAR;
\r
5730 M68KMAKE_OP(lsl, 16, r, .)
\r
5732 uint* r_dst = &DY;
\r
5733 uint shift = DX & 0x3f;
\r
5734 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
5735 uint res = MASK_OUT_ABOVE_16(src << shift);
\r
5739 USE_CYCLES(shift<<CYC_SHIFT);
\r
5743 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
5744 FLAG_X = FLAG_C = (src << shift) >> 8;
\r
5745 FLAG_N = NFLAG_16(res);
\r
5747 FLAG_V = VFLAG_CLEAR;
\r
5751 *r_dst &= 0xffff0000;
\r
5752 FLAG_X = XFLAG_CLEAR;
\r
5753 FLAG_C = CFLAG_CLEAR;
\r
5754 FLAG_N = NFLAG_CLEAR;
\r
5755 FLAG_Z = ZFLAG_SET;
\r
5756 FLAG_V = VFLAG_CLEAR;
\r
5760 FLAG_C = CFLAG_CLEAR;
\r
5761 FLAG_N = NFLAG_16(src);
\r
5763 FLAG_V = VFLAG_CLEAR;
\r
5767 M68KMAKE_OP(lsl, 32, r, .)
\r
5769 uint* r_dst = &DY;
\r
5770 uint shift = DX & 0x3f;
\r
5771 uint src = *r_dst;
\r
5772 uint res = MASK_OUT_ABOVE_32(src << shift);
\r
5776 USE_CYCLES(shift<<CYC_SHIFT);
\r
5781 FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;
\r
5782 FLAG_N = NFLAG_32(res);
\r
5784 FLAG_V = VFLAG_CLEAR;
\r
5789 FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;
\r
5790 FLAG_N = NFLAG_CLEAR;
\r
5791 FLAG_Z = ZFLAG_SET;
\r
5792 FLAG_V = VFLAG_CLEAR;
\r
5796 FLAG_C = CFLAG_CLEAR;
\r
5797 FLAG_N = NFLAG_32(src);
\r
5799 FLAG_V = VFLAG_CLEAR;
\r
5803 M68KMAKE_OP(lsl, 16, ., .)
\r
5805 uint ea = M68KMAKE_GET_EA_AY_16;
\r
5806 uint src = m68ki_read_16(ea);
\r
5807 uint res = MASK_OUT_ABOVE_16(src << 1);
\r
5809 m68ki_write_16(ea, res);
\r
5811 FLAG_N = NFLAG_16(res);
\r
5813 FLAG_X = FLAG_C = src >> 7;
\r
5814 FLAG_V = VFLAG_CLEAR;
\r
5818 M68KMAKE_OP(move, 8, d, d)
\r
5820 uint res = MASK_OUT_ABOVE_8(DY);
\r
5821 uint* r_dst = &DX;
\r
5823 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
5825 FLAG_N = NFLAG_8(res);
\r
5827 FLAG_V = VFLAG_CLEAR;
\r
5828 FLAG_C = CFLAG_CLEAR;
\r
5832 M68KMAKE_OP(move, 8, d, .)
\r
5834 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5835 uint* r_dst = &DX;
\r
5837 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
5839 FLAG_N = NFLAG_8(res);
\r
5841 FLAG_V = VFLAG_CLEAR;
\r
5842 FLAG_C = CFLAG_CLEAR;
\r
5846 M68KMAKE_OP(move, 8, ai, d)
\r
5848 uint res = MASK_OUT_ABOVE_8(DY);
\r
5849 uint ea = EA_AX_AI_8();
\r
5851 m68ki_write_8(ea, res);
\r
5853 FLAG_N = NFLAG_8(res);
\r
5855 FLAG_V = VFLAG_CLEAR;
\r
5856 FLAG_C = CFLAG_CLEAR;
\r
5860 M68KMAKE_OP(move, 8, ai, .)
\r
5862 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5863 uint ea = EA_AX_AI_8();
\r
5865 m68ki_write_8(ea, res);
\r
5867 FLAG_N = NFLAG_8(res);
\r
5869 FLAG_V = VFLAG_CLEAR;
\r
5870 FLAG_C = CFLAG_CLEAR;
\r
5874 M68KMAKE_OP(move, 8, pi7, d)
\r
5876 uint res = MASK_OUT_ABOVE_8(DY);
\r
5877 uint ea = EA_A7_PI_8();
\r
5879 m68ki_write_8(ea, res);
\r
5881 FLAG_N = NFLAG_8(res);
\r
5883 FLAG_V = VFLAG_CLEAR;
\r
5884 FLAG_C = CFLAG_CLEAR;
\r
5888 M68KMAKE_OP(move, 8, pi, d)
\r
5890 uint res = MASK_OUT_ABOVE_8(DY);
\r
5891 uint ea = EA_AX_PI_8();
\r
5893 m68ki_write_8(ea, res);
\r
5895 FLAG_N = NFLAG_8(res);
\r
5897 FLAG_V = VFLAG_CLEAR;
\r
5898 FLAG_C = CFLAG_CLEAR;
\r
5902 M68KMAKE_OP(move, 8, pi7, .)
\r
5904 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5905 uint ea = EA_A7_PI_8();
\r
5907 m68ki_write_8(ea, res);
\r
5909 FLAG_N = NFLAG_8(res);
\r
5911 FLAG_V = VFLAG_CLEAR;
\r
5912 FLAG_C = CFLAG_CLEAR;
\r
5916 M68KMAKE_OP(move, 8, pi, .)
\r
5918 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5919 uint ea = EA_AX_PI_8();
\r
5921 m68ki_write_8(ea, res);
\r
5923 FLAG_N = NFLAG_8(res);
\r
5925 FLAG_V = VFLAG_CLEAR;
\r
5926 FLAG_C = CFLAG_CLEAR;
\r
5930 M68KMAKE_OP(move, 8, pd7, d)
\r
5932 uint res = MASK_OUT_ABOVE_8(DY);
\r
5933 uint ea = EA_A7_PD_8();
\r
5935 m68ki_write_8(ea, res);
\r
5937 FLAG_N = NFLAG_8(res);
\r
5939 FLAG_V = VFLAG_CLEAR;
\r
5940 FLAG_C = CFLAG_CLEAR;
\r
5944 M68KMAKE_OP(move, 8, pd, d)
\r
5946 uint res = MASK_OUT_ABOVE_8(DY);
\r
5947 uint ea = EA_AX_PD_8();
\r
5949 m68ki_write_8(ea, res);
\r
5951 FLAG_N = NFLAG_8(res);
\r
5953 FLAG_V = VFLAG_CLEAR;
\r
5954 FLAG_C = CFLAG_CLEAR;
\r
5958 M68KMAKE_OP(move, 8, pd7, .)
\r
5960 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5961 uint ea = EA_A7_PD_8();
\r
5963 m68ki_write_8(ea, res);
\r
5965 FLAG_N = NFLAG_8(res);
\r
5967 FLAG_V = VFLAG_CLEAR;
\r
5968 FLAG_C = CFLAG_CLEAR;
\r
5972 M68KMAKE_OP(move, 8, pd, .)
\r
5974 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5975 uint ea = EA_AX_PD_8();
\r
5977 m68ki_write_8(ea, res);
\r
5979 FLAG_N = NFLAG_8(res);
\r
5981 FLAG_V = VFLAG_CLEAR;
\r
5982 FLAG_C = CFLAG_CLEAR;
\r
5986 M68KMAKE_OP(move, 8, di, d)
\r
5988 uint res = MASK_OUT_ABOVE_8(DY);
\r
5989 uint ea = EA_AX_DI_8();
\r
5991 m68ki_write_8(ea, res);
\r
5993 FLAG_N = NFLAG_8(res);
\r
5995 FLAG_V = VFLAG_CLEAR;
\r
5996 FLAG_C = CFLAG_CLEAR;
\r
6000 M68KMAKE_OP(move, 8, di, .)
\r
6002 uint res = M68KMAKE_GET_OPER_AY_8;
\r
6003 uint ea = EA_AX_DI_8();
\r
6005 m68ki_write_8(ea, res);
\r
6007 FLAG_N = NFLAG_8(res);
\r
6009 FLAG_V = VFLAG_CLEAR;
\r
6010 FLAG_C = CFLAG_CLEAR;
\r
6014 M68KMAKE_OP(move, 8, ix, d)
\r
6016 uint res = MASK_OUT_ABOVE_8(DY);
\r
6017 uint ea = EA_AX_IX_8();
\r
6019 m68ki_write_8(ea, res);
\r
6021 FLAG_N = NFLAG_8(res);
\r
6023 FLAG_V = VFLAG_CLEAR;
\r
6024 FLAG_C = CFLAG_CLEAR;
\r
6028 M68KMAKE_OP(move, 8, ix, .)
\r
6030 uint res = M68KMAKE_GET_OPER_AY_8;
\r
6031 uint ea = EA_AX_IX_8();
\r
6033 m68ki_write_8(ea, res);
\r
6035 FLAG_N = NFLAG_8(res);
\r
6037 FLAG_V = VFLAG_CLEAR;
\r
6038 FLAG_C = CFLAG_CLEAR;
\r
6042 M68KMAKE_OP(move, 8, aw, d)
\r
6044 uint res = MASK_OUT_ABOVE_8(DY);
\r
6045 uint ea = EA_AW_8();
\r
6047 m68ki_write_8(ea, res);
\r
6049 FLAG_N = NFLAG_8(res);
\r
6051 FLAG_V = VFLAG_CLEAR;
\r
6052 FLAG_C = CFLAG_CLEAR;
\r
6056 M68KMAKE_OP(move, 8, aw, .)
\r
6058 uint res = M68KMAKE_GET_OPER_AY_8;
\r
6059 uint ea = EA_AW_8();
\r
6061 m68ki_write_8(ea, res);
\r
6063 FLAG_N = NFLAG_8(res);
\r
6065 FLAG_V = VFLAG_CLEAR;
\r
6066 FLAG_C = CFLAG_CLEAR;
\r
6070 M68KMAKE_OP(move, 8, al, d)
\r
6072 uint res = MASK_OUT_ABOVE_8(DY);
\r
6073 uint ea = EA_AL_8();
\r
6075 m68ki_write_8(ea, res);
\r
6077 FLAG_N = NFLAG_8(res);
\r
6079 FLAG_V = VFLAG_CLEAR;
\r
6080 FLAG_C = CFLAG_CLEAR;
\r
6084 M68KMAKE_OP(move, 8, al, .)
\r
6086 uint res = M68KMAKE_GET_OPER_AY_8;
\r
6087 uint ea = EA_AL_8();
\r
6089 m68ki_write_8(ea, res);
\r
6091 FLAG_N = NFLAG_8(res);
\r
6093 FLAG_V = VFLAG_CLEAR;
\r
6094 FLAG_C = CFLAG_CLEAR;
\r
6098 M68KMAKE_OP(move, 16, d, d)
\r
6100 uint res = MASK_OUT_ABOVE_16(DY);
\r
6101 uint* r_dst = &DX;
\r
6103 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
6105 FLAG_N = NFLAG_16(res);
\r
6107 FLAG_V = VFLAG_CLEAR;
\r
6108 FLAG_C = CFLAG_CLEAR;
\r
6112 M68KMAKE_OP(move, 16, d, a)
\r
6114 uint res = MASK_OUT_ABOVE_16(AY);
\r
6115 uint* r_dst = &DX;
\r
6117 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
6119 FLAG_N = NFLAG_16(res);
\r
6121 FLAG_V = VFLAG_CLEAR;
\r
6122 FLAG_C = CFLAG_CLEAR;
\r
6126 M68KMAKE_OP(move, 16, d, .)
\r
6128 uint res = M68KMAKE_GET_OPER_AY_16;
\r
6129 uint* r_dst = &DX;
\r
6131 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
6133 FLAG_N = NFLAG_16(res);
\r
6135 FLAG_V = VFLAG_CLEAR;
\r
6136 FLAG_C = CFLAG_CLEAR;
\r
6140 M68KMAKE_OP(move, 16, ai, d)
\r
6142 uint res = MASK_OUT_ABOVE_16(DY);
\r
6143 uint ea = EA_AX_AI_16();
\r
6145 m68ki_write_16(ea, res);
\r
6147 FLAG_N = NFLAG_16(res);
\r
6149 FLAG_V = VFLAG_CLEAR;
\r
6150 FLAG_C = CFLAG_CLEAR;
\r
6154 M68KMAKE_OP(move, 16, ai, a)
\r
6156 uint res = MASK_OUT_ABOVE_16(AY);
\r
6157 uint ea = EA_AX_AI_16();
\r
6159 m68ki_write_16(ea, res);
\r
6161 FLAG_N = NFLAG_16(res);
\r
6163 FLAG_V = VFLAG_CLEAR;
\r
6164 FLAG_C = CFLAG_CLEAR;
\r
6168 M68KMAKE_OP(move, 16, ai, .)
\r
6170 uint res = M68KMAKE_GET_OPER_AY_16;
\r
6171 uint ea = EA_AX_AI_16();
\r
6173 m68ki_write_16(ea, res);
\r
6175 FLAG_N = NFLAG_16(res);
\r
6177 FLAG_V = VFLAG_CLEAR;
\r
6178 FLAG_C = CFLAG_CLEAR;
\r
6182 M68KMAKE_OP(move, 16, pi, d)
\r
6184 uint res = MASK_OUT_ABOVE_16(DY);
\r
6185 uint ea = EA_AX_PI_16();
\r
6187 m68ki_write_16(ea, res);
\r
6189 FLAG_N = NFLAG_16(res);
\r
6191 FLAG_V = VFLAG_CLEAR;
\r
6192 FLAG_C = CFLAG_CLEAR;
\r
6196 M68KMAKE_OP(move, 16, pi, a)
\r
6198 uint res = MASK_OUT_ABOVE_16(AY);
\r
6199 uint ea = EA_AX_PI_16();
\r
6201 m68ki_write_16(ea, res);
\r
6203 FLAG_N = NFLAG_16(res);
\r
6205 FLAG_V = VFLAG_CLEAR;
\r
6206 FLAG_C = CFLAG_CLEAR;
\r
6210 M68KMAKE_OP(move, 16, pi, .)
\r
6212 uint res = M68KMAKE_GET_OPER_AY_16;
\r
6213 uint ea = EA_AX_PI_16();
\r
6215 m68ki_write_16(ea, res);
\r
6217 FLAG_N = NFLAG_16(res);
\r
6219 FLAG_V = VFLAG_CLEAR;
\r
6220 FLAG_C = CFLAG_CLEAR;
\r
6224 M68KMAKE_OP(move, 16, pd, d)
\r
6226 uint res = MASK_OUT_ABOVE_16(DY);
\r
6227 uint ea = EA_AX_PD_16();
\r
6229 m68ki_write_16(ea, res);
\r
6231 FLAG_N = NFLAG_16(res);
\r
6233 FLAG_V = VFLAG_CLEAR;
\r
6234 FLAG_C = CFLAG_CLEAR;
\r
6238 M68KMAKE_OP(move, 16, pd, a)
\r
6240 uint res = MASK_OUT_ABOVE_16(AY);
\r
6241 uint ea = EA_AX_PD_16();
\r
6243 m68ki_write_16(ea, res);
\r
6245 FLAG_N = NFLAG_16(res);
\r
6247 FLAG_V = VFLAG_CLEAR;
\r
6248 FLAG_C = CFLAG_CLEAR;
\r
6252 M68KMAKE_OP(move, 16, pd, .)
\r
6254 uint res = M68KMAKE_GET_OPER_AY_16;
\r
6255 uint ea = EA_AX_PD_16();
\r
6257 m68ki_write_16(ea, res);
\r
6259 FLAG_N = NFLAG_16(res);
\r
6261 FLAG_V = VFLAG_CLEAR;
\r
6262 FLAG_C = CFLAG_CLEAR;
\r
6266 M68KMAKE_OP(move, 16, di, d)
\r
6268 uint res = MASK_OUT_ABOVE_16(DY);
\r
6269 uint ea = EA_AX_DI_16();
\r
6271 m68ki_write_16(ea, res);
\r
6273 FLAG_N = NFLAG_16(res);
\r
6275 FLAG_V = VFLAG_CLEAR;
\r
6276 FLAG_C = CFLAG_CLEAR;
\r
6280 M68KMAKE_OP(move, 16, di, a)
\r
6282 uint res = MASK_OUT_ABOVE_16(AY);
\r
6283 uint ea = EA_AX_DI_16();
\r
6285 m68ki_write_16(ea, res);
\r
6287 FLAG_N = NFLAG_16(res);
\r
6289 FLAG_V = VFLAG_CLEAR;
\r
6290 FLAG_C = CFLAG_CLEAR;
\r
6294 M68KMAKE_OP(move, 16, di, .)
\r
6296 uint res = M68KMAKE_GET_OPER_AY_16;
\r
6297 uint ea = EA_AX_DI_16();
\r
6299 m68ki_write_16(ea, res);
\r
6301 FLAG_N = NFLAG_16(res);
\r
6303 FLAG_V = VFLAG_CLEAR;
\r
6304 FLAG_C = CFLAG_CLEAR;
\r
6308 M68KMAKE_OP(move, 16, ix, d)
\r
6310 uint res = MASK_OUT_ABOVE_16(DY);
\r
6311 uint ea = EA_AX_IX_16();
\r
6313 m68ki_write_16(ea, res);
\r
6315 FLAG_N = NFLAG_16(res);
\r
6317 FLAG_V = VFLAG_CLEAR;
\r
6318 FLAG_C = CFLAG_CLEAR;
\r
6322 M68KMAKE_OP(move, 16, ix, a)
\r
6324 uint res = MASK_OUT_ABOVE_16(AY);
\r
6325 uint ea = EA_AX_IX_16();
\r
6327 m68ki_write_16(ea, res);
\r
6329 FLAG_N = NFLAG_16(res);
\r
6331 FLAG_V = VFLAG_CLEAR;
\r
6332 FLAG_C = CFLAG_CLEAR;
\r
6336 M68KMAKE_OP(move, 16, ix, .)
\r
6338 uint res = M68KMAKE_GET_OPER_AY_16;
\r
6339 uint ea = EA_AX_IX_16();
\r
6341 m68ki_write_16(ea, res);
\r
6343 FLAG_N = NFLAG_16(res);
\r
6345 FLAG_V = VFLAG_CLEAR;
\r
6346 FLAG_C = CFLAG_CLEAR;
\r
6350 M68KMAKE_OP(move, 16, aw, d)
\r
6352 uint res = MASK_OUT_ABOVE_16(DY);
\r
6353 uint ea = EA_AW_16();
\r
6355 m68ki_write_16(ea, res);
\r
6357 FLAG_N = NFLAG_16(res);
\r
6359 FLAG_V = VFLAG_CLEAR;
\r
6360 FLAG_C = CFLAG_CLEAR;
\r
6364 M68KMAKE_OP(move, 16, aw, a)
\r
6366 uint res = MASK_OUT_ABOVE_16(AY);
\r
6367 uint ea = EA_AW_16();
\r
6369 m68ki_write_16(ea, res);
\r
6371 FLAG_N = NFLAG_16(res);
\r
6373 FLAG_V = VFLAG_CLEAR;
\r
6374 FLAG_C = CFLAG_CLEAR;
\r
6378 M68KMAKE_OP(move, 16, aw, .)
\r
6380 uint res = M68KMAKE_GET_OPER_AY_16;
\r
6381 uint ea = EA_AW_16();
\r
6383 m68ki_write_16(ea, res);
\r
6385 FLAG_N = NFLAG_16(res);
\r
6387 FLAG_V = VFLAG_CLEAR;
\r
6388 FLAG_C = CFLAG_CLEAR;
\r
6392 M68KMAKE_OP(move, 16, al, d)
\r
6394 uint res = MASK_OUT_ABOVE_16(DY);
\r
6395 uint ea = EA_AL_16();
\r
6397 m68ki_write_16(ea, res);
\r
6399 FLAG_N = NFLAG_16(res);
\r
6401 FLAG_V = VFLAG_CLEAR;
\r
6402 FLAG_C = CFLAG_CLEAR;
\r
6406 M68KMAKE_OP(move, 16, al, a)
\r
6408 uint res = MASK_OUT_ABOVE_16(AY);
\r
6409 uint ea = EA_AL_16();
\r
6411 m68ki_write_16(ea, res);
\r
6413 FLAG_N = NFLAG_16(res);
\r
6415 FLAG_V = VFLAG_CLEAR;
\r
6416 FLAG_C = CFLAG_CLEAR;
\r
6420 M68KMAKE_OP(move, 16, al, .)
\r
6422 uint res = M68KMAKE_GET_OPER_AY_16;
\r
6423 uint ea = EA_AL_16();
\r
6425 m68ki_write_16(ea, res);
\r
6427 FLAG_N = NFLAG_16(res);
\r
6429 FLAG_V = VFLAG_CLEAR;
\r
6430 FLAG_C = CFLAG_CLEAR;
\r
6434 M68KMAKE_OP(move, 32, d, d)
\r
6437 uint* r_dst = &DX;
\r
6441 FLAG_N = NFLAG_32(res);
\r
6443 FLAG_V = VFLAG_CLEAR;
\r
6444 FLAG_C = CFLAG_CLEAR;
\r
6448 M68KMAKE_OP(move, 32, d, a)
\r
6451 uint* r_dst = &DX;
\r
6455 FLAG_N = NFLAG_32(res);
\r
6457 FLAG_V = VFLAG_CLEAR;
\r
6458 FLAG_C = CFLAG_CLEAR;
\r
6462 M68KMAKE_OP(move, 32, d, .)
\r
6464 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6465 uint* r_dst = &DX;
\r
6469 FLAG_N = NFLAG_32(res);
\r
6471 FLAG_V = VFLAG_CLEAR;
\r
6472 FLAG_C = CFLAG_CLEAR;
\r
6476 M68KMAKE_OP(move, 32, ai, d)
\r
6479 uint ea = EA_AX_AI_32();
\r
6481 m68ki_write_32(ea, res);
\r
6483 FLAG_N = NFLAG_32(res);
\r
6485 FLAG_V = VFLAG_CLEAR;
\r
6486 FLAG_C = CFLAG_CLEAR;
\r
6490 M68KMAKE_OP(move, 32, ai, a)
\r
6493 uint ea = EA_AX_AI_32();
\r
6495 m68ki_write_32(ea, res);
\r
6497 FLAG_N = NFLAG_32(res);
\r
6499 FLAG_V = VFLAG_CLEAR;
\r
6500 FLAG_C = CFLAG_CLEAR;
\r
6504 M68KMAKE_OP(move, 32, ai, .)
\r
6506 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6507 uint ea = EA_AX_AI_32();
\r
6509 m68ki_write_32(ea, res);
\r
6511 FLAG_N = NFLAG_32(res);
\r
6513 FLAG_V = VFLAG_CLEAR;
\r
6514 FLAG_C = CFLAG_CLEAR;
\r
6518 M68KMAKE_OP(move, 32, pi, d)
\r
6521 uint ea = EA_AX_PI_32();
\r
6523 m68ki_write_32(ea, res);
\r
6525 FLAG_N = NFLAG_32(res);
\r
6527 FLAG_V = VFLAG_CLEAR;
\r
6528 FLAG_C = CFLAG_CLEAR;
\r
6532 M68KMAKE_OP(move, 32, pi, a)
\r
6535 uint ea = EA_AX_PI_32();
\r
6537 m68ki_write_32(ea, res);
\r
6539 FLAG_N = NFLAG_32(res);
\r
6541 FLAG_V = VFLAG_CLEAR;
\r
6542 FLAG_C = CFLAG_CLEAR;
\r
6546 M68KMAKE_OP(move, 32, pi, .)
\r
6548 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6549 uint ea = EA_AX_PI_32();
\r
6551 m68ki_write_32(ea, res);
\r
6553 FLAG_N = NFLAG_32(res);
\r
6555 FLAG_V = VFLAG_CLEAR;
\r
6556 FLAG_C = CFLAG_CLEAR;
\r
6560 M68KMAKE_OP(move, 32, pd, d)
\r
6563 uint ea = EA_AX_PD_32();
\r
6565 m68ki_write_16(ea+2, res & 0xFFFF );
\r
6566 m68ki_write_16(ea, (res >> 16) & 0xFFFF );
\r
6568 FLAG_N = NFLAG_32(res);
\r
6570 FLAG_V = VFLAG_CLEAR;
\r
6571 FLAG_C = CFLAG_CLEAR;
\r
6575 M68KMAKE_OP(move, 32, pd, a)
\r
6578 uint ea = EA_AX_PD_32();
\r
6580 m68ki_write_16(ea+2, res & 0xFFFF );
\r
6581 m68ki_write_16(ea, (res >> 16) & 0xFFFF );
\r
6583 FLAG_N = NFLAG_32(res);
\r
6585 FLAG_V = VFLAG_CLEAR;
\r
6586 FLAG_C = CFLAG_CLEAR;
\r
6590 M68KMAKE_OP(move, 32, pd, .)
\r
6592 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6593 uint ea = EA_AX_PD_32();
\r
6595 m68ki_write_16(ea+2, res & 0xFFFF );
\r
6596 m68ki_write_16(ea, (res >> 16) & 0xFFFF );
\r
6598 FLAG_N = NFLAG_32(res);
\r
6600 FLAG_V = VFLAG_CLEAR;
\r
6601 FLAG_C = CFLAG_CLEAR;
\r
6605 M68KMAKE_OP(move, 32, di, d)
\r
6608 uint ea = EA_AX_DI_32();
\r
6610 m68ki_write_32(ea, res);
\r
6612 FLAG_N = NFLAG_32(res);
\r
6614 FLAG_V = VFLAG_CLEAR;
\r
6615 FLAG_C = CFLAG_CLEAR;
\r
6619 M68KMAKE_OP(move, 32, di, a)
\r
6622 uint ea = EA_AX_DI_32();
\r
6624 m68ki_write_32(ea, res);
\r
6626 FLAG_N = NFLAG_32(res);
\r
6628 FLAG_V = VFLAG_CLEAR;
\r
6629 FLAG_C = CFLAG_CLEAR;
\r
6633 M68KMAKE_OP(move, 32, di, .)
\r
6635 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6636 uint ea = EA_AX_DI_32();
\r
6638 m68ki_write_32(ea, res);
\r
6640 FLAG_N = NFLAG_32(res);
\r
6642 FLAG_V = VFLAG_CLEAR;
\r
6643 FLAG_C = CFLAG_CLEAR;
\r
6647 M68KMAKE_OP(move, 32, ix, d)
\r
6650 uint ea = EA_AX_IX_32();
\r
6652 m68ki_write_32(ea, res);
\r
6654 FLAG_N = NFLAG_32(res);
\r
6656 FLAG_V = VFLAG_CLEAR;
\r
6657 FLAG_C = CFLAG_CLEAR;
\r
6661 M68KMAKE_OP(move, 32, ix, a)
\r
6664 uint ea = EA_AX_IX_32();
\r
6666 m68ki_write_32(ea, res);
\r
6668 FLAG_N = NFLAG_32(res);
\r
6670 FLAG_V = VFLAG_CLEAR;
\r
6671 FLAG_C = CFLAG_CLEAR;
\r
6675 M68KMAKE_OP(move, 32, ix, .)
\r
6677 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6678 uint ea = EA_AX_IX_32();
\r
6680 m68ki_write_32(ea, res);
\r
6682 FLAG_N = NFLAG_32(res);
\r
6684 FLAG_V = VFLAG_CLEAR;
\r
6685 FLAG_C = CFLAG_CLEAR;
\r
6689 M68KMAKE_OP(move, 32, aw, d)
\r
6692 uint ea = EA_AW_32();
\r
6694 m68ki_write_32(ea, res);
\r
6696 FLAG_N = NFLAG_32(res);
\r
6698 FLAG_V = VFLAG_CLEAR;
\r
6699 FLAG_C = CFLAG_CLEAR;
\r
6703 M68KMAKE_OP(move, 32, aw, a)
\r
6706 uint ea = EA_AW_32();
\r
6708 m68ki_write_32(ea, res);
\r
6710 FLAG_N = NFLAG_32(res);
\r
6712 FLAG_V = VFLAG_CLEAR;
\r
6713 FLAG_C = CFLAG_CLEAR;
\r
6717 M68KMAKE_OP(move, 32, aw, .)
\r
6719 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6720 uint ea = EA_AW_32();
\r
6722 m68ki_write_32(ea, res);
\r
6724 FLAG_N = NFLAG_32(res);
\r
6726 FLAG_V = VFLAG_CLEAR;
\r
6727 FLAG_C = CFLAG_CLEAR;
\r
6731 M68KMAKE_OP(move, 32, al, d)
\r
6734 uint ea = EA_AL_32();
\r
6736 m68ki_write_32(ea, res);
\r
6738 FLAG_N = NFLAG_32(res);
\r
6740 FLAG_V = VFLAG_CLEAR;
\r
6741 FLAG_C = CFLAG_CLEAR;
\r
6745 M68KMAKE_OP(move, 32, al, a)
\r
6748 uint ea = EA_AL_32();
\r
6750 m68ki_write_32(ea, res);
\r
6752 FLAG_N = NFLAG_32(res);
\r
6754 FLAG_V = VFLAG_CLEAR;
\r
6755 FLAG_C = CFLAG_CLEAR;
\r
6759 M68KMAKE_OP(move, 32, al, .)
\r
6761 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6762 uint ea = EA_AL_32();
\r
6764 m68ki_write_32(ea, res);
\r
6766 FLAG_N = NFLAG_32(res);
\r
6768 FLAG_V = VFLAG_CLEAR;
\r
6769 FLAG_C = CFLAG_CLEAR;
\r
6773 M68KMAKE_OP(movea, 16, ., d)
\r
6775 AX = MAKE_INT_16(DY);
\r
6779 M68KMAKE_OP(movea, 16, ., a)
\r
6781 AX = MAKE_INT_16(AY);
\r
6785 M68KMAKE_OP(movea, 16, ., .)
\r
6787 AX = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
\r
6791 M68KMAKE_OP(movea, 32, ., d)
\r
6797 M68KMAKE_OP(movea, 32, ., a)
\r
6803 M68KMAKE_OP(movea, 32, ., .)
\r
6805 AX = M68KMAKE_GET_OPER_AY_32;
\r
6809 M68KMAKE_OP(move, 16, frc, d)
\r
6811 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
6813 DY = MASK_OUT_BELOW_16(DY) | m68ki_get_ccr();
\r
6816 m68ki_exception_illegal();
\r
6820 M68KMAKE_OP(move, 16, frc, .)
\r
6822 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
6824 m68ki_write_16(M68KMAKE_GET_EA_AY_16, m68ki_get_ccr());
\r
6827 m68ki_exception_illegal();
\r
6831 M68KMAKE_OP(move, 16, toc, d)
\r
6833 m68ki_set_ccr(DY);
\r
6837 M68KMAKE_OP(move, 16, toc, .)
\r
6839 m68ki_set_ccr(M68KMAKE_GET_OPER_AY_16);
\r
6843 M68KMAKE_OP(move, 16, frs, d)
\r
6845 if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */
\r
6847 DY = MASK_OUT_BELOW_16(DY) | m68ki_get_sr();
\r
6850 m68ki_exception_privilege_violation();
\r
6854 M68KMAKE_OP(move, 16, frs, .)
\r
6856 if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */
\r
6858 uint ea = M68KMAKE_GET_EA_AY_16;
\r
6859 m68ki_write_16(ea, m68ki_get_sr());
\r
6862 m68ki_exception_privilege_violation();
\r
6866 M68KMAKE_OP(move, 16, tos, d)
\r
6873 m68ki_exception_privilege_violation();
\r
6877 M68KMAKE_OP(move, 16, tos, .)
\r
6881 uint new_sr = M68KMAKE_GET_OPER_AY_16;
\r
6882 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
6883 m68ki_set_sr(new_sr);
\r
6886 m68ki_exception_privilege_violation();
\r
6890 M68KMAKE_OP(move, 32, fru, .)
\r
6897 m68ki_exception_privilege_violation();
\r
6901 M68KMAKE_OP(move, 32, tou, .)
\r
6905 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
6909 m68ki_exception_privilege_violation();
\r
6913 M68KMAKE_OP(movec, 32, cr, .)
\r
6915 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
6919 uint word2 = OPER_I_16();
\r
6921 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
6922 switch (word2 & 0xfff)
\r
6924 case 0x000: /* SFC */
\r
6925 REG_DA[(word2 >> 12) & 15] = REG_SFC;
\r
6927 case 0x001: /* DFC */
\r
6928 REG_DA[(word2 >> 12) & 15] = REG_DFC;
\r
6930 case 0x002: /* CACR */
\r
6931 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6933 REG_DA[(word2 >> 12) & 15] = REG_CACR;
\r
6937 case 0x800: /* USP */
\r
6938 REG_DA[(word2 >> 12) & 15] = REG_USP;
\r
6940 case 0x801: /* VBR */
\r
6941 REG_DA[(word2 >> 12) & 15] = REG_VBR;
\r
6943 case 0x802: /* CAAR */
\r
6944 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6946 REG_DA[(word2 >> 12) & 15] = REG_CAAR;
\r
6949 m68ki_exception_illegal();
\r
6951 case 0x803: /* MSP */
\r
6952 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6954 REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_SP : REG_MSP;
\r
6957 m68ki_exception_illegal();
\r
6959 case 0x804: /* ISP */
\r
6960 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6962 REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_ISP : REG_SP;
\r
6965 m68ki_exception_illegal();
\r
6967 case 0x003: /* TC */
\r
6968 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6973 m68ki_exception_illegal();
\r
6975 case 0x004: /* ITT0 */
\r
6976 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6981 m68ki_exception_illegal();
\r
6983 case 0x005: /* ITT1 */
\r
6984 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6989 m68ki_exception_illegal();
\r
6991 case 0x006: /* DTT0 */
\r
6992 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6997 m68ki_exception_illegal();
\r
6999 case 0x007: /* DTT1 */
\r
7000 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7005 m68ki_exception_illegal();
\r
7007 case 0x805: /* MMUSR */
\r
7008 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7013 m68ki_exception_illegal();
\r
7015 case 0x806: /* URP */
\r
7016 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7021 m68ki_exception_illegal();
\r
7023 case 0x807: /* SRP */
\r
7024 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7029 m68ki_exception_illegal();
\r
7032 m68ki_exception_illegal();
\r
7036 m68ki_exception_privilege_violation();
\r
7039 m68ki_exception_illegal();
\r
7043 M68KMAKE_OP(movec, 32, rc, .)
\r
7045 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
7049 uint word2 = OPER_I_16();
\r
7051 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
7052 switch (word2 & 0xfff)
\r
7054 case 0x000: /* SFC */
\r
7055 REG_SFC = REG_DA[(word2 >> 12) & 15] & 7;
\r
7057 case 0x001: /* DFC */
\r
7058 REG_DFC = REG_DA[(word2 >> 12) & 15] & 7;
\r
7060 case 0x002: /* CACR */
\r
7061 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
7063 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7065 REG_CACR = REG_DA[(word2 >> 12) & 15];
\r
7069 /* non 68040 can only set the lower 4 bits (C,CE,F,E) */
\r
7070 REG_CACR = REG_DA[(word2 >> 12) & 15] & 0x0f;
\r
7074 m68ki_exception_illegal();
\r
7076 case 0x800: /* USP */
\r
7077 REG_USP = REG_DA[(word2 >> 12) & 15];
\r
7079 case 0x801: /* VBR */
\r
7080 REG_VBR = REG_DA[(word2 >> 12) & 15];
\r
7082 case 0x802: /* CAAR */
\r
7083 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
7085 REG_CAAR = REG_DA[(word2 >> 12) & 15];
\r
7088 m68ki_exception_illegal();
\r
7090 case 0x803: /* MSP */
\r
7091 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
7093 /* we are in supervisor mode so just check for M flag */
\r
7096 REG_MSP = REG_DA[(word2 >> 12) & 15];
\r
7099 REG_SP = REG_DA[(word2 >> 12) & 15];
\r
7102 m68ki_exception_illegal();
\r
7104 case 0x804: /* ISP */
\r
7105 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
7109 REG_SP = REG_DA[(word2 >> 12) & 15];
\r
7112 REG_ISP = REG_DA[(word2 >> 12) & 15];
\r
7115 m68ki_exception_illegal();
\r
7117 case 0x003: /* TC */
\r
7118 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7123 m68ki_exception_illegal();
\r
7125 case 0x004: /* ITT0 */
\r
7126 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7131 m68ki_exception_illegal();
\r
7133 case 0x005: /* ITT1 */
\r
7134 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7139 m68ki_exception_illegal();
\r
7141 case 0x006: /* DTT0 */
\r
7142 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7147 m68ki_exception_illegal();
\r
7149 case 0x007: /* DTT1 */
\r
7150 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7155 m68ki_exception_illegal();
\r
7157 case 0x805: /* MMUSR */
\r
7158 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7163 m68ki_exception_illegal();
\r
7165 case 0x806: /* URP */
\r
7166 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7171 m68ki_exception_illegal();
\r
7173 case 0x807: /* SRP */
\r
7174 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7179 m68ki_exception_illegal();
\r
7182 m68ki_exception_illegal();
\r
7186 m68ki_exception_privilege_violation();
\r
7189 m68ki_exception_illegal();
\r
7193 M68KMAKE_OP(movem, 16, re, pd)
\r
7196 uint register_list = OPER_I_16();
\r
7200 for(; i < 16; i++)
\r
7201 if(register_list & (1 << i))
\r
7204 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[15-i]));
\r
7209 USE_CYCLES(count<<CYC_MOVEM_W);
\r
7213 M68KMAKE_OP(movem, 16, re, .)
\r
7216 uint register_list = OPER_I_16();
\r
7217 uint ea = M68KMAKE_GET_EA_AY_16;
\r
7220 for(; i < 16; i++)
\r
7221 if(register_list & (1 << i))
\r
7223 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));
\r
7228 USE_CYCLES(count<<CYC_MOVEM_W);
\r
7232 M68KMAKE_OP(movem, 32, re, pd)
\r
7235 uint register_list = OPER_I_16();
\r
7239 for(; i < 16; i++)
\r
7240 if(register_list & (1 << i))
\r
7244 m68ki_write_32(ea, REG_DA[15-i] ); // notaz Cyclone hack
\r
7246 m68ki_write_16(ea+2, REG_DA[15-i] & 0xFFFF );
\r
7247 m68ki_write_16(ea, (REG_DA[15-i] >> 16) & 0xFFFF );
\r
7253 USE_CYCLES(count<<CYC_MOVEM_L);
\r
7257 M68KMAKE_OP(movem, 32, re, .)
\r
7260 uint register_list = OPER_I_16();
\r
7261 uint ea = M68KMAKE_GET_EA_AY_32;
\r
7264 for(; i < 16; i++)
\r
7265 if(register_list & (1 << i))
\r
7267 m68ki_write_32(ea, REG_DA[i]);
\r
7272 USE_CYCLES(count<<CYC_MOVEM_L);
\r
7276 M68KMAKE_OP(movem, 16, er, pi)
\r
7279 uint register_list = OPER_I_16();
\r
7283 for(; i < 16; i++)
\r
7284 if(register_list & (1 << i))
\r
7286 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
\r
7292 USE_CYCLES(count<<CYC_MOVEM_W);
\r
7296 M68KMAKE_OP(movem, 16, er, pcdi)
\r
7299 uint register_list = OPER_I_16();
\r
7300 uint ea = EA_PCDI_16();
\r
7303 for(; i < 16; i++)
\r
7304 if(register_list & (1 << i))
\r
7306 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));
\r
7311 USE_CYCLES(count<<CYC_MOVEM_W);
\r
7315 M68KMAKE_OP(movem, 16, er, pcix)
\r
7318 uint register_list = OPER_I_16();
\r
7319 uint ea = EA_PCIX_16();
\r
7322 for(; i < 16; i++)
\r
7323 if(register_list & (1 << i))
\r
7325 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));
\r
7330 USE_CYCLES(count<<CYC_MOVEM_W);
\r
7334 M68KMAKE_OP(movem, 16, er, .)
\r
7337 uint register_list = OPER_I_16();
\r
7338 uint ea = M68KMAKE_GET_EA_AY_16;
\r
7341 for(; i < 16; i++)
\r
7342 if(register_list & (1 << i))
\r
7344 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
\r
7349 USE_CYCLES(count<<CYC_MOVEM_W);
\r
7353 M68KMAKE_OP(movem, 32, er, pi)
\r
7356 uint register_list = OPER_I_16();
\r
7360 for(; i < 16; i++)
\r
7361 if(register_list & (1 << i))
\r
7363 REG_DA[i] = m68ki_read_32(ea);
\r
7369 USE_CYCLES(count<<CYC_MOVEM_L);
\r
7373 M68KMAKE_OP(movem, 32, er, pcdi)
\r
7376 uint register_list = OPER_I_16();
\r
7377 uint ea = EA_PCDI_32();
\r
7380 for(; i < 16; i++)
\r
7381 if(register_list & (1 << i))
\r
7383 REG_DA[i] = m68ki_read_pcrel_32(ea);
\r
7388 USE_CYCLES(count<<CYC_MOVEM_L);
\r
7392 M68KMAKE_OP(movem, 32, er, pcix)
\r
7395 uint register_list = OPER_I_16();
\r
7396 uint ea = EA_PCIX_32();
\r
7399 for(; i < 16; i++)
\r
7400 if(register_list & (1 << i))
\r
7402 REG_DA[i] = m68ki_read_pcrel_32(ea);
\r
7407 USE_CYCLES(count<<CYC_MOVEM_L);
\r
7411 M68KMAKE_OP(movem, 32, er, .)
\r
7414 uint register_list = OPER_I_16();
\r
7415 uint ea = M68KMAKE_GET_EA_AY_32;
\r
7418 for(; i < 16; i++)
\r
7419 if(register_list & (1 << i))
\r
7421 REG_DA[i] = m68ki_read_32(ea);
\r
7426 USE_CYCLES(count<<CYC_MOVEM_L);
\r
7430 M68KMAKE_OP(movep, 16, re, .)
\r
7432 uint ea = EA_AY_DI_16();
\r
7435 m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 8));
\r
7436 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));
\r
7440 M68KMAKE_OP(movep, 32, re, .)
\r
7442 uint ea = EA_AY_DI_32();
\r
7445 m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 24));
\r
7446 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 16));
\r
7447 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 8));
\r
7448 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));
\r
7452 M68KMAKE_OP(movep, 16, er, .)
\r
7454 uint ea = EA_AY_DI_16();
\r
7455 uint* r_dst = &DX;
\r
7457 *r_dst = MASK_OUT_BELOW_16(*r_dst) | ((m68ki_read_8(ea) << 8) + m68ki_read_8(ea + 2));
\r
7461 M68KMAKE_OP(movep, 32, er, .)
\r
7463 uint ea = EA_AY_DI_32();
\r
7465 DX = (m68ki_read_8(ea) << 24) + (m68ki_read_8(ea + 2) << 16)
\r
7466 + (m68ki_read_8(ea + 4) << 8) + m68ki_read_8(ea + 6);
\r
7470 M68KMAKE_OP(moves, 8, ., .)
\r
7472 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
7476 uint word2 = OPER_I_16();
\r
7477 uint ea = M68KMAKE_GET_EA_AY_8;
\r
7479 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
7480 if(BIT_B(word2)) /* Register to memory */
\r
7482 m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));
\r
7485 if(BIT_F(word2)) /* Memory to address register */
\r
7487 REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC));
\r
7488 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
7492 /* Memory to data register */
\r
7493 REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC);
\r
7494 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
7498 m68ki_exception_privilege_violation();
\r
7501 m68ki_exception_illegal();
\r
7505 M68KMAKE_OP(moves, 16, ., .)
\r
7507 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
7511 uint word2 = OPER_I_16();
\r
7512 uint ea = M68KMAKE_GET_EA_AY_16;
\r
7514 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
7515 if(BIT_B(word2)) /* Register to memory */
\r
7517 m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15]));
\r
7520 if(BIT_F(word2)) /* Memory to address register */
\r
7522 REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC));
\r
7523 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
7527 /* Memory to data register */
\r
7528 REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC);
\r
7529 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
7533 m68ki_exception_privilege_violation();
\r
7536 m68ki_exception_illegal();
\r
7540 M68KMAKE_OP(moves, 32, ., .)
\r
7542 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
7546 uint word2 = OPER_I_16();
\r
7547 uint ea = M68KMAKE_GET_EA_AY_32;
\r
7549 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
7550 if(BIT_B(word2)) /* Register to memory */
\r
7552 m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]);
\r
7553 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
7557 /* Memory to register */
\r
7558 REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC);
\r
7559 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
7563 m68ki_exception_privilege_violation();
\r
7566 m68ki_exception_illegal();
\r
7570 M68KMAKE_OP(moveq, 32, ., .)
\r
7572 uint res = DX = MAKE_INT_8(MASK_OUT_ABOVE_8(REG_IR));
\r
7574 FLAG_N = NFLAG_32(res);
\r
7576 FLAG_V = VFLAG_CLEAR;
\r
7577 FLAG_C = CFLAG_CLEAR;
\r
7581 M68KMAKE_OP(move16, 32, ., .)
\r
7583 UINT16 w2 = OPER_I_16();
\r
7584 int ax = REG_IR & 7;
\r
7585 int ay = (w2 >> 12) & 7;
\r
7587 m68ki_write_32(REG_A[ay], m68ki_read_32(REG_A[ax]));
\r
7588 m68ki_write_32(REG_A[ay]+4, m68ki_read_32(REG_A[ax]+4));
\r
7589 m68ki_write_32(REG_A[ay]+8, m68ki_read_32(REG_A[ax]+8));
\r
7590 m68ki_write_32(REG_A[ay]+12, m68ki_read_32(REG_A[ax]+12));
\r
7597 M68KMAKE_OP(muls, 16, ., d)
\r
7599 uint* r_dst = &DX;
\r
7600 uint x = MAKE_INT_16(DY);
\r
7601 uint res = MASK_OUT_ABOVE_32(x * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
\r
7604 USE_CYCLES(m68ki_muls_cycles(x));
\r
7607 FLAG_N = NFLAG_32(res);
\r
7608 FLAG_V = VFLAG_CLEAR;
\r
7609 FLAG_C = CFLAG_CLEAR;
\r
7613 M68KMAKE_OP(muls, 16, ., .)
\r
7615 uint* r_dst = &DX;
\r
7616 uint x = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
\r
7617 uint res = MASK_OUT_ABOVE_32(x * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
\r
7620 USE_CYCLES(m68ki_muls_cycles(x));
\r
7623 FLAG_N = NFLAG_32(res);
\r
7624 FLAG_V = VFLAG_CLEAR;
\r
7625 FLAG_C = CFLAG_CLEAR;
\r
7629 M68KMAKE_OP(mulu, 16, ., d)
\r
7631 uint* r_dst = &DX;
\r
7632 uint x = MASK_OUT_ABOVE_16(DY);
\r
7633 uint res = x * MASK_OUT_ABOVE_16(*r_dst);
\r
7636 USE_CYCLES(m68ki_mulu_cycles(x));
\r
7639 FLAG_N = NFLAG_32(res);
\r
7640 FLAG_V = VFLAG_CLEAR;
\r
7641 FLAG_C = CFLAG_CLEAR;
\r
7645 M68KMAKE_OP(mulu, 16, ., .)
\r
7647 uint* r_dst = &DX;
\r
7648 uint x = M68KMAKE_GET_OPER_AY_16;
\r
7649 uint res = x * MASK_OUT_ABOVE_16(*r_dst);
\r
7652 USE_CYCLES(m68ki_mulu_cycles(x));
\r
7655 FLAG_N = NFLAG_32(res);
\r
7656 FLAG_V = VFLAG_CLEAR;
\r
7657 FLAG_C = CFLAG_CLEAR;
\r
7661 M68KMAKE_OP(mull, 32, ., d)
\r
7663 #if M68K_USE_64_BIT
\r
7665 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
7667 uint word2 = OPER_I_16();
\r
7669 uint64 dst = REG_D[(word2 >> 12) & 7];
\r
7672 FLAG_C = CFLAG_CLEAR;
\r
7674 if(BIT_B(word2)) /* signed */
\r
7676 res = (sint64)((sint32)src) * (sint64)((sint32)dst);
\r
7679 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
7680 FLAG_N = NFLAG_32(res);
\r
7681 FLAG_V = ((sint64)res != (sint32)res)<<7;
\r
7682 REG_D[(word2 >> 12) & 7] = FLAG_Z;
\r
7685 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
\r
7686 FLAG_N = NFLAG_64(res);
\r
7687 FLAG_V = VFLAG_CLEAR;
\r
7688 REG_D[word2 & 7] = (res >> 32);
\r
7689 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
\r
7696 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
7697 FLAG_N = NFLAG_32(res);
\r
7698 FLAG_V = (res > 0xffffffff)<<7;
\r
7699 REG_D[(word2 >> 12) & 7] = FLAG_Z;
\r
7702 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
\r
7703 FLAG_N = NFLAG_64(res);
\r
7704 FLAG_V = VFLAG_CLEAR;
\r
7705 REG_D[word2 & 7] = (res >> 32);
\r
7706 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
\r
7709 m68ki_exception_illegal();
\r
7713 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
7715 uint word2 = OPER_I_16();
\r
7717 uint dst = REG_D[(word2 >> 12) & 7];
\r
7718 uint neg = GET_MSB_32(src ^ dst);
\r
7730 FLAG_C = CFLAG_CLEAR;
\r
7732 if(BIT_B(word2)) /* signed */
\r
7734 if(GET_MSB_32(src))
\r
7735 src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
\r
7736 if(GET_MSB_32(dst))
\r
7737 dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
\r
7740 src1 = MASK_OUT_ABOVE_16(src);
\r
7742 dst1 = MASK_OUT_ABOVE_16(dst);
\r
7751 lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
\r
7752 hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
\r
7754 if(BIT_B(word2) && neg)
\r
7756 hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
\r
7757 lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
\r
7762 REG_D[word2 & 7] = hi;
\r
7763 REG_D[(word2 >> 12) & 7] = lo;
\r
7764 FLAG_N = NFLAG_32(hi);
\r
7766 FLAG_V = VFLAG_CLEAR;
\r
7770 REG_D[(word2 >> 12) & 7] = lo;
\r
7771 FLAG_N = NFLAG_32(lo);
\r
7774 FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
\r
7776 FLAG_V = (hi != 0) << 7;
\r
7779 m68ki_exception_illegal();
\r
7785 M68KMAKE_OP(mull, 32, ., .)
\r
7787 #if M68K_USE_64_BIT
\r
7789 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
7791 uint word2 = OPER_I_16();
\r
7792 uint64 src = M68KMAKE_GET_OPER_AY_32;
\r
7793 uint64 dst = REG_D[(word2 >> 12) & 7];
\r
7796 FLAG_C = CFLAG_CLEAR;
\r
7798 if(BIT_B(word2)) /* signed */
\r
7800 res = (sint64)((sint32)src) * (sint64)((sint32)dst);
\r
7803 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
7804 FLAG_N = NFLAG_32(res);
\r
7805 FLAG_V = ((sint64)res != (sint32)res)<<7;
\r
7806 REG_D[(word2 >> 12) & 7] = FLAG_Z;
\r
7809 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
\r
7810 FLAG_N = NFLAG_64(res);
\r
7811 FLAG_V = VFLAG_CLEAR;
\r
7812 REG_D[word2 & 7] = (res >> 32);
\r
7813 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
\r
7820 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
7821 FLAG_N = NFLAG_32(res);
\r
7822 FLAG_V = (res > 0xffffffff)<<7;
\r
7823 REG_D[(word2 >> 12) & 7] = FLAG_Z;
\r
7826 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
\r
7827 FLAG_N = NFLAG_64(res);
\r
7828 FLAG_V = VFLAG_CLEAR;
\r
7829 REG_D[word2 & 7] = (res >> 32);
\r
7830 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
\r
7833 m68ki_exception_illegal();
\r
7837 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
7839 uint word2 = OPER_I_16();
\r
7840 uint src = M68KMAKE_GET_OPER_AY_32;
\r
7841 uint dst = REG_D[(word2 >> 12) & 7];
\r
7842 uint neg = GET_MSB_32(src ^ dst);
\r
7854 FLAG_C = CFLAG_CLEAR;
\r
7856 if(BIT_B(word2)) /* signed */
\r
7858 if(GET_MSB_32(src))
\r
7859 src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
\r
7860 if(GET_MSB_32(dst))
\r
7861 dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
\r
7864 src1 = MASK_OUT_ABOVE_16(src);
\r
7866 dst1 = MASK_OUT_ABOVE_16(dst);
\r
7875 lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
\r
7876 hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
\r
7878 if(BIT_B(word2) && neg)
\r
7880 hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
\r
7881 lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
\r
7886 REG_D[word2 & 7] = hi;
\r
7887 REG_D[(word2 >> 12) & 7] = lo;
\r
7888 FLAG_N = NFLAG_32(hi);
\r
7890 FLAG_V = VFLAG_CLEAR;
\r
7894 REG_D[(word2 >> 12) & 7] = lo;
\r
7895 FLAG_N = NFLAG_32(lo);
\r
7898 FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
\r
7900 FLAG_V = (hi != 0) << 7;
\r
7903 m68ki_exception_illegal();
\r
7909 M68KMAKE_OP(nbcd, 8, ., d)
\r
7911 uint* r_dst = &DY;
\r
7912 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
7913 uint res = -dst - XFLAG_AS_1();
\r
7917 FLAG_V = res; /* Undefined V behavior */
\r
7919 if(((res|dst) & 0x0f) == 0)
\r
7920 res = (res & 0xf0) + 6;
\r
7922 res = MASK_OUT_ABOVE_8(res + 0x9a);
\r
7924 FLAG_V &= ~res; /* Undefined V behavior part II */
\r
7926 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
7929 FLAG_C = CFLAG_SET;
\r
7930 FLAG_X = XFLAG_SET;
\r
7934 FLAG_V = VFLAG_CLEAR;
\r
7935 FLAG_C = CFLAG_CLEAR;
\r
7936 FLAG_X = XFLAG_CLEAR;
\r
7938 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
7942 M68KMAKE_OP(nbcd, 8, ., .)
\r
7944 uint ea = M68KMAKE_GET_EA_AY_8;
\r
7945 uint dst = m68ki_read_8(ea);
\r
7946 uint res = -dst - XFLAG_AS_1();
\r
7950 FLAG_V = res; /* Undefined V behavior */
\r
7952 if(((res|dst) & 0x0f) == 0)
\r
7953 res = (res & 0xf0) + 6;
\r
7955 res = MASK_OUT_ABOVE_8(res + 0x9a);
\r
7957 FLAG_V &= ~res; /* Undefined V behavior part II */
\r
7959 m68ki_write_8(ea, MASK_OUT_ABOVE_8(res));
\r
7962 FLAG_C = CFLAG_SET;
\r
7963 FLAG_X = XFLAG_SET;
\r
7967 FLAG_V = VFLAG_CLEAR;
\r
7968 FLAG_C = CFLAG_CLEAR;
\r
7969 FLAG_X = XFLAG_CLEAR;
\r
7971 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
7975 M68KMAKE_OP(neg, 8, ., d)
\r
7977 uint* r_dst = &DY;
\r
7978 uint res = 0 - MASK_OUT_ABOVE_8(*r_dst);
\r
7980 FLAG_N = NFLAG_8(res);
\r
7981 FLAG_C = FLAG_X = CFLAG_8(res);
\r
7982 FLAG_V = *r_dst & res;
\r
7983 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
7985 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
7989 M68KMAKE_OP(neg, 8, ., .)
\r
7991 uint ea = M68KMAKE_GET_EA_AY_8;
\r
7992 uint src = m68ki_read_8(ea);
\r
7993 uint res = 0 - src;
\r
7995 FLAG_N = NFLAG_8(res);
\r
7996 FLAG_C = FLAG_X = CFLAG_8(res);
\r
7997 FLAG_V = src & res;
\r
7998 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
8000 m68ki_write_8(ea, FLAG_Z);
\r
8004 M68KMAKE_OP(neg, 16, ., d)
\r
8006 uint* r_dst = &DY;
\r
8007 uint res = 0 - MASK_OUT_ABOVE_16(*r_dst);
\r
8009 FLAG_N = NFLAG_16(res);
\r
8010 FLAG_C = FLAG_X = CFLAG_16(res);
\r
8011 FLAG_V = (*r_dst & res)>>8;
\r
8012 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
8014 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
8018 M68KMAKE_OP(neg, 16, ., .)
\r
8020 uint ea = M68KMAKE_GET_EA_AY_16;
\r
8021 uint src = m68ki_read_16(ea);
\r
8022 uint res = 0 - src;
\r
8024 FLAG_N = NFLAG_16(res);
\r
8025 FLAG_C = FLAG_X = CFLAG_16(res);
\r
8026 FLAG_V = (src & res)>>8;
\r
8027 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
8029 m68ki_write_16(ea, FLAG_Z);
\r
8033 M68KMAKE_OP(neg, 32, ., d)
\r
8035 uint* r_dst = &DY;
\r
8036 uint res = 0 - *r_dst;
\r
8038 FLAG_N = NFLAG_32(res);
\r
8039 FLAG_C = FLAG_X = CFLAG_SUB_32(*r_dst, 0, res);
\r
8040 FLAG_V = (*r_dst & res)>>24;
\r
8041 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
8047 M68KMAKE_OP(neg, 32, ., .)
\r
8049 uint ea = M68KMAKE_GET_EA_AY_32;
\r
8050 uint src = m68ki_read_32(ea);
\r
8051 uint res = 0 - src;
\r
8053 FLAG_N = NFLAG_32(res);
\r
8054 FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
\r
8055 FLAG_V = (src & res)>>24;
\r
8056 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
8058 m68ki_write_32(ea, FLAG_Z);
\r
8062 M68KMAKE_OP(negx, 8, ., d)
\r
8064 uint* r_dst = &DY;
\r
8065 uint res = 0 - MASK_OUT_ABOVE_8(*r_dst) - XFLAG_AS_1();
\r
8067 FLAG_N = NFLAG_8(res);
\r
8068 FLAG_X = FLAG_C = CFLAG_8(res);
\r
8069 FLAG_V = *r_dst & res;
\r
8071 res = MASK_OUT_ABOVE_8(res);
\r
8074 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8078 M68KMAKE_OP(negx, 8, ., .)
\r
8080 uint ea = M68KMAKE_GET_EA_AY_8;
\r
8081 uint src = m68ki_read_8(ea);
\r
8082 uint res = 0 - src - XFLAG_AS_1();
\r
8084 FLAG_N = NFLAG_8(res);
\r
8085 FLAG_X = FLAG_C = CFLAG_8(res);
\r
8086 FLAG_V = src & res;
\r
8088 res = MASK_OUT_ABOVE_8(res);
\r
8091 m68ki_write_8(ea, res);
\r
8095 M68KMAKE_OP(negx, 16, ., d)
\r
8097 uint* r_dst = &DY;
\r
8098 uint res = 0 - MASK_OUT_ABOVE_16(*r_dst) - XFLAG_AS_1();
\r
8100 FLAG_N = NFLAG_16(res);
\r
8101 FLAG_X = FLAG_C = CFLAG_16(res);
\r
8102 FLAG_V = (*r_dst & res)>>8;
\r
8104 res = MASK_OUT_ABOVE_16(res);
\r
8107 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8111 M68KMAKE_OP(negx, 16, ., .)
\r
8113 uint ea = M68KMAKE_GET_EA_AY_16;
\r
8114 uint src = m68ki_read_16(ea);
\r
8115 uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
\r
8117 FLAG_N = NFLAG_16(res);
\r
8118 FLAG_X = FLAG_C = CFLAG_16(res);
\r
8119 FLAG_V = (src & res)>>8;
\r
8121 res = MASK_OUT_ABOVE_16(res);
\r
8124 m68ki_write_16(ea, res);
\r
8128 M68KMAKE_OP(negx, 32, ., d)
\r
8130 uint* r_dst = &DY;
\r
8131 uint res = 0 - MASK_OUT_ABOVE_32(*r_dst) - XFLAG_AS_1();
\r
8133 FLAG_N = NFLAG_32(res);
\r
8134 FLAG_X = FLAG_C = CFLAG_SUB_32(*r_dst, 0, res);
\r
8135 FLAG_V = (*r_dst & res)>>24;
\r
8137 res = MASK_OUT_ABOVE_32(res);
\r
8144 M68KMAKE_OP(negx, 32, ., .)
\r
8146 uint ea = M68KMAKE_GET_EA_AY_32;
\r
8147 uint src = m68ki_read_32(ea);
\r
8148 uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
\r
8150 FLAG_N = NFLAG_32(res);
\r
8151 FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
\r
8152 FLAG_V = (src & res)>>24;
\r
8154 res = MASK_OUT_ABOVE_32(res);
\r
8157 m68ki_write_32(ea, res);
\r
8161 M68KMAKE_OP(nop, 0, ., .)
\r
8163 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
8167 M68KMAKE_OP(not, 8, ., d)
\r
8169 uint* r_dst = &DY;
\r
8170 uint res = MASK_OUT_ABOVE_8(~*r_dst);
\r
8172 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8174 FLAG_N = NFLAG_8(res);
\r
8176 FLAG_C = CFLAG_CLEAR;
\r
8177 FLAG_V = VFLAG_CLEAR;
\r
8181 M68KMAKE_OP(not, 8, ., .)
\r
8183 uint ea = M68KMAKE_GET_EA_AY_8;
\r
8184 uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
\r
8186 m68ki_write_8(ea, res);
\r
8188 FLAG_N = NFLAG_8(res);
\r
8190 FLAG_C = CFLAG_CLEAR;
\r
8191 FLAG_V = VFLAG_CLEAR;
\r
8195 M68KMAKE_OP(not, 16, ., d)
\r
8197 uint* r_dst = &DY;
\r
8198 uint res = MASK_OUT_ABOVE_16(~*r_dst);
\r
8200 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8202 FLAG_N = NFLAG_16(res);
\r
8204 FLAG_C = CFLAG_CLEAR;
\r
8205 FLAG_V = VFLAG_CLEAR;
\r
8209 M68KMAKE_OP(not, 16, ., .)
\r
8211 uint ea = M68KMAKE_GET_EA_AY_16;
\r
8212 uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
\r
8214 m68ki_write_16(ea, res);
\r
8216 FLAG_N = NFLAG_16(res);
\r
8218 FLAG_C = CFLAG_CLEAR;
\r
8219 FLAG_V = VFLAG_CLEAR;
\r
8223 M68KMAKE_OP(not, 32, ., d)
\r
8225 uint* r_dst = &DY;
\r
8226 uint res = *r_dst = MASK_OUT_ABOVE_32(~*r_dst);
\r
8228 FLAG_N = NFLAG_32(res);
\r
8230 FLAG_C = CFLAG_CLEAR;
\r
8231 FLAG_V = VFLAG_CLEAR;
\r
8235 M68KMAKE_OP(not, 32, ., .)
\r
8237 uint ea = M68KMAKE_GET_EA_AY_32;
\r
8238 uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
\r
8240 m68ki_write_32(ea, res);
\r
8242 FLAG_N = NFLAG_32(res);
\r
8244 FLAG_C = CFLAG_CLEAR;
\r
8245 FLAG_V = VFLAG_CLEAR;
\r
8249 M68KMAKE_OP(or, 8, er, d)
\r
8251 uint res = MASK_OUT_ABOVE_8((DX |= MASK_OUT_ABOVE_8(DY)));
\r
8253 FLAG_N = NFLAG_8(res);
\r
8255 FLAG_C = CFLAG_CLEAR;
\r
8256 FLAG_V = VFLAG_CLEAR;
\r
8260 M68KMAKE_OP(or, 8, er, .)
\r
8262 uint res = MASK_OUT_ABOVE_8((DX |= M68KMAKE_GET_OPER_AY_8));
\r
8264 FLAG_N = NFLAG_8(res);
\r
8266 FLAG_C = CFLAG_CLEAR;
\r
8267 FLAG_V = VFLAG_CLEAR;
\r
8271 M68KMAKE_OP(or, 16, er, d)
\r
8273 uint res = MASK_OUT_ABOVE_16((DX |= MASK_OUT_ABOVE_16(DY)));
\r
8275 FLAG_N = NFLAG_16(res);
\r
8277 FLAG_C = CFLAG_CLEAR;
\r
8278 FLAG_V = VFLAG_CLEAR;
\r
8282 M68KMAKE_OP(or, 16, er, .)
\r
8284 uint res = MASK_OUT_ABOVE_16((DX |= M68KMAKE_GET_OPER_AY_16));
\r
8286 FLAG_N = NFLAG_16(res);
\r
8288 FLAG_C = CFLAG_CLEAR;
\r
8289 FLAG_V = VFLAG_CLEAR;
\r
8293 M68KMAKE_OP(or, 32, er, d)
\r
8295 uint res = DX |= DY;
\r
8297 FLAG_N = NFLAG_32(res);
\r
8299 FLAG_C = CFLAG_CLEAR;
\r
8300 FLAG_V = VFLAG_CLEAR;
\r
8304 M68KMAKE_OP(or, 32, er, .)
\r
8306 uint res = DX |= M68KMAKE_GET_OPER_AY_32;
\r
8308 FLAG_N = NFLAG_32(res);
\r
8310 FLAG_C = CFLAG_CLEAR;
\r
8311 FLAG_V = VFLAG_CLEAR;
\r
8315 M68KMAKE_OP(or, 8, re, .)
\r
8317 uint ea = M68KMAKE_GET_EA_AY_8;
\r
8318 uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
\r
8320 m68ki_write_8(ea, res);
\r
8322 FLAG_N = NFLAG_8(res);
\r
8324 FLAG_C = CFLAG_CLEAR;
\r
8325 FLAG_V = VFLAG_CLEAR;
\r
8329 M68KMAKE_OP(or, 16, re, .)
\r
8331 uint ea = M68KMAKE_GET_EA_AY_16;
\r
8332 uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
\r
8334 m68ki_write_16(ea, res);
\r
8336 FLAG_N = NFLAG_16(res);
\r
8338 FLAG_C = CFLAG_CLEAR;
\r
8339 FLAG_V = VFLAG_CLEAR;
\r
8343 M68KMAKE_OP(or, 32, re, .)
\r
8345 uint ea = M68KMAKE_GET_EA_AY_32;
\r
8346 uint res = DX | m68ki_read_32(ea);
\r
8348 m68ki_write_32(ea, res);
\r
8350 FLAG_N = NFLAG_32(res);
\r
8352 FLAG_C = CFLAG_CLEAR;
\r
8353 FLAG_V = VFLAG_CLEAR;
\r
8357 M68KMAKE_OP(ori, 8, ., d)
\r
8359 uint res = MASK_OUT_ABOVE_8((DY |= OPER_I_8()));
\r
8361 FLAG_N = NFLAG_8(res);
\r
8363 FLAG_C = CFLAG_CLEAR;
\r
8364 FLAG_V = VFLAG_CLEAR;
\r
8368 M68KMAKE_OP(ori, 8, ., .)
\r
8370 uint src = OPER_I_8();
\r
8371 uint ea = M68KMAKE_GET_EA_AY_8;
\r
8372 uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
\r
8374 m68ki_write_8(ea, res);
\r
8376 FLAG_N = NFLAG_8(res);
\r
8378 FLAG_C = CFLAG_CLEAR;
\r
8379 FLAG_V = VFLAG_CLEAR;
\r
8383 M68KMAKE_OP(ori, 16, ., d)
\r
8385 uint res = MASK_OUT_ABOVE_16(DY |= OPER_I_16());
\r
8387 FLAG_N = NFLAG_16(res);
\r
8389 FLAG_C = CFLAG_CLEAR;
\r
8390 FLAG_V = VFLAG_CLEAR;
\r
8394 M68KMAKE_OP(ori, 16, ., .)
\r
8396 uint src = OPER_I_16();
\r
8397 uint ea = M68KMAKE_GET_EA_AY_16;
\r
8398 uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
\r
8400 m68ki_write_16(ea, res);
\r
8402 FLAG_N = NFLAG_16(res);
\r
8404 FLAG_C = CFLAG_CLEAR;
\r
8405 FLAG_V = VFLAG_CLEAR;
\r
8409 M68KMAKE_OP(ori, 32, ., d)
\r
8411 uint res = DY |= OPER_I_32();
\r
8413 FLAG_N = NFLAG_32(res);
\r
8415 FLAG_C = CFLAG_CLEAR;
\r
8416 FLAG_V = VFLAG_CLEAR;
\r
8420 M68KMAKE_OP(ori, 32, ., .)
\r
8422 uint src = OPER_I_32();
\r
8423 uint ea = M68KMAKE_GET_EA_AY_32;
\r
8424 uint res = src | m68ki_read_32(ea);
\r
8426 m68ki_write_32(ea, res);
\r
8428 FLAG_N = NFLAG_32(res);
\r
8430 FLAG_C = CFLAG_CLEAR;
\r
8431 FLAG_V = VFLAG_CLEAR;
\r
8435 M68KMAKE_OP(ori, 16, toc, .)
\r
8437 m68ki_set_ccr(m68ki_get_ccr() | OPER_I_16());
\r
8441 M68KMAKE_OP(ori, 16, tos, .)
\r
8445 uint src = OPER_I_16();
\r
8446 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
8447 m68ki_set_sr(m68ki_get_sr() | src);
\r
8450 m68ki_exception_privilege_violation();
\r
8454 M68KMAKE_OP(pack, 16, rr, .)
\r
8456 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
8458 /* Note: DX and DY are reversed in Motorola's docs */
\r
8459 uint src = DY + OPER_I_16();
\r
8460 uint* r_dst = &DX;
\r
8462 *r_dst = MASK_OUT_BELOW_8(*r_dst) | ((src >> 4) & 0x00f0) | (src & 0x000f);
\r
8465 m68ki_exception_illegal();
\r
8469 M68KMAKE_OP(pack, 16, mm, ax7)
\r
8471 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
8473 /* Note: AX and AY are reversed in Motorola's docs */
\r
8474 uint ea_src = EA_AY_PD_8();
\r
8475 uint src = m68ki_read_8(ea_src);
\r
8476 ea_src = EA_AY_PD_8();
\r
8477 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
\r
8479 m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
\r
8482 m68ki_exception_illegal();
\r
8486 M68KMAKE_OP(pack, 16, mm, ay7)
\r
8488 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
8490 /* Note: AX and AY are reversed in Motorola's docs */
\r
8491 uint ea_src = EA_A7_PD_8();
\r
8492 uint src = m68ki_read_8(ea_src);
\r
8493 ea_src = EA_A7_PD_8();
\r
8494 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
\r
8496 m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
\r
8499 m68ki_exception_illegal();
\r
8503 M68KMAKE_OP(pack, 16, mm, axy7)
\r
8505 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
8507 uint ea_src = EA_A7_PD_8();
\r
8508 uint src = m68ki_read_8(ea_src);
\r
8509 ea_src = EA_A7_PD_8();
\r
8510 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
\r
8512 m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
\r
8515 m68ki_exception_illegal();
\r
8519 M68KMAKE_OP(pack, 16, mm, .)
\r
8521 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
8523 /* Note: AX and AY are reversed in Motorola's docs */
\r
8524 uint ea_src = EA_AY_PD_8();
\r
8525 uint src = m68ki_read_8(ea_src);
\r
8526 ea_src = EA_AY_PD_8();
\r
8527 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
\r
8529 m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
\r
8532 m68ki_exception_illegal();
\r
8536 M68KMAKE_OP(pea, 32, ., .)
\r
8538 uint ea = M68KMAKE_GET_EA_AY_32;
\r
8540 m68ki_push_32(ea);
\r
8544 M68KMAKE_OP(pflush, 32, ., .)
\r
8546 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
8548 // Nothing to do, unless address translation cache is emulated
\r
8551 m68ki_exception_illegal();
\r
8555 M68KMAKE_OP(reset, 0, ., .)
\r
8559 m68ki_output_reset(); /* auto-disable (see m68kcpu.h) */
\r
8560 USE_CYCLES(CYC_RESET);
\r
8563 m68ki_exception_privilege_violation();
\r
8567 M68KMAKE_OP(ror, 8, s, .)
\r
8569 uint* r_dst = &DY;
\r
8570 uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8571 uint shift = orig_shift & 7;
\r
8572 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
8573 uint res = ROR_8(src, shift);
\r
8575 if(orig_shift != 0)
\r
8576 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8578 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8580 FLAG_N = NFLAG_8(res);
\r
8582 FLAG_C = src << (9-orig_shift);
\r
8583 FLAG_V = VFLAG_CLEAR;
\r
8587 M68KMAKE_OP(ror, 16, s, .)
\r
8589 uint* r_dst = &DY;
\r
8590 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8591 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
8592 uint res = ROR_16(src, shift);
\r
8595 USE_CYCLES(shift<<CYC_SHIFT);
\r
8597 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8599 FLAG_N = NFLAG_16(res);
\r
8601 FLAG_C = src << (9-shift);
\r
8602 FLAG_V = VFLAG_CLEAR;
\r
8606 M68KMAKE_OP(ror, 32, s, .)
\r
8608 uint* r_dst = &DY;
\r
8609 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8610 uint64 src = *r_dst;
\r
8611 uint res = ROR_32(src, shift);
\r
8614 USE_CYCLES(shift<<CYC_SHIFT);
\r
8618 FLAG_N = NFLAG_32(res);
\r
8620 FLAG_C = src << (9-shift);
\r
8621 FLAG_V = VFLAG_CLEAR;
\r
8625 M68KMAKE_OP(ror, 8, r, .)
\r
8627 uint* r_dst = &DY;
\r
8628 uint orig_shift = DX & 0x3f;
\r
8629 uint shift = orig_shift & 7;
\r
8630 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
8631 uint res = ROR_8(src, shift);
\r
8633 if(orig_shift != 0)
\r
8635 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8637 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8638 FLAG_C = src << (8-((shift-1)&7));
\r
8639 FLAG_N = NFLAG_8(res);
\r
8641 FLAG_V = VFLAG_CLEAR;
\r
8645 FLAG_C = CFLAG_CLEAR;
\r
8646 FLAG_N = NFLAG_8(src);
\r
8648 FLAG_V = VFLAG_CLEAR;
\r
8652 M68KMAKE_OP(ror, 16, r, .)
\r
8654 uint* r_dst = &DY;
\r
8655 uint orig_shift = DX & 0x3f;
\r
8656 uint shift = orig_shift & 15;
\r
8657 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
8658 uint res = ROR_16(src, shift);
\r
8660 if(orig_shift != 0)
\r
8662 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8664 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8665 FLAG_C = (src >> ((shift - 1) & 15)) << 8;
\r
8666 FLAG_N = NFLAG_16(res);
\r
8668 FLAG_V = VFLAG_CLEAR;
\r
8672 FLAG_C = CFLAG_CLEAR;
\r
8673 FLAG_N = NFLAG_16(src);
\r
8675 FLAG_V = VFLAG_CLEAR;
\r
8679 M68KMAKE_OP(ror, 32, r, .)
\r
8681 uint* r_dst = &DY;
\r
8682 uint orig_shift = DX & 0x3f;
\r
8683 uint shift = orig_shift & 31;
\r
8684 uint64 src = *r_dst;
\r
8685 uint res = ROR_32(src, shift);
\r
8687 if(orig_shift != 0)
\r
8689 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8692 FLAG_C = (src >> ((shift - 1) & 31)) << 8;
\r
8693 FLAG_N = NFLAG_32(res);
\r
8695 FLAG_V = VFLAG_CLEAR;
\r
8699 FLAG_C = CFLAG_CLEAR;
\r
8700 FLAG_N = NFLAG_32(src);
\r
8702 FLAG_V = VFLAG_CLEAR;
\r
8706 M68KMAKE_OP(ror, 16, ., .)
\r
8708 uint ea = M68KMAKE_GET_EA_AY_16;
\r
8709 uint src = m68ki_read_16(ea);
\r
8710 uint res = ROR_16(src, 1);
\r
8712 m68ki_write_16(ea, res);
\r
8714 FLAG_N = NFLAG_16(res);
\r
8716 FLAG_C = src << 8;
\r
8717 FLAG_V = VFLAG_CLEAR;
\r
8721 M68KMAKE_OP(rol, 8, s, .)
\r
8723 uint* r_dst = &DY;
\r
8724 uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8725 uint shift = orig_shift & 7;
\r
8726 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
8727 uint res = ROL_8(src, shift);
\r
8729 if(orig_shift != 0)
\r
8730 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8732 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8734 FLAG_N = NFLAG_8(res);
\r
8736 FLAG_C = src << orig_shift;
\r
8737 FLAG_V = VFLAG_CLEAR;
\r
8741 M68KMAKE_OP(rol, 16, s, .)
\r
8743 uint* r_dst = &DY;
\r
8744 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8745 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
8746 uint res = ROL_16(src, shift);
\r
8749 USE_CYCLES(shift<<CYC_SHIFT);
\r
8751 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8753 FLAG_N = NFLAG_16(res);
\r
8755 FLAG_C = src >> (8-shift);
\r
8756 FLAG_V = VFLAG_CLEAR;
\r
8760 M68KMAKE_OP(rol, 32, s, .)
\r
8762 uint* r_dst = &DY;
\r
8763 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8764 uint64 src = *r_dst;
\r
8765 uint res = ROL_32(src, shift);
\r
8768 USE_CYCLES(shift<<CYC_SHIFT);
\r
8772 FLAG_N = NFLAG_32(res);
\r
8774 FLAG_C = src >> (24-shift);
\r
8775 FLAG_V = VFLAG_CLEAR;
\r
8779 M68KMAKE_OP(rol, 8, r, .)
\r
8781 uint* r_dst = &DY;
\r
8782 uint orig_shift = DX & 0x3f;
\r
8783 uint shift = orig_shift & 7;
\r
8784 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
8785 uint res = ROL_8(src, shift);
\r
8787 if(orig_shift != 0)
\r
8789 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8793 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8794 FLAG_C = src << shift;
\r
8795 FLAG_N = NFLAG_8(res);
\r
8797 FLAG_V = VFLAG_CLEAR;
\r
8800 FLAG_C = (src & 1)<<8;
\r
8801 FLAG_N = NFLAG_8(src);
\r
8803 FLAG_V = VFLAG_CLEAR;
\r
8807 FLAG_C = CFLAG_CLEAR;
\r
8808 FLAG_N = NFLAG_8(src);
\r
8810 FLAG_V = VFLAG_CLEAR;
\r
8814 M68KMAKE_OP(rol, 16, r, .)
\r
8816 uint* r_dst = &DY;
\r
8817 uint orig_shift = DX & 0x3f;
\r
8818 uint shift = orig_shift & 15;
\r
8819 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
8820 uint res = MASK_OUT_ABOVE_16(ROL_16(src, shift));
\r
8822 if(orig_shift != 0)
\r
8824 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8828 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8829 FLAG_C = (src << shift) >> 8;
\r
8830 FLAG_N = NFLAG_16(res);
\r
8832 FLAG_V = VFLAG_CLEAR;
\r
8835 FLAG_C = (src & 1)<<8;
\r
8836 FLAG_N = NFLAG_16(src);
\r
8838 FLAG_V = VFLAG_CLEAR;
\r
8842 FLAG_C = CFLAG_CLEAR;
\r
8843 FLAG_N = NFLAG_16(src);
\r
8845 FLAG_V = VFLAG_CLEAR;
\r
8849 M68KMAKE_OP(rol, 32, r, .)
\r
8851 uint* r_dst = &DY;
\r
8852 uint orig_shift = DX & 0x3f;
\r
8853 uint shift = orig_shift & 31;
\r
8854 uint64 src = *r_dst;
\r
8855 uint res = ROL_32(src, shift);
\r
8857 if(orig_shift != 0)
\r
8859 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8863 FLAG_C = (src >> ((32 - shift) & 0x1f)) << 8;
\r
8864 FLAG_N = NFLAG_32(res);
\r
8866 FLAG_V = VFLAG_CLEAR;
\r
8870 FLAG_C = CFLAG_CLEAR;
\r
8871 FLAG_N = NFLAG_32(src);
\r
8873 FLAG_V = VFLAG_CLEAR;
\r
8877 M68KMAKE_OP(rol, 16, ., .)
\r
8879 uint ea = M68KMAKE_GET_EA_AY_16;
\r
8880 uint src = m68ki_read_16(ea);
\r
8881 uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
\r
8883 m68ki_write_16(ea, res);
\r
8885 FLAG_N = NFLAG_16(res);
\r
8887 FLAG_C = src >> 7;
\r
8888 FLAG_V = VFLAG_CLEAR;
\r
8892 M68KMAKE_OP(roxr, 8, s, .)
\r
8894 uint* r_dst = &DY;
\r
8895 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8896 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
8897 uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);
\r
8900 USE_CYCLES(shift<<CYC_SHIFT);
\r
8902 FLAG_C = FLAG_X = res;
\r
8903 res = MASK_OUT_ABOVE_8(res);
\r
8905 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8907 FLAG_N = NFLAG_8(res);
\r
8909 FLAG_V = VFLAG_CLEAR;
\r
8913 M68KMAKE_OP(roxr, 16, s, .)
\r
8915 uint* r_dst = &DY;
\r
8916 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8917 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
8918 uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);
\r
8921 USE_CYCLES(shift<<CYC_SHIFT);
\r
8923 FLAG_C = FLAG_X = res >> 8;
\r
8924 res = MASK_OUT_ABOVE_16(res);
\r
8926 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8928 FLAG_N = NFLAG_16(res);
\r
8930 FLAG_V = VFLAG_CLEAR;
\r
8934 M68KMAKE_OP(roxr, 32, s, .)
\r
8936 #if M68K_USE_64_BIT
\r
8938 uint* r_dst = &DY;
\r
8939 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8940 uint64 src = *r_dst;
\r
8941 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
\r
8944 USE_CYCLES(shift<<CYC_SHIFT);
\r
8946 res = ROR_33_64(res, shift);
\r
8948 FLAG_C = FLAG_X = res >> 24;
\r
8949 res = MASK_OUT_ABOVE_32(res);
\r
8953 FLAG_N = NFLAG_32(res);
\r
8955 FLAG_V = VFLAG_CLEAR;
\r
8959 uint* r_dst = &DY;
\r
8960 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8961 uint src = *r_dst;
\r
8962 uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));
\r
8963 uint new_x_flag = src & (1 << (shift - 1));
\r
8966 USE_CYCLES(shift<<CYC_SHIFT);
\r
8970 FLAG_C = FLAG_X = (new_x_flag != 0)<<8;
\r
8971 FLAG_N = NFLAG_32(res);
\r
8973 FLAG_V = VFLAG_CLEAR;
\r
8979 M68KMAKE_OP(roxr, 8, r, .)
\r
8981 uint* r_dst = &DY;
\r
8982 uint orig_shift = DX & 0x3f;
\r
8984 if(orig_shift != 0)
\r
8986 uint shift = orig_shift % 9;
\r
8987 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
8988 uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);
\r
8990 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8992 FLAG_C = FLAG_X = res;
\r
8993 res = MASK_OUT_ABOVE_8(res);
\r
8995 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8996 FLAG_N = NFLAG_8(res);
\r
8998 FLAG_V = VFLAG_CLEAR;
\r
9003 FLAG_N = NFLAG_8(*r_dst);
\r
9004 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
\r
9005 FLAG_V = VFLAG_CLEAR;
\r
9009 M68KMAKE_OP(roxr, 16, r, .)
\r
9011 uint* r_dst = &DY;
\r
9012 uint orig_shift = DX & 0x3f;
\r
9014 if(orig_shift != 0)
\r
9016 uint shift = orig_shift % 17;
\r
9017 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
9018 uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);
\r
9020 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
9022 FLAG_C = FLAG_X = res >> 8;
\r
9023 res = MASK_OUT_ABOVE_16(res);
\r
9025 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
9026 FLAG_N = NFLAG_16(res);
\r
9028 FLAG_V = VFLAG_CLEAR;
\r
9033 FLAG_N = NFLAG_16(*r_dst);
\r
9034 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
\r
9035 FLAG_V = VFLAG_CLEAR;
\r
9039 M68KMAKE_OP(roxr, 32, r, .)
\r
9041 #if M68K_USE_64_BIT
\r
9043 uint* r_dst = &DY;
\r
9044 uint orig_shift = DX & 0x3f;
\r
9046 if(orig_shift != 0)
\r
9048 uint shift = orig_shift % 33;
\r
9049 uint64 src = *r_dst;
\r
9050 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
\r
9052 res = ROR_33_64(res, shift);
\r
9054 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
9056 FLAG_C = FLAG_X = res >> 24;
\r
9057 res = MASK_OUT_ABOVE_32(res);
\r
9060 FLAG_N = NFLAG_32(res);
\r
9062 FLAG_V = VFLAG_CLEAR;
\r
9067 FLAG_N = NFLAG_32(*r_dst);
\r
9069 FLAG_V = VFLAG_CLEAR;
\r
9073 uint* r_dst = &DY;
\r
9074 uint orig_shift = DX & 0x3f;
\r
9075 uint shift = orig_shift % 33;
\r
9076 uint src = *r_dst;
\r
9077 uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));
\r
9078 uint new_x_flag = src & (1 << (shift - 1));
\r
9080 if(orig_shift != 0)
\r
9081 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
9086 FLAG_X = (new_x_flag != 0)<<8;
\r
9091 FLAG_N = NFLAG_32(res);
\r
9093 FLAG_V = VFLAG_CLEAR;
\r
9099 M68KMAKE_OP(roxr, 16, ., .)
\r
9101 uint ea = M68KMAKE_GET_EA_AY_16;
\r
9102 uint src = m68ki_read_16(ea);
\r
9103 uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
\r
9105 FLAG_C = FLAG_X = res >> 8;
\r
9106 res = MASK_OUT_ABOVE_16(res);
\r
9108 m68ki_write_16(ea, res);
\r
9110 FLAG_N = NFLAG_16(res);
\r
9112 FLAG_V = VFLAG_CLEAR;
\r
9116 M68KMAKE_OP(roxl, 8, s, .)
\r
9118 uint* r_dst = &DY;
\r
9119 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9120 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
9121 uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);
\r
9124 USE_CYCLES(shift<<CYC_SHIFT);
\r
9126 FLAG_C = FLAG_X = res;
\r
9127 res = MASK_OUT_ABOVE_8(res);
\r
9129 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
9131 FLAG_N = NFLAG_8(res);
\r
9133 FLAG_V = VFLAG_CLEAR;
\r
9137 M68KMAKE_OP(roxl, 16, s, .)
\r
9139 uint* r_dst = &DY;
\r
9140 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9141 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
9142 uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);
\r
9145 USE_CYCLES(shift<<CYC_SHIFT);
\r
9147 FLAG_C = FLAG_X = res >> 8;
\r
9148 res = MASK_OUT_ABOVE_16(res);
\r
9150 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
9152 FLAG_N = NFLAG_16(res);
\r
9154 FLAG_V = VFLAG_CLEAR;
\r
9158 M68KMAKE_OP(roxl, 32, s, .)
\r
9160 #if M68K_USE_64_BIT
\r
9162 uint* r_dst = &DY;
\r
9163 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9164 uint64 src = *r_dst;
\r
9165 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
\r
9168 USE_CYCLES(shift<<CYC_SHIFT);
\r
9170 res = ROL_33_64(res, shift);
\r
9172 FLAG_C = FLAG_X = res >> 24;
\r
9173 res = MASK_OUT_ABOVE_32(res);
\r
9177 FLAG_N = NFLAG_32(res);
\r
9179 FLAG_V = VFLAG_CLEAR;
\r
9183 uint* r_dst = &DY;
\r
9184 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9185 uint src = *r_dst;
\r
9186 uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));
\r
9187 uint new_x_flag = src & (1 << (32 - shift));
\r
9190 USE_CYCLES(shift<<CYC_SHIFT);
\r
9194 FLAG_C = FLAG_X = (new_x_flag != 0)<<8;
\r
9195 FLAG_N = NFLAG_32(res);
\r
9197 FLAG_V = VFLAG_CLEAR;
\r
9203 M68KMAKE_OP(roxl, 8, r, .)
\r
9205 uint* r_dst = &DY;
\r
9206 uint orig_shift = DX & 0x3f;
\r
9209 if(orig_shift != 0)
\r
9211 uint shift = orig_shift % 9;
\r
9212 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
9213 uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);
\r
9215 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
9217 FLAG_C = FLAG_X = res;
\r
9218 res = MASK_OUT_ABOVE_8(res);
\r
9220 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
9221 FLAG_N = NFLAG_8(res);
\r
9223 FLAG_V = VFLAG_CLEAR;
\r
9228 FLAG_N = NFLAG_8(*r_dst);
\r
9229 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
\r
9230 FLAG_V = VFLAG_CLEAR;
\r
9234 M68KMAKE_OP(roxl, 16, r, .)
\r
9236 uint* r_dst = &DY;
\r
9237 uint orig_shift = DX & 0x3f;
\r
9239 if(orig_shift != 0)
\r
9241 uint shift = orig_shift % 17;
\r
9242 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
9243 uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);
\r
9245 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
9247 FLAG_C = FLAG_X = res >> 8;
\r
9248 res = MASK_OUT_ABOVE_16(res);
\r
9250 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
9251 FLAG_N = NFLAG_16(res);
\r
9253 FLAG_V = VFLAG_CLEAR;
\r
9258 FLAG_N = NFLAG_16(*r_dst);
\r
9259 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
\r
9260 FLAG_V = VFLAG_CLEAR;
\r
9264 M68KMAKE_OP(roxl, 32, r, .)
\r
9266 #if M68K_USE_64_BIT
\r
9268 uint* r_dst = &DY;
\r
9269 uint orig_shift = DX & 0x3f;
\r
9271 if(orig_shift != 0)
\r
9273 uint shift = orig_shift % 33;
\r
9274 uint64 src = *r_dst;
\r
9275 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
\r
9277 res = ROL_33_64(res, shift);
\r
9279 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
9281 FLAG_C = FLAG_X = res >> 24;
\r
9282 res = MASK_OUT_ABOVE_32(res);
\r
9285 FLAG_N = NFLAG_32(res);
\r
9287 FLAG_V = VFLAG_CLEAR;
\r
9292 FLAG_N = NFLAG_32(*r_dst);
\r
9294 FLAG_V = VFLAG_CLEAR;
\r
9298 uint* r_dst = &DY;
\r
9299 uint orig_shift = DX & 0x3f;
\r
9300 uint shift = orig_shift % 33;
\r
9301 uint src = *r_dst;
\r
9302 uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));
\r
9303 uint new_x_flag = src & (1 << (32 - shift));
\r
9305 if(orig_shift != 0)
\r
9306 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
9311 FLAG_X = (new_x_flag != 0)<<8;
\r
9316 FLAG_N = NFLAG_32(res);
\r
9318 FLAG_V = VFLAG_CLEAR;
\r
9324 M68KMAKE_OP(roxl, 16, ., .)
\r
9326 uint ea = M68KMAKE_GET_EA_AY_16;
\r
9327 uint src = m68ki_read_16(ea);
\r
9328 uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
\r
9330 FLAG_C = FLAG_X = res >> 8;
\r
9331 res = MASK_OUT_ABOVE_16(res);
\r
9333 m68ki_write_16(ea, res);
\r
9335 FLAG_N = NFLAG_16(res);
\r
9337 FLAG_V = VFLAG_CLEAR;
\r
9341 M68KMAKE_OP(rtd, 32, ., .)
\r
9343 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
9345 uint new_pc = m68ki_pull_32();
\r
9347 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
9348 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
\r
9349 m68ki_jump(new_pc);
\r
9352 m68ki_exception_illegal();
\r
9356 M68KMAKE_OP(rte, 32, ., .)
\r
9364 m68ki_rte_callback(); /* auto-disable (see m68kcpu.h) */
\r
9365 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
9367 if(CPU_TYPE_IS_000(CPU_TYPE))
\r
9369 new_sr = m68ki_pull_16();
\r
9370 new_pc = m68ki_pull_32();
\r
9371 m68ki_jump(new_pc);
\r
9372 m68ki_set_sr(new_sr);
\r
9374 CPU_INSTR_MODE = INSTRUCTION_YES;
\r
9375 CPU_RUN_MODE = RUN_MODE_NORMAL;
\r
9380 if(CPU_TYPE_IS_010(CPU_TYPE))
\r
9382 format_word = m68ki_read_16(REG_A[7]+6) >> 12;
\r
9383 if(format_word == 0)
\r
9385 new_sr = m68ki_pull_16();
\r
9386 new_pc = m68ki_pull_32();
\r
9387 m68ki_fake_pull_16(); /* format word */
\r
9388 m68ki_jump(new_pc);
\r
9389 m68ki_set_sr(new_sr);
\r
9390 CPU_INSTR_MODE = INSTRUCTION_YES;
\r
9391 CPU_RUN_MODE = RUN_MODE_NORMAL;
\r
9394 CPU_INSTR_MODE = INSTRUCTION_YES;
\r
9395 CPU_RUN_MODE = RUN_MODE_NORMAL;
\r
9396 /* Not handling bus fault (9) */
\r
9397 m68ki_exception_format_error();
\r
9401 /* Otherwise it's 020 */
\r
9403 format_word = m68ki_read_16(REG_A[7]+6) >> 12;
\r
9404 switch(format_word)
\r
9406 case 0: /* Normal */
\r
9407 new_sr = m68ki_pull_16();
\r
9408 new_pc = m68ki_pull_32();
\r
9409 m68ki_fake_pull_16(); /* format word */
\r
9410 m68ki_jump(new_pc);
\r
9411 m68ki_set_sr(new_sr);
\r
9412 CPU_INSTR_MODE = INSTRUCTION_YES;
\r
9413 CPU_RUN_MODE = RUN_MODE_NORMAL;
\r
9415 case 1: /* Throwaway */
\r
9416 new_sr = m68ki_pull_16();
\r
9417 m68ki_fake_pull_32(); /* program counter */
\r
9418 m68ki_fake_pull_16(); /* format word */
\r
9419 m68ki_set_sr_noint(new_sr);
\r
9421 case 2: /* Trap */
\r
9422 new_sr = m68ki_pull_16();
\r
9423 new_pc = m68ki_pull_32();
\r
9424 m68ki_fake_pull_16(); /* format word */
\r
9425 m68ki_fake_pull_32(); /* address */
\r
9426 m68ki_jump(new_pc);
\r
9427 m68ki_set_sr(new_sr);
\r
9428 CPU_INSTR_MODE = INSTRUCTION_YES;
\r
9429 CPU_RUN_MODE = RUN_MODE_NORMAL;
\r
9432 /* Not handling long or short bus fault */
\r
9433 CPU_INSTR_MODE = INSTRUCTION_YES;
\r
9434 CPU_RUN_MODE = RUN_MODE_NORMAL;
\r
9435 m68ki_exception_format_error();
\r
9438 m68ki_exception_privilege_violation();
\r
9442 M68KMAKE_OP(rtm, 32, ., .)
\r
9444 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
9446 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
9447 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
9448 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
9449 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
9452 m68ki_exception_illegal();
\r
9456 M68KMAKE_OP(rtr, 32, ., .)
\r
9458 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
9459 m68ki_set_ccr(m68ki_pull_16());
\r
9460 m68ki_jump(m68ki_pull_32());
\r
9464 M68KMAKE_OP(rts, 32, ., .)
\r
9466 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
9467 m68ki_jump(m68ki_pull_32());
\r
9471 M68KMAKE_OP(sbcd, 8, rr, .)
\r
9473 uint* r_dst = &DX;
\r
9475 uint dst = *r_dst;
\r
9476 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
\r
9481 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
\r
9482 FLAG_V = res; /* Undefined V behavior */
\r
9486 FLAG_X = FLAG_C = CFLAG_SET;
\r
9488 else if(res < corf)
\r
9489 FLAG_X = FLAG_C = CFLAG_SET;
\r
9491 FLAG_X = FLAG_C = 0;
\r
9493 res = MASK_OUT_ABOVE_8(res - corf);
\r
9495 FLAG_V &= ~res; /* Undefined V behavior part II */
\r
9496 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
9499 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
9503 M68KMAKE_OP(sbcd, 8, mm, ax7)
\r
9505 uint src = OPER_AY_PD_8();
\r
9506 uint ea = EA_A7_PD_8();
\r
9507 uint dst = m68ki_read_8(ea);
\r
9508 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
\r
9513 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
\r
9514 FLAG_V = res; /* Undefined V behavior */
\r
9518 FLAG_X = FLAG_C = CFLAG_SET;
\r
9520 else if(res < corf)
\r
9521 FLAG_X = FLAG_C = CFLAG_SET;
\r
9523 FLAG_X = FLAG_C = 0;
\r
9525 res = MASK_OUT_ABOVE_8(res - corf);
\r
9527 FLAG_V &= ~res; /* Undefined V behavior part II */
\r
9528 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
9531 m68ki_write_8(ea, res);
\r
9535 M68KMAKE_OP(sbcd, 8, mm, ay7)
\r
9537 uint src = OPER_A7_PD_8();
\r
9538 uint ea = EA_AX_PD_8();
\r
9539 uint dst = m68ki_read_8(ea);
\r
9540 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
\r
9545 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
\r
9546 FLAG_V = res; /* Undefined V behavior */
\r
9550 FLAG_X = FLAG_C = CFLAG_SET;
\r
9552 else if(res < corf)
\r
9553 FLAG_X = FLAG_C = CFLAG_SET;
\r
9555 FLAG_X = FLAG_C = 0;
\r
9557 res = MASK_OUT_ABOVE_8(res - corf);
\r
9559 FLAG_V &= ~res; /* Undefined V behavior part II */
\r
9560 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
9563 m68ki_write_8(ea, res);
\r
9567 M68KMAKE_OP(sbcd, 8, mm, axy7)
\r
9569 uint src = OPER_A7_PD_8();
\r
9570 uint ea = EA_A7_PD_8();
\r
9571 uint dst = m68ki_read_8(ea);
\r
9572 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
\r
9577 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
\r
9578 FLAG_V = res; /* Undefined V behavior */
\r
9582 FLAG_X = FLAG_C = CFLAG_SET;
\r
9584 else if(res < corf)
\r
9585 FLAG_X = FLAG_C = CFLAG_SET;
\r
9587 FLAG_X = FLAG_C = 0;
\r
9589 res = MASK_OUT_ABOVE_8(res - corf);
\r
9591 FLAG_V &= ~res; /* Undefined V behavior part II */
\r
9592 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
9595 m68ki_write_8(ea, res);
\r
9599 M68KMAKE_OP(sbcd, 8, mm, .)
\r
9601 uint src = OPER_AY_PD_8();
\r
9602 uint ea = EA_AX_PD_8();
\r
9603 uint dst = m68ki_read_8(ea);
\r
9604 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
\r
9609 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
\r
9610 FLAG_V = res; /* Undefined V behavior */
\r
9614 FLAG_X = FLAG_C = CFLAG_SET;
\r
9616 else if(res < corf)
\r
9617 FLAG_X = FLAG_C = CFLAG_SET;
\r
9619 FLAG_X = FLAG_C = 0;
\r
9621 res = MASK_OUT_ABOVE_8(res - corf);
\r
9623 FLAG_V &= ~res; /* Undefined V behavior part II */
\r
9624 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
9627 m68ki_write_8(ea, res);
\r
9631 M68KMAKE_OP(st, 8, ., d)
\r
9637 M68KMAKE_OP(st, 8, ., .)
\r
9639 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0xff);
\r
9643 M68KMAKE_OP(sf, 8, ., d)
\r
9649 M68KMAKE_OP(sf, 8, ., .)
\r
9651 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);
\r
9655 M68KMAKE_OP(scc, 8, ., d)
\r
9660 USE_CYCLES(CYC_SCC_R_TRUE);
\r
9667 M68KMAKE_OP(scc, 8, ., .)
\r
9669 m68ki_write_8(M68KMAKE_GET_EA_AY_8, M68KMAKE_CC ? 0xff : 0);
\r
9673 M68KMAKE_OP(stop, 0, ., .)
\r
9677 uint new_sr = OPER_I_16();
\r
9678 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
9679 CPU_STOPPED |= STOP_LEVEL_STOP;
\r
9680 m68ki_set_sr(new_sr);
\r
9681 m68ki_remaining_cycles = 0;
\r
9684 m68ki_exception_privilege_violation();
\r
9688 M68KMAKE_OP(sub, 8, er, d)
\r
9690 uint* r_dst = &DX;
\r
9691 uint src = MASK_OUT_ABOVE_8(DY);
\r
9692 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
9693 uint res = dst - src;
\r
9695 FLAG_N = NFLAG_8(res);
\r
9696 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9697 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9698 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
9700 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
9704 M68KMAKE_OP(sub, 8, er, .)
\r
9706 uint* r_dst = &DX;
\r
9707 uint src = M68KMAKE_GET_OPER_AY_8;
\r
9708 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
9709 uint res = dst - src;
\r
9711 FLAG_N = NFLAG_8(res);
\r
9712 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9713 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9714 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
9716 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
9720 M68KMAKE_OP(sub, 16, er, d)
\r
9722 uint* r_dst = &DX;
\r
9723 uint src = MASK_OUT_ABOVE_16(DY);
\r
9724 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
9725 uint res = dst - src;
\r
9727 FLAG_N = NFLAG_16(res);
\r
9728 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9729 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9730 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9732 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
9736 M68KMAKE_OP(sub, 16, er, a)
\r
9738 uint* r_dst = &DX;
\r
9739 uint src = MASK_OUT_ABOVE_16(AY);
\r
9740 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
9741 uint res = dst - src;
\r
9743 FLAG_N = NFLAG_16(res);
\r
9744 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9745 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9746 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9748 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
9752 M68KMAKE_OP(sub, 16, er, .)
\r
9754 uint* r_dst = &DX;
\r
9755 uint src = M68KMAKE_GET_OPER_AY_16;
\r
9756 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
9757 uint res = dst - src;
\r
9759 FLAG_N = NFLAG_16(res);
\r
9760 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9761 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9762 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9764 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
9768 M68KMAKE_OP(sub, 32, er, d)
\r
9770 uint* r_dst = &DX;
\r
9772 uint dst = *r_dst;
\r
9773 uint res = dst - src;
\r
9775 FLAG_N = NFLAG_32(res);
\r
9776 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9777 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9778 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9784 M68KMAKE_OP(sub, 32, er, a)
\r
9786 uint* r_dst = &DX;
\r
9788 uint dst = *r_dst;
\r
9789 uint res = dst - src;
\r
9791 FLAG_N = NFLAG_32(res);
\r
9792 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9793 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9794 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9800 M68KMAKE_OP(sub, 32, er, .)
\r
9802 uint* r_dst = &DX;
\r
9803 uint src = M68KMAKE_GET_OPER_AY_32;
\r
9804 uint dst = *r_dst;
\r
9805 uint res = dst - src;
\r
9807 FLAG_N = NFLAG_32(res);
\r
9808 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9809 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9810 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9816 M68KMAKE_OP(sub, 8, re, .)
\r
9818 uint ea = M68KMAKE_GET_EA_AY_8;
\r
9819 uint src = MASK_OUT_ABOVE_8(DX);
\r
9820 uint dst = m68ki_read_8(ea);
\r
9821 uint res = dst - src;
\r
9823 FLAG_N = NFLAG_8(res);
\r
9824 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
9825 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9826 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9828 m68ki_write_8(ea, FLAG_Z);
\r
9832 M68KMAKE_OP(sub, 16, re, .)
\r
9834 uint ea = M68KMAKE_GET_EA_AY_16;
\r
9835 uint src = MASK_OUT_ABOVE_16(DX);
\r
9836 uint dst = m68ki_read_16(ea);
\r
9837 uint res = dst - src;
\r
9839 FLAG_N = NFLAG_16(res);
\r
9840 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9841 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9842 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9844 m68ki_write_16(ea, FLAG_Z);
\r
9848 M68KMAKE_OP(sub, 32, re, .)
\r
9850 uint ea = M68KMAKE_GET_EA_AY_32;
\r
9852 uint dst = m68ki_read_32(ea);
\r
9853 uint res = dst - src;
\r
9855 FLAG_N = NFLAG_32(res);
\r
9856 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9857 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9858 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9860 m68ki_write_32(ea, FLAG_Z);
\r
9864 M68KMAKE_OP(suba, 16, ., d)
\r
9866 uint* r_dst = &AX;
\r
9868 *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(DY));
\r
9872 M68KMAKE_OP(suba, 16, ., a)
\r
9874 uint* r_dst = &AX;
\r
9876 *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(AY));
\r
9880 M68KMAKE_OP(suba, 16, ., .)
\r
9882 uint* r_dst = &AX;
\r
9883 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
\r
9885 *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
\r
9889 M68KMAKE_OP(suba, 32, ., d)
\r
9891 uint* r_dst = &AX;
\r
9893 *r_dst = MASK_OUT_ABOVE_32(*r_dst - DY);
\r
9897 M68KMAKE_OP(suba, 32, ., a)
\r
9899 uint* r_dst = &AX;
\r
9901 *r_dst = MASK_OUT_ABOVE_32(*r_dst - AY);
\r
9905 M68KMAKE_OP(suba, 32, ., .)
\r
9907 uint* r_dst = &AX;
\r
9908 uint src = M68KMAKE_GET_OPER_AY_32; // notaz
\r
9910 *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
\r
9914 M68KMAKE_OP(subi, 8, ., d)
\r
9916 uint* r_dst = &DY;
\r
9917 uint src = OPER_I_8();
\r
9918 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
9919 uint res = dst - src;
\r
9921 FLAG_N = NFLAG_8(res);
\r
9922 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
9923 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9924 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9926 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
9930 M68KMAKE_OP(subi, 8, ., .)
\r
9932 uint src = OPER_I_8();
\r
9933 uint ea = M68KMAKE_GET_EA_AY_8;
\r
9934 uint dst = m68ki_read_8(ea);
\r
9935 uint res = dst - src;
\r
9937 FLAG_N = NFLAG_8(res);
\r
9938 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
9939 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9940 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9942 m68ki_write_8(ea, FLAG_Z);
\r
9946 M68KMAKE_OP(subi, 16, ., d)
\r
9948 uint* r_dst = &DY;
\r
9949 uint src = OPER_I_16();
\r
9950 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
9951 uint res = dst - src;
\r
9953 FLAG_N = NFLAG_16(res);
\r
9954 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9955 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9956 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9958 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
9962 M68KMAKE_OP(subi, 16, ., .)
\r
9964 uint src = OPER_I_16();
\r
9965 uint ea = M68KMAKE_GET_EA_AY_16;
\r
9966 uint dst = m68ki_read_16(ea);
\r
9967 uint res = dst - src;
\r
9969 FLAG_N = NFLAG_16(res);
\r
9970 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9971 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9972 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9974 m68ki_write_16(ea, FLAG_Z);
\r
9978 M68KMAKE_OP(subi, 32, ., d)
\r
9980 uint* r_dst = &DY;
\r
9981 uint src = OPER_I_32();
\r
9982 uint dst = *r_dst;
\r
9983 uint res = dst - src;
\r
9985 FLAG_N = NFLAG_32(res);
\r
9986 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9987 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9988 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9994 M68KMAKE_OP(subi, 32, ., .)
\r
9996 uint src = OPER_I_32();
\r
9997 uint ea = M68KMAKE_GET_EA_AY_32;
\r
9998 uint dst = m68ki_read_32(ea);
\r
9999 uint res = dst - src;
\r
10001 FLAG_N = NFLAG_32(res);
\r
10002 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
10003 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
10004 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
10006 m68ki_write_32(ea, FLAG_Z);
\r
10010 M68KMAKE_OP(subq, 8, ., d)
\r
10012 uint* r_dst = &DY;
\r
10013 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
10014 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
10015 uint res = dst - src;
\r
10017 FLAG_N = NFLAG_8(res);
\r
10018 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
10019 FLAG_X = FLAG_C = CFLAG_8(res);
\r
10020 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
10022 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
10026 M68KMAKE_OP(subq, 8, ., .)
\r
10028 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
10029 uint ea = M68KMAKE_GET_EA_AY_8;
\r
10030 uint dst = m68ki_read_8(ea);
\r
10031 uint res = dst - src;
\r
10033 FLAG_N = NFLAG_8(res);
\r
10034 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
10035 FLAG_X = FLAG_C = CFLAG_8(res);
\r
10036 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
10038 m68ki_write_8(ea, FLAG_Z);
\r
10042 M68KMAKE_OP(subq, 16, ., d)
\r
10044 uint* r_dst = &DY;
\r
10045 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
10046 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
10047 uint res = dst - src;
\r
10049 FLAG_N = NFLAG_16(res);
\r
10050 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
10051 FLAG_X = FLAG_C = CFLAG_16(res);
\r
10052 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
10054 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
10058 M68KMAKE_OP(subq, 16, ., a)
\r
10060 uint* r_dst = &AY;
\r
10062 *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));
\r
10066 M68KMAKE_OP(subq, 16, ., .)
\r
10068 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
10069 uint ea = M68KMAKE_GET_EA_AY_16;
\r
10070 uint dst = m68ki_read_16(ea);
\r
10071 uint res = dst - src;
\r
10073 FLAG_N = NFLAG_16(res);
\r
10074 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
10075 FLAG_X = FLAG_C = CFLAG_16(res);
\r
10076 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
10078 m68ki_write_16(ea, FLAG_Z);
\r
10082 M68KMAKE_OP(subq, 32, ., d)
\r
10084 uint* r_dst = &DY;
\r
10085 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
10086 uint dst = *r_dst;
\r
10087 uint res = dst - src;
\r
10089 FLAG_N = NFLAG_32(res);
\r
10090 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
10091 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
10092 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
10098 M68KMAKE_OP(subq, 32, ., a)
\r
10100 uint* r_dst = &AY;
\r
10102 *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));
\r
10106 M68KMAKE_OP(subq, 32, ., .)
\r
10108 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
10109 uint ea = M68KMAKE_GET_EA_AY_32;
\r
10110 uint dst = m68ki_read_32(ea);
\r
10111 uint res = dst - src;
\r
10113 FLAG_N = NFLAG_32(res);
\r
10114 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
10115 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
10116 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
10118 m68ki_write_32(ea, FLAG_Z);
\r
10122 M68KMAKE_OP(subx, 8, rr, .)
\r
10124 uint* r_dst = &DX;
\r
10125 uint src = MASK_OUT_ABOVE_8(DY);
\r
10126 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
10127 uint res = dst - src - XFLAG_AS_1();
\r
10129 FLAG_N = NFLAG_8(res);
\r
10130 FLAG_X = FLAG_C = CFLAG_8(res);
\r
10131 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
10133 res = MASK_OUT_ABOVE_8(res);
\r
10136 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
10140 M68KMAKE_OP(subx, 16, rr, .)
\r
10142 uint* r_dst = &DX;
\r
10143 uint src = MASK_OUT_ABOVE_16(DY);
\r
10144 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
10145 uint res = dst - src - XFLAG_AS_1();
\r
10147 FLAG_N = NFLAG_16(res);
\r
10148 FLAG_X = FLAG_C = CFLAG_16(res);
\r
10149 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
10151 res = MASK_OUT_ABOVE_16(res);
\r
10154 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
10158 M68KMAKE_OP(subx, 32, rr, .)
\r
10160 uint* r_dst = &DX;
\r
10162 uint dst = *r_dst;
\r
10163 uint res = dst - src - XFLAG_AS_1();
\r
10165 FLAG_N = NFLAG_32(res);
\r
10166 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
10167 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
10169 res = MASK_OUT_ABOVE_32(res);
\r
10176 M68KMAKE_OP(subx, 8, mm, ax7)
\r
10178 uint src = OPER_AY_PD_8();
\r
10179 uint ea = EA_A7_PD_8();
\r
10180 uint dst = m68ki_read_8(ea);
\r
10181 uint res = dst - src - XFLAG_AS_1();
\r
10183 FLAG_N = NFLAG_8(res);
\r
10184 FLAG_X = FLAG_C = CFLAG_8(res);
\r
10185 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
10187 res = MASK_OUT_ABOVE_8(res);
\r
10190 m68ki_write_8(ea, res);
\r
10194 M68KMAKE_OP(subx, 8, mm, ay7)
\r
10196 uint src = OPER_A7_PD_8();
\r
10197 uint ea = EA_AX_PD_8();
\r
10198 uint dst = m68ki_read_8(ea);
\r
10199 uint res = dst - src - XFLAG_AS_1();
\r
10201 FLAG_N = NFLAG_8(res);
\r
10202 FLAG_X = FLAG_C = CFLAG_8(res);
\r
10203 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
10205 res = MASK_OUT_ABOVE_8(res);
\r
10208 m68ki_write_8(ea, res);
\r
10212 M68KMAKE_OP(subx, 8, mm, axy7)
\r
10214 uint src = OPER_A7_PD_8();
\r
10215 uint ea = EA_A7_PD_8();
\r
10216 uint dst = m68ki_read_8(ea);
\r
10217 uint res = dst - src - XFLAG_AS_1();
\r
10219 FLAG_N = NFLAG_8(res);
\r
10220 FLAG_X = FLAG_C = CFLAG_8(res);
\r
10221 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
10223 res = MASK_OUT_ABOVE_8(res);
\r
10226 m68ki_write_8(ea, res);
\r
10230 M68KMAKE_OP(subx, 8, mm, .)
\r
10232 uint src = OPER_AY_PD_8();
\r
10233 uint ea = EA_AX_PD_8();
\r
10234 uint dst = m68ki_read_8(ea);
\r
10235 uint res = dst - src - XFLAG_AS_1();
\r
10237 FLAG_N = NFLAG_8(res);
\r
10238 FLAG_X = FLAG_C = CFLAG_8(res);
\r
10239 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
10241 res = MASK_OUT_ABOVE_8(res);
\r
10244 m68ki_write_8(ea, res);
\r
10248 M68KMAKE_OP(subx, 16, mm, .)
\r
10250 uint src = OPER_AY_PD_16();
\r
10251 uint ea = EA_AX_PD_16();
\r
10252 uint dst = m68ki_read_16(ea);
\r
10253 uint res = dst - src - XFLAG_AS_1();
\r
10255 FLAG_N = NFLAG_16(res);
\r
10256 FLAG_X = FLAG_C = CFLAG_16(res);
\r
10257 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
10259 res = MASK_OUT_ABOVE_16(res);
\r
10262 m68ki_write_16(ea, res);
\r
10266 M68KMAKE_OP(subx, 32, mm, .)
\r
10268 uint src = OPER_AY_PD_32();
\r
10269 uint ea = EA_AX_PD_32();
\r
10270 uint dst = m68ki_read_32(ea);
\r
10271 uint res = dst - src - XFLAG_AS_1();
\r
10273 FLAG_N = NFLAG_32(res);
\r
10274 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
10275 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
10277 res = MASK_OUT_ABOVE_32(res);
\r
10280 m68ki_write_32(ea, res);
\r
10284 M68KMAKE_OP(swap, 32, ., .)
\r
10286 uint* r_dst = &DY;
\r
10288 FLAG_Z = MASK_OUT_ABOVE_32(*r_dst<<16);
\r
10289 *r_dst = (*r_dst>>16) | FLAG_Z;
\r
10292 FLAG_N = NFLAG_32(*r_dst);
\r
10293 FLAG_C = CFLAG_CLEAR;
\r
10294 FLAG_V = VFLAG_CLEAR;
\r
10298 M68KMAKE_OP(tas, 8, ., d)
\r
10300 uint* r_dst = &DY;
\r
10302 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
\r
10303 FLAG_N = NFLAG_8(*r_dst);
\r
10304 FLAG_V = VFLAG_CLEAR;
\r
10305 FLAG_C = CFLAG_CLEAR;
\r
10310 M68KMAKE_OP(tas, 8, ., .)
\r
10312 uint ea = M68KMAKE_GET_EA_AY_8;
\r
10313 uint dst = m68ki_read_8(ea);
\r
10314 uint allow_writeback;
\r
10317 FLAG_N = NFLAG_8(dst);
\r
10318 FLAG_V = VFLAG_CLEAR;
\r
10319 FLAG_C = CFLAG_CLEAR;
\r
10321 /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback
\r
10322 disabled in order to function properly. Some Amiga software may also rely
\r
10323 on this, but only when accessing specific addresses so additional functionality
\r
10324 will be needed. */
\r
10325 allow_writeback = m68ki_tas_callback();
\r
10327 if (allow_writeback==1) m68ki_write_8(ea, dst | 0x80);
\r
10331 M68KMAKE_OP(trap, 0, ., .)
\r
10333 /* Trap#n stacks exception frame type 0 */
\r
10334 m68ki_exception_trapN(EXCEPTION_TRAP_BASE + (REG_IR & 0xf)); /* HJB 990403 */
\r
10338 M68KMAKE_OP(trapt, 0, ., .)
\r
10340 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10342 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
10345 m68ki_exception_illegal();
\r
10349 M68KMAKE_OP(trapt, 16, ., .)
\r
10351 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10353 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
10356 m68ki_exception_illegal();
\r
10360 M68KMAKE_OP(trapt, 32, ., .)
\r
10362 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10364 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
10367 m68ki_exception_illegal();
\r
10371 M68KMAKE_OP(trapf, 0, ., .)
\r
10373 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10377 m68ki_exception_illegal();
\r
10381 M68KMAKE_OP(trapf, 16, ., .)
\r
10383 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10388 m68ki_exception_illegal();
\r
10392 M68KMAKE_OP(trapf, 32, ., .)
\r
10394 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10399 m68ki_exception_illegal();
\r
10403 M68KMAKE_OP(trapcc, 0, ., .)
\r
10405 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10408 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
10411 m68ki_exception_illegal();
\r
10415 M68KMAKE_OP(trapcc, 16, ., .)
\r
10417 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10421 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
10427 m68ki_exception_illegal();
\r
10431 M68KMAKE_OP(trapcc, 32, ., .)
\r
10433 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10437 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
10443 m68ki_exception_illegal();
\r
10447 M68KMAKE_OP(trapv, 0, ., .)
\r
10453 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
10457 M68KMAKE_OP(tst, 8, ., d)
\r
10459 uint res = MASK_OUT_ABOVE_8(DY);
\r
10461 FLAG_N = NFLAG_8(res);
\r
10463 FLAG_V = VFLAG_CLEAR;
\r
10464 FLAG_C = CFLAG_CLEAR;
\r
10468 M68KMAKE_OP(tst, 8, ., .)
\r
10470 uint res = M68KMAKE_GET_OPER_AY_8;
\r
10472 FLAG_N = NFLAG_8(res);
\r
10474 FLAG_V = VFLAG_CLEAR;
\r
10475 FLAG_C = CFLAG_CLEAR;
\r
10479 M68KMAKE_OP(tst, 8, ., pcdi)
\r
10481 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10483 uint res = OPER_PCDI_8();
\r
10485 FLAG_N = NFLAG_8(res);
\r
10487 FLAG_V = VFLAG_CLEAR;
\r
10488 FLAG_C = CFLAG_CLEAR;
\r
10491 m68ki_exception_illegal();
\r
10495 M68KMAKE_OP(tst, 8, ., pcix)
\r
10497 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10499 uint res = OPER_PCIX_8();
\r
10501 FLAG_N = NFLAG_8(res);
\r
10503 FLAG_V = VFLAG_CLEAR;
\r
10504 FLAG_C = CFLAG_CLEAR;
\r
10507 m68ki_exception_illegal();
\r
10511 M68KMAKE_OP(tst, 8, ., i)
\r
10513 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10515 uint res = OPER_I_8();
\r
10517 FLAG_N = NFLAG_8(res);
\r
10519 FLAG_V = VFLAG_CLEAR;
\r
10520 FLAG_C = CFLAG_CLEAR;
\r
10523 m68ki_exception_illegal();
\r
10527 M68KMAKE_OP(tst, 16, ., d)
\r
10529 uint res = MASK_OUT_ABOVE_16(DY);
\r
10531 FLAG_N = NFLAG_16(res);
\r
10533 FLAG_V = VFLAG_CLEAR;
\r
10534 FLAG_C = CFLAG_CLEAR;
\r
10538 M68KMAKE_OP(tst, 16, ., a)
\r
10540 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10542 uint res = MAKE_INT_16(AY);
\r
10544 FLAG_N = NFLAG_16(res);
\r
10546 FLAG_V = VFLAG_CLEAR;
\r
10547 FLAG_C = CFLAG_CLEAR;
\r
10550 m68ki_exception_illegal();
\r
10554 M68KMAKE_OP(tst, 16, ., .)
\r
10556 uint res = M68KMAKE_GET_OPER_AY_16;
\r
10558 FLAG_N = NFLAG_16(res);
\r
10560 FLAG_V = VFLAG_CLEAR;
\r
10561 FLAG_C = CFLAG_CLEAR;
\r
10565 M68KMAKE_OP(tst, 16, ., pcdi)
\r
10567 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10569 uint res = OPER_PCDI_16();
\r
10571 FLAG_N = NFLAG_16(res);
\r
10573 FLAG_V = VFLAG_CLEAR;
\r
10574 FLAG_C = CFLAG_CLEAR;
\r
10577 m68ki_exception_illegal();
\r
10581 M68KMAKE_OP(tst, 16, ., pcix)
\r
10583 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10585 uint res = OPER_PCIX_16();
\r
10587 FLAG_N = NFLAG_16(res);
\r
10589 FLAG_V = VFLAG_CLEAR;
\r
10590 FLAG_C = CFLAG_CLEAR;
\r
10593 m68ki_exception_illegal();
\r
10597 M68KMAKE_OP(tst, 16, ., i)
\r
10599 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10601 uint res = OPER_I_16();
\r
10603 FLAG_N = NFLAG_16(res);
\r
10605 FLAG_V = VFLAG_CLEAR;
\r
10606 FLAG_C = CFLAG_CLEAR;
\r
10609 m68ki_exception_illegal();
\r
10613 M68KMAKE_OP(tst, 32, ., d)
\r
10617 FLAG_N = NFLAG_32(res);
\r
10619 FLAG_V = VFLAG_CLEAR;
\r
10620 FLAG_C = CFLAG_CLEAR;
\r
10624 M68KMAKE_OP(tst, 32, ., a)
\r
10626 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10630 FLAG_N = NFLAG_32(res);
\r
10632 FLAG_V = VFLAG_CLEAR;
\r
10633 FLAG_C = CFLAG_CLEAR;
\r
10636 m68ki_exception_illegal();
\r
10640 M68KMAKE_OP(tst, 32, ., .)
\r
10642 uint res = M68KMAKE_GET_OPER_AY_32;
\r
10644 FLAG_N = NFLAG_32(res);
\r
10646 FLAG_V = VFLAG_CLEAR;
\r
10647 FLAG_C = CFLAG_CLEAR;
\r
10651 M68KMAKE_OP(tst, 32, ., pcdi)
\r
10653 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10655 uint res = OPER_PCDI_32();
\r
10657 FLAG_N = NFLAG_32(res);
\r
10659 FLAG_V = VFLAG_CLEAR;
\r
10660 FLAG_C = CFLAG_CLEAR;
\r
10663 m68ki_exception_illegal();
\r
10667 M68KMAKE_OP(tst, 32, ., pcix)
\r
10669 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10671 uint res = OPER_PCIX_32();
\r
10673 FLAG_N = NFLAG_32(res);
\r
10675 FLAG_V = VFLAG_CLEAR;
\r
10676 FLAG_C = CFLAG_CLEAR;
\r
10679 m68ki_exception_illegal();
\r
10683 M68KMAKE_OP(tst, 32, ., i)
\r
10685 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10687 uint res = OPER_I_32();
\r
10689 FLAG_N = NFLAG_32(res);
\r
10691 FLAG_V = VFLAG_CLEAR;
\r
10692 FLAG_C = CFLAG_CLEAR;
\r
10695 m68ki_exception_illegal();
\r
10699 M68KMAKE_OP(unlk, 32, ., a7)
\r
10701 REG_A[7] = m68ki_read_32(REG_A[7]);
\r
10705 M68KMAKE_OP(unlk, 32, ., .)
\r
10707 uint* r_dst = &AY;
\r
10709 REG_A[7] = *r_dst;
\r
10710 *r_dst = m68ki_pull_32();
\r
10714 M68KMAKE_OP(unpk, 16, rr, .)
\r
10716 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10718 /* Note: DX and DY are reversed in Motorola's docs */
\r
10720 uint* r_dst = &DX;
\r
10722 *r_dst = MASK_OUT_BELOW_16(*r_dst) | (((((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16()) & 0xffff);
\r
10725 m68ki_exception_illegal();
\r
10729 M68KMAKE_OP(unpk, 16, mm, ax7)
\r
10731 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10733 /* Note: AX and AY are reversed in Motorola's docs */
\r
10734 uint src = OPER_AY_PD_8();
\r
10737 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
\r
10738 ea_dst = EA_A7_PD_8();
\r
10739 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
\r
10740 ea_dst = EA_A7_PD_8();
\r
10741 m68ki_write_8(ea_dst, src & 0xff);
\r
10744 m68ki_exception_illegal();
\r
10748 M68KMAKE_OP(unpk, 16, mm, ay7)
\r
10750 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10752 /* Note: AX and AY are reversed in Motorola's docs */
\r
10753 uint src = OPER_A7_PD_8();
\r
10756 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
\r
10757 ea_dst = EA_AX_PD_8();
\r
10758 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
\r
10759 ea_dst = EA_AX_PD_8();
\r
10760 m68ki_write_8(ea_dst, src & 0xff);
\r
10763 m68ki_exception_illegal();
\r
10767 M68KMAKE_OP(unpk, 16, mm, axy7)
\r
10769 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10771 uint src = OPER_A7_PD_8();
\r
10774 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
\r
10775 ea_dst = EA_A7_PD_8();
\r
10776 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
\r
10777 ea_dst = EA_A7_PD_8();
\r
10778 m68ki_write_8(ea_dst, src & 0xff);
\r
10781 m68ki_exception_illegal();
\r
10785 M68KMAKE_OP(unpk, 16, mm, .)
\r
10787 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10789 /* Note: AX and AY are reversed in Motorola's docs */
\r
10790 uint src = OPER_AY_PD_8();
\r
10793 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
\r
10794 ea_dst = EA_AX_PD_8();
\r
10795 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
\r
10796 ea_dst = EA_AX_PD_8();
\r
10797 m68ki_write_8(ea_dst, src & 0xff);
\r
10800 m68ki_exception_illegal();
\r
10805 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
\r
notaz.gp2x.de / picodrive.git / blob