2 * vim:shiftwidth=2:expandtab
9 #include "../../pico/pico_int.h"
12 #include "../drc/cmn.h"
20 #define dbg(l,...) { \
21 if ((l) & DRC_DEBUG) \
22 elprintf(EL_STATUS, ##__VA_ARGS__); \
25 #include "mame/sh2dasm.h"
26 #include <platform/linux/host_dasm.h>
27 static int insns_compiled, hash_collisions, host_insn_count;
36 static u8 *tcache_dsm_ptrs[3];
37 static char sh2dasm_buff[64];
38 #define do_host_disasm(tcid) \
39 host_dasm(tcache_dsm_ptrs[tcid], tcache_ptr - tcache_dsm_ptrs[tcid]); \
40 tcache_dsm_ptrs[tcid] = tcache_ptr
42 #define do_host_disasm(x)
46 static void REGPARM(3) *sh2_drc_announce_entry(void *block, SH2 *sh2, u32 sr)
49 dbg(4, "= %csh2 enter %08x %p, c=%d", sh2->is_slave ? 's' : 'm',
50 sh2->pc, block, (signed int)sr >> 12);
56 #define BLOCK_CYCLE_LIMIT 100
57 #define MAX_BLOCK_SIZE (BLOCK_CYCLE_LIMIT * 6 * 6)
59 // we have 3 translation cache buffers, split from one drc/cmn buffer.
60 // BIOS shares tcache with data array because it's only used for init
61 // and can be discarded early
62 // XXX: need to tune sizes
63 static const int tcache_sizes[3] = {
64 DRC_TCACHE_SIZE * 6 / 8, // ROM, DRAM
65 DRC_TCACHE_SIZE / 8, // BIOS, data array in master sh2
66 DRC_TCACHE_SIZE / 8, // ... slave
69 static u8 *tcache_bases[3];
70 static u8 *tcache_ptrs[3];
72 // ptr for code emiters
73 static u8 *tcache_ptr;
75 // host register tracking
78 HR_CACHED, // 'val' has sh2_reg_e
80 HR_CONST, // 'val' has constant
81 HR_TEMP, // reg used for temp storage
87 u16 stamp; // kind of a timestamp
91 // note: reg_temp[] must have at least the amount of
92 // registers used by handlers in worst case (currently 4)
94 #include "../drc/emit_arm.c"
96 static const int reg_map_g2h[] = {
105 static temp_reg_t reg_temp[] = {
114 #elif defined(__i386__)
115 #include "../drc/emit_x86.c"
117 static const int reg_map_g2h[] = {
126 // ax, cx, dx are usually temporaries by convention
127 static temp_reg_t reg_temp[] = {
135 #error unsupported arch
143 #define T_save 0x00000800
149 typedef struct block_desc_ {
150 u32 addr; // SH2 PC address
151 u32 end_addr; // TODO rm?
152 void *tcache_ptr; // translated block for above PC
153 struct block_desc_ *next; // next block with the same PC hash
159 static const int block_max_counts[3] = {
164 static block_desc *block_tables[3];
165 static int block_counts[3];
168 #define MAX_HASH_ENTRIES 1024
169 #define HASH_MASK (MAX_HASH_ENTRIES - 1)
170 static void **hash_table;
172 #define HASH_FUNC(hash_tab, addr) \
173 ((block_desc **)(hash_tab))[(addr) & HASH_MASK]
175 static void REGPARM(1) (*sh2_drc_entry)(SH2 *sh2);
176 static void (*sh2_drc_dispatcher)(void);
177 static void (*sh2_drc_exit)(void);
178 static void (*sh2_drc_test_irq)(void);
179 static void REGPARM(2) (*sh2_drc_write8)(u32 a, u32 d);
180 static void REGPARM(2) (*sh2_drc_write8_slot)(u32 a, u32 d);
181 static void REGPARM(2) (*sh2_drc_write16)(u32 a, u32 d);
182 static void REGPARM(2) (*sh2_drc_write16_slot)(u32 a, u32 d);
184 extern void REGPARM(2) sh2_do_op(SH2 *sh2, int opcode);
186 static void flush_tcache(int tcid)
188 dbg(1, "tcache #%d flush! (%d/%d, bds %d/%d)", tcid,
189 tcache_ptrs[tcid] - tcache_bases[tcid], tcache_sizes[tcid],
190 block_counts[tcid], block_max_counts[tcid]);
192 block_counts[tcid] = 0;
193 tcache_ptrs[tcid] = tcache_bases[tcid];
194 if (tcid == 0) { // ROM, RAM
195 memset(hash_table, 0, sizeof(hash_table[0]) * MAX_HASH_ENTRIES);
196 memset(Pico32xMem->drcblk_ram, 0, sizeof(Pico32xMem->drcblk_ram));
199 memset(Pico32xMem->drcblk_da[tcid - 1], 0, sizeof(Pico32xMem->drcblk_da[0]));
201 tcache_dsm_ptrs[tcid] = tcache_bases[tcid];
205 static void *dr_find_block(block_desc *tab, u32 addr)
207 for (tab = tab->next; tab != NULL; tab = tab->next)
208 if (tab->addr == addr)
212 return tab->tcache_ptr;
214 printf("block miss for %08x\n", addr);
218 static block_desc *dr_add_block(u32 addr, int tcache_id, int *blk_id)
220 int *bcount = &block_counts[tcache_id];
223 if (*bcount >= block_max_counts[tcache_id])
226 bd = &block_tables[tcache_id][*bcount];
228 bd->tcache_ptr = tcache_ptr;
232 if ((addr & 0xc6000000) == 0x02000000) { // ROM
233 bd->next = HASH_FUNC(hash_table, addr);
234 HASH_FUNC(hash_table, addr) = bd;
236 if (bd->next != NULL) {
237 printf(" hash collision with %08x\n", bd->next->addr);
246 int find_in_array(u32 *array, size_t size, u32 what)
249 for (i = 0; i < size; i++)
250 if (what == array[i])
256 // ---------------------------------------------------------------
259 static u16 rcache_counter;
261 static temp_reg_t *rcache_evict(void)
263 // evict reg with oldest stamp
265 u16 min_stamp = (u16)-1;
267 for (i = 0; i < ARRAY_SIZE(reg_temp); i++) {
268 if (reg_temp[i].type == HR_CACHED || reg_temp[i].type == HR_CACHED_DIRTY)
269 if (reg_temp[i].stamp <= min_stamp) {
270 min_stamp = reg_temp[i].stamp;
276 printf("no registers to evict, aborting\n");
281 if (reg_temp[i].type == HR_CACHED_DIRTY) {
283 emith_ctx_write(reg_temp[i].reg, reg_temp[i].val * 4);
295 // note: must not be called when doing conditional code
296 static int rcache_get_reg(sh2_reg_e r, rc_gr_mode mode)
301 // maybe already statically mapped?
308 // maybe already cached?
309 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
310 if ((reg_temp[i].type == HR_CACHED || reg_temp[i].type == HR_CACHED_DIRTY) &&
311 reg_temp[i].val == r)
313 reg_temp[i].stamp = rcache_counter;
314 if (mode != RC_GR_READ)
315 reg_temp[i].type = HR_CACHED_DIRTY;
316 return reg_temp[i].reg;
321 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
322 if (reg_temp[i].type == HR_FREE || reg_temp[i].type == HR_CONST) {
331 if (mode != RC_GR_WRITE)
332 emith_ctx_read(tr->reg, r * 4);
334 tr->type = mode != RC_GR_READ ? HR_CACHED_DIRTY : HR_CACHED;
336 tr->stamp = rcache_counter;
340 static int rcache_get_tmp(void)
345 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
346 if (reg_temp[i].type == HR_FREE || reg_temp[i].type == HR_CONST) {
358 static int rcache_get_arg_id(int arg)
361 host_arg2reg(r, arg);
363 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
364 if (reg_temp[i].reg == r)
367 if (i == ARRAY_SIZE(reg_temp))
368 // let's just say it's untracked arg reg
371 if (reg_temp[i].type == HR_CACHED_DIRTY) {
373 emith_ctx_write(reg_temp[i].reg, reg_temp[i].val * 4);
375 else if (reg_temp[i].type == HR_TEMP) {
376 printf("arg %d reg %d already used, aborting\n", arg, r);
383 // get a reg to be used as function arg
384 // it's assumed that regs are cleaned before call
385 static int rcache_get_tmp_arg(int arg)
387 int id = rcache_get_arg_id(arg);
388 reg_temp[id].type = HR_TEMP;
390 return reg_temp[id].reg;
393 // same but caches reg. RC_GR_READ only.
394 static int rcache_get_reg_arg(int arg, sh2_reg_e r)
396 int i, srcr, dstr, dstid;
398 dstid = rcache_get_arg_id(arg);
399 dstr = reg_temp[dstid].reg;
401 // maybe already statically mapped?
402 srcr = reg_map_g2h[r];
406 // maybe already cached?
407 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
408 if ((reg_temp[i].type == HR_CACHED || reg_temp[i].type == HR_CACHED_DIRTY) &&
409 reg_temp[i].val == r)
411 srcr = reg_temp[i].reg;
418 emith_ctx_read(srcr, r * 4);
422 emith_move_r_r(dstr, srcr);
424 reg_temp[dstid].stamp = ++rcache_counter;
425 reg_temp[dstid].type = HR_CACHED;
426 reg_temp[dstid].val = r;
430 static void rcache_free_tmp(int hr)
433 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
434 if (reg_temp[i].reg == hr)
437 if (i == ARRAY_SIZE(reg_temp) || reg_temp[i].type != HR_TEMP) {
438 printf("rcache_free_tmp fail: #%i hr %d, type %d\n", i, hr, reg_temp[i].type);
442 reg_temp[i].type = HR_FREE;
445 static void rcache_clean(void)
448 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
449 if (reg_temp[i].type == HR_CACHED_DIRTY) {
451 emith_ctx_write(reg_temp[i].reg, reg_temp[i].val * 4);
452 reg_temp[i].type = HR_CACHED;
456 static void rcache_invalidate(void)
459 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
460 reg_temp[i].type = HR_FREE;
464 static void rcache_flush(void)
470 // ---------------------------------------------------------------
472 static void emit_move_r_imm32(sh2_reg_e dst, u32 imm)
474 // TODO: propagate this constant
475 int hr = rcache_get_reg(dst, RC_GR_WRITE);
476 emith_move_r_imm(hr, imm);
479 static void emit_move_r_r(sh2_reg_e dst, sh2_reg_e src)
481 int hr_d = rcache_get_reg(dst, RC_GR_WRITE);
482 int hr_s = rcache_get_reg(src, RC_GR_READ);
484 emith_move_r_r(hr_d, hr_s);
487 // T must be clear, and comparison done just before this
488 static void emit_or_t_if_eq(int srr)
490 EMITH_SJMP_START(DCOND_NE);
491 emith_or_r_imm_c(DCOND_EQ, srr, T);
492 EMITH_SJMP_END(DCOND_NE);
495 // arguments must be ready
496 // reg cache must be clean before call
497 static int emit_memhandler_read(int size)
500 host_arg2reg(ctxr, 1);
501 emith_move_r_r(ctxr, CONTEXT_REG);
504 // must writeback cycles for poll detection stuff
505 if (reg_map_g2h[SHR_SR] != -1)
506 emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
507 emith_call(p32x_sh2_read8);
510 if (reg_map_g2h[SHR_SR] != -1)
511 emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
512 emith_call(p32x_sh2_read16);
515 emith_call(p32x_sh2_read32);
519 // assuming arg0 and retval reg matches
520 return rcache_get_tmp_arg(0);
523 static void emit_memhandler_write(int size, u32 pc, int delay)
526 host_arg2reg(ctxr, 2);
529 // XXX: consider inlining sh2_drc_write8
531 emith_call(sh2_drc_write8_slot);
533 emit_move_r_imm32(SHR_PC, pc);
535 emith_call(sh2_drc_write8);
540 emith_call(sh2_drc_write16_slot);
542 emit_move_r_imm32(SHR_PC, pc);
544 emith_call(sh2_drc_write16);
548 emith_move_r_r(ctxr, CONTEXT_REG);
549 emith_call(p32x_sh2_write32);
556 static int emit_indirect_indexed_read(int rx, int ry, int size)
560 a0 = rcache_get_reg_arg(0, rx);
561 t = rcache_get_reg(ry, RC_GR_READ);
562 emith_add_r_r(a0, t);
563 return emit_memhandler_read(size);
567 static void emit_indirect_read_double(u32 *rnr, u32 *rmr, int rn, int rm, int size)
572 rcache_get_reg_arg(0, rn);
573 tmp = emit_memhandler_read(size);
574 emith_ctx_write(tmp, offsetof(SH2, drc_tmp));
575 rcache_free_tmp(tmp);
576 tmp = rcache_get_reg(rn, RC_GR_RMW);
577 emith_add_r_imm(tmp, 1 << size);
580 rcache_get_reg_arg(0, rm);
581 *rmr = emit_memhandler_read(size);
582 *rnr = rcache_get_tmp();
583 emith_ctx_read(*rnr, offsetof(SH2, drc_tmp));
584 tmp = rcache_get_reg(rm, RC_GR_RMW);
585 emith_add_r_imm(tmp, 1 << size);
588 static void emit_do_static_regs(int is_write, int tmpr)
592 for (i = 0; i < ARRAY_SIZE(reg_map_g2h); i++) {
597 for (count = 1; i < ARRAY_SIZE(reg_map_g2h) - 1; i++, r++) {
598 if (reg_map_g2h[i + 1] != r + 1)
604 // i, r point to last item
606 emith_ctx_write_multiple(r - count + 1, (i - count + 1) * 4, count, tmpr);
608 emith_ctx_read_multiple(r - count + 1, (i - count + 1) * 4, count, tmpr);
611 emith_ctx_write(r, i * 4);
613 emith_ctx_read(r, i * 4);
618 static void emit_block_entry(void)
620 int arg0, arg1, arg2;
622 host_arg2reg(arg0, 0);
623 host_arg2reg(arg1, 1);
624 host_arg2reg(arg2, 2);
627 emith_move_r_r(arg1, CONTEXT_REG);
628 emith_move_r_r(arg2, rcache_get_reg(SHR_SR, RC_GR_READ));
629 emith_call(sh2_drc_announce_entry);
632 emith_tst_r_r(arg0, arg0);
633 EMITH_SJMP_START(DCOND_EQ);
634 emith_jump_reg_c(DCOND_NE, arg0);
635 EMITH_SJMP_END(DCOND_EQ);
638 static void REGPARM(3) *lookup_block(u32 pc, int is_slave, int *tcache_id)
640 block_desc *bd = NULL;
644 // we have full block id tables for data_array and RAM
645 // BIOS goes to data_array table too
646 if ((pc & 0xe0000000) == 0xc0000000 || (pc & ~0xfff) == 0) {
647 int blkid = Pico32xMem->drcblk_da[is_slave][(pc & 0xfff) >> SH2_DRCBLK_DA_SHIFT];
648 *tcache_id = 1 + is_slave;
650 bd = &block_tables[*tcache_id][blkid >> 1];
651 block = bd->tcache_ptr;
655 else if ((pc & 0xc6000000) == 0x06000000) {
656 int blkid = Pico32xMem->drcblk_ram[(pc & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT];
658 bd = &block_tables[0][blkid >> 1];
659 block = bd->tcache_ptr;
663 else if ((pc & 0xc6000000) == 0x02000000) {
664 bd = HASH_FUNC(hash_table, pc);
668 block = bd->tcache_ptr;
670 block = dr_find_block(bd, pc);
684 #define DELAY_SAVE_T(sr) { \
685 emith_bic_r_imm(sr, T_save); \
686 emith_tst_r_imm(sr, T); \
687 EMITH_SJMP_START(DCOND_EQ); \
688 emith_or_r_imm_c(DCOND_NE, sr, T_save); \
689 EMITH_SJMP_END(DCOND_EQ); \
690 drcf.use_saved_t = 1; \
693 #define FLUSH_CYCLES(sr) \
695 emith_sub_r_imm(sr, cycles << 12); \
699 #define CHECK_UNHANDLED_BITS(mask) { \
700 if ((op & (mask)) != 0) \
707 #define GET_Rm GET_Fx
712 #define CHECK_FX_LT(n) \
716 #define MAX_LOCAL_BRANCHES 16
718 // op_flags: data from 1st pass
719 #define OP_FLAGS(pc) op_flags[((pc) - base_pc) / 2]
720 #define OF_DELAY_OP (1 << 0)
722 static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
724 // XXX: maybe use structs instead?
725 void *branch_target_ptr[MAX_LOCAL_BRANCHES];
726 u32 branch_target_pc[MAX_LOCAL_BRANCHES];
727 int branch_target_count = 0;
728 void *branch_patch_ptr[MAX_LOCAL_BRANCHES];
729 u32 branch_patch_pc[MAX_LOCAL_BRANCHES];
730 int branch_patch_count = 0;
731 int branch_patch_cond = -1;
732 u8 op_flags[BLOCK_CYCLE_LIMIT + 1];
736 u32 use_saved_t:1; // delayed op modifies T
740 block_desc *this_block;
741 u32 pc, base_pc, end_pc; // PC of current, first, last insn
752 if ((tmp != 0 && tmp != 1 && tmp != 6) || base_pc == 0) {
753 printf("invalid PC, aborting: %08x\n", base_pc);
754 // FIXME: be less destructive
758 tcache_ptr = tcache_ptrs[tcache_id];
759 this_block = dr_add_block(base_pc, tcache_id, &blkid_main);
761 // predict tcache overflow
762 tmp = tcache_ptr - tcache_bases[tcache_id];
763 if (tmp > tcache_sizes[tcache_id] - MAX_BLOCK_SIZE || this_block == NULL)
766 block_entry = tcache_ptr;
767 dbg(1, "== %csh2 block #%d,%d %08x -> %p", sh2->is_slave ? 's' : 'm',
768 tcache_id, blkid_main, base_pc, block_entry);
770 // 1st pass: scan forward for local branches
771 memset(op_flags, 0, sizeof(op_flags));
772 for (cycles = 0, pc = base_pc; cycles < BLOCK_CYCLE_LIMIT; cycles++, pc += 2) {
773 op = p32x_sh2_read16(pc, sh2);
774 if ((op & 0xf000) == 0xa000 || (op & 0xf000) == 0xb000) { // BRA, BSR
776 OP_FLAGS(pc) |= OF_DELAY_OP;
779 if ((op & 0xf000) == 0) {
781 if (op == 0x23 || op == 0x03 || op == 0x0b) { // BRAF, BSRF, RTS
783 OP_FLAGS(pc) |= OF_DELAY_OP;
788 if ((op & 0xf0df) == 0x400b) { // JMP, JSR
790 OP_FLAGS(pc) |= OF_DELAY_OP;
793 if ((op & 0xf900) == 0x8900) { // BT(S), BF(S)
794 signed int offs = ((signed int)(op << 24) >> 23);
796 OP_FLAGS(pc + 2) |= OF_DELAY_OP;
797 branch_target_pc[branch_target_count++] = pc + offs + 4;
798 if (branch_target_count == MAX_LOCAL_BRANCHES) {
799 printf("warning: branch target overflow\n");
800 // will only spawn additional blocks
808 // clean branch_targets that are not really local,
809 // and that land on delay slots
810 for (i = 0, tmp = 0; i < branch_target_count; i++) {
811 pc = branch_target_pc[i];
812 if (base_pc <= pc && pc <= end_pc && !(OP_FLAGS(pc) & OF_DELAY_OP))
813 branch_target_pc[tmp++] = branch_target_pc[i];
815 branch_target_count = tmp;
816 memset(branch_target_ptr, 0, sizeof(branch_target_ptr[0]) * branch_target_count);
818 // -------------------------------------------------
819 // 2nd pass: actual compilation
821 for (cycles = 0; pc <= end_pc || drcf.delayed_op; )
825 if (drcf.delayed_op > 0)
828 i = find_in_array(branch_target_pc, branch_target_count, pc);
833 /* make "subblock" - just a mid-block entry */
834 block_desc *subblock;
838 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
841 do_host_disasm(tcache_id);
843 subblock = dr_add_block(pc, tcache_id, &blkid);
844 if (subblock == NULL)
846 subblock->end_addr = pc;
848 if (tcache_id != 0) { // data array, BIOS
849 drcblk = Pico32xMem->drcblk_da[sh2->is_slave];
850 drcblk += (pc & 0x00fff) >> SH2_DRCBLK_DA_SHIFT;
851 *drcblk = (blkid << 1) | 1;
852 } else if ((this_block->addr & 0xc7fc0000) == 0x06000000) { // DRAM
853 drcblk = Pico32xMem->drcblk_ram;
854 drcblk += (pc & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT;
855 *drcblk = (blkid << 1) | 1;
858 dbg(1, "=== %csh2 subblock #%d,%d %08x -> %p", sh2->is_slave ? 's' : 'm',
859 tcache_id, blkid, pc, tcache_ptr);
861 branch_target_ptr[i] = tcache_ptr;
864 emit_move_r_imm32(SHR_PC, pc);
868 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
869 emith_cmp_r_imm(sr, 0);
870 emith_jump_cond(DCOND_LE, sh2_drc_exit);
873 op = p32x_sh2_read16(pc, sh2);
878 DasmSH2(sh2dasm_buff, pc, op);
879 printf("%08x %04x %s\n", pc, op, sh2dasm_buff);
886 switch ((op >> 12) & 0x0f)
888 /////////////////////////////////////////////
893 tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
896 case 0: // STC SR,Rn 0000nnnn00000010
899 case 1: // STC GBR,Rn 0000nnnn00010010
902 case 2: // STC VBR,Rn 0000nnnn00100010
908 tmp3 = rcache_get_reg(tmp2, RC_GR_READ);
909 emith_move_r_r(tmp, tmp3);
911 emith_clear_msb(tmp, tmp, 22); // reserved bits defined by ISA as 0
914 CHECK_UNHANDLED_BITS(0xd0);
915 // BRAF Rm 0000mmmm00100011
916 // BSRF Rm 0000mmmm00000011
918 tmp = rcache_get_reg(SHR_PC, RC_GR_WRITE);
919 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
920 emith_move_r_r(tmp, tmp2);
922 emith_add_r_imm(tmp, pc + 2);
924 tmp3 = rcache_get_reg(SHR_PR, RC_GR_WRITE);
925 emith_move_r_imm(tmp3, pc + 2);
926 emith_add_r_r(tmp, tmp3);
930 case 0x04: // MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100
931 case 0x05: // MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101
932 case 0x06: // MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110
934 tmp = rcache_get_reg_arg(1, GET_Rm());
935 tmp2 = rcache_get_reg_arg(0, SHR_R0);
936 tmp3 = rcache_get_reg(GET_Rn(), RC_GR_READ);
937 emith_add_r_r(tmp2, tmp3);
938 emit_memhandler_write(op & 3, pc, drcf.delayed_op);
941 // MUL.L Rm,Rn 0000nnnnmmmm0111
942 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
943 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
944 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
945 emith_mul(tmp3, tmp2, tmp);
949 CHECK_UNHANDLED_BITS(0xf00);
952 case 0: // CLRT 0000000000001000
953 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
956 emith_bic_r_imm(sr, T);
958 case 1: // SETT 0000000000011000
959 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
962 emith_or_r_imm(sr, T);
964 case 2: // CLRMAC 0000000000101000
965 tmp = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
966 emith_move_r_imm(tmp, 0);
967 tmp = rcache_get_reg(SHR_MACH, RC_GR_WRITE);
968 emith_move_r_imm(tmp, 0);
977 case 0: // NOP 0000000000001001
978 CHECK_UNHANDLED_BITS(0xf00);
980 case 1: // DIV0U 0000000000011001
981 CHECK_UNHANDLED_BITS(0xf00);
982 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
985 emith_bic_r_imm(sr, M|Q|T);
987 case 2: // MOVT Rn 0000nnnn00101001
988 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
989 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
990 emith_clear_msb(tmp2, sr, 31);
997 tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1000 case 0: // STS MACH,Rn 0000nnnn00001010
1003 case 1: // STS MACL,Rn 0000nnnn00011010
1006 case 2: // STS PR,Rn 0000nnnn00101010
1012 tmp2 = rcache_get_reg(tmp2, RC_GR_READ);
1013 emith_move_r_r(tmp, tmp2);
1016 CHECK_UNHANDLED_BITS(0xf00);
1019 case 0: // RTS 0000000000001011
1021 emit_move_r_r(SHR_PC, SHR_PR);
1024 case 1: // SLEEP 0000000000011011
1025 emit_move_r_imm32(SHR_PC, pc - 2);
1026 tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
1027 emith_clear_msb(tmp, tmp, 20); // clear cycles
1030 case 2: // RTE 0000000000101011
1034 rcache_get_reg_arg(0, SHR_SP);
1035 tmp = emit_memhandler_read(2);
1036 tmp2 = rcache_get_reg(SHR_PC, RC_GR_WRITE);
1037 emith_move_r_r(tmp2, tmp);
1038 rcache_free_tmp(tmp);
1041 tmp = rcache_get_reg_arg(0, SHR_SP);
1042 emith_add_r_imm(tmp, 4);
1043 tmp = emit_memhandler_read(2);
1044 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1045 emith_write_sr(sr, tmp);
1046 rcache_free_tmp(tmp);
1047 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
1048 emith_add_r_imm(tmp, 4*2);
1056 case 0x0c: // MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100
1057 case 0x0d: // MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101
1058 case 0x0e: // MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110
1059 tmp = emit_indirect_indexed_read(SHR_R0, GET_Rm(), op & 3);
1060 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1061 if ((op & 3) != 2) {
1062 emith_sext(tmp2, tmp, (op & 1) ? 16 : 8);
1064 emith_move_r_r(tmp2, tmp);
1065 rcache_free_tmp(tmp);
1067 case 0x0f: // MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111
1068 emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 2);
1069 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1070 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW);
1071 /* MS 16 MAC bits unused if saturated */
1072 emith_tst_r_imm(sr, S);
1073 EMITH_SJMP_START(DCOND_EQ);
1074 emith_clear_msb_c(DCOND_NE, tmp4, tmp4, 16);
1075 EMITH_SJMP_END(DCOND_EQ);
1076 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW); // might evict SR
1077 emith_mula_s64(tmp3, tmp4, tmp, tmp2);
1078 rcache_free_tmp(tmp2);
1079 sr = rcache_get_reg(SHR_SR, RC_GR_READ); // reget just in case
1080 emith_tst_r_imm(sr, S);
1082 EMITH_JMP_START(DCOND_EQ);
1083 emith_asr(tmp, tmp4, 15);
1084 emith_cmp_r_imm(tmp, -1); // negative overflow (0x80000000..0xffff7fff)
1085 EMITH_SJMP_START(DCOND_GE);
1086 emith_move_r_imm_c(DCOND_LT, tmp4, 0x8000);
1087 emith_move_r_imm_c(DCOND_LT, tmp3, 0x0000);
1088 EMITH_SJMP_END(DCOND_GE);
1089 emith_cmp_r_imm(tmp, 0); // positive overflow (0x00008000..0x7fffffff)
1090 EMITH_SJMP_START(DCOND_LE);
1091 emith_move_r_imm_c(DCOND_GT, tmp4, 0x00007fff);
1092 emith_move_r_imm_c(DCOND_GT, tmp3, 0xffffffff);
1093 EMITH_SJMP_END(DCOND_LE);
1094 EMITH_JMP_END(DCOND_EQ);
1096 rcache_free_tmp(tmp);
1102 /////////////////////////////////////////////
1104 // MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd
1106 tmp = rcache_get_reg_arg(0, GET_Rn());
1107 tmp2 = rcache_get_reg_arg(1, GET_Rm());
1108 emith_add_r_imm(tmp, (op & 0x0f) * 4);
1109 emit_memhandler_write(2, pc, drcf.delayed_op);
1115 case 0x00: // MOV.B Rm,@Rn 0010nnnnmmmm0000
1116 case 0x01: // MOV.W Rm,@Rn 0010nnnnmmmm0001
1117 case 0x02: // MOV.L Rm,@Rn 0010nnnnmmmm0010
1119 rcache_get_reg_arg(0, GET_Rn());
1120 rcache_get_reg_arg(1, GET_Rm());
1121 emit_memhandler_write(op & 3, pc, drcf.delayed_op);
1123 case 0x04: // MOV.B Rm,@–Rn 0010nnnnmmmm0100
1124 case 0x05: // MOV.W Rm,@–Rn 0010nnnnmmmm0101
1125 case 0x06: // MOV.L Rm,@–Rn 0010nnnnmmmm0110
1126 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1127 emith_sub_r_imm(tmp, (1 << (op & 3)));
1129 rcache_get_reg_arg(0, GET_Rn());
1130 rcache_get_reg_arg(1, GET_Rm());
1131 emit_memhandler_write(op & 3, pc, drcf.delayed_op);
1133 case 0x07: // DIV0S Rm,Rn 0010nnnnmmmm0111
1134 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1135 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1136 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1137 if (drcf.delayed_op)
1139 emith_bic_r_imm(sr, M|Q|T);
1140 emith_tst_r_imm(tmp2, (1<<31));
1141 EMITH_SJMP_START(DCOND_EQ);
1142 emith_or_r_imm_c(DCOND_NE, sr, Q);
1143 EMITH_SJMP_END(DCOND_EQ);
1144 emith_tst_r_imm(tmp3, (1<<31));
1145 EMITH_SJMP_START(DCOND_EQ);
1146 emith_or_r_imm_c(DCOND_NE, sr, M);
1147 EMITH_SJMP_END(DCOND_EQ);
1148 emith_teq_r_r(tmp2, tmp3);
1149 EMITH_SJMP_START(DCOND_PL);
1150 emith_or_r_imm_c(DCOND_MI, sr, T);
1151 EMITH_SJMP_END(DCOND_PL);
1153 case 0x08: // TST Rm,Rn 0010nnnnmmmm1000
1154 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1155 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1156 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1157 if (drcf.delayed_op)
1159 emith_bic_r_imm(sr, T);
1160 emith_tst_r_r(tmp2, tmp3);
1161 emit_or_t_if_eq(sr);
1163 case 0x09: // AND Rm,Rn 0010nnnnmmmm1001
1164 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1165 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1166 emith_and_r_r(tmp, tmp2);
1168 case 0x0a: // XOR Rm,Rn 0010nnnnmmmm1010
1169 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1170 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1171 emith_eor_r_r(tmp, tmp2);
1173 case 0x0b: // OR Rm,Rn 0010nnnnmmmm1011
1174 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1175 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1176 emith_or_r_r(tmp, tmp2);
1178 case 0x0c: // CMP/STR Rm,Rn 0010nnnnmmmm1100
1179 tmp = rcache_get_tmp();
1180 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1181 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1182 emith_eor_r_r_r(tmp, tmp2, tmp3);
1183 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1184 if (drcf.delayed_op)
1186 emith_bic_r_imm(sr, T);
1187 emith_tst_r_imm(tmp, 0x000000ff);
1188 emit_or_t_if_eq(tmp);
1189 emith_tst_r_imm(tmp, 0x0000ff00);
1190 emit_or_t_if_eq(tmp);
1191 emith_tst_r_imm(tmp, 0x00ff0000);
1192 emit_or_t_if_eq(tmp);
1193 emith_tst_r_imm(tmp, 0xff000000);
1194 emit_or_t_if_eq(tmp);
1195 rcache_free_tmp(tmp);
1197 case 0x0d: // XTRCT Rm,Rn 0010nnnnmmmm1101
1198 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1199 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1200 emith_lsr(tmp, tmp, 16);
1201 emith_or_r_r_lsl(tmp, tmp2, 16);
1203 case 0x0e: // MULU.W Rm,Rn 0010nnnnmmmm1110
1204 case 0x0f: // MULS.W Rm,Rn 0010nnnnmmmm1111
1205 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1206 tmp = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1208 emith_sext(tmp, tmp2, 16);
1210 emith_clear_msb(tmp, tmp2, 16);
1211 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1212 tmp2 = rcache_get_tmp();
1214 emith_sext(tmp2, tmp3, 16);
1216 emith_clear_msb(tmp2, tmp3, 16);
1217 emith_mul(tmp, tmp, tmp2);
1218 rcache_free_tmp(tmp2);
1219 // FIXME: causes timing issues in Doom?
1225 /////////////////////////////////////////////
1229 case 0x00: // CMP/EQ Rm,Rn 0011nnnnmmmm0000
1230 case 0x02: // CMP/HS Rm,Rn 0011nnnnmmmm0010
1231 case 0x03: // CMP/GE Rm,Rn 0011nnnnmmmm0011
1232 case 0x06: // CMP/HI Rm,Rn 0011nnnnmmmm0110
1233 case 0x07: // CMP/GT Rm,Rn 0011nnnnmmmm0111
1234 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1235 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1236 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1237 if (drcf.delayed_op)
1239 emith_bic_r_imm(sr, T);
1240 emith_cmp_r_r(tmp2, tmp3);
1243 case 0x00: // CMP/EQ
1244 emit_or_t_if_eq(sr);
1246 case 0x02: // CMP/HS
1247 EMITH_SJMP_START(DCOND_LO);
1248 emith_or_r_imm_c(DCOND_HS, sr, T);
1249 EMITH_SJMP_END(DCOND_LO);
1251 case 0x03: // CMP/GE
1252 EMITH_SJMP_START(DCOND_LT);
1253 emith_or_r_imm_c(DCOND_GE, sr, T);
1254 EMITH_SJMP_END(DCOND_LT);
1256 case 0x06: // CMP/HI
1257 EMITH_SJMP_START(DCOND_LS);
1258 emith_or_r_imm_c(DCOND_HI, sr, T);
1259 EMITH_SJMP_END(DCOND_LS);
1261 case 0x07: // CMP/GT
1262 EMITH_SJMP_START(DCOND_LE);
1263 emith_or_r_imm_c(DCOND_GT, sr, T);
1264 EMITH_SJMP_END(DCOND_LE);
1268 case 0x04: // DIV1 Rm,Rn 0011nnnnmmmm0100
1269 // Q1 = carry(Rn = (Rn << 1) | T)
1271 // Q2 = carry(Rn += Rm)
1273 // Q2 = carry(Rn -= Rm)
1275 // T = (Q == M) = !(Q ^ M) = !(Q1 ^ Q2)
1276 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1277 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1278 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1279 if (drcf.delayed_op)
1281 emith_tpop_carry(sr, 0);
1282 emith_adcf_r_r(tmp2, tmp2);
1283 emith_tpush_carry(sr, 0); // keep Q1 in T for now
1284 tmp4 = rcache_get_tmp();
1285 emith_and_r_r_imm(tmp4, sr, M);
1286 emith_eor_r_r_lsr(sr, tmp4, M_SHIFT - Q_SHIFT); // Q ^= M
1287 rcache_free_tmp(tmp4);
1288 // add or sub, invert T if carry to get Q1 ^ Q2
1289 // in: (Q ^ M) passed in Q, Q1 in T
1290 emith_sh2_div1_step(tmp2, tmp3, sr);
1291 emith_bic_r_imm(sr, Q);
1292 emith_tst_r_imm(sr, M);
1293 EMITH_SJMP_START(DCOND_EQ);
1294 emith_or_r_imm_c(DCOND_NE, sr, Q); // Q = M
1295 EMITH_SJMP_END(DCOND_EQ);
1296 emith_tst_r_imm(sr, T);
1297 EMITH_SJMP_START(DCOND_EQ);
1298 emith_eor_r_imm_c(DCOND_NE, sr, Q); // Q = M ^ Q1 ^ Q2
1299 EMITH_SJMP_END(DCOND_EQ);
1300 emith_eor_r_imm(sr, T); // T = !(Q1 ^ Q2)
1302 case 0x05: // DMULU.L Rm,Rn 0011nnnnmmmm0101
1303 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
1304 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1305 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1306 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE);
1307 emith_mul_u64(tmp3, tmp4, tmp, tmp2);
1309 case 0x08: // SUB Rm,Rn 0011nnnnmmmm1000
1310 case 0x0c: // ADD Rm,Rn 0011nnnnmmmm1100
1311 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1312 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1314 emith_add_r_r(tmp, tmp2);
1316 emith_sub_r_r(tmp, tmp2);
1318 case 0x0a: // SUBC Rm,Rn 0011nnnnmmmm1010
1319 case 0x0e: // ADDC Rm,Rn 0011nnnnmmmm1110
1320 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1321 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1322 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1323 if (drcf.delayed_op)
1325 if (op & 4) { // adc
1326 emith_tpop_carry(sr, 0);
1327 emith_adcf_r_r(tmp, tmp2);
1328 emith_tpush_carry(sr, 0);
1330 emith_tpop_carry(sr, 1);
1331 emith_sbcf_r_r(tmp, tmp2);
1332 emith_tpush_carry(sr, 1);
1335 case 0x0b: // SUBV Rm,Rn 0011nnnnmmmm1011
1336 case 0x0f: // ADDV Rm,Rn 0011nnnnmmmm1111
1337 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1338 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1339 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1340 if (drcf.delayed_op)
1342 emith_bic_r_imm(sr, T);
1344 emith_addf_r_r(tmp, tmp2);
1346 emith_subf_r_r(tmp, tmp2);
1347 EMITH_SJMP_START(DCOND_VC);
1348 emith_or_r_imm_c(DCOND_VS, sr, T);
1349 EMITH_SJMP_END(DCOND_VC);
1351 case 0x0d: // DMULS.L Rm,Rn 0011nnnnmmmm1101
1352 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
1353 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1354 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1355 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE);
1356 emith_mul_s64(tmp3, tmp4, tmp, tmp2);
1361 /////////////////////////////////////////////
1368 case 0: // SHLL Rn 0100nnnn00000000
1369 case 2: // SHAL Rn 0100nnnn00100000
1370 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1371 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1372 if (drcf.delayed_op)
1374 emith_tpop_carry(sr, 0); // dummy
1375 emith_lslf(tmp, tmp, 1);
1376 emith_tpush_carry(sr, 0);
1378 case 1: // DT Rn 0100nnnn00010000
1379 if (p32x_sh2_read16(pc, sh2) == 0x8bfd) { // BF #-2
1380 emith_sh2_dtbf_loop();
1383 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1384 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1385 if (drcf.delayed_op)
1387 emith_bic_r_imm(sr, T);
1388 emith_subf_r_imm(tmp, 1);
1389 emit_or_t_if_eq(sr);
1396 case 0: // SHLR Rn 0100nnnn00000001
1397 case 2: // SHAR Rn 0100nnnn00100001
1398 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1399 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1400 if (drcf.delayed_op)
1402 emith_tpop_carry(sr, 0); // dummy
1404 emith_asrf(tmp, tmp, 1);
1406 emith_lsrf(tmp, tmp, 1);
1407 emith_tpush_carry(sr, 0);
1409 case 1: // CMP/PZ Rn 0100nnnn00010001
1410 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1411 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1412 if (drcf.delayed_op)
1414 emith_bic_r_imm(sr, T);
1415 emith_cmp_r_imm(tmp, 0);
1416 EMITH_SJMP_START(DCOND_LT);
1417 emith_or_r_imm_c(DCOND_GE, sr, T);
1418 EMITH_SJMP_END(DCOND_LT);
1426 case 0x02: // STS.L MACH,@–Rn 0100nnnn00000010
1429 case 0x12: // STS.L MACL,@–Rn 0100nnnn00010010
1432 case 0x22: // STS.L PR,@–Rn 0100nnnn00100010
1435 case 0x03: // STC.L SR,@–Rn 0100nnnn00000011
1438 case 0x13: // STC.L GBR,@–Rn 0100nnnn00010011
1441 case 0x23: // STC.L VBR,@–Rn 0100nnnn00100011
1447 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1448 emith_sub_r_imm(tmp2, 4);
1450 rcache_get_reg_arg(0, GET_Rn());
1451 tmp3 = rcache_get_reg_arg(1, tmp);
1453 emith_clear_msb(tmp3, tmp3, 22); // reserved bits defined by ISA as 0
1454 emit_memhandler_write(2, pc, drcf.delayed_op);
1460 case 0x04: // ROTL Rn 0100nnnn00000100
1461 case 0x05: // ROTR Rn 0100nnnn00000101
1462 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1463 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1464 if (drcf.delayed_op)
1466 emith_tpop_carry(sr, 0); // dummy
1468 emith_rorf(tmp, tmp, 1);
1470 emith_rolf(tmp, tmp, 1);
1471 emith_tpush_carry(sr, 0);
1473 case 0x24: // ROTCL Rn 0100nnnn00100100
1474 case 0x25: // ROTCR Rn 0100nnnn00100101
1475 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1476 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1477 if (drcf.delayed_op)
1479 emith_tpop_carry(sr, 0);
1484 emith_tpush_carry(sr, 0);
1486 case 0x15: // CMP/PL Rn 0100nnnn00010101
1487 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1488 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1489 if (drcf.delayed_op)
1491 emith_bic_r_imm(sr, T);
1492 emith_cmp_r_imm(tmp, 0);
1493 EMITH_SJMP_START(DCOND_LE);
1494 emith_or_r_imm_c(DCOND_GT, sr, T);
1495 EMITH_SJMP_END(DCOND_LE);
1503 case 0x06: // LDS.L @Rm+,MACH 0100mmmm00000110
1506 case 0x16: // LDS.L @Rm+,MACL 0100mmmm00010110
1509 case 0x26: // LDS.L @Rm+,PR 0100mmmm00100110
1512 case 0x07: // LDC.L @Rm+,SR 0100mmmm00000111
1515 case 0x17: // LDC.L @Rm+,GBR 0100mmmm00010111
1518 case 0x27: // LDC.L @Rm+,VBR 0100mmmm00100111
1525 rcache_get_reg_arg(0, GET_Rn());
1526 tmp2 = emit_memhandler_read(2);
1527 if (tmp == SHR_SR) {
1528 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1529 if (drcf.delayed_op)
1531 emith_write_sr(sr, tmp2);
1534 tmp = rcache_get_reg(tmp, RC_GR_WRITE);
1535 emith_move_r_r(tmp, tmp2);
1537 rcache_free_tmp(tmp2);
1538 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1539 emith_add_r_imm(tmp, 4);
1546 // SHLL2 Rn 0100nnnn00001000
1547 // SHLR2 Rn 0100nnnn00001001
1551 // SHLL8 Rn 0100nnnn00011000
1552 // SHLR8 Rn 0100nnnn00011001
1556 // SHLL16 Rn 0100nnnn00101000
1557 // SHLR16 Rn 0100nnnn00101001
1563 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1565 emith_lsr(tmp2, tmp2, tmp);
1567 emith_lsl(tmp2, tmp2, tmp);
1572 case 0: // LDS Rm,MACH 0100mmmm00001010
1575 case 1: // LDS Rm,MACL 0100mmmm00011010
1578 case 2: // LDS Rm,PR 0100mmmm00101010
1584 emit_move_r_r(tmp2, GET_Rn());
1589 case 0: // JSR @Rm 0100mmmm00001011
1590 case 2: // JMP @Rm 0100mmmm00101011
1593 emit_move_r_imm32(SHR_PR, pc + 2);
1594 emit_move_r_r(SHR_PC, (op >> 8) & 0x0f);
1597 case 1: // TAS.B @Rn 0100nnnn00011011
1598 // XXX: is TAS working on 32X?
1600 rcache_get_reg_arg(0, GET_Rn());
1601 tmp = emit_memhandler_read(0);
1602 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1603 if (drcf.delayed_op)
1605 emith_bic_r_imm(sr, T);
1606 emith_cmp_r_imm(tmp, 0);
1607 emit_or_t_if_eq(sr);
1609 emith_or_r_imm(tmp, 0x80);
1610 tmp2 = rcache_get_tmp_arg(1); // assuming it differs to tmp
1611 emith_move_r_r(tmp2, tmp);
1612 rcache_free_tmp(tmp);
1613 rcache_get_reg_arg(0, GET_Rn());
1614 emit_memhandler_write(0, pc, drcf.delayed_op);
1622 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
1625 case 0: // LDC Rm,SR 0100mmmm00001110
1628 case 1: // LDC Rm,GBR 0100mmmm00011110
1631 case 2: // LDC Rm,VBR 0100mmmm00101110
1637 if (tmp2 == SHR_SR) {
1638 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1639 if (drcf.delayed_op)
1641 emith_write_sr(sr, tmp);
1644 tmp2 = rcache_get_reg(tmp2, RC_GR_WRITE);
1645 emith_move_r_r(tmp2, tmp);
1649 // MAC @Rm+,@Rn+ 0100nnnnmmmm1111
1650 emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 1);
1651 emith_sext(tmp, tmp, 16);
1652 emith_sext(tmp2, tmp2, 16);
1653 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW);
1654 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW);
1655 emith_mula_s64(tmp3, tmp4, tmp, tmp2);
1656 rcache_free_tmp(tmp2);
1657 // XXX: MACH should be untouched when S is set?
1658 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1659 emith_tst_r_imm(sr, S);
1660 EMITH_JMP_START(DCOND_EQ);
1662 emith_asr(tmp, tmp3, 31);
1663 emith_eorf_r_r(tmp, tmp4); // tmp = ((signed)macl >> 31) ^ mach
1664 EMITH_JMP_START(DCOND_EQ);
1665 emith_move_r_imm(tmp3, 0x80000000);
1666 emith_tst_r_r(tmp4, tmp4);
1667 EMITH_SJMP_START(DCOND_MI);
1668 emith_sub_r_imm_c(DCOND_PL, tmp3, 1); // positive
1669 EMITH_SJMP_END(DCOND_MI);
1670 EMITH_JMP_END(DCOND_EQ);
1672 EMITH_JMP_END(DCOND_EQ);
1673 rcache_free_tmp(tmp);
1679 /////////////////////////////////////////////
1681 // MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd
1683 tmp = rcache_get_reg_arg(0, GET_Rm());
1684 emith_add_r_imm(tmp, (op & 0x0f) * 4);
1685 tmp = emit_memhandler_read(2);
1686 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1687 emith_move_r_r(tmp2, tmp);
1688 rcache_free_tmp(tmp);
1691 /////////////////////////////////////////////
1695 case 0x00: // MOV.B @Rm,Rn 0110nnnnmmmm0000
1696 case 0x01: // MOV.W @Rm,Rn 0110nnnnmmmm0001
1697 case 0x02: // MOV.L @Rm,Rn 0110nnnnmmmm0010
1698 case 0x04: // MOV.B @Rm+,Rn 0110nnnnmmmm0100
1699 case 0x05: // MOV.W @Rm+,Rn 0110nnnnmmmm0101
1700 case 0x06: // MOV.L @Rm+,Rn 0110nnnnmmmm0110
1702 rcache_get_reg_arg(0, GET_Rm());
1703 tmp = emit_memhandler_read(op & 3);
1704 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1705 if ((op & 3) != 2) {
1706 emith_sext(tmp2, tmp, (op & 1) ? 16 : 8);
1708 emith_move_r_r(tmp2, tmp);
1709 rcache_free_tmp(tmp);
1710 if ((op & 7) >= 4 && GET_Rn() != GET_Rm()) {
1711 tmp = rcache_get_reg(GET_Rm(), RC_GR_RMW);
1712 emith_add_r_imm(tmp, (1 << (op & 3)));
1717 tmp = rcache_get_reg(GET_Rm(), RC_GR_READ);
1718 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1721 case 0x03: // MOV Rm,Rn 0110nnnnmmmm0011
1722 emith_move_r_r(tmp2, tmp);
1724 case 0x07: // NOT Rm,Rn 0110nnnnmmmm0111
1725 emith_mvn_r_r(tmp2, tmp);
1727 case 0x08: // SWAP.B Rm,Rn 0110nnnnmmmm1000
1730 tmp3 = rcache_get_tmp();
1731 tmp4 = rcache_get_tmp();
1732 emith_lsr(tmp3, tmp, 16);
1733 emith_or_r_r_lsl(tmp3, tmp, 24);
1734 emith_and_r_r_imm(tmp4, tmp, 0xff00);
1735 emith_or_r_r_lsl(tmp3, tmp4, 8);
1736 emith_rol(tmp2, tmp3, 16);
1737 rcache_free_tmp(tmp4);
1739 rcache_free_tmp(tmp3);
1741 case 0x09: // SWAP.W Rm,Rn 0110nnnnmmmm1001
1742 emith_rol(tmp2, tmp, 16);
1744 case 0x0a: // NEGC Rm,Rn 0110nnnnmmmm1010
1745 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1746 if (drcf.delayed_op)
1748 emith_tpop_carry(sr, 1);
1749 emith_negcf_r_r(tmp2, tmp);
1750 emith_tpush_carry(sr, 1);
1752 case 0x0b: // NEG Rm,Rn 0110nnnnmmmm1011
1753 emith_neg_r_r(tmp2, tmp);
1755 case 0x0c: // EXTU.B Rm,Rn 0110nnnnmmmm1100
1756 emith_clear_msb(tmp2, tmp, 24);
1758 case 0x0d: // EXTU.W Rm,Rn 0110nnnnmmmm1101
1759 emith_clear_msb(tmp2, tmp, 16);
1761 case 0x0e: // EXTS.B Rm,Rn 0110nnnnmmmm1110
1762 emith_sext(tmp2, tmp, 8);
1764 case 0x0f: // EXTS.W Rm,Rn 0110nnnnmmmm1111
1765 emith_sext(tmp2, tmp, 16);
1772 /////////////////////////////////////////////
1774 // ADD #imm,Rn 0111nnnniiiiiiii
1775 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1776 if (op & 0x80) { // adding negative
1777 emith_sub_r_imm(tmp, -op & 0xff);
1779 emith_add_r_imm(tmp, op & 0xff);
1782 /////////////////////////////////////////////
1784 switch (op & 0x0f00)
1786 case 0x0000: // MOV.B R0,@(disp,Rn) 10000000nnnndddd
1787 case 0x0100: // MOV.W R0,@(disp,Rn) 10000001nnnndddd
1789 tmp = rcache_get_reg_arg(0, GET_Rm());
1790 tmp2 = rcache_get_reg_arg(1, SHR_R0);
1791 tmp3 = (op & 0x100) >> 8;
1792 emith_add_r_imm(tmp, (op & 0x0f) << tmp3);
1793 emit_memhandler_write(tmp3, pc, drcf.delayed_op);
1795 case 0x0400: // MOV.B @(disp,Rm),R0 10000100mmmmdddd
1796 case 0x0500: // MOV.W @(disp,Rm),R0 10000101mmmmdddd
1798 tmp = rcache_get_reg_arg(0, GET_Rm());
1799 tmp3 = (op & 0x100) >> 8;
1800 emith_add_r_imm(tmp, (op & 0x0f) << tmp3);
1801 tmp = emit_memhandler_read(tmp3);
1802 tmp2 = rcache_get_reg(0, RC_GR_WRITE);
1803 emith_sext(tmp2, tmp, 8 << tmp3);
1804 rcache_free_tmp(tmp);
1806 case 0x0800: // CMP/EQ #imm,R0 10001000iiiiiiii
1807 // XXX: could use cmn
1808 tmp = rcache_get_tmp();
1809 tmp2 = rcache_get_reg(0, RC_GR_READ);
1810 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1811 if (drcf.delayed_op)
1813 emith_move_r_imm_s8(tmp, op & 0xff);
1814 emith_bic_r_imm(sr, T);
1815 emith_cmp_r_r(tmp2, tmp);
1816 emit_or_t_if_eq(sr);
1817 rcache_free_tmp(tmp);
1819 case 0x0d00: // BT/S label 10001101dddddddd
1820 case 0x0f00: // BF/S label 10001111dddddddd
1824 case 0x0900: // BT label 10001001dddddddd
1825 case 0x0b00: { // BF label 10001011dddddddd
1826 // jmp_cond ~ cond when guest doesn't jump
1827 int jmp_cond = (op & 0x0200) ? DCOND_NE : DCOND_EQ;
1828 int insn_cond = (op & 0x0200) ? DCOND_EQ : DCOND_NE;
1829 signed int offs = ((signed int)(op << 24) >> 23);
1830 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1831 if (find_in_array(branch_target_pc, branch_target_count, pc + offs + 2) >= 0) {
1832 branch_patch_pc[branch_patch_count] = pc + offs + 2;
1833 branch_patch_cond = insn_cond;
1837 // can't resolve branch, cause end of block
1838 tmp = rcache_get_reg(SHR_PC, RC_GR_WRITE);
1839 emith_move_r_imm(tmp, pc + (drcf.delayed_op ? 2 : 0));
1840 emith_tst_r_imm(sr, T);
1841 EMITH_SJMP_START(jmp_cond);
1842 if (!drcf.delayed_op)
1845 emith_sub_r_imm_c(insn_cond, tmp, -offs);
1847 emith_add_r_imm_c(insn_cond, tmp, offs);
1848 EMITH_SJMP_END(jmp_cond);
1850 if (!drcf.delayed_op)
1856 /////////////////////////////////////////////
1858 // MOV.W @(disp,PC),Rn 1001nnnndddddddd
1860 tmp = rcache_get_tmp_arg(0);
1861 emith_move_r_imm(tmp, pc + (op & 0xff) * 2 + 2);
1862 tmp = emit_memhandler_read(1);
1863 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1864 emith_sext(tmp2, tmp, 16);
1865 rcache_free_tmp(tmp);
1868 /////////////////////////////////////////////
1870 // BRA label 1010dddddddddddd
1873 tmp = ((signed int)(op << 20) >> 19);
1874 emit_move_r_imm32(SHR_PC, pc + tmp + 2);
1878 /////////////////////////////////////////////
1880 // BSR label 1011dddddddddddd
1882 emit_move_r_imm32(SHR_PR, pc + 2);
1885 /////////////////////////////////////////////
1887 switch (op & 0x0f00)
1889 case 0x0000: // MOV.B R0,@(disp,GBR) 11000000dddddddd
1890 case 0x0100: // MOV.W R0,@(disp,GBR) 11000001dddddddd
1891 case 0x0200: // MOV.L R0,@(disp,GBR) 11000010dddddddd
1893 tmp = rcache_get_reg_arg(0, SHR_GBR);
1894 tmp2 = rcache_get_reg_arg(1, SHR_R0);
1895 tmp3 = (op & 0x300) >> 8;
1896 emith_add_r_imm(tmp, (op & 0xff) << tmp3);
1897 emit_memhandler_write(tmp3, pc, drcf.delayed_op);
1899 case 0x0400: // MOV.B @(disp,GBR),R0 11000100dddddddd
1900 case 0x0500: // MOV.W @(disp,GBR),R0 11000101dddddddd
1901 case 0x0600: // MOV.L @(disp,GBR),R0 11000110dddddddd
1903 tmp = rcache_get_reg_arg(0, SHR_GBR);
1904 tmp3 = (op & 0x300) >> 8;
1905 emith_add_r_imm(tmp, (op & 0xff) << tmp3);
1906 tmp = emit_memhandler_read(tmp3);
1907 tmp2 = rcache_get_reg(0, RC_GR_WRITE);
1909 emith_sext(tmp2, tmp, 8 << tmp3);
1911 emith_move_r_r(tmp2, tmp);
1912 rcache_free_tmp(tmp);
1914 case 0x0300: // TRAPA #imm 11000011iiiiiiii
1915 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
1916 emith_sub_r_imm(tmp, 4*2);
1919 tmp = rcache_get_reg_arg(0, SHR_SP);
1920 emith_add_r_imm(tmp, 4);
1921 tmp = rcache_get_reg_arg(1, SHR_SR);
1922 emith_clear_msb(tmp, tmp, 22);
1923 emit_memhandler_write(2, pc, drcf.delayed_op);
1925 rcache_get_reg_arg(0, SHR_SP);
1926 tmp = rcache_get_tmp_arg(1);
1927 emith_move_r_imm(tmp, pc);
1928 emit_memhandler_write(2, pc, drcf.delayed_op);
1930 tmp = rcache_get_reg_arg(0, SHR_VBR);
1931 emith_add_r_imm(tmp, (op & 0xff) * 4);
1932 tmp = emit_memhandler_read(2);
1933 tmp2 = rcache_get_reg(SHR_PC, RC_GR_WRITE);
1934 emith_move_r_r(tmp2, tmp);
1935 rcache_free_tmp(tmp);
1938 case 0x0700: // MOVA @(disp,PC),R0 11000111dddddddd
1939 emit_move_r_imm32(SHR_R0, (pc + (op & 0xff) * 4 + 2) & ~3);
1941 case 0x0800: // TST #imm,R0 11001000iiiiiiii
1942 tmp = rcache_get_reg(SHR_R0, RC_GR_READ);
1943 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1944 if (drcf.delayed_op)
1946 emith_bic_r_imm(sr, T);
1947 emith_tst_r_imm(tmp, op & 0xff);
1948 emit_or_t_if_eq(sr);
1950 case 0x0900: // AND #imm,R0 11001001iiiiiiii
1951 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
1952 emith_and_r_imm(tmp, op & 0xff);
1954 case 0x0a00: // XOR #imm,R0 11001010iiiiiiii
1955 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
1956 emith_eor_r_imm(tmp, op & 0xff);
1958 case 0x0b00: // OR #imm,R0 11001011iiiiiiii
1959 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
1960 emith_or_r_imm(tmp, op & 0xff);
1962 case 0x0c00: // TST.B #imm,@(R0,GBR) 11001100iiiiiiii
1963 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
1964 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1965 if (drcf.delayed_op)
1967 emith_bic_r_imm(sr, T);
1968 emith_tst_r_imm(tmp, op & 0xff);
1969 emit_or_t_if_eq(sr);
1970 rcache_free_tmp(tmp);
1973 case 0x0d00: // AND.B #imm,@(R0,GBR) 11001101iiiiiiii
1974 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
1975 emith_and_r_imm(tmp, op & 0xff);
1977 case 0x0e00: // XOR.B #imm,@(R0,GBR) 11001110iiiiiiii
1978 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
1979 emith_eor_r_imm(tmp, op & 0xff);
1981 case 0x0f00: // OR.B #imm,@(R0,GBR) 11001111iiiiiiii
1982 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
1983 emith_or_r_imm(tmp, op & 0xff);
1985 tmp2 = rcache_get_tmp_arg(1);
1986 emith_move_r_r(tmp2, tmp);
1987 rcache_free_tmp(tmp);
1988 tmp3 = rcache_get_reg_arg(0, SHR_GBR);
1989 tmp4 = rcache_get_reg(SHR_R0, RC_GR_READ);
1990 emith_add_r_r(tmp3, tmp4);
1991 emit_memhandler_write(0, pc, drcf.delayed_op);
1997 /////////////////////////////////////////////
1999 // MOV.L @(disp,PC),Rn 1101nnnndddddddd
2001 tmp = rcache_get_tmp_arg(0);
2002 emith_move_r_imm(tmp, (pc + (op & 0xff) * 4 + 2) & ~3);
2003 tmp = emit_memhandler_read(2);
2004 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
2005 emith_move_r_r(tmp2, tmp);
2006 rcache_free_tmp(tmp);
2009 /////////////////////////////////////////////
2011 // MOV #imm,Rn 1110nnnniiiiiiii
2012 tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
2013 emith_move_r_imm_s8(tmp, op & 0xff);
2018 elprintf(EL_ANOMALY, "%csh2 drc: unhandled op %04x @ %08x",
2019 sh2->is_slave ? 's' : 'm', op, pc - 2);
2020 #ifdef DRC_DEBUG_INTERP
2021 emit_move_r_imm32(SHR_PC, pc - 2);
2023 emith_pass_arg_r(0, CONTEXT_REG);
2024 emith_pass_arg_imm(1, op);
2025 emith_call(sh2_do_op);
2031 // block-local conditional branch handling (with/without delay)
2032 if (branch_patch_cond != -1 && drcf.delayed_op != 2) {
2033 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2038 if (drcf.use_saved_t)
2039 emith_tst_r_imm(sr, T_save);
2041 emith_tst_r_imm(sr, T);
2042 branch_patch_ptr[branch_patch_count] = tcache_ptr;
2043 emith_jump_patchable(branch_patch_cond);
2045 drcf.use_saved_t = 0;
2046 branch_patch_cond = -1;
2047 branch_patch_count++;
2048 drcf.delayed_op = 0; // XXX: delayed_op ends block, so must override
2049 if (branch_patch_count == MAX_LOCAL_BRANCHES) {
2050 printf("too many local branches\n");
2055 // XXX: delay slots..
2056 if (drcf.test_irq && drcf.delayed_op != 2) {
2057 if (!drcf.delayed_op)
2058 emit_move_r_imm32(SHR_PC, pc);
2059 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2062 emith_call(sh2_drc_test_irq);
2065 if (drcf.delayed_op == 1)
2068 do_host_disasm(tcache_id);
2071 // delayed_op means some kind of branch - PC already handled
2072 if (!drcf.delayed_op)
2073 emit_move_r_imm32(SHR_PC, pc);
2076 this_block->end_addr = pc;
2078 tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
2081 emith_jump(sh2_drc_dispatcher);
2083 // link local branches
2084 for (i = 0; i < branch_patch_count; i++) {
2087 //printf("patch %08x %p\n", branch_patch_pc[i], branch_patch_ptr[i]);
2088 t = find_in_array(branch_target_pc, branch_target_count, branch_patch_pc[i]);
2089 if (branch_target_ptr[t] != NULL)
2090 target = branch_target_ptr[t];
2092 // flush pc and go back to dispatcher (for now)
2093 printf("stray branch to %08x %p\n", branch_patch_pc[i], tcache_ptr);
2094 target = tcache_ptr;
2095 emit_move_r_imm32(SHR_PC, branch_patch_pc[i]);
2097 emith_jump(sh2_drc_dispatcher);
2099 emith_jump_patch(branch_patch_ptr[i], target);
2102 // mark memory blocks as containing compiled code
2103 if (tcache_id != 0) {
2105 u16 *drcblk = Pico32xMem->drcblk_da[sh2->is_slave];
2106 tmp = (this_block->addr & 0xfff) >> SH2_DRCBLK_DA_SHIFT;
2107 tmp2 = (this_block->end_addr & 0xfff) >> SH2_DRCBLK_DA_SHIFT;
2108 drcblk[tmp] = (blkid_main << 1) | 1;
2109 for (++tmp; tmp < tmp2; tmp++) {
2111 continue; // dont overwrite overlay block(s)
2112 drcblk[tmp] = blkid_main << 1;
2115 else if ((this_block->addr & 0xc7fc0000) == 0x06000000) { // DRAM
2116 tmp = (this_block->addr & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT;
2117 tmp2 = (this_block->end_addr & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT;
2118 Pico32xMem->drcblk_ram[tmp] = (blkid_main << 1) | 1;
2119 for (++tmp; tmp < tmp2; tmp++) {
2120 if (Pico32xMem->drcblk_ram[tmp])
2122 Pico32xMem->drcblk_ram[tmp] = blkid_main << 1;
2126 tcache_ptrs[tcache_id] = tcache_ptr;
2129 cache_flush_d_inval_i(block_entry, tcache_ptr);
2132 do_host_disasm(tcache_id);
2133 dbg(1, " block #%d,%d tcache %d/%d, insns %d -> %d %.3f",
2134 tcache_id, block_counts[tcache_id],
2135 tcache_ptr - tcache_bases[tcache_id], tcache_sizes[tcache_id],
2136 insns_compiled, host_insn_count, (double)host_insn_count / insns_compiled);
2137 if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM
2138 dbg(1, " hash collisions %d/%d", hash_collisions, block_counts[tcache_id]);
2141 tcache_dsm_ptrs[tcache_id] = block_entry;
2142 do_host_disasm(tcache_id);
2154 do_host_disasm(tcache_id);
2159 static void sh2_generate_utils(void)
2161 int arg0, arg1, arg2, sr, tmp;
2162 void *sh2_drc_write_end, *sh2_drc_write_slot_end;
2164 host_arg2reg(arg0, 0);
2165 host_arg2reg(arg1, 1);
2166 host_arg2reg(arg2, 2);
2167 emith_move_r_r(arg0, arg0); // nop
2169 // sh2_drc_exit(void)
2170 sh2_drc_exit = (void *)tcache_ptr;
2171 emit_do_static_regs(1, arg2);
2172 emith_sh2_drc_exit();
2174 // sh2_drc_dispatcher(void)
2175 sh2_drc_dispatcher = (void *)tcache_ptr;
2176 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2177 emith_cmp_r_imm(sr, 0);
2178 emith_jump_cond(DCOND_LT, sh2_drc_exit);
2179 rcache_invalidate();
2180 emith_ctx_read(arg0, SHR_PC * 4);
2181 emith_ctx_read(arg1, offsetof(SH2, is_slave));
2182 emith_add_r_r_imm(arg2, CONTEXT_REG, offsetof(SH2, drc_tmp));
2183 emith_call(lookup_block);
2185 // lookup failed, call sh2_translate()
2186 emith_move_r_r(arg0, CONTEXT_REG);
2187 emith_ctx_read(arg1, offsetof(SH2, drc_tmp)); // tcache_id
2188 emith_call(sh2_translate);
2190 // sh2_translate() failed, flush cache and retry
2191 emith_ctx_read(arg0, offsetof(SH2, drc_tmp));
2192 emith_call(flush_tcache);
2193 emith_move_r_r(arg0, CONTEXT_REG);
2194 emith_ctx_read(arg1, offsetof(SH2, drc_tmp));
2195 emith_call(sh2_translate);
2197 // XXX: can't translate, fail
2200 // sh2_drc_test_irq(void)
2201 // assumes it's called from main function (may jump to dispatcher)
2202 sh2_drc_test_irq = (void *)tcache_ptr;
2203 emith_ctx_read(arg1, offsetof(SH2, pending_level));
2204 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2205 emith_lsr(arg0, sr, I_SHIFT);
2206 emith_and_r_imm(arg0, 0x0f);
2207 emith_cmp_r_r(arg1, arg0); // pending_level > ((sr >> 4) & 0x0f)?
2208 EMITH_SJMP_START(DCOND_GT);
2209 emith_ret_c(DCOND_LE); // nope, return
2210 EMITH_SJMP_END(DCOND_GT);
2212 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
2213 emith_sub_r_imm(tmp, 4*2);
2216 tmp = rcache_get_reg_arg(0, SHR_SP);
2217 emith_add_r_imm(tmp, 4);
2218 tmp = rcache_get_reg_arg(1, SHR_SR);
2219 emith_clear_msb(tmp, tmp, 22);
2220 emith_move_r_r(arg2, CONTEXT_REG);
2221 emith_call(p32x_sh2_write32);
2222 rcache_invalidate();
2224 rcache_get_reg_arg(0, SHR_SP);
2225 emith_ctx_read(arg1, SHR_PC * 4);
2226 emith_move_r_r(arg2, CONTEXT_REG);
2227 emith_call(p32x_sh2_write32);
2228 rcache_invalidate();
2229 // update I, cycles, do callback
2230 emith_ctx_read(arg1, offsetof(SH2, pending_level));
2231 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2232 emith_bic_r_imm(sr, I);
2233 emith_or_r_r_lsl(sr, arg1, I_SHIFT);
2234 emith_sub_r_imm(sr, 13 << 12); // at least 13 cycles
2236 emith_move_r_r(arg0, CONTEXT_REG);
2237 emith_call_ctx(offsetof(SH2, irq_callback)); // vector = sh2->irq_callback(sh2, level);
2239 emith_lsl(arg0, arg0, 2);
2240 emith_ctx_read(arg1, SHR_VBR * 4);
2241 emith_add_r_r(arg0, arg1);
2242 emit_memhandler_read(2);
2243 emith_ctx_write(arg0, SHR_PC * 4);
2245 emith_add_r_imm(xSP, 4); // fix stack
2247 emith_jump(sh2_drc_dispatcher);
2248 rcache_invalidate();
2250 // sh2_drc_entry(SH2 *sh2)
2251 sh2_drc_entry = (void *)tcache_ptr;
2252 emith_sh2_drc_entry();
2253 emith_move_r_r(CONTEXT_REG, arg0); // move ctx, arg0
2254 emit_do_static_regs(0, arg2);
2255 emith_call(sh2_drc_test_irq);
2256 emith_jump(sh2_drc_dispatcher);
2258 // write-caused irq detection
2259 sh2_drc_write_end = tcache_ptr;
2260 emith_tst_r_r(arg0, arg0);
2261 EMITH_SJMP_START(DCOND_NE);
2262 emith_jump_ctx_c(DCOND_EQ, offsetof(SH2, drc_tmp)); // return
2263 EMITH_SJMP_END(DCOND_NE);
2264 // since PC is up to date, jump to it's block instead of returning
2265 emith_call(sh2_drc_test_irq);
2266 emith_jump_ctx(offsetof(SH2, drc_tmp));
2268 // write-caused irq detection for writes in delay slot
2269 sh2_drc_write_slot_end = tcache_ptr;
2270 emith_tst_r_r(arg0, arg0);
2271 EMITH_SJMP_START(DCOND_NE);
2272 emith_jump_ctx_c(DCOND_EQ, offsetof(SH2, drc_tmp));
2273 EMITH_SJMP_END(DCOND_NE);
2274 // just burn cycles to get back to dispatcher after branch is handled
2275 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2276 emith_ctx_write(sr, offsetof(SH2, irq_cycles));
2277 emith_clear_msb(sr, sr, 20); // clear cycles
2279 emith_jump_ctx(offsetof(SH2, drc_tmp));
2281 // sh2_drc_write8(u32 a, u32 d)
2282 sh2_drc_write8 = (void *)tcache_ptr;
2283 emith_ret_to_ctx(offsetof(SH2, drc_tmp));
2284 emith_ctx_read(arg2, offsetof(SH2, write8_tab));
2285 emith_sh2_wcall(arg0, arg2, sh2_drc_write_end);
2287 // sh2_drc_write16(u32 a, u32 d)
2288 sh2_drc_write16 = (void *)tcache_ptr;
2289 emith_ret_to_ctx(offsetof(SH2, drc_tmp));
2290 emith_ctx_read(arg2, offsetof(SH2, write16_tab));
2291 emith_sh2_wcall(arg0, arg2, sh2_drc_write_end);
2293 // sh2_drc_write8_slot(u32 a, u32 d)
2294 sh2_drc_write8_slot = (void *)tcache_ptr;
2295 emith_ret_to_ctx(offsetof(SH2, drc_tmp));
2296 emith_ctx_read(arg2, offsetof(SH2, write8_tab));
2297 emith_sh2_wcall(arg0, arg2, sh2_drc_write_slot_end);
2299 // sh2_drc_write16_slot(u32 a, u32 d)
2300 sh2_drc_write16_slot = (void *)tcache_ptr;
2301 emith_ret_to_ctx(offsetof(SH2, drc_tmp));
2302 emith_ctx_read(arg2, offsetof(SH2, write16_tab));
2303 emith_sh2_wcall(arg0, arg2, sh2_drc_write_slot_end);
2305 rcache_invalidate();
2307 host_dasm_new_symbol(sh2_drc_entry);
2308 host_dasm_new_symbol(sh2_drc_dispatcher);
2309 host_dasm_new_symbol(sh2_drc_exit);
2310 host_dasm_new_symbol(sh2_drc_test_irq);
2311 host_dasm_new_symbol(sh2_drc_write_end);
2312 host_dasm_new_symbol(sh2_drc_write_slot_end);
2313 host_dasm_new_symbol(sh2_drc_write8);
2314 host_dasm_new_symbol(sh2_drc_write8_slot);
2315 host_dasm_new_symbol(sh2_drc_write16);
2316 host_dasm_new_symbol(sh2_drc_write16_slot);
2320 static void sh2_smc_rm_block(u16 *drcblk, u16 *p, block_desc *btab, u32 a)
2323 block_desc *bd = btab + id;
2325 // FIXME: skip subblocks; do both directions
2326 dbg(1, " killing block %08x", bd->addr);
2327 bd->addr = bd->end_addr = 0;
2329 while (p > drcblk && (p[-1] >> 1) == id)
2332 // check for possible overlay block
2333 if (p > 0 && p[-1] != 0) {
2334 bd = btab + (p[-1] >> 1);
2335 if (bd->addr <= a && a < bd->end_addr)
2336 sh2_smc_rm_block(drcblk, p - 1, btab, a);
2342 while ((*p >> 1) == id);
2345 void sh2_drc_wcheck_ram(unsigned int a, int val, int cpuid)
2347 u16 *drcblk = Pico32xMem->drcblk_ram;
2348 u16 *p = drcblk + ((a & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT);
2350 dbg(1, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
2351 sh2_smc_rm_block(drcblk, p, block_tables[0], a);
2354 void sh2_drc_wcheck_da(unsigned int a, int val, int cpuid)
2356 u16 *drcblk = Pico32xMem->drcblk_da[cpuid];
2357 u16 *p = drcblk + ((a & 0xfff) >> SH2_DRCBLK_DA_SHIFT);
2359 dbg(1, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
2360 sh2_smc_rm_block(drcblk, p, block_tables[1 + cpuid], a);
2363 void sh2_execute(SH2 *sh2c, int cycles)
2368 sh2c->cycles_aim += cycles;
2369 cycles = sh2c->cycles_aim - sh2c->cycles_done;
2371 // cycles are kept in SHR_SR unused bits (upper 20)
2372 // bit19 contains T saved for delay slot
2373 // others are usual SH2 flags
2375 sh2c->sr |= cycles << 12;
2376 sh2_drc_entry(sh2c);
2379 ret_cycles = (signed int)sh2c->sr >> 12;
2381 printf("warning: drc returned with cycles: %d\n", ret_cycles);
2383 sh2c->cycles_done += cycles - ret_cycles;
2387 static void block_stats(void)
2389 int c, b, i, total = 0;
2391 for (b = 0; b < ARRAY_SIZE(block_tables); b++)
2392 for (i = 0; i < block_counts[b]; i++)
2393 if (block_tables[b][i].addr != 0)
2394 total += block_tables[b][i].refcount;
2396 for (c = 0; c < 10; c++) {
2397 block_desc *blk, *maxb = NULL;
2399 for (b = 0; b < ARRAY_SIZE(block_tables); b++) {
2400 for (i = 0; i < block_counts[b]; i++) {
2401 blk = &block_tables[b][i];
2402 if (blk->addr != 0 && blk->refcount > max) {
2403 max = blk->refcount;
2410 printf("%08x %9d %2.3f%%\n", maxb->addr, maxb->refcount,
2411 (double)maxb->refcount / total * 100.0);
2415 for (b = 0; b < ARRAY_SIZE(block_tables); b++)
2416 for (i = 0; i < block_counts[b]; i++)
2417 block_tables[b][i].refcount = 0;
2420 #define block_stats()
2423 void sh2_drc_flush_all(void)
2431 int sh2_drc_init(SH2 *sh2)
2433 if (block_tables[0] == NULL) {
2438 cnt = block_max_counts[0] + block_max_counts[1] + block_max_counts[2];
2439 block_tables[0] = calloc(cnt, sizeof(*block_tables[0]));
2440 if (block_tables[0] == NULL)
2443 tcache_ptr = tcache;
2444 sh2_generate_utils();
2446 cache_flush_d_inval_i(tcache, tcache_ptr);
2449 memset(block_counts, 0, sizeof(block_counts));
2450 tcache_bases[0] = tcache_ptrs[0] = tcache_ptr;
2452 for (i = 1; i < ARRAY_SIZE(block_tables); i++) {
2453 block_tables[i] = block_tables[i - 1] + block_max_counts[i - 1];
2454 tcache_bases[i] = tcache_ptrs[i] = tcache_bases[i - 1] + tcache_sizes[i - 1];
2458 PicoOpt |= POPT_DIS_VDP_FIFO;
2461 for (i = 0; i < ARRAY_SIZE(block_tables); i++)
2462 tcache_dsm_ptrs[i] = tcache_bases[i];
2464 tcache_dsm_ptrs[0] = tcache;
2468 hash_collisions = 0;
2472 if (hash_table == NULL) {
2473 hash_table = calloc(sizeof(hash_table[0]), MAX_HASH_ENTRIES);
2474 if (hash_table == NULL)
2481 void sh2_drc_finish(SH2 *sh2)
2483 if (block_tables[0] != NULL) {
2485 free(block_tables[0]);
2486 memset(block_tables, 0, sizeof(block_tables));
2491 if (hash_table != NULL) {