cpu/sh2/mame/sh2pico.c

   1 #include "../sh2.h"
   2
   3 #ifdef DRC_CMP
   4 #include "../compiler.h"
   5 #define BUSY_LOOP_HACKS 0
   6 #else
   7 #define BUSY_LOOP_HACKS 1
   8 #endif
   9
  10 // MAME types
  11 #ifndef INT8
  12 typedef s8  INT8;
  13 typedef s16 INT16;
  14 typedef s32 INT32;
  15 typedef u32 UINT32;
  16 typedef u16 UINT16;
  17 typedef u8  UINT8;
  18 #endif
  19
  20 #ifdef DRC_SH2
  21
  22 // this nasty conversion is needed for drc-expecting memhandlers
  23 #define MAKE_READFUNC(name, cname) \
  24 static __inline unsigned int name(SH2 *sh2, unsigned int a) \
  25 { \
  26         unsigned int ret; \
  27         sh2->sr |= (sh2->icount << 12) | (sh2->no_polling); \
  28         ret = cname(a, sh2); \
  29         sh2->icount = (signed int)sh2->sr >> 12; \
  30         sh2->no_polling = (sh2->sr & SH2_NO_POLLING); \
  31         sh2->sr &= 0x3f3; \
  32         return ret; \
  33 }
  34
  35 #define MAKE_WRITEFUNC(name, cname) \
  36 static __inline void name(SH2 *sh2, unsigned int a, unsigned int d) \
  37 { \
  38         sh2->sr |= (sh2->icount << 12) | (sh2->no_polling); \
  39         cname(a, d, sh2); \
  40         sh2->icount = (signed int)sh2->sr >> 12; \
  41         sh2->no_polling = (sh2->sr & SH2_NO_POLLING); \
  42         sh2->sr &= 0x3f3; \
  43 }
  44
  45 MAKE_READFUNC(RB, p32x_sh2_read8)
  46 MAKE_READFUNC(RW, p32x_sh2_read16)
  47 MAKE_READFUNC(RL, p32x_sh2_read32)
  48 MAKE_WRITEFUNC(WB, p32x_sh2_write8)
  49 MAKE_WRITEFUNC(WW, p32x_sh2_write16)
  50 MAKE_WRITEFUNC(WL, p32x_sh2_write32)
  51
  52 #else
  53
  54 #define RB(sh2, a) p32x_sh2_read8(a, sh2)
  55 #define RW(sh2, a) p32x_sh2_read16(a, sh2)
  56 #define RL(sh2, a) p32x_sh2_read32(a, sh2)
  57 #define WB(sh2, a, d) p32x_sh2_write8(a, d, sh2)
  58 #define WW(sh2, a, d) p32x_sh2_write16(a, d, sh2)
  59 #define WL(sh2, a, d) p32x_sh2_write32(a, d, sh2)
  60
  61 #endif
  62
  63 // some stuff from sh2comn.h
  64 #define T       0x00000001
  65 #define S       0x00000002
  66 #define I       0x000000f0
  67 #define Q       0x00000100
  68 #define M       0x00000200
  69
  70 #define AM      0xc7ffffff
  71
  72 #define FLAGS   (M|Q|I|S|T)
  73
  74 #define Rn      ((opcode>>8)&15)
  75 #define Rm      ((opcode>>4)&15)
  76
  77 #define sh2_state SH2
  78
  79 extern void lprintf(const char *fmt, ...);
  80 #define logerror lprintf
  81
  82 #ifdef SH2_STATS
  83 static SH2 sh2_stats;
  84 static unsigned int op_refs[0x10000];
  85 # define LRN  1
  86 # define LRM  2
  87 # define LRNM (LRN|LRM)
  88 # define rlog(rnm) {   \
  89   int op = opcode;     \
  90   if ((rnm) & LRN) {   \
  91     op &= ~0x0f00;     \
  92     sh2_stats.r[Rn]++; \
  93   }                    \
  94   if ((rnm) & LRM) {   \
  95     op &= ~0x00f0;     \
  96     sh2_stats.r[Rm]++; \
  97   }                    \
  98   op_refs[op]++;       \
  99 }
 100 # define rlog1(x) sh2_stats.r[x]++
 101 # define rlog2(x1,x2) sh2_stats.r[x1]++; sh2_stats.r[x2]++
 102 #else
 103 # define rlog(x)
 104 # define rlog1(...)
 105 # define rlog2(...)
 106 #endif
 107
 108 #include "sh2.c"
 109
 110 #ifndef DRC_CMP
 111
 112 int sh2_execute_interpreter(SH2 *sh2, int cycles)
 113 {
 114         UINT32 opcode;
 115
 116         sh2->icount = cycles;
 117
 118         if (sh2->icount <= 0)
 119                 goto out;
 120
 121         do
 122         {
 123                 if (sh2->delay)
 124                 {
 125                         sh2->ppc = sh2->delay;
 126                         opcode = (UINT32)(UINT16)RW(sh2, sh2->delay);
 127
 128                         // TODO: more branch types
 129                         if ((opcode >> 13) == 5) { // BRA/BSR
 130                                 sh2->r[15] -= 4;
 131                                 WL(sh2, sh2->r[15], sh2->sr);
 132                                 sh2->r[15] -= 4;
 133                                 WL(sh2, sh2->r[15], sh2->pc);
 134                                 sh2->pc = RL(sh2, sh2->vbr + 6 * 4);
 135                                 sh2->icount -= 5;
 136                                 opcode = 9; // NOP
 137                         }
 138
 139                         sh2->pc -= 2;
 140                 }
 141                 else
 142                 {
 143                         sh2->ppc = sh2->pc;
 144                         opcode = (UINT32)(UINT16)RW(sh2, sh2->pc);
 145                 }
 146
 147                 sh2->delay = 0;
 148                 sh2->pc += 2;
 149
 150                 switch (opcode & ( 15 << 12))
 151                 {
 152                 case  0<<12: op0000(sh2, opcode); break;
 153                 case  1<<12: op0001(sh2, opcode); break;
 154                 case  2<<12: op0010(sh2, opcode); break;
 155                 case  3<<12: op0011(sh2, opcode); break;
 156                 case  4<<12: op0100(sh2, opcode); break;
 157                 case  5<<12: op0101(sh2, opcode); break;
 158                 case  6<<12: op0110(sh2, opcode); break;
 159                 case  7<<12: op0111(sh2, opcode); break;
 160                 case  8<<12: op1000(sh2, opcode); break;
 161                 case  9<<12: op1001(sh2, opcode); break;
 162                 case 10<<12: op1010(sh2, opcode); break;
 163                 case 11<<12: op1011(sh2, opcode); break;
 164                 case 12<<12: op1100(sh2, opcode); break;
 165                 case 13<<12: op1101(sh2, opcode); break;
 166                 case 14<<12: op1110(sh2, opcode); break;
 167                 default: op1111(sh2, opcode); break;
 168                 }
 169
 170                 sh2->icount--;
 171
 172                 if (sh2->test_irq && !sh2->delay)
 173                 {
 174                         int level = sh2->pending_level;
 175                         if (level > ((sh2->sr >> 4) & 0x0f))
 176                         {
 177                                 int vector = sh2->irq_callback(sh2, level);
 178                                 sh2_do_irq(sh2, level, vector);
 179                         }
 180                         sh2->test_irq = 0;
 181                 }
 182         }
 183         while (sh2->icount > 0 || sh2->delay);  /* can't interrupt before delay */
 184
 185 out:
 186         return sh2->icount;
 187 }
 188
 189 #else // if DRC_CMP
 190
 191 int sh2_execute_interpreter(SH2 *sh2, int cycles)
 192 {
 193         static unsigned int base_pc_[2] = { 0, 0 };
 194         static unsigned int end_pc_[2] = { 0, 0 };
 195         static unsigned char op_flags_[2][BLOCK_INSN_LIMIT];
 196         unsigned int *base_pc = &base_pc_[sh2->is_slave];
 197         unsigned int *end_pc = &end_pc_[sh2->is_slave];
 198         unsigned char *op_flags = op_flags_[sh2->is_slave];
 199         unsigned int pc_expect;
 200         UINT32 opcode;
 201
 202         sh2->icount = sh2->cycles_timeslice = cycles;
 203
 204         if (sh2->pending_level > ((sh2->sr >> 4) & 0x0f))
 205         {
 206                 int level = sh2->pending_level;
 207                 int vector = sh2->irq_callback(sh2, level);
 208                 sh2_do_irq(sh2, level, vector);
 209         }
 210         pc_expect = sh2->pc;
 211
 212         if (sh2->icount <= 0)
 213                 goto out;
 214
 215         do
 216         {
 217                 if (!sh2->delay) {
 218                         if (sh2->pc < *base_pc || sh2->pc >= *end_pc) {
 219                                 *base_pc = sh2->pc;
 220                                 scan_block(*base_pc, sh2->is_slave,
 221                                         op_flags, end_pc, NULL, NULL);
 222                         }
 223                         if ((op_flags[(sh2->pc - *base_pc) / 2]
 224                                 & OF_BTARGET) || sh2->pc == *base_pc
 225                                 || pc_expect != sh2->pc) // branched
 226                         {
 227                                 pc_expect = sh2->pc;
 228                                 if (sh2->icount <= 0)
 229                                         break;
 230                         }
 231
 232                         do_sh2_trace(sh2, sh2->icount);
 233                 }
 234                 pc_expect += 2;
 235
 236                 if (sh2->delay)
 237                 {
 238                         sh2->ppc = sh2->delay;
 239                         opcode = (UINT32)(UINT16)RW(sh2, sh2->delay);
 240                         sh2->pc -= 2;
 241                 }
 242                 else
 243                 {
 244                         sh2->ppc = sh2->pc;
 245                         opcode = (UINT32)(UINT16)RW(sh2, sh2->pc);
 246                 }
 247
 248                 sh2->delay = 0;
 249                 sh2->pc += 2;
 250
 251                 switch (opcode & ( 15 << 12))
 252                 {
 253                 case  0<<12: op0000(sh2, opcode); break;
 254                 case  1<<12: op0001(sh2, opcode); break;
 255                 case  2<<12: op0010(sh2, opcode); break;
 256                 case  3<<12: op0011(sh2, opcode); break;
 257                 case  4<<12: op0100(sh2, opcode); break;
 258                 case  5<<12: op0101(sh2, opcode); break;
 259                 case  6<<12: op0110(sh2, opcode); break;
 260                 case  7<<12: op0111(sh2, opcode); break;
 261                 case  8<<12: op1000(sh2, opcode); break;
 262                 case  9<<12: op1001(sh2, opcode); break;
 263                 case 10<<12: op1010(sh2, opcode); break;
 264                 case 11<<12: op1011(sh2, opcode); break;
 265                 case 12<<12: op1100(sh2, opcode); break;
 266                 case 13<<12: op1101(sh2, opcode); break;
 267                 case 14<<12: op1110(sh2, opcode); break;
 268                 default: op1111(sh2, opcode); break;
 269                 }
 270
 271                 sh2->icount--;
 272
 273                 if (sh2->test_irq && !sh2->delay && sh2->pending_level > ((sh2->sr >> 4) & 0x0f))
 274                 {
 275                         int level = sh2->pending_level;
 276                         int vector = sh2->irq_callback(sh2, level);
 277                         sh2_do_irq(sh2, level, vector);
 278                         sh2->test_irq = 0;
 279                 }
 280
 281         }
 282         while (1);
 283
 284 out:
 285         return sh2->icount;
 286 }
 287
 288 #endif // DRC_CMP
 289
 290 #ifdef SH2_STATS
 291 #include <stdio.h>
 292 #include <string.h>
 293 #include "sh2dasm.h"
 294
 295 void sh2_dump_stats(void)
 296 {
 297         static const char *rnames[] = {
 298                 "R0", "R1", "R2",  "R3",  "R4",  "R5",  "R6",  "R7",
 299                 "R8", "R9", "R10", "R11", "R12", "R13", "R14", "SP",
 300                 "PC", "", "PR", "SR", "GBR", "VBR", "MACH", "MACL"
 301         };
 302         long long total;
 303         char buff[64];
 304         int u, i;
 305
 306         // dump reg usage
 307         total = 0;
 308         for (i = 0; i < 24; i++)
 309                 total += sh2_stats.r[i];
 310
 311         for (i = 0; i < 24; i++) {
 312                 if (i == 16 || i == 17 || i == 19)
 313                         continue;
 314                 printf("r %6.3f%% %-4s %9d\n", (double)sh2_stats.r[i] * 100.0 / total,
 315                         rnames[i], sh2_stats.r[i]);
 316         }
 317
 318         memset(&sh2_stats, 0, sizeof(sh2_stats));
 319
 320         // dump ops
 321         printf("\n");
 322         total = 0;
 323         for (i = 0; i < 0x10000; i++)
 324                 total += op_refs[i];
 325
 326         for (u = 0; u < 16; u++) {
 327                 int max = 0, op = 0;
 328                 for (i = 0; i < 0x10000; i++) {
 329                         if (op_refs[i] > max) {
 330                                 max = op_refs[i];
 331                                 op = i;
 332                         }
 333                 }
 334                 DasmSH2(buff, 0, op);
 335                 printf("i %6.3f%% %9d %s\n", (double)op_refs[op] * 100.0 / total,
 336                         op_refs[op], buff);
 337                 op_refs[op] = 0;
 338         }
 339         memset(op_refs, 0, sizeof(op_refs));
 340 }
 341 #endif
 342