1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - dbg_debugger_local.h *
3 * Mupen64Plus homepage: http://code.google.com/p/mupen64plus/ *
4 * Copyright (C) 2010 Marshall B. Rogers <mbr@64.vg> *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
20 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
21 #ifndef __DECODER_LOCAL_H__
22 #define __DECODER_LOCAL_H__
26 /* $NetBSD: cpuregs.h,v 1.77 2009/12/14 00:46:04 matt Exp $ */
29 * Copyright (c) 1992, 1993
30 * The Regents of the University of California. All rights reserved.
32 * This code is derived from software contributed to Berkeley by
33 * Ralph Campbell and Rick Macklem.
35 * Redistribution and use in source and binary forms, with or without
36 * modification, are permitted provided that the following conditions
38 * 1. Redistributions of source code must retain the above copyright
39 * notice, this list of conditions and the following disclaimer.
40 * 2. Redistributions in binary form must reproduce the above copyright
41 * notice, this list of conditions and the following disclaimer in the
42 * documentation and/or other materials provided with the distribution.
43 * 3. Neither the name of the University nor the names of its contributors
44 * may be used to endorse or promote products derived from this software
45 * without specific prior written permission.
47 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
48 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
49 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
50 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
51 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
52 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
53 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
54 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
55 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
56 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
59 * @(#)machConst.h 8.1 (Berkeley) 6/10/93
63 * Machine dependent constants.
65 * Copyright (C) 1989 Digital Equipment Corporation.
66 * Permission to use, copy, modify, and distribute this software and
67 * its documentation for any purpose and without fee is hereby granted,
68 * provided that the above copyright notice appears in all copies.
69 * Digital Equipment Corporation makes no representations about the
70 * suitability of this software for any purpose. It is provided "as is"
71 * without express or implied warranty.
73 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h,
74 * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL)
75 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h,
76 * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL)
77 * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h,
78 * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL)
81 #ifndef _MIPS_CPUREGS_H_
82 #define _MIPS_CPUREGS_H_
87 * 32-bit mips CPUS partition their 32-bit address space into four segments:
89 * kuseg 0x00000000 - 0x7fffffff User virtual mem, mapped
90 * kseg0 0x80000000 - 0x9fffffff Physical memory, cached, unmapped
91 * kseg1 0xa0000000 - 0xbfffffff Physical memory, uncached, unmapped
92 * kseg2 0xc0000000 - 0xffffffff kernel-virtual, mapped
94 * mips1 physical memory is limited to 512Mbytes, which is
95 * doubly mapped in kseg0 (cached) and kseg1 (uncached.)
96 * Caching of mapped addresses is controlled by bits in the TLB entry.
100 #define MIPS_XUSEG_START (0L << 62)
101 #define MIPS_XUSEG_P(x) (((uint64_t)(x) >> 62) == 0)
102 #define MIPS_USEG_P(x) ((uintptr_t)(x) < 0x80000000L)
103 #define MIPS_XSSEG_START (1L << 62)
104 #define MIPS_XSSEG_P(x) (((uint64_t)(x) >> 62) == 1)
108 * MIPS addresses are signed and we defining as negative so that
109 * in LP64 kern they get sign-extended correctly.
112 #define MIPS_KSEG0_START (-0x7fffffffL-1) /* 0x80000000 */
113 #define MIPS_KSEG1_START -0x60000000L /* 0xa0000000 */
114 #define MIPS_KSEG2_START -0x40000000L /* 0xc0000000 */
115 #define MIPS_MAX_MEM_ADDR -0x42000000L /* 0xbe000000 */
116 #define MIPS_RESERVED_ADDR -0x40380000L /* 0xbfc80000 */
119 #define MIPS_PHYS_MASK 0x1fffffff
121 #define MIPS_KSEG0_TO_PHYS(x) ((uintptr_t)(x) & MIPS_PHYS_MASK)
122 #define MIPS_PHYS_TO_KSEG0(x) ((uintptr_t)(x) | (intptr_t)MIPS_KSEG0_START)
123 #define MIPS_KSEG1_TO_PHYS(x) ((uintptr_t)(x) & MIPS_PHYS_MASK)
124 #define MIPS_PHYS_TO_KSEG1(x) ((uintptr_t)(x) | (intptr_t)MIPS_KSEG1_START)
126 #define MIPS_KSEG0_P(x) (((intptr_t)(x) & ~MIPS_PHYS_MASK) == MIPS_KSEG0_START)
127 #define MIPS_KSEG1_P(x) (((intptr_t)(x) & ~MIPS_PHYS_MASK) == MIPS_KSEG1_START)
128 #define MIPS_KSEG2_P(x) ((uintptr_t)MIPS_KSEG2_START <= (uintptr_t)(x))
130 /* Map virtual address to index in mips3 r4k virtually-indexed cache */
131 #define MIPS3_VA_TO_CINDEX(x) \
132 (((intptr_t)(x) & 0xffffff) | MIPS_KSEG0_START)
135 #define MIPS_XSEG_MASK (0x3fffffffffffffffLL)
136 #define MIPS_XKSEG_START (0x3ULL << 62)
137 #define MIPS_XKSEG_P(x) (((uint64_t)(x) >> 62) == 3)
139 #define MIPS_XKPHYS_START (0x2ULL << 62)
140 #define MIPS_PHYS_TO_XKPHYS_UNCACHED(x) \
141 (MIPS_XKPHYS_START | ((uint64_t)(CCA_UNCACHED) << 59) | (x))
142 #define MIPS_PHYS_TO_XKPHYS_CACHED(x) \
143 (mips3_xkphys_cached | (x))
144 #define MIPS_PHYS_TO_XKPHYS(cca,x) \
145 (MIPS_XKPHYS_START | ((uint64_t)(cca) << 59) | (x))
146 #define MIPS_XKPHYS_TO_PHYS(x) ((uint64_t)(x) & 0x07ffffffffffffffLL)
147 #define MIPS_XKPHYS_TO_CCA(x) (((uint64_t)(x) >> 59) & 7)
148 #define MIPS_XKPHYS_P(x) (((uint64_t)(x) >> 62) == 2)
151 #define CCA_UNCACHED 2
152 #define CCA_CACHEABLE 3 /* cacheable non-coherent */
154 /* CPU dependent mtc0 hazard hook */
155 #define COP0_SYNC /* nothing */
156 #define COP0_HAZARD_FPUENABLE nop; nop; nop; nop;
159 * The bits in the cause register.
161 * Bits common to r3000 and r4000:
163 * MIPS_CR_BR_DELAY Exception happened in branch delay slot.
164 * MIPS_CR_COP_ERR Coprocessor error.
165 * MIPS_CR_IP Interrupt pending bits defined below.
166 * (same meaning as in CAUSE register).
167 * MIPS_CR_EXC_CODE The exception type (see exception codes below).
170 * r3k has 4 bits of execption type, r4k has 5 bits.
172 #define MIPS_CR_BR_DELAY 0x80000000
173 #define MIPS_CR_COP_ERR 0x30000000
174 #define MIPS1_CR_EXC_CODE 0x0000003C /* four bits */
175 #define MIPS3_CR_EXC_CODE 0x0000007C /* five bits */
176 #define MIPS_CR_IP 0x0000FF00
177 #define MIPS_CR_EXC_CODE_SHIFT 2
180 * The bits in the status register. All bits are active when set to 1.
182 * R3000 status register fields:
183 * MIPS_SR_COP_USABILITY Control the usability of the four coprocessors.
184 * MIPS_SR_TS TLB shutdown.
186 * MIPS_SR_INT_IE Master (current) interrupt enable bit.
189 * r3k has cache control is via frobbing SR register bits, whereas the
190 * r4k cache control is via explicit instructions.
191 * r3k has a 3-entry stack of kernel/user bits, whereas the
192 * r4k has kernel/supervisor/user.
194 #define MIPS_SR_COP_USABILITY 0xf0000000
195 #define MIPS_SR_COP_0_BIT 0x10000000
196 #define MIPS_SR_COP_1_BIT 0x20000000
198 /* r4k and r3k differences, see below */
200 #define MIPS_SR_MX 0x01000000 /* MIPS64 */
201 #define MIPS_SR_PX 0x00800000 /* MIPS64 */
202 #define MIPS_SR_BEV 0x00400000 /* Use boot exception vector */
203 #define MIPS_SR_TS 0x00200000
205 /* r4k and r3k differences, see below */
207 #define MIPS_SR_INT_IE 0x00000001
208 /*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */
209 /*#define MIPS_SR_INT_MASK 0x0000ff00*/
213 * The R2000/R3000-specific status register bit definitions.
214 * all bits are active when set to 1.
216 * MIPS_SR_PARITY_ERR Parity error.
217 * MIPS_SR_CACHE_MISS Most recent D-cache load resulted in a miss.
218 * MIPS_SR_PARITY_ZERO Zero replaces outgoing parity bits.
219 * MIPS_SR_SWAP_CACHES Swap I-cache and D-cache.
220 * MIPS_SR_ISOL_CACHES Isolate D-cache from main memory.
221 * Interrupt enable bits defined below.
222 * MIPS_SR_KU_OLD Old kernel/user mode bit. 1 => user mode.
223 * MIPS_SR_INT_ENA_OLD Old interrupt enable bit.
224 * MIPS_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode.
225 * MIPS_SR_INT_ENA_PREV Previous interrupt enable bit.
226 * MIPS_SR_KU_CUR Current kernel/user mode bit. 1 => user mode.
229 #define MIPS1_PARITY_ERR 0x00100000
230 #define MIPS1_CACHE_MISS 0x00080000
231 #define MIPS1_PARITY_ZERO 0x00040000
232 #define MIPS1_SWAP_CACHES 0x00020000
233 #define MIPS1_ISOL_CACHES 0x00010000
235 #define MIPS1_SR_KU_OLD 0x00000020 /* 2nd stacked KU/IE*/
236 #define MIPS1_SR_INT_ENA_OLD 0x00000010 /* 2nd stacked KU/IE*/
237 #define MIPS1_SR_KU_PREV 0x00000008 /* 1st stacked KU/IE*/
238 #define MIPS1_SR_INT_ENA_PREV 0x00000004 /* 1st stacked KU/IE*/
239 #define MIPS1_SR_KU_CUR 0x00000002 /* current KU */
241 /* backwards compatibility */
242 #define MIPS_SR_PARITY_ERR MIPS1_PARITY_ERR
243 #define MIPS_SR_CACHE_MISS MIPS1_CACHE_MISS
244 #define MIPS_SR_PARITY_ZERO MIPS1_PARITY_ZERO
245 #define MIPS_SR_SWAP_CACHES MIPS1_SWAP_CACHES
246 #define MIPS_SR_ISOL_CACHES MIPS1_ISOL_CACHES
248 #define MIPS_SR_KU_OLD MIPS1_SR_KU_OLD
249 #define MIPS_SR_INT_ENA_OLD MIPS1_SR_INT_ENA_OLD
250 #define MIPS_SR_KU_PREV MIPS1_SR_KU_PREV
251 #define MIPS_SR_KU_CUR MIPS1_SR_KU_CUR
252 #define MIPS_SR_INT_ENA_PREV MIPS1_SR_INT_ENA_PREV
255 * R4000 status register bit definitons,
256 * where different from r2000/r3000.
258 #define MIPS3_SR_XX 0x80000000
259 #define MIPS3_SR_RP 0x08000000
260 #define MIPS3_SR_FR 0x04000000
261 #define MIPS3_SR_RE 0x02000000
263 #define MIPS3_SR_DIAG_DL 0x01000000 /* QED 52xx */
264 #define MIPS3_SR_DIAG_IL 0x00800000 /* QED 52xx */
265 #define MIPS3_SR_PX 0x00800000 /* MIPS64 */
266 #define MIPS3_SR_SR 0x00100000
267 #define MIPS3_SR_NMI 0x00080000 /* MIPS32/64 */
268 #define MIPS3_SR_DIAG_CH 0x00040000
269 #define MIPS3_SR_DIAG_CE 0x00020000
270 #define MIPS3_SR_DIAG_PE 0x00010000
271 #define MIPS3_SR_EIE 0x00010000 /* TX79/R5900 */
272 #define MIPS3_SR_KX 0x00000080
273 #define MIPS3_SR_SX 0x00000040
274 #define MIPS3_SR_UX 0x00000020
275 #define MIPS3_SR_KSU_MASK 0x00000018
276 #define MIPS3_SR_KSU_USER 0x00000010
277 #define MIPS3_SR_KSU_SUPER 0x00000008
278 #define MIPS3_SR_KSU_KERNEL 0x00000000
279 #define MIPS3_SR_ERL 0x00000004
280 #define MIPS3_SR_EXL 0x00000002
283 #undef MIPS_SR_INT_IE
284 #define MIPS_SR_INT_IE 0x00010001 /* XXX */
287 #define MIPS_SR_SOFT_RESET MIPS3_SR_SOFT_RESET
288 #define MIPS_SR_DIAG_CH MIPS3_SR_DIAG_CH
289 #define MIPS_SR_DIAG_CE MIPS3_SR_DIAG_CE
290 #define MIPS_SR_DIAG_PE MIPS3_SR_DIAG_PE
291 #define MIPS_SR_KX MIPS3_SR_KX
292 #define MIPS_SR_SX MIPS3_SR_SX
293 #define MIPS_SR_UX MIPS3_SR_UX
295 #define MIPS_SR_KSU_MASK MIPS3_SR_KSU_MASK
296 #define MIPS_SR_KSU_USER MIPS3_SR_KSU_USER
297 #define MIPS_SR_KSU_SUPER MIPS3_SR_KSU_SUPER
298 #define MIPS_SR_KSU_KERNEL MIPS3_SR_KSU_KERNEL
299 #define MIPS_SR_ERL MIPS3_SR_ERL
300 #define MIPS_SR_EXL MIPS3_SR_EXL
304 * The interrupt masks.
305 * If a bit in the mask is 1 then the interrupt is enabled (or pending).
307 #define MIPS_INT_MASK 0xff00
308 #define MIPS_INT_MASK_5 0x8000
309 #define MIPS_INT_MASK_4 0x4000
310 #define MIPS_INT_MASK_3 0x2000
311 #define MIPS_INT_MASK_2 0x1000
312 #define MIPS_INT_MASK_1 0x0800
313 #define MIPS_INT_MASK_0 0x0400
314 #define MIPS_HARD_INT_MASK 0xfc00
315 #define MIPS_SOFT_INT_MASK_1 0x0200
316 #define MIPS_SOFT_INT_MASK_0 0x0100
319 * mips3 CPUs have on-chip timer at INT_MASK_5. Each platform can
320 * choose to enable this interrupt.
322 #if defined(MIPS3_ENABLE_CLOCK_INTR)
323 #define MIPS3_INT_MASK MIPS_INT_MASK
324 #define MIPS3_HARD_INT_MASK MIPS_HARD_INT_MASK
326 #define MIPS3_INT_MASK (MIPS_INT_MASK & ~MIPS_INT_MASK_5)
327 #define MIPS3_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MIPS_INT_MASK_5)
331 * The bits in the context register.
333 #define MIPS1_CNTXT_PTE_BASE 0xFFE00000
334 #define MIPS1_CNTXT_BAD_VPN 0x001FFFFC
336 #define MIPS3_CNTXT_PTE_BASE 0xFF800000
337 #define MIPS3_CNTXT_BAD_VPN2 0x007FFFF0
340 * The bits in the MIPS3 config register.
342 * bit 0..5: R/W, Bit 6..31: R/O
345 /* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */
346 #define MIPS3_CONFIG_K0_MASK 0x00000007
349 * R/W Update on Store Conditional
350 * 0: Store Conditional uses coherency algorithm specified by TLB
351 * 1: Store Conditional uses cacheable coherent update on write
353 #define MIPS3_CONFIG_CU 0x00000008
355 #define MIPS3_CONFIG_DB 0x00000010 /* Primary D-cache line size */
356 #define MIPS3_CONFIG_IB 0x00000020 /* Primary I-cache line size */
357 #define MIPS3_CONFIG_CACHE_L1_LSIZE(config, bit) \
358 (((config) & (bit)) ? 32 : 16)
360 #define MIPS3_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */
361 #define MIPS3_CONFIG_DC_SHIFT 6
362 #define MIPS3_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */
363 #define MIPS3_CONFIG_IC_SHIFT 9
364 #define MIPS3_CONFIG_C_DEFBASE 0x1000 /* default base 2^12 */
366 /* Cache size mode indication: available only on Vr41xx CPUs */
367 #define MIPS3_CONFIG_CS 0x00001000
368 #define MIPS3_CONFIG_C_4100BASE 0x0400 /* base is 2^10 if CS=1 */
369 #define MIPS3_CONFIG_CACHE_SIZE(config, mask, base, shift) \
370 ((base) << (((config) & (mask)) >> (shift)))
372 /* External cache enable: Controls L2 for R5000/Rm527x and L3 for Rm7000 */
373 #define MIPS3_CONFIG_SE 0x00001000
375 /* Block ordering: 0: sequential, 1: sub-block */
376 #define MIPS3_CONFIG_EB 0x00002000
378 /* ECC mode - 0: ECC mode, 1: parity mode */
379 #define MIPS3_CONFIG_EM 0x00004000
381 /* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */
382 #define MIPS3_CONFIG_BE 0x00008000
384 /* Dirty Shared coherency state - 0: enabled, 1: disabled */
385 #define MIPS3_CONFIG_SM 0x00010000
387 /* Secondary Cache - 0: present, 1: not present */
388 #define MIPS3_CONFIG_SC 0x00020000
390 /* System Port width - 0: 64-bit, 1: 32-bit (QED RM523x), 2,3: reserved */
391 #define MIPS3_CONFIG_EW_MASK 0x000c0000
392 #define MIPS3_CONFIG_EW_SHIFT 18
394 /* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */
395 #define MIPS3_CONFIG_SW 0x00100000
397 /* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */
398 #define MIPS3_CONFIG_SS 0x00200000
400 /* Secondary Cache line size */
401 #define MIPS3_CONFIG_SB_MASK 0x00c00000
402 #define MIPS3_CONFIG_SB_SHIFT 22
403 #define MIPS3_CONFIG_CACHE_L2_LSIZE(config) \
404 (0x10 << (((config) & MIPS3_CONFIG_SB_MASK) >> MIPS3_CONFIG_SB_SHIFT))
406 /* Write back data rate */
407 #define MIPS3_CONFIG_EP_MASK 0x0f000000
408 #define MIPS3_CONFIG_EP_SHIFT 24
410 /* System clock ratio - this value is CPU dependent */
411 #define MIPS3_CONFIG_EC_MASK 0x70000000
412 #define MIPS3_CONFIG_EC_SHIFT 28
414 /* Master-Checker Mode - 1: enabled */
415 #define MIPS3_CONFIG_CM 0x80000000
418 * The bits in the MIPS4 config register.
421 /* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */
422 #define MIPS4_CONFIG_K0_MASK MIPS3_CONFIG_K0_MASK
423 #define MIPS4_CONFIG_DN_MASK 0x00000018 /* Device number */
424 #define MIPS4_CONFIG_CT 0x00000020 /* CohPrcReqTar */
425 #define MIPS4_CONFIG_PE 0x00000040 /* PreElmReq */
426 #define MIPS4_CONFIG_PM_MASK 0x00000180 /* PreReqMax */
427 #define MIPS4_CONFIG_EC_MASK 0x00001e00 /* SysClkDiv */
428 #define MIPS4_CONFIG_SB 0x00002000 /* SCBlkSize */
429 #define MIPS4_CONFIG_SK 0x00004000 /* SCColEn */
430 #define MIPS4_CONFIG_BE 0x00008000 /* MemEnd */
431 #define MIPS4_CONFIG_SS_MASK 0x00070000 /* SCSize */
432 #define MIPS4_CONFIG_SC_MASK 0x00380000 /* SCClkDiv */
433 #define MIPS4_CONFIG_RESERVED 0x03c00000 /* Reserved wired 0 */
434 #define MIPS4_CONFIG_DC_MASK 0x1c000000 /* Primary D-Cache size */
435 #define MIPS4_CONFIG_IC_MASK 0xe0000000 /* Primary I-Cache size */
437 #define MIPS4_CONFIG_DC_SHIFT 26
438 #define MIPS4_CONFIG_IC_SHIFT 29
440 #define MIPS4_CONFIG_CACHE_SIZE(config, mask, base, shift) \
441 ((base) << (((config) & (mask)) >> (shift)))
443 #define MIPS4_CONFIG_CACHE_L2_LSIZE(config) \
444 (((config) & MIPS4_CONFIG_SB) ? 128 : 64)
447 * Location of exception vectors.
449 * Common vectors: reset and UTLB miss.
451 #define MIPS_RESET_EXC_VEC MIPS_PHYS_TO_KSEG1(0x1FC00000)
452 #define MIPS_UTLB_MISS_EXC_VEC MIPS_PHYS_TO_KSEG0(0)
455 * MIPS-1 general exception vector (everything else)
457 #define MIPS1_GEN_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0080)
460 * MIPS-III exception vectors
462 #define MIPS3_XTLB_MISS_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0080)
463 #define MIPS3_CACHE_ERR_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0100)
464 #define MIPS3_GEN_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0180)
467 * TX79 (R5900) exception vectors
469 #define MIPS_R5900_COUNTER_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0080)
470 #define MIPS_R5900_DEBUG_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0100)
473 * MIPS32/MIPS64 (and some MIPS3) dedicated interrupt vector.
475 #define MIPS3_INTR_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0200)
478 * Coprocessor 0 registers:
480 * v--- width for mips I,III,32,64
481 * (3=32bit, 6=64bit, i=impl dep)
482 * 0 MIPS_COP_0_TLB_INDEX 3333 TLB Index.
483 * 1 MIPS_COP_0_TLB_RANDOM 3333 TLB Random.
484 * 2 MIPS_COP_0_TLB_LOW 3... r3k TLB entry low.
485 * 2 MIPS_COP_0_TLB_LO0 .636 r4k TLB entry low.
486 * 3 MIPS_COP_0_TLB_LO1 .636 r4k TLB entry low, extended.
487 * 4 MIPS_COP_0_TLB_CONTEXT 3636 TLB Context.
488 * 5 MIPS_COP_0_TLB_PG_MASK .333 TLB Page Mask register.
489 * 6 MIPS_COP_0_TLB_WIRED .333 Wired TLB number.
490 * 8 MIPS_COP_0_BAD_VADDR 3636 Bad virtual address.
491 * 9 MIPS_COP_0_COUNT .333 Count register.
492 * 10 MIPS_COP_0_TLB_HI 3636 TLB entry high.
493 * 11 MIPS_COP_0_COMPARE .333 Compare (against Count).
494 * 12 MIPS_COP_0_STATUS 3333 Status register.
495 * 13 MIPS_COP_0_CAUSE 3333 Exception cause register.
496 * 14 MIPS_COP_0_EXC_PC 3636 Exception PC.
497 * 15 MIPS_COP_0_PRID 3333 Processor revision identifier.
498 * 15/1 MIPS_COP_0_EBASE ..33 Exception Base
499 * 16 MIPS_COP_0_CONFIG 3333 Configuration register.
500 * 16/1 MIPS_COP_0_CONFIG1 ..33 Configuration register 1.
501 * 16/2 MIPS_COP_0_CONFIG2 ..33 Configuration register 2.
502 * 16/3 MIPS_COP_0_CONFIG3 ..33 Configuration register 3.
503 * 17 MIPS_COP_0_LLADDR .336 Load Linked Address.
504 * 18 MIPS_COP_0_WATCH_LO .336 WatchLo register.
505 * 19 MIPS_COP_0_WATCH_HI .333 WatchHi register.
506 * 20 MIPS_COP_0_TLB_XCONTEXT .6.6 TLB XContext register.
507 * 23 MIPS_COP_0_DEBUG .... Debug JTAG register.
508 * 24 MIPS_COP_0_DEPC .... DEPC JTAG register.
509 * 25 MIPS_COP_0_PERFCNT ..36 Performance Counter register.
510 * 26 MIPS_COP_0_ECC .3ii ECC / Error Control register.
511 * 27 MIPS_COP_0_CACHE_ERR .3ii Cache Error register.
512 * 28/0 MIPS_COP_0_TAG_LO .3ii Cache TagLo register (instr).
513 * 28/1 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (instr).
514 * 28/2 MIPS_COP_0_TAG_LO ..ii Cache TagLo register (data).
515 * 28/3 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (data).
516 * 29/0 MIPS_COP_0_TAG_HI .3ii Cache TagHi register (instr).
517 * 29/1 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (instr).
518 * 29/2 MIPS_COP_0_TAG_HI ..ii Cache TagHi register (data).
519 * 29/3 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (data).
520 * 30 MIPS_COP_0_ERROR_PC .636 Error EPC register.
521 * 31 MIPS_COP_0_DESAVE .... DESAVE JTAG register.
524 #define _(n) __CONCAT($,n)
528 #define MIPS_COP_0_TLB_INDEX _(0)
529 #define MIPS_COP_0_TLB_RANDOM _(1)
530 /* Name and meaning of TLB bits for $2 differ on r3k and r4k. */
532 #define MIPS_COP_0_TLB_CONTEXT _(4)
533 /* $5 and $6 new with MIPS-III */
534 #define MIPS_COP_0_BAD_VADDR _(8)
535 #define MIPS_COP_0_TLB_HI _(10)
536 #define MIPS_COP_0_STATUS _(12)
537 #define MIPS_COP_0_CAUSE _(13)
538 #define MIPS_COP_0_EXC_PC _(14)
539 #define MIPS_COP_0_PRID _(15)
543 #define MIPS_COP_0_TLB_LOW _(2)
546 #define MIPS_COP_0_TLB_LO0 _(2)
547 #define MIPS_COP_0_TLB_LO1 _(3)
549 #define MIPS_COP_0_TLB_PG_MASK _(5)
550 #define MIPS_COP_0_TLB_WIRED _(6)
552 #define MIPS_COP_0_COUNT _(9)
553 #define MIPS_COP_0_COMPARE _(11)
555 #define MIPS_COP_0_CONFIG _(16)
556 #define MIPS_COP_0_LLADDR _(17)
557 #define MIPS_COP_0_WATCH_LO _(18)
558 #define MIPS_COP_0_WATCH_HI _(19)
559 #define MIPS_COP_0_TLB_XCONTEXT _(20)
560 #define MIPS_COP_0_ECC _(26)
561 #define MIPS_COP_0_CACHE_ERR _(27)
562 #define MIPS_COP_0_TAG_LO _(28)
563 #define MIPS_COP_0_TAG_HI _(29)
564 #define MIPS_COP_0_ERROR_PC _(30)
567 #define MIPS_COP_0_DEBUG _(23)
568 #define MIPS_COP_0_DEPC _(24)
569 #define MIPS_COP_0_PERFCNT _(25)
570 #define MIPS_COP_0_DATA_LO _(28)
571 #define MIPS_COP_0_DATA_HI _(29)
572 #define MIPS_COP_0_DESAVE _(31)
575 * Values for the code field in a break instruction.
577 #define MIPS_BREAK_INSTR 0x0000000d
578 #define MIPS_BREAK_VAL_MASK 0x03ff0000
579 #define MIPS_BREAK_VAL_SHIFT 16
580 #define MIPS_BREAK_KDB_VAL 512
581 #define MIPS_BREAK_SSTEP_VAL 513
582 #define MIPS_BREAK_BRKPT_VAL 514
583 #define MIPS_BREAK_SOVER_VAL 515
584 #define MIPS_BREAK_KDB (MIPS_BREAK_INSTR | \
585 (MIPS_BREAK_KDB_VAL << MIPS_BREAK_VAL_SHIFT))
586 #define MIPS_BREAK_SSTEP (MIPS_BREAK_INSTR | \
587 (MIPS_BREAK_SSTEP_VAL << MIPS_BREAK_VAL_SHIFT))
588 #define MIPS_BREAK_BRKPT (MIPS_BREAK_INSTR | \
589 (MIPS_BREAK_BRKPT_VAL << MIPS_BREAK_VAL_SHIFT))
590 #define MIPS_BREAK_SOVER (MIPS_BREAK_INSTR | \
591 (MIPS_BREAK_SOVER_VAL << MIPS_BREAK_VAL_SHIFT))
594 * Mininum and maximum cache sizes.
596 #define MIPS_MIN_CACHE_SIZE (16 * 1024)
597 #define MIPS_MAX_CACHE_SIZE (256 * 1024)
598 #define MIPS3_MAX_PCACHE_SIZE (32 * 1024) /* max. primary cache size */
601 * The floating point version and status registers.
603 #define MIPS_FPU_ID $0
604 #define MIPS_FPU_CSR $31
607 * The floating point coprocessor status register bits.
609 #define MIPS_FPU_ROUNDING_BITS 0x00000003
610 #define MIPS_FPU_ROUND_RN 0x00000000
611 #define MIPS_FPU_ROUND_RZ 0x00000001
612 #define MIPS_FPU_ROUND_RP 0x00000002
613 #define MIPS_FPU_ROUND_RM 0x00000003
614 #define MIPS_FPU_STICKY_BITS 0x0000007c
615 #define MIPS_FPU_STICKY_INEXACT 0x00000004
616 #define MIPS_FPU_STICKY_UNDERFLOW 0x00000008
617 #define MIPS_FPU_STICKY_OVERFLOW 0x00000010
618 #define MIPS_FPU_STICKY_DIV0 0x00000020
619 #define MIPS_FPU_STICKY_INVALID 0x00000040
620 #define MIPS_FPU_ENABLE_BITS 0x00000f80
621 #define MIPS_FPU_ENABLE_INEXACT 0x00000080
622 #define MIPS_FPU_ENABLE_UNDERFLOW 0x00000100
623 #define MIPS_FPU_ENABLE_OVERFLOW 0x00000200
624 #define MIPS_FPU_ENABLE_DIV0 0x00000400
625 #define MIPS_FPU_ENABLE_INVALID 0x00000800
626 #define MIPS_FPU_EXCEPTION_BITS 0x0003f000
627 #define MIPS_FPU_EXCEPTION_INEXACT 0x00001000
628 #define MIPS_FPU_EXCEPTION_UNDERFLOW 0x00002000
629 #define MIPS_FPU_EXCEPTION_OVERFLOW 0x00004000
630 #define MIPS_FPU_EXCEPTION_DIV0 0x00008000
631 #define MIPS_FPU_EXCEPTION_INVALID 0x00010000
632 #define MIPS_FPU_EXCEPTION_UNIMPL 0x00020000
633 #define MIPS_FPU_COND_BIT 0x00800000
634 #define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */
635 #define MIPS1_FPC_MBZ_BITS 0xff7c0000
636 #define MIPS3_FPC_MBZ_BITS 0xfe7c0000
640 * Constants to determine if have a floating point instruction.
642 #define MIPS_OPCODE_SHIFT 26
643 #define MIPS_OPCODE_C1 0x11
647 * The low part of the TLB entry.
649 #define MIPS1_TLB_PFN 0xfffff000
650 #define MIPS1_TLB_NON_CACHEABLE_BIT 0x00000800
651 #define MIPS1_TLB_DIRTY_BIT 0x00000400
652 #define MIPS1_TLB_VALID_BIT 0x00000200
653 #define MIPS1_TLB_GLOBAL_BIT 0x00000100
655 #define MIPS3_TLB_PFN 0x3fffffc0
656 #define MIPS3_TLB_ATTR_MASK 0x00000038
657 #define MIPS3_TLB_ATTR_SHIFT 3
658 #define MIPS3_TLB_DIRTY_BIT 0x00000004
659 #define MIPS3_TLB_VALID_BIT 0x00000002
660 #define MIPS3_TLB_GLOBAL_BIT 0x00000001
662 #define MIPS1_TLB_PHYS_PAGE_SHIFT 12
663 #define MIPS3_TLB_PHYS_PAGE_SHIFT 6
664 #define MIPS1_TLB_PF_NUM MIPS1_TLB_PFN
665 #define MIPS3_TLB_PF_NUM MIPS3_TLB_PFN
666 #define MIPS1_TLB_MOD_BIT MIPS1_TLB_DIRTY_BIT
667 #define MIPS3_TLB_MOD_BIT MIPS3_TLB_DIRTY_BIT
670 * MIPS3_TLB_ATTR values - coherency algorithm:
671 * 0: cacheable, noncoherent, write-through, no write allocate
672 * 1: cacheable, noncoherent, write-through, write allocate
674 * 3: cacheable, noncoherent, write-back (noncoherent)
675 * 4: cacheable, coherent, write-back, exclusive (exclusive)
676 * 5: cacheable, coherent, write-back, exclusive on write (sharable)
677 * 6: cacheable, coherent, write-back, update on write (update)
678 * 7: uncached, accelerated (gather STORE operations)
680 #define MIPS3_TLB_ATTR_WT 0 /* IDT */
681 #define MIPS3_TLB_ATTR_WT_WRITEALLOCATE 1 /* IDT */
682 #define MIPS3_TLB_ATTR_UNCACHED 2 /* R4000/R4400, IDT */
683 #define MIPS3_TLB_ATTR_WB_NONCOHERENT 3 /* R4000/R4400, IDT */
684 #define MIPS3_TLB_ATTR_WB_EXCLUSIVE 4 /* R4000/R4400 */
685 #define MIPS3_TLB_ATTR_WB_SHARABLE 5 /* R4000/R4400 */
686 #define MIPS3_TLB_ATTR_WB_UPDATE 6 /* R4000/R4400 */
687 #define MIPS4_TLB_ATTR_UNCACHED_ACCELERATED 7 /* R10000 */
691 * The high part of the TLB entry.
693 #define MIPS1_TLB_VPN 0xfffff000
694 #define MIPS1_TLB_PID 0x00000fc0
695 #define MIPS1_TLB_PID_SHIFT 6
697 #define MIPS3_TLB_VPN2 0xffffe000
698 #define MIPS3_TLB_ASID 0x000000ff
700 #define MIPS1_TLB_VIRT_PAGE_NUM MIPS1_TLB_VPN
701 #define MIPS3_TLB_VIRT_PAGE_NUM MIPS3_TLB_VPN2
702 #define MIPS3_TLB_PID MIPS3_TLB_ASID
703 #define MIPS_TLB_VIRT_PAGE_SHIFT 12
706 * r3000: shift count to put the index in the right spot.
708 #define MIPS1_TLB_INDEX_SHIFT 8
711 * The first TLB that write random hits.
713 #define MIPS1_TLB_FIRST_RAND_ENTRY 8
714 #define MIPS3_TLB_WIRED_UPAGES 1
717 * The number of process id entries.
719 #define MIPS1_TLB_NUM_PIDS 64
720 #define MIPS3_TLB_NUM_ASIDS 256
723 * Patch codes to hide CPU design differences between MIPS1 and MIPS3.
726 /* XXX simonb: this is before MIPS3_PLUS is defined (and is ugly!) */
728 #if !(defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \
729 && defined(MIPS1) /* XXX simonb must be neater! */
730 #define MIPS_TLB_PID_SHIFT MIPS1_TLB_PID_SHIFT
731 #define MIPS_TLB_NUM_PIDS MIPS1_TLB_NUM_PIDS
734 #if (defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \
735 && !defined(MIPS1) /* XXX simonb must be neater! */
736 #define MIPS_TLB_PID_SHIFT 0
737 #define MIPS_TLB_NUM_PIDS MIPS3_TLB_NUM_ASIDS
741 #if !defined(MIPS_TLB_PID_SHIFT)
742 #define MIPS_TLB_PID_SHIFT \
743 ((MIPS_HAS_R4K_MMU) ? 0 : MIPS1_TLB_PID_SHIFT)
745 #define MIPS_TLB_NUM_PIDS \
746 ((MIPS_HAS_R4K_MMU) ? MIPS3_TLB_NUM_ASIDS : MIPS1_TLB_NUM_PIDS)
750 * CPU processor revision IDs for company ID == 0 (non mips32/64 chips)
752 #define MIPS_R2000 0x01 /* MIPS R2000 ISA I */
753 #define MIPS_R3000 0x02 /* MIPS R3000 ISA I */
754 #define MIPS_R6000 0x03 /* MIPS R6000 ISA II */
755 #define MIPS_R4000 0x04 /* MIPS R4000/R4400 ISA III */
756 #define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivative ISA I */
757 #define MIPS_R6000A 0x06 /* MIPS R6000A ISA II */
758 #define MIPS_R3IDT 0x07 /* IDT R3041 or RC36100 ISA I */
759 #define MIPS_R10000 0x09 /* MIPS R10000 ISA IV */
760 #define MIPS_R4200 0x0a /* NEC VR4200 ISA III */
761 #define MIPS_R4300 0x0b /* NEC VR4300 ISA III */
762 #define MIPS_R4100 0x0c /* NEC VR4100 ISA III */
763 #define MIPS_R12000 0x0e /* MIPS R12000 ISA IV */
764 #define MIPS_R14000 0x0f /* MIPS R14000 ISA IV */
765 #define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */
766 #define MIPS_RC32300 0x18 /* IDT RC32334,332,355 ISA 32 */
767 #define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */
768 #define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */
769 #define MIPS_R3SONY 0x21 /* Sony R3000 based ISA I */
770 #define MIPS_R4650 0x22 /* QED R4650 ISA III */
771 #define MIPS_TX3900 0x22 /* Toshiba TX39 family ISA I */
772 #define MIPS_R5000 0x23 /* MIPS R5000 ISA IV */
773 #define MIPS_R3NKK 0x23 /* NKK R3000 based ISA I */
774 #define MIPS_RC32364 0x26 /* IDT RC32364 ISA 32 */
775 #define MIPS_RM7000 0x27 /* QED RM7000 ISA IV */
776 #define MIPS_RM5200 0x28 /* QED RM5200s ISA IV */
777 #define MIPS_TX4900 0x2d /* Toshiba TX49 family ISA III */
778 #define MIPS_R5900 0x2e /* Toshiba R5900 (EECore) ISA --- */
779 #define MIPS_RC64470 0x30 /* IDT RC64474/RC64475 ISA III */
780 #define MIPS_TX7900 0x38 /* Toshiba TX79 ISA III+*/
781 #define MIPS_R5400 0x54 /* NEC VR5400 ISA IV */
782 #define MIPS_R5500 0x55 /* NEC VR5500 ISA IV */
783 #define MIPS_LOONGSON2 0x63 /* ICT Loongson-2 ISA III */
786 * CPU revision IDs for some prehistoric processors.
790 #define MIPS_REV_R2000A 0x16 /* R2000A uses R3000 proc revision */
791 #define MIPS_REV_R3000 0x20
792 #define MIPS_REV_R3000A 0x30
794 /* For MIPS_TX3900 */
795 #define MIPS_REV_TX3912 0x10
796 #define MIPS_REV_TX3922 0x30
797 #define MIPS_REV_TX3927 0x40
800 #define MIPS_REV_R4000_A 0x00
801 #define MIPS_REV_R4000_B 0x22
802 #define MIPS_REV_R4000_C 0x30
803 #define MIPS_REV_R4400_A 0x40
804 #define MIPS_REV_R4400_B 0x50
805 #define MIPS_REV_R4400_C 0x60
807 /* For MIPS_TX4900 */
808 #define MIPS_REV_TX4927 0x22
810 /* For MIPS_LOONGSON2 */
811 #define MIPS_REV_LOONGSON2E 0x02
812 #define MIPS_REV_LOONGSON2F 0x03
815 * CPU processor revision IDs for company ID == 1 (MIPS)
817 #define MIPS_4Kc 0x80 /* MIPS 4Kc ISA 32 */
818 #define MIPS_5Kc 0x81 /* MIPS 5Kc ISA 64 */
819 #define MIPS_20Kc 0x82 /* MIPS 20Kc ISA 64 */
820 #define MIPS_4Kmp 0x83 /* MIPS 4Km/4Kp ISA 32 */
821 #define MIPS_4KEc 0x84 /* MIPS 4KEc ISA 32 */
822 #define MIPS_4KEmp 0x85 /* MIPS 4KEm/4KEp ISA 32 */
823 #define MIPS_4KSc 0x86 /* MIPS 4KSc ISA 32 */
824 #define MIPS_M4K 0x87 /* MIPS M4K ISA 32 Rel 2 */
825 #define MIPS_25Kf 0x88 /* MIPS 25Kf ISA 64 */
826 #define MIPS_5KE 0x89 /* MIPS 5KE ISA 64 Rel 2 */
827 #define MIPS_4KEc_R2 0x90 /* MIPS 4KEc_R2 ISA 32 Rel 2 */
828 #define MIPS_4KEmp_R2 0x91 /* MIPS 4KEm/4KEp_R2 ISA 32 Rel 2 */
829 #define MIPS_4KSd 0x92 /* MIPS 4KSd ISA 32 Rel 2 */
830 #define MIPS_24K 0x93 /* MIPS 24Kc/24Kf ISA 32 Rel 2 */
831 #define MIPS_34K 0x95 /* MIPS 34K ISA 32 R2 MT */
832 #define MIPS_24KE 0x96 /* MIPS 24KEc ISA 32 Rel 2 */
833 #define MIPS_74K 0x97 /* MIPS 74Kc/74Kf ISA 32 Rel 2 */
836 * Alchemy (company ID 3) use the processor ID field to donote the CPU core
837 * revision and the company options field do donate the SOC chip type.
839 /* CPU processor revision IDs */
840 #define MIPS_AU_REV1 0x01 /* Alchemy Au1000 (Rev 1) ISA 32 */
841 #define MIPS_AU_REV2 0x02 /* Alchemy Au1000 (Rev 2) ISA 32 */
842 /* CPU company options IDs */
843 #define MIPS_AU1000 0x00
844 #define MIPS_AU1500 0x01
845 #define MIPS_AU1100 0x02
846 #define MIPS_AU1550 0x03
849 * CPU processor revision IDs for company ID == 4 (SiByte)
851 #define MIPS_SB1 0x01 /* SiByte SB1 ISA 64 */
854 * CPU processor revision IDs for company ID == 5 (SandCraft)
856 #define MIPS_SR7100 0x04 /* SandCraft SR7100 ISA 64 */
859 * CPU processor revision IDs for company ID == 12 (RMI)
861 #define MIPS_XLR732 0x00 /* RMI XLR732-C ISA 64 */
862 #define MIPS_XLR716 0x02 /* RMI XLR716-C ISA 64 */
863 #define MIPS_XLR532 0x08 /* RMI XLR532-C ISA 64 */
864 #define MIPS_XLR516 0x0a /* RMI XLR516-C ISA 64 */
865 #define MIPS_XLR508 0x0b /* RMI XLR508-C ISA 64 */
866 #define MIPS_XLR308 0x0f /* RMI XLR308-C ISA 64 */
867 #define MIPS_XLS616 0x40 /* RMI XLS616 ISA 64 */
868 #define MIPS_XLS416 0x44 /* RMI XLS416 ISA 64 */
869 #define MIPS_XLS608 0x4A /* RMI XLS608 ISA 64 */
870 #define MIPS_XLS408 0x4E /* RMI XLS406 ISA 64 */
871 #define MIPS_XLS404 0x4F /* RMI XLS404 ISA 64 */
872 #define MIPS_XLS408LITE 0x88 /* RMI XLS408-Lite ISA 64 */
873 #define MIPS_XLS404LITE 0x8C /* RMI XLS404-Lite ISA 64 */
874 #define MIPS_XLS208 0x8E /* RMI XLS208 ISA 64 */
875 #define MIPS_XLS204 0x8F /* RMI XLS204 ISA 64 */
876 #define MIPS_XLS108 0xCE /* RMI XLS108 ISA 64 */
877 #define MIPS_XLS104 0xCF /* RMI XLS104 ISA 64 */
880 * FPU processor revision ID
882 #define MIPS_SOFT 0x00 /* Software emulation ISA I */
883 #define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */
884 #define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */
885 #define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */
886 #define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */
887 #define MIPS_R4010 0x05 /* MIPS R4010 FPC ISA II */
888 #define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */
889 #define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */
891 #endif /* _MIPS_CPUREGS_H_ */
893 /* $NetBSD: cpu.h,v 1.94 2009/12/14 00:46:04 matt Exp $ */
896 * Copyright (c) 1992, 1993
897 * The Regents of the University of California. All rights reserved.
899 * This code is derived from software contributed to Berkeley by
900 * Ralph Campbell and Rick Macklem.
902 * Redistribution and use in source and binary forms, with or without
903 * modification, are permitted provided that the following conditions
905 * 1. Redistributions of source code must retain the above copyright
906 * notice, this list of conditions and the following disclaimer.
907 * 2. Redistributions in binary form must reproduce the above copyright
908 * notice, this list of conditions and the following disclaimer in the
909 * documentation and/or other materials provided with the distribution.
910 * 3. Neither the name of the University nor the names of its contributors
911 * may be used to endorse or promote products derived from this software
912 * without specific prior written permission.
914 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
915 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
916 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
917 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
918 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
919 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
920 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
921 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
922 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
923 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
926 * @(#)cpu.h 8.4 (Berkeley) 1/4/94
934 * bitfield defines for cpu_cp0flags
936 #define MIPS_CP0FL_USE __BIT(0) /* use these flags */
937 #define MIPS_CP0FL_ECC __BIT(1)
938 #define MIPS_CP0FL_CACHE_ERR __BIT(2)
939 #define MIPS_CP0FL_EIRR __BIT(3)
940 #define MIPS_CP0FL_EIMR __BIT(4)
941 #define MIPS_CP0FL_EBASE __BIT(5)
942 #define MIPS_CP0FL_CONFIG __BIT(6)
943 #define MIPS_CP0FL_CONFIGn(n) (__BIT(7) << ((n) & 7))
946 * cpu_cidflags defines, by company
949 * RMI company-specific cpu_cidflags
951 #define MIPS_CIDFL_RMI_TYPE __BITS(0,2)
952 #define CIDFL_RMI_TYPE_XLR 0
953 #define CIDFL_RMI_TYPE_XLS 1
954 #define CIDFL_RMI_TYPE_XLP 2
957 #define CPU_INFO_ITERATOR int
958 #define CPU_INFO_FOREACH(cii, ci) \
959 (void)(cii), ci = &cpu_info_store; ci != NULL; ci = ci->ci_next
963 * CTL_MACHDEP definitions.
965 #define CPU_CONSDEV 1 /* dev_t: console terminal device */
966 #define CPU_BOOTED_KERNEL 2 /* string: booted kernel name */
967 #define CPU_ROOT_DEVICE 3 /* string: root device name */
968 #define CPU_LLSC 4 /* OS/CPU supports LL/SC instruction */
971 * Platform can override, but note this breaks userland compatibility
972 * with other mips platforms.
975 #define CPU_MAXID 5 /* number of valid machdep ids */
980 #if defined(_LKM) || defined(_STANDALONE)
981 /* Assume all CPU architectures are valid for LKM's and standlone progs */
989 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 0
990 #error at least one of MIPS1, MIPS3, MIPS4, MIPS32 or MIPS64 must be specified
993 /* Shortcut for MIPS3 or above defined */
994 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)
1001 * Macros to find the CPU architecture we're on at run-time,
1002 * or if possible, at compile-time.
1005 #define CPU_ARCH_MIPSx 0 /* XXX unknown */
1006 #define CPU_ARCH_MIPS1 (1 << 0)
1007 #define CPU_ARCH_MIPS2 (1 << 1)
1008 #define CPU_ARCH_MIPS3 (1 << 2)
1009 #define CPU_ARCH_MIPS4 (1 << 3)
1010 #define CPU_ARCH_MIPS5 (1 << 4)
1011 #define CPU_ARCH_MIPS32 (1 << 5)
1012 #define CPU_ARCH_MIPS64 (1 << 6)
1014 /* Note: must be kept in sync with -ffixed-?? Makefile.mips. */
1015 #define MIPS_CURLWP $23
1016 #define MIPS_CURLWP_QUOTED "$23"
1017 #define MIPS_CURLWP_CARD 23
1018 #define MIPS_CURLWP_FRAME(x) FRAME_S7(x)
1022 #define curlwp mips_curlwp
1023 #define curcpu() (curlwp->l_cpu)
1024 #define curpcb ((struct pcb *)lwp_getpcb(curlwp))
1025 #define fpcurlwp (curcpu()->ci_fpcurlwp)
1026 #define cpu_number() (0)
1027 #define cpu_proc_fork(p1, p2) ((void)((p2)->p_md.md_abi = (p1)->p_md.md_abi))
1030 * Should the following be in a cpu_info type structure?
1031 * And how many of these are per-cpu vs. per-system? (Ie,
1032 * we can assume that all cpus have the same mmu-type, but
1033 * maybe not that all cpus run at the same clock speed.
1034 * Some SGI's apparently support R12k and R14k in the same
1038 #define CPU_MIPS_R4K_MMU 0x0001
1039 #define CPU_MIPS_NO_LLSC 0x0002
1040 #define CPU_MIPS_CAUSE_IV 0x0004
1041 #define CPU_MIPS_HAVE_SPECIAL_CCA 0x0008 /* Defaults to '3' if not set. */
1042 #define CPU_MIPS_CACHED_CCA_MASK 0x0070
1043 #define CPU_MIPS_CACHED_CCA_SHIFT 4
1044 #define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */
1045 #define CPU_MIPS_USE_WAIT 0x0100 /* Use "wait"-based cpu_idle() */
1046 #define CPU_MIPS_NO_WAIT 0x0200 /* Inverse of previous, for mips32/64 */
1047 #define CPU_MIPS_D_CACHE_COHERENT 0x0400 /* D-cache is fully coherent */
1048 #define CPU_MIPS_I_D_CACHE_COHERENT 0x0800 /* I-cache funcs don't need to flush the D-cache */
1049 #define CPU_MIPS_NO_LLADDR 0x1000
1050 #define CPU_MIPS_HAVE_MxCR 0x2000 /* have mfcr, mtcr insns */
1051 #define MIPS_NOT_SUPP 0x8000
1053 #endif /* !_LOCORE */
1055 #if ((MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 1) || defined(_LOCORE)
1059 # define CPUISMIPS3 0
1060 # define CPUIS64BITS 0
1061 # define CPUISMIPS32 0
1062 # define CPUISMIPS64 0
1063 # define CPUISMIPSNN 0
1064 # define MIPS_HAS_R4K_MMU 0
1065 # define MIPS_HAS_CLOCK 0
1066 # define MIPS_HAS_LLSC 0
1067 # define MIPS_HAS_LLADDR 0
1069 #elif defined(MIPS3) || defined(MIPS4)
1071 # define CPUISMIPS3 1
1072 # define CPUIS64BITS 1
1073 # define CPUISMIPS32 0
1074 # define CPUISMIPS64 0
1075 # define CPUISMIPSNN 0
1076 # define MIPS_HAS_R4K_MMU 1
1077 # define MIPS_HAS_CLOCK 1
1078 # if defined(_LOCORE)
1079 # if !defined(MIPS3_5900) && !defined(MIPS3_4100)
1080 # define MIPS_HAS_LLSC 1
1082 # define MIPS_HAS_LLSC 0
1084 # else /* _LOCORE */
1085 # define MIPS_HAS_LLSC (mips_has_llsc)
1086 # endif /* _LOCORE */
1087 # define MIPS_HAS_LLADDR ((mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0)
1089 #elif defined(MIPS32)
1091 # define CPUISMIPS3 1
1092 # define CPUIS64BITS 0
1093 # define CPUISMIPS32 1
1094 # define CPUISMIPS64 0
1095 # define CPUISMIPSNN 1
1096 # define MIPS_HAS_R4K_MMU 1
1097 # define MIPS_HAS_CLOCK 1
1098 # define MIPS_HAS_LLSC 1
1099 # define MIPS_HAS_LLADDR ((mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0)
1101 #elif defined(MIPS64)
1103 # define CPUISMIPS3 1
1104 # define CPUIS64BITS 1
1105 # define CPUISMIPS32 0
1106 # define CPUISMIPS64 1
1107 # define CPUISMIPSNN 1
1108 # define MIPS_HAS_R4K_MMU 1
1109 # define MIPS_HAS_CLOCK 1
1110 # define MIPS_HAS_LLSC 1
1111 # define MIPS_HAS_LLADDR ((mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0)
1115 #else /* run-time test */
1119 #define MIPS_HAS_R4K_MMU (mips_has_r4k_mmu)
1120 #define MIPS_HAS_LLSC (mips_has_llsc)
1121 #define MIPS_HAS_LLADDR ((mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0)
1123 /* This test is ... rather bogus */
1124 #define CPUISMIPS3 ((cpu_arch & \
1125 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0)
1127 /* And these aren't much better while the previous test exists as is... */
1128 #define CPUISMIPS32 ((cpu_arch & CPU_ARCH_MIPS32) != 0)
1129 #define CPUISMIPS64 ((cpu_arch & CPU_ARCH_MIPS64) != 0)
1130 #define CPUISMIPSNN ((cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0)
1131 #define CPUIS64BITS ((cpu_arch & \
1132 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64)) != 0)
1134 #define MIPS_HAS_CLOCK (cpu_arch >= CPU_ARCH_MIPS3)
1136 #else /* !_LOCORE */
1138 #define MIPS_HAS_LLSC 0
1140 #endif /* !_LOCORE */
1142 #endif /* run-time test */
1147 * A port must provde CLKF_USERMODE() for use in machine-independent code.
1148 * These differ on r4000 and r3000 systems; provide them in the
1149 * port-dependent file that includes this one, using the macros below.
1152 /* mips1 versions */
1153 #define MIPS1_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KU_PREV)
1155 /* mips3 versions */
1156 #define MIPS3_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KSU_USER)
1158 #define CLKF_PC(framep) ((framep)->pc)
1159 #define CLKF_INTR(framep) (0)
1161 #if defined(MIPS3_PLUS) && !defined(MIPS1) /* XXX bogus! */
1162 #define CLKF_USERMODE(framep) MIPS3_CLKF_USERMODE(framep)
1165 #if !defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */
1166 #define CLKF_USERMODE(framep) MIPS1_CLKF_USERMODE(framep)
1169 #if defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */
1170 #define CLKF_USERMODE(framep) \
1171 ((CPUISMIPS3) ? MIPS3_CLKF_USERMODE(framep): MIPS1_CLKF_USERMODE(framep))
1175 * This is used during profiling to integrate system time. It can safely
1176 * assume that the process is resident.
1178 #define PROC_PC(p) \
1179 (((struct frame *)(p)->p_md.md_regs)->f_regs[37]) /* XXX PC */
1182 * Preempt the current process if in interrupt from user mode,
1183 * or after the current trap/syscall if in system mode.
1187 * Give a profiling tick to the current process when the user profiling
1188 * buffer pages are invalid. On the MIPS, request an ast to send us
1189 * through trap, marking the proc as needing a profiling tick.
1191 #define cpu_need_proftick(l) \
1193 (l)->l_pflag |= LP_OWEUPC; \
1195 } while (/*CONSTCOND*/0)
1198 * Notify the current lwp (l) that it has a signal pending,
1199 * process as soon as possible.
1201 #define cpu_signotify(l) aston(l)
1203 #define aston(l) ((l)->l_md.md_astpending = 1)
1206 #endif /* ! _LOCORE */
1207 #endif /* _KERNEL */
1208 #endif /* _CPU_H_ */
1211 /* $NetBSD: mips_opcode.h,v 1.13 2009/08/06 04:34:50 msaitoh Exp $ */
1214 * Copyright (c) 1992, 1993
1215 * The Regents of the University of California. All rights reserved.
1217 * This code is derived from software contributed to Berkeley by
1220 * Redistribution and use in source and binary forms, with or without
1221 * modification, are permitted provided that the following conditions
1223 * 1. Redistributions of source code must retain the above copyright
1224 * notice, this list of conditions and the following disclaimer.
1225 * 2. Redistributions in binary form must reproduce the above copyright
1226 * notice, this list of conditions and the following disclaimer in the
1227 * documentation and/or other materials provided with the distribution.
1228 * 3. Neither the name of the University nor the names of its contributors
1229 * may be used to endorse or promote products derived from this software
1230 * without specific prior written permission.
1232 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
1233 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
1234 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
1235 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
1236 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
1237 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
1238 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
1239 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
1240 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
1241 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
1244 * @(#)mips_opcode.h 8.1 (Berkeley) 6/10/93
1248 * Define the instruction formats and opcode values for the
1249 * MIPS instruction set.
1253 * Define the instruction formats.
1267 unsigned target: 26;
1286 unsigned : 1; /* always '1' */
1287 unsigned op: 6; /* always '0x11' */
1292 * Values for the 'op' field.
1294 #define OP_SPECIAL 000
1295 #define OP_BCOND 001
1304 #define OP_ADDIU 011
1306 #define OP_SLTIU 013
1316 #define OP_BEQL 024 /* MIPS-II, for r4000 port */
1317 #define OP_BNEL 025 /* MIPS-II, for r4000 port */
1318 #define OP_BLEZL 026 /* MIPS-II, for r4000 port */
1319 #define OP_BGTZL 027 /* MIPS-II, for r4000 port */
1321 #define OP_DADDI 030 /* MIPS-II, for r4000 port */
1322 #define OP_DADDIU 031 /* MIPS-II, for r4000 port */
1323 #define OP_LDL 032 /* MIPS-II, for r4000 port */
1324 #define OP_LDR 033 /* MIPS-II, for r4000 port */
1326 #define OP_SPECIAL2 034 /* QED opcodes */
1337 #define OP_LWU 047 /* MIPS-II, for r4000 port */
1343 #define OP_SDL 054 /* MIPS-II, for r4000 port */
1344 #define OP_SDR 055 /* MIPS-II, for r4000 port */
1346 #define OP_CACHE 057 /* MIPS-II, for r4000 port */
1349 #define OP_LWC0 OP_LL /* backwards source compatibility */
1353 #define OP_LLD 064 /* MIPS-II, for r4000 port */
1355 #define OP_LD 067 /* MIPS-II, for r4000 port */
1358 #define OP_SWC0 OP_SC /* backwards source compatibility */
1362 #define OP_SCD 074 /* MIPS-II, for r4000 port */
1364 #define OP_SD 077 /* MIPS-II, for r4000 port */
1367 * Values for the 'func' field when 'op' == OP_SPECIAL.
1378 #define OP_SYSCALL 014
1379 #define OP_BREAK 015
1380 #define OP_SYNC 017 /* MIPS-II, for r4000 port */
1386 #define OP_DSLLV 024 /* MIPS-II, for r4000 port */
1387 #define OP_DSRLV 026 /* MIPS-II, for r4000 port */
1388 #define OP_DSRAV 027 /* MIPS-II, for r4000 port */
1391 #define OP_MULTU 031
1394 #define OP_DMULT 034 /* MIPS-II, for r4000 port */
1395 #define OP_DMULTU 035 /* MIPS-II, for r4000 port */
1396 #define OP_DDIV 036 /* MIPS-II, for r4000 port */
1397 #define OP_DDIVU 037 /* MIPS-II, for r4000 port */
1410 #define OP_DADD 054 /* MIPS-II, for r4000 port */
1411 #define OP_DADDU 055 /* MIPS-II, for r4000 port */
1412 #define OP_DSUB 056 /* MIPS-II, for r4000 port */
1413 #define OP_DSUBU 057 /* MIPS-II, for r4000 port */
1415 #define OP_TGE 060 /* MIPS-II, for r4000 port */
1416 #define OP_TGEU 061 /* MIPS-II, for r4000 port */
1417 #define OP_TLT 062 /* MIPS-II, for r4000 port */
1418 #define OP_TLTU 063 /* MIPS-II, for r4000 port */
1419 #define OP_TEQ 064 /* MIPS-II, for r4000 port */
1420 #define OP_TNE 066 /* MIPS-II, for r4000 port */
1422 #define OP_DSLL 070 /* MIPS-II, for r4000 port */
1423 #define OP_DSRL 072 /* MIPS-II, for r4000 port */
1424 #define OP_DSRA 073 /* MIPS-II, for r4000 port */
1425 #define OP_DSLL32 074 /* MIPS-II, for r4000 port */
1426 #define OP_DSRL32 076 /* MIPS-II, for r4000 port */
1427 #define OP_DSRA32 077 /* MIPS-II, for r4000 port */
1430 * Values for the 'func' field when 'op' == OP_SPECIAL2.
1432 #define OP_MAD 000 /* QED */
1433 #define OP_MADU 001 /* QED */
1434 #define OP_MUL 002 /* QED */
1437 * Values for the 'func' field when 'op' == OP_BCOND.
1441 #define OP_BLTZL 002 /* MIPS-II, for r4000 port */
1442 #define OP_BGEZL 003 /* MIPS-II, for r4000 port */
1444 #define OP_TGEI 010 /* MIPS-II, for r4000 port */
1445 #define OP_TGEIU 011 /* MIPS-II, for r4000 port */
1446 #define OP_TLTI 012 /* MIPS-II, for r4000 port */
1447 #define OP_TLTIU 013 /* MIPS-II, for r4000 port */
1448 #define OP_TEQI 014 /* MIPS-II, for r4000 port */
1449 #define OP_TNEI 016 /* MIPS-II, for r4000 port */
1451 #define OP_BLTZAL 020 /* MIPS-II, for r4000 port */
1452 #define OP_BGEZAL 021
1453 #define OP_BLTZALL 022
1454 #define OP_BGEZALL 023
1457 * Values for the 'rs' field when 'op' == OP_COPz.
1460 #define OP_DMF 001 /* MIPS-II, for r4000 port */
1464 #define OP_DMT 005 /* MIPS-II, for r4000 port */
1471 * Values for the 'rt' field when 'op' == OP_COPz.
1473 #define COPz_BC_TF_MASK 0x01
1474 #define COPz_BC_TRUE 0x01
1475 #define COPz_BC_FALSE 0x00
1476 #define COPz_BCL_TF_MASK 0x02 /* MIPS-II, for r4000 port */
1477 #define COPz_BCL_TRUE 0x02 /* MIPS-II, for r4000 port */
1478 #define COPz_BCL_FALSE 0x00 /* MIPS-II, for r4000 port */
1480 #endif /* __DECODER_LOCAL_H__ */