1 // SPDX-License-Identifier: LGPL-2.1-or-later
3 * Copyright (C) 2014-2021 Paul Cercueil <paul@crapouillou.net>
6 #include "lightrec-config.h"
7 #include "disassembler.h"
9 #include "memmanager.h"
10 #include "optimizer.h"
18 #define IF_OPT(opt, ptr) ((opt) ? (ptr) : NULL)
20 struct optimizer_list {
21 void (**optimizers)(struct opcode *);
22 unsigned int nb_optimizers;
25 static bool is_nop(union code op);
27 bool is_unconditional_jump(union code c)
31 return c.r.op == OP_SPECIAL_JR || c.r.op == OP_SPECIAL_JALR;
37 return c.i.rs == c.i.rt;
39 return (c.r.rt == OP_REGIMM_BGEZ ||
40 c.r.rt == OP_REGIMM_BGEZAL) && c.i.rs == 0;
46 bool is_syscall(union code c)
48 return (c.i.op == OP_SPECIAL && c.r.op == OP_SPECIAL_SYSCALL) ||
49 (c.i.op == OP_CP0 && (c.r.rs == OP_CP0_MTC0 ||
50 c.r.rs == OP_CP0_CTC0) &&
51 (c.r.rd == 12 || c.r.rd == 13));
54 static u64 opcode_read_mask(union code op)
59 case OP_SPECIAL_SYSCALL:
60 case OP_SPECIAL_BREAK:
79 return BIT(op.r.rs) | BIT(op.r.rt);
90 if (op.r.op == OP_CP2_BASIC) {
92 case OP_CP2_BASIC_MTC2:
93 case OP_CP2_BASIC_CTC2:
105 if (op.i.rs == op.i.rt)
116 return BIT(op.i.rs) | BIT(op.i.rt);
122 static u64 mult_div_write_mask(union code op)
126 if (!OPT_FLAG_MULT_DIV)
127 return BIT(REG_LO) | BIT(REG_HI);
130 flags = BIT(op.r.rd);
134 flags |= BIT(op.r.imm);
136 flags |= BIT(REG_HI);
141 static u64 opcode_write_mask(union code op)
146 return mult_div_write_mask(op);
150 case OP_SPECIAL_SYSCALL:
151 case OP_SPECIAL_BREAK:
153 case OP_SPECIAL_MULT:
154 case OP_SPECIAL_MULTU:
156 case OP_SPECIAL_DIVU:
157 return mult_div_write_mask(op);
158 case OP_SPECIAL_MTHI:
160 case OP_SPECIAL_MTLO:
196 if (op.r.op == OP_CP2_BASIC) {
198 case OP_CP2_BASIC_MFC2:
199 case OP_CP2_BASIC_CFC2:
208 case OP_REGIMM_BLTZAL:
209 case OP_REGIMM_BGEZAL:
221 bool opcode_reads_register(union code op, u8 reg)
223 return opcode_read_mask(op) & BIT(reg);
226 bool opcode_writes_register(union code op, u8 reg)
228 return opcode_write_mask(op) & BIT(reg);
231 static int find_prev_writer(const struct opcode *list, unsigned int offset, u8 reg)
236 if (op_flag_sync(list[offset].flags))
239 for (i = offset; i > 0; i--) {
242 if (opcode_writes_register(c, reg)) {
243 if (i > 1 && has_delay_slot(list[i - 2].c))
249 if (op_flag_sync(list[i - 1].flags) ||
251 opcode_reads_register(c, reg))
258 static int find_next_reader(const struct opcode *list, unsigned int offset, u8 reg)
263 if (op_flag_sync(list[offset].flags))
266 for (i = offset; ; i++) {
269 if (opcode_reads_register(c, reg)) {
270 if (i > 0 && has_delay_slot(list[i - 1].c))
276 if (op_flag_sync(list[i].flags) ||
277 has_delay_slot(c) || opcode_writes_register(c, reg))
284 static bool reg_is_dead(const struct opcode *list, unsigned int offset, u8 reg)
288 if (op_flag_sync(list[offset].flags))
291 for (i = offset + 1; ; i++) {
292 if (opcode_reads_register(list[i].c, reg))
295 if (opcode_writes_register(list[i].c, reg))
298 if (has_delay_slot(list[i].c)) {
299 if (op_flag_no_ds(list[i].flags) ||
300 opcode_reads_register(list[i + 1].c, reg))
303 return opcode_writes_register(list[i + 1].c, reg);
308 static bool reg_is_read(const struct opcode *list,
309 unsigned int a, unsigned int b, u8 reg)
311 /* Return true if reg is read in one of the opcodes of the interval
314 if (!is_nop(list[a].c) && opcode_reads_register(list[a].c, reg))
321 static bool reg_is_written(const struct opcode *list,
322 unsigned int a, unsigned int b, u8 reg)
324 /* Return true if reg is written in one of the opcodes of the interval
328 if (!is_nop(list[a].c) && opcode_writes_register(list[a].c, reg))
335 static bool reg_is_read_or_written(const struct opcode *list,
336 unsigned int a, unsigned int b, u8 reg)
338 return reg_is_read(list, a, b, reg) || reg_is_written(list, a, b, reg);
341 static bool opcode_is_load(union code op)
358 static bool opcode_is_store(union code op)
373 static u8 opcode_get_io_size(union code op)
389 bool opcode_is_io(union code op)
391 return opcode_is_load(op) || opcode_is_store(op);
395 static bool is_nop(union code op)
397 if (opcode_writes_register(op, 0)) {
400 return op.r.rs != OP_CP0_MFC0;
418 return op.r.rd == op.r.rt && op.r.rd == op.r.rs;
420 case OP_SPECIAL_ADDU:
421 return (op.r.rd == op.r.rt && op.r.rs == 0) ||
422 (op.r.rd == op.r.rs && op.r.rt == 0);
424 case OP_SPECIAL_SUBU:
425 return op.r.rd == op.r.rs && op.r.rt == 0;
427 if (op.r.rd == op.r.rt)
428 return op.r.rd == op.r.rs || op.r.rs == 0;
430 return (op.r.rd == op.r.rs) && op.r.rt == 0;
434 return op.r.rd == op.r.rt && op.r.imm == 0;
435 case OP_SPECIAL_MFHI:
436 case OP_SPECIAL_MFLO:
444 return op.i.rt == op.i.rs && op.i.imm == 0;
446 return (op.i.rs == 0 || op.i.imm == 1);
448 return (op.i.op == OP_REGIMM_BLTZ ||
449 op.i.op == OP_REGIMM_BLTZAL) &&
450 (op.i.rs == 0 || op.i.imm == 1);
452 return (op.i.rs == op.i.rt || op.i.imm == 1);
458 bool load_in_delay_slot(union code op)
472 if (op.r.op == OP_CP2_BASIC) {
474 case OP_CP2_BASIC_MFC2:
475 case OP_CP2_BASIC_CFC2:
498 static u32 lightrec_propagate_consts(const struct opcode *op,
499 const struct opcode *prev,
502 union code c = prev->c;
504 /* Register $zero is always, well, zero */
508 if (op_flag_sync(op->flags))
515 if (known & BIT(c.r.rt)) {
516 known |= BIT(c.r.rd);
517 v[c.r.rd] = v[c.r.rt] << c.r.imm;
519 known &= ~BIT(c.r.rd);
523 if (known & BIT(c.r.rt)) {
524 known |= BIT(c.r.rd);
525 v[c.r.rd] = v[c.r.rt] >> c.r.imm;
527 known &= ~BIT(c.r.rd);
531 if (known & BIT(c.r.rt)) {
532 known |= BIT(c.r.rd);
533 v[c.r.rd] = (s32)v[c.r.rt] >> c.r.imm;
535 known &= ~BIT(c.r.rd);
538 case OP_SPECIAL_SLLV:
539 if (known & BIT(c.r.rt) && known & BIT(c.r.rs)) {
540 known |= BIT(c.r.rd);
541 v[c.r.rd] = v[c.r.rt] << (v[c.r.rs] & 0x1f);
543 known &= ~BIT(c.r.rd);
546 case OP_SPECIAL_SRLV:
547 if (known & BIT(c.r.rt) && known & BIT(c.r.rs)) {
548 known |= BIT(c.r.rd);
549 v[c.r.rd] = v[c.r.rt] >> (v[c.r.rs] & 0x1f);
551 known &= ~BIT(c.r.rd);
554 case OP_SPECIAL_SRAV:
555 if (known & BIT(c.r.rt) && known & BIT(c.r.rs)) {
556 known |= BIT(c.r.rd);
557 v[c.r.rd] = (s32)v[c.r.rt]
558 >> (v[c.r.rs] & 0x1f);
560 known &= ~BIT(c.r.rd);
564 case OP_SPECIAL_ADDU:
565 if (known & BIT(c.r.rt) && known & BIT(c.r.rs)) {
566 known |= BIT(c.r.rd);
567 v[c.r.rd] = (s32)v[c.r.rt] + (s32)v[c.r.rs];
569 known &= ~BIT(c.r.rd);
573 case OP_SPECIAL_SUBU:
574 if (known & BIT(c.r.rt) && known & BIT(c.r.rs)) {
575 known |= BIT(c.r.rd);
576 v[c.r.rd] = v[c.r.rt] - v[c.r.rs];
578 known &= ~BIT(c.r.rd);
582 if (known & BIT(c.r.rt) && known & BIT(c.r.rs)) {
583 known |= BIT(c.r.rd);
584 v[c.r.rd] = v[c.r.rt] & v[c.r.rs];
586 known &= ~BIT(c.r.rd);
590 if (known & BIT(c.r.rt) && known & BIT(c.r.rs)) {
591 known |= BIT(c.r.rd);
592 v[c.r.rd] = v[c.r.rt] | v[c.r.rs];
594 known &= ~BIT(c.r.rd);
598 if (known & BIT(c.r.rt) && known & BIT(c.r.rs)) {
599 known |= BIT(c.r.rd);
600 v[c.r.rd] = v[c.r.rt] ^ v[c.r.rs];
602 known &= ~BIT(c.r.rd);
606 if (known & BIT(c.r.rt) && known & BIT(c.r.rs)) {
607 known |= BIT(c.r.rd);
608 v[c.r.rd] = ~(v[c.r.rt] | v[c.r.rs]);
610 known &= ~BIT(c.r.rd);
614 if (known & BIT(c.r.rt) && known & BIT(c.r.rs)) {
615 known |= BIT(c.r.rd);
616 v[c.r.rd] = (s32)v[c.r.rs] < (s32)v[c.r.rt];
618 known &= ~BIT(c.r.rd);
621 case OP_SPECIAL_SLTU:
622 if (known & BIT(c.r.rt) && known & BIT(c.r.rs)) {
623 known |= BIT(c.r.rd);
624 v[c.r.rd] = v[c.r.rs] < v[c.r.rt];
626 known &= ~BIT(c.r.rd);
629 case OP_SPECIAL_MULT:
630 case OP_SPECIAL_MULTU:
632 case OP_SPECIAL_DIVU:
633 if (OPT_FLAG_MULT_DIV && c.r.rd)
634 known &= ~BIT(c.r.rd);
635 if (OPT_FLAG_MULT_DIV && c.r.imm)
636 known &= ~BIT(c.r.imm);
644 if (OPT_FLAG_MULT_DIV && (known & BIT(c.r.rs))) {
646 known |= BIT(c.r.rd);
649 v[c.r.rd] = v[c.r.rs] << c.r.op;
655 known |= BIT(c.r.imm);
658 v[c.r.imm] = v[c.r.rs] << (c.r.op - 32);
659 else if (c.i.op == OP_META_MULT2)
660 v[c.r.imm] = (s32) v[c.r.rs] >> (32 - c.r.op);
662 v[c.r.imm] = v[c.r.rs] >> (32 - c.r.op);
665 if (OPT_FLAG_MULT_DIV && c.r.rd)
666 known &= ~BIT(c.r.rd);
667 if (OPT_FLAG_MULT_DIV && c.r.imm)
668 known &= ~BIT(c.r.imm);
675 if (known & BIT(c.i.rs)) {
676 known |= BIT(c.i.rt);
677 v[c.i.rt] = v[c.i.rs] + (s32)(s16)c.i.imm;
679 known &= ~BIT(c.i.rt);
683 if (known & BIT(c.i.rs)) {
684 known |= BIT(c.i.rt);
685 v[c.i.rt] = (s32)v[c.i.rs] < (s32)(s16)c.i.imm;
687 known &= ~BIT(c.i.rt);
691 if (known & BIT(c.i.rs)) {
692 known |= BIT(c.i.rt);
693 v[c.i.rt] = v[c.i.rs] < (u32)(s32)(s16)c.i.imm;
695 known &= ~BIT(c.i.rt);
699 if (known & BIT(c.i.rs)) {
700 known |= BIT(c.i.rt);
701 v[c.i.rt] = v[c.i.rs] & c.i.imm;
703 known &= ~BIT(c.i.rt);
707 if (known & BIT(c.i.rs)) {
708 known |= BIT(c.i.rt);
709 v[c.i.rt] = v[c.i.rs] | c.i.imm;
711 known &= ~BIT(c.i.rt);
715 if (known & BIT(c.i.rs)) {
716 known |= BIT(c.i.rt);
717 v[c.i.rt] = v[c.i.rs] ^ c.i.imm;
719 known &= ~BIT(c.i.rt);
723 known |= BIT(c.i.rt);
724 v[c.i.rt] = c.i.imm << 16;
730 known &= ~BIT(c.r.rt);
735 if (c.r.op == OP_CP2_BASIC) {
737 case OP_CP2_BASIC_MFC2:
738 case OP_CP2_BASIC_CFC2:
739 known &= ~BIT(c.r.rt);
752 known &= ~BIT(c.i.rt);
755 if (known & BIT(c.r.rs)) {
756 known |= BIT(c.r.rd);
757 v[c.r.rd] = v[c.r.rs];
759 known &= ~BIT(c.r.rd);
769 static void lightrec_optimize_sll_sra(struct opcode *list, unsigned int offset)
771 struct opcode *prev, *prev2 = NULL, *curr = &list[offset];
772 struct opcode *to_change, *to_nop;
775 if (curr->r.imm != 24 && curr->r.imm != 16)
778 idx = find_prev_writer(list, offset, curr->r.rt);
784 if (prev->i.op != OP_SPECIAL || prev->r.op != OP_SPECIAL_SLL ||
785 prev->r.imm != curr->r.imm || prev->r.rd != curr->r.rt)
788 if (prev->r.rd != prev->r.rt && curr->r.rd != curr->r.rt) {
793 if (!reg_is_dead(list, offset, curr->r.rt) ||
794 reg_is_read_or_written(list, idx, offset, curr->r.rd))
797 /* If rY is dead after the SRL, and rZ is not used after the SLL,
798 * we can change rY to rZ */
800 pr_debug("Detected SLL/SRA with middle temp register\n");
801 prev->r.rd = curr->r.rd;
802 curr->r.rt = prev->r.rd;
805 /* We got a SLL/SRA combo. If imm #16, that's a cast to u16.
806 * If imm #24 that's a cast to u8.
808 * First of all, make sure that the target register of the SLL is not
809 * read before the SRA. */
811 if (prev->r.rd == prev->r.rt) {
818 /* rX is used after the SRA - we cannot convert it. */
819 if (prev->r.rd != curr->r.rd && !reg_is_dead(list, offset, prev->r.rd))
829 idx2 = find_prev_writer(list, idx, prev->r.rt);
831 /* Note that PSX games sometimes do casts after
832 * a LHU or LBU; in this case we can change the
833 * load opcode to a LH or LB, and the cast can
834 * be changed to a MOV or a simple NOP. */
838 if (curr->r.rd != prev2->i.rt &&
839 !reg_is_dead(list, offset, prev2->i.rt))
841 else if (curr->r.imm == 16 && prev2->i.op == OP_LHU)
843 else if (curr->r.imm == 24 && prev2->i.op == OP_LBU)
849 if (curr->r.rd == prev2->i.rt) {
850 to_change->opcode = 0;
851 } else if (reg_is_dead(list, offset, prev2->i.rt) &&
852 !reg_is_read_or_written(list, idx2 + 1, offset, curr->r.rd)) {
853 /* The target register of the SRA is dead after the
854 * LBU/LHU; we can change the target register of the
855 * LBU/LHU to the one of the SRA. */
856 prev2->i.rt = curr->r.rd;
857 to_change->opcode = 0;
859 to_change->i.op = OP_META_MOV;
860 to_change->r.rd = curr->r.rd;
861 to_change->r.rs = prev2->i.rt;
864 if (to_nop->r.imm == 24)
865 pr_debug("Convert LBU+SLL+SRA to LB\n");
867 pr_debug("Convert LHU+SLL+SRA to LH\n");
872 pr_debug("Convert SLL/SRA #%u to EXT%c\n",
874 prev->r.imm == 24 ? 'C' : 'S');
876 if (to_change == prev) {
877 to_change->i.rs = prev->r.rt;
878 to_change->i.rt = curr->r.rd;
880 to_change->i.rt = curr->r.rd;
881 to_change->i.rs = prev->r.rt;
884 if (to_nop->r.imm == 24)
885 to_change->i.op = OP_META_EXTC;
887 to_change->i.op = OP_META_EXTS;
893 static void lightrec_remove_useless_lui(struct block *block, unsigned int offset,
894 u32 known, u32 *values)
896 struct opcode *list = block->opcode_list,
897 *op = &block->opcode_list[offset];
900 if (!op_flag_sync(op->flags) && (known & BIT(op->i.rt)) &&
901 values[op->i.rt] == op->i.imm << 16) {
902 pr_debug("Converting duplicated LUI to NOP\n");
907 if (op->i.imm != 0 || op->i.rt == 0)
910 reader = find_next_reader(list, offset + 1, op->i.rt);
914 if (opcode_writes_register(list[reader].c, op->i.rt) ||
915 reg_is_dead(list, reader, op->i.rt)) {
916 pr_debug("Removing useless LUI 0x0\n");
918 if (list[reader].i.rs == op->i.rt)
919 list[reader].i.rs = 0;
920 if (list[reader].i.op == OP_SPECIAL &&
921 list[reader].i.rt == op->i.rt)
922 list[reader].i.rt = 0;
927 static void lightrec_modify_lui(struct block *block, unsigned int offset)
929 union code c, *lui = &block->opcode_list[offset].c;
930 bool stop = false, stop_next = false;
933 for (i = offset + 1; !stop && i < block->nb_ops; i++) {
934 c = block->opcode_list[i].c;
937 if ((opcode_is_store(c) && c.i.rt == lui->i.rt)
938 || (!opcode_is_load(c) && opcode_reads_register(c, lui->i.rt)))
941 if (opcode_writes_register(c, lui->i.rt)) {
942 pr_debug("Convert LUI at offset 0x%x to kuseg\n",
944 lui->i.imm = kunseg(lui->i.imm << 16) >> 16;
948 if (has_delay_slot(c))
953 static int lightrec_transform_branches(struct lightrec_state *state,
960 for (i = 0; i < block->nb_ops; i++) {
961 op = &block->opcode_list[i];
965 /* Transform J opcode into BEQ $zero, $zero if possible. */
966 offset = (s32)((block->pc & 0xf0000000) >> 2 | op->j.imm)
967 - (s32)(block->pc >> 2) - (s32)i - 1;
969 if (offset == (s16)offset) {
970 pr_debug("Transform J into BEQ $zero, $zero\n");
986 static inline bool is_power_of_two(u32 value)
988 return popcount32(value) == 1;
991 static int lightrec_transform_ops(struct lightrec_state *state, struct block *block)
993 struct opcode *list = block->opcode_list;
994 struct opcode *prev, *op = NULL;
996 u32 values[32] = { 0 };
1000 for (i = 0; i < block->nb_ops; i++) {
1005 known = lightrec_propagate_consts(op, prev, known, values);
1007 /* Transform all opcodes detected as useless to real NOPs
1008 * (0x0: SLL r0, r0, #0) */
1009 if (op->opcode != 0 && is_nop(op->c)) {
1010 pr_debug("Converting useless opcode 0x%08x to NOP\n",
1020 if (op->i.rs == op->i.rt) {
1023 } else if (op->i.rs == 0) {
1024 op->i.rs = op->i.rt;
1030 if (op->i.rs == 0) {
1031 op->i.rs = op->i.rt;
1037 if (!prev || !has_delay_slot(prev->c))
1038 lightrec_modify_lui(block, i);
1039 lightrec_remove_useless_lui(block, i, known, values);
1042 /* Transform ORI/ADDI/ADDIU with imm #0 or ORR/ADD/ADDU/SUB/SUBU
1043 * with register $zero to the MOV meta-opcode */
1047 if (op->i.imm == 0) {
1048 pr_debug("Convert ORI/ADDI/ADDIU #0 to MOV\n");
1049 op->i.op = OP_META_MOV;
1050 op->r.rd = op->i.rt;
1055 case OP_SPECIAL_SRA:
1056 if (op->r.imm == 0) {
1057 pr_debug("Convert SRA #0 to MOV\n");
1058 op->i.op = OP_META_MOV;
1059 op->r.rs = op->r.rt;
1063 lightrec_optimize_sll_sra(block->opcode_list, i);
1065 case OP_SPECIAL_SLL:
1066 case OP_SPECIAL_SRL:
1067 if (op->r.imm == 0) {
1068 pr_debug("Convert SLL/SRL #0 to MOV\n");
1069 op->i.op = OP_META_MOV;
1070 op->r.rs = op->r.rt;
1073 case OP_SPECIAL_MULT:
1074 case OP_SPECIAL_MULTU:
1075 if ((known & BIT(op->r.rs)) &&
1076 is_power_of_two(values[op->r.rs])) {
1078 op->c.i.rs = op->c.i.rt;
1080 } else if (!(known & BIT(op->r.rt)) ||
1081 !is_power_of_two(values[op->r.rt])) {
1085 pr_debug("Multiply by power-of-two: %u\n",
1088 if (op->r.op == OP_SPECIAL_MULT)
1089 op->i.op = OP_META_MULT2;
1091 op->i.op = OP_META_MULTU2;
1093 op->r.op = ffs32(values[op->r.rt]);
1096 case OP_SPECIAL_ADD:
1097 case OP_SPECIAL_ADDU:
1098 if (op->r.rs == 0) {
1099 pr_debug("Convert OR/ADD $zero to MOV\n");
1100 op->i.op = OP_META_MOV;
1101 op->r.rs = op->r.rt;
1104 case OP_SPECIAL_SUB:
1105 case OP_SPECIAL_SUBU:
1106 if (op->r.rt == 0) {
1107 pr_debug("Convert OR/ADD/SUB $zero to MOV\n");
1108 op->i.op = OP_META_MOV;
1123 static bool lightrec_can_switch_delay_slot(union code op, union code next_op)
1128 case OP_SPECIAL_JALR:
1129 if (opcode_reads_register(next_op, op.r.rd) ||
1130 opcode_writes_register(next_op, op.r.rd))
1134 if (opcode_writes_register(next_op, op.r.rs))
1144 if (opcode_reads_register(next_op, 31) ||
1145 opcode_writes_register(next_op, 31))
1151 if (op.i.rt && opcode_writes_register(next_op, op.i.rt))
1156 if (op.i.rs && opcode_writes_register(next_op, op.i.rs))
1161 case OP_REGIMM_BLTZAL:
1162 case OP_REGIMM_BGEZAL:
1163 if (opcode_reads_register(next_op, 31) ||
1164 opcode_writes_register(next_op, 31))
1167 case OP_REGIMM_BLTZ:
1168 case OP_REGIMM_BGEZ:
1169 if (op.i.rs && opcode_writes_register(next_op, op.i.rs))
1181 static int lightrec_switch_delay_slots(struct lightrec_state *state, struct block *block)
1183 struct opcode *list, *next = &block->opcode_list[0];
1185 union code op, next_op;
1188 for (i = 0; i < block->nb_ops - 1; i++) {
1190 next = &block->opcode_list[i + 1];
1194 if (!has_delay_slot(op) || op_flag_no_ds(list->flags) ||
1195 op_flag_emulate_branch(list->flags) ||
1196 op.opcode == 0 || next_op.opcode == 0)
1199 if (i && has_delay_slot(block->opcode_list[i - 1].c) &&
1200 !op_flag_no_ds(block->opcode_list[i - 1].flags))
1203 if (op_flag_sync(next->flags))
1206 if (!lightrec_can_switch_delay_slot(list->c, next_op))
1209 pr_debug("Swap branch and delay slot opcodes "
1210 "at offsets 0x%x / 0x%x\n",
1211 i << 2, (i + 1) << 2);
1213 flags = next->flags | (list->flags & LIGHTREC_SYNC);
1216 next->flags = (list->flags | LIGHTREC_NO_DS) & ~LIGHTREC_SYNC;
1217 list->flags = flags | LIGHTREC_NO_DS;
1223 static int shrink_opcode_list(struct lightrec_state *state, struct block *block, u16 new_size)
1225 struct opcode_list *list, *old_list;
1227 if (new_size >= block->nb_ops) {
1228 pr_err("Invalid shrink size (%u vs %u)\n",
1229 new_size, block->nb_ops);
1233 list = lightrec_malloc(state, MEM_FOR_IR,
1234 sizeof(*list) + sizeof(struct opcode) * new_size);
1236 pr_err("Unable to allocate memory\n");
1240 old_list = container_of(block->opcode_list, struct opcode_list, ops);
1241 memcpy(list->ops, old_list->ops, sizeof(struct opcode) * new_size);
1243 lightrec_free_opcode_list(state, block->opcode_list);
1244 list->nb_ops = new_size;
1245 block->nb_ops = new_size;
1246 block->opcode_list = list->ops;
1248 pr_debug("Shrunk opcode list of block PC 0x%08x to %u opcodes\n",
1249 block->pc, new_size);
1254 static int lightrec_detect_impossible_branches(struct lightrec_state *state,
1255 struct block *block)
1257 struct opcode *op, *list = block->opcode_list, *next = &list[0];
1262 for (i = 0; i < block->nb_ops - 1; i++) {
1264 next = &list[i + 1];
1266 if (!has_delay_slot(op->c) ||
1267 (!load_in_delay_slot(next->c) &&
1268 !has_delay_slot(next->c) &&
1269 !(next->i.op == OP_CP0 && next->r.rs == OP_CP0_RFE)))
1272 if (op->c.opcode == next->c.opcode) {
1273 /* The delay slot is the exact same opcode as the branch
1274 * opcode: this is effectively a NOP */
1279 offset = i + 1 + (s16)op->i.imm;
1280 if (load_in_delay_slot(next->c) &&
1281 (offset >= 0 && offset < block->nb_ops) &&
1282 !opcode_reads_register(list[offset].c, next->c.i.rt)) {
1283 /* The 'impossible' branch is a local branch - we can
1284 * verify here that the first opcode of the target does
1285 * not use the target register of the delay slot */
1287 pr_debug("Branch at offset 0x%x has load delay slot, "
1288 "but is local and dest opcode does not read "
1289 "dest register\n", i << 2);
1293 op->flags |= LIGHTREC_EMULATE_BRANCH;
1296 pr_debug("First opcode of block PC 0x%08x is an impossible branch\n",
1299 /* If the first opcode is an 'impossible' branch, we
1300 * only keep the first two opcodes of the block (the
1301 * branch itself + its delay slot) */
1302 if (block->nb_ops > 2)
1303 ret = shrink_opcode_list(state, block, 2);
1311 static int lightrec_local_branches(struct lightrec_state *state, struct block *block)
1313 struct opcode *list;
1317 for (i = 0; i < block->nb_ops; i++) {
1318 list = &block->opcode_list[i];
1320 if (should_emulate(list))
1323 switch (list->i.op) {
1329 offset = i + 1 + (s16)list->i.imm;
1330 if (offset >= 0 && offset < block->nb_ops)
1337 pr_debug("Found local branch to offset 0x%x\n", offset << 2);
1339 if (should_emulate(&block->opcode_list[offset])) {
1340 pr_debug("Branch target must be emulated - skip\n");
1344 if (offset && has_delay_slot(block->opcode_list[offset - 1].c)) {
1345 pr_debug("Branch target is a delay slot - skip\n");
1349 pr_debug("Adding sync at offset 0x%x\n", offset << 2);
1351 block->opcode_list[offset].flags |= LIGHTREC_SYNC;
1352 list->flags |= LIGHTREC_LOCAL_BRANCH;
1358 bool has_delay_slot(union code op)
1364 case OP_SPECIAL_JALR:
1382 bool should_emulate(const struct opcode *list)
1384 return op_flag_emulate_branch(list->flags) && has_delay_slot(list->c);
1387 static bool op_writes_rd(union code c)
1398 static void lightrec_add_reg_op(struct opcode *op, u8 reg, u32 reg_op)
1400 if (op_writes_rd(op->c) && reg == op->r.rd)
1401 op->flags |= LIGHTREC_REG_RD(reg_op);
1402 else if (op->i.rs == reg)
1403 op->flags |= LIGHTREC_REG_RS(reg_op);
1404 else if (op->i.rt == reg)
1405 op->flags |= LIGHTREC_REG_RT(reg_op);
1407 pr_debug("Cannot add unload/clean/discard flag: "
1408 "opcode does not touch register %s!\n",
1409 lightrec_reg_name(reg));
1412 static void lightrec_add_unload(struct opcode *op, u8 reg)
1414 lightrec_add_reg_op(op, reg, LIGHTREC_REG_UNLOAD);
1417 static void lightrec_add_discard(struct opcode *op, u8 reg)
1419 lightrec_add_reg_op(op, reg, LIGHTREC_REG_DISCARD);
1422 static void lightrec_add_clean(struct opcode *op, u8 reg)
1424 lightrec_add_reg_op(op, reg, LIGHTREC_REG_CLEAN);
1428 lightrec_early_unload_sync(struct opcode *list, s16 *last_r, s16 *last_w)
1433 for (reg = 0; reg < 34; reg++) {
1434 offset = s16_max(last_w[reg], last_r[reg]);
1437 lightrec_add_unload(&list[offset], reg);
1440 memset(last_r, 0xff, sizeof(*last_r) * 34);
1441 memset(last_w, 0xff, sizeof(*last_w) * 34);
1444 static int lightrec_early_unload(struct lightrec_state *state, struct block *block)
1448 s16 last_r[34], last_w[34], last_sync = 0, next_sync = 0;
1449 u64 mask_r, mask_w, dirty = 0, loaded = 0;
1452 memset(last_r, 0xff, sizeof(last_r));
1453 memset(last_w, 0xff, sizeof(last_w));
1457 * - the register is dirty, and is read again after a branch opcode
1460 * - the register is dirty or loaded, and is not read again
1461 * - the register is dirty or loaded, and is written again after a branch opcode
1462 * - the next opcode has the SYNC flag set
1465 * - the register is dirty or loaded, and is written again
1468 for (i = 0; i < block->nb_ops; i++) {
1469 op = &block->opcode_list[i];
1471 if (op_flag_sync(op->flags) || should_emulate(op)) {
1472 /* The next opcode has the SYNC flag set, or is a branch
1473 * that should be emulated: unload all registers. */
1474 lightrec_early_unload_sync(block->opcode_list, last_r, last_w);
1479 if (next_sync == i) {
1481 pr_debug("Last sync: 0x%x\n", last_sync << 2);
1484 if (has_delay_slot(op->c)) {
1485 next_sync = i + 1 + !op_flag_no_ds(op->flags);
1486 pr_debug("Next sync: 0x%x\n", next_sync << 2);
1489 mask_r = opcode_read_mask(op->c);
1490 mask_w = opcode_write_mask(op->c);
1492 for (reg = 0; reg < 34; reg++) {
1493 if (mask_r & BIT(reg)) {
1494 if (dirty & BIT(reg) && last_w[reg] < last_sync) {
1495 /* The register is dirty, and is read
1496 * again after a branch: clean it */
1498 lightrec_add_clean(&block->opcode_list[last_w[reg]], reg);
1506 if (mask_w & BIT(reg)) {
1507 if ((dirty & BIT(reg) && last_w[reg] < last_sync) ||
1508 (loaded & BIT(reg) && last_r[reg] < last_sync)) {
1509 /* The register is dirty or loaded, and
1510 * is written again after a branch:
1513 offset = s16_max(last_w[reg], last_r[reg]);
1514 lightrec_add_unload(&block->opcode_list[offset], reg);
1516 loaded &= ~BIT(reg);
1517 } else if (!(mask_r & BIT(reg)) &&
1518 ((dirty & BIT(reg) && last_w[reg] > last_sync) ||
1519 (loaded & BIT(reg) && last_r[reg] > last_sync))) {
1520 /* The register is dirty or loaded, and
1521 * is written again: discard it */
1523 offset = s16_max(last_w[reg], last_r[reg]);
1524 lightrec_add_discard(&block->opcode_list[offset], reg);
1526 loaded &= ~BIT(reg);
1538 /* Unload all registers that are dirty or loaded at the end of block. */
1539 lightrec_early_unload_sync(block->opcode_list, last_r, last_w);
1544 static int lightrec_flag_io(struct lightrec_state *state, struct block *block)
1546 struct opcode *prev = NULL, *list = NULL;
1547 enum psx_map psx_map;
1549 u32 values[32] = { 0 };
1551 u32 val, kunseg_val;
1554 for (i = 0; i < block->nb_ops; i++) {
1556 list = &block->opcode_list[i];
1559 known = lightrec_propagate_consts(list, prev, known, values);
1561 switch (list->i.op) {
1565 if (OPT_FLAG_STORES) {
1566 /* Mark all store operations that target $sp or $gp
1567 * as not requiring code invalidation. This is based
1568 * on the heuristic that stores using one of these
1569 * registers as address will never hit a code page. */
1570 if (list->i.rs >= 28 && list->i.rs <= 29 &&
1571 !state->maps[PSX_MAP_KERNEL_USER_RAM].ops) {
1572 pr_debug("Flaging opcode 0x%08x as not "
1573 "requiring invalidation\n",
1575 list->flags |= LIGHTREC_NO_INVALIDATE;
1576 list->flags |= LIGHTREC_IO_MODE(LIGHTREC_IO_DIRECT);
1579 /* Detect writes whose destination address is inside the
1580 * current block, using constant propagation. When these
1581 * occur, we mark the blocks as not compilable. */
1582 if ((known & BIT(list->i.rs)) &&
1583 kunseg(values[list->i.rs]) >= kunseg(block->pc) &&
1584 kunseg(values[list->i.rs]) < (kunseg(block->pc) +
1585 block->nb_ops * 4)) {
1586 pr_debug("Self-modifying block detected\n");
1587 block_set_flags(block, BLOCK_NEVER_COMPILE);
1588 list->flags |= LIGHTREC_SMC;
1603 if (OPT_FLAG_IO && (known & BIT(list->i.rs))) {
1604 val = values[list->i.rs] + (s16) list->i.imm;
1605 kunseg_val = kunseg(val);
1606 psx_map = lightrec_get_map_idx(state, kunseg_val);
1608 list->flags &= ~LIGHTREC_IO_MASK;
1609 no_mask = val == kunseg_val;
1612 case PSX_MAP_KERNEL_USER_RAM:
1614 list->flags |= LIGHTREC_NO_MASK;
1616 case PSX_MAP_MIRROR1:
1617 case PSX_MAP_MIRROR2:
1618 case PSX_MAP_MIRROR3:
1619 pr_debug("Flaging opcode %u as RAM access\n", i);
1620 list->flags |= LIGHTREC_IO_MODE(LIGHTREC_IO_RAM);
1621 if (no_mask && state->mirrors_mapped)
1622 list->flags |= LIGHTREC_NO_MASK;
1625 pr_debug("Flaging opcode %u as BIOS access\n", i);
1626 list->flags |= LIGHTREC_IO_MODE(LIGHTREC_IO_BIOS);
1628 list->flags |= LIGHTREC_NO_MASK;
1630 case PSX_MAP_SCRATCH_PAD:
1631 pr_debug("Flaging opcode %u as scratchpad access\n", i);
1632 list->flags |= LIGHTREC_IO_MODE(LIGHTREC_IO_SCRATCH);
1634 list->flags |= LIGHTREC_NO_MASK;
1636 /* Consider that we're never going to run code from
1637 * the scratchpad. */
1638 list->flags |= LIGHTREC_NO_INVALIDATE;
1640 case PSX_MAP_HW_REGISTERS:
1641 if (state->ops.hw_direct &&
1642 state->ops.hw_direct(kunseg_val,
1643 opcode_is_store(list->c),
1644 opcode_get_io_size(list->c))) {
1645 pr_debug("Flagging opcode %u as direct I/O access\n",
1647 list->flags |= LIGHTREC_IO_MODE(LIGHTREC_IO_DIRECT_HW);
1652 pr_debug("Flagging opcode %u as I/O access\n",
1654 list->flags |= LIGHTREC_IO_MODE(LIGHTREC_IO_HW);
1667 static u8 get_mfhi_mflo_reg(const struct block *block, u16 offset,
1668 const struct opcode *last,
1669 u32 mask, bool sync, bool mflo, bool another)
1671 const struct opcode *op, *next = &block->opcode_list[offset];
1673 u8 reg2, reg = mflo ? REG_LO : REG_HI;
1677 for (i = offset; i < block->nb_ops; i++) {
1679 next = &block->opcode_list[i + 1];
1682 /* If any other opcode writes or reads to the register
1683 * we'd use, then we cannot use it anymore. */
1684 mask |= opcode_read_mask(op->c);
1685 mask |= opcode_write_mask(op->c);
1687 if (op_flag_sync(op->flags))
1696 /* TODO: handle backwards branches too */
1697 if (!last && op_flag_local_branch(op->flags) &&
1698 (s16)op->c.i.imm >= 0) {
1699 branch_offset = i + 1 + (s16)op->c.i.imm
1700 - !!op_flag_no_ds(op->flags);
1702 reg = get_mfhi_mflo_reg(block, branch_offset, NULL,
1703 mask, sync, mflo, false);
1704 reg2 = get_mfhi_mflo_reg(block, offset + 1, next,
1705 mask, sync, mflo, false);
1706 if (reg > 0 && reg == reg2)
1712 return mflo ? REG_LO : REG_HI;
1714 case OP_META_MULTU2:
1718 case OP_SPECIAL_MULT:
1719 case OP_SPECIAL_MULTU:
1720 case OP_SPECIAL_DIV:
1721 case OP_SPECIAL_DIVU:
1723 case OP_SPECIAL_MTHI:
1727 case OP_SPECIAL_MTLO:
1735 if (!sync && !op_flag_no_ds(op->flags) &&
1736 (next->i.op == OP_SPECIAL) &&
1737 ((!mflo && next->r.op == OP_SPECIAL_MFHI) ||
1738 (mflo && next->r.op == OP_SPECIAL_MFLO)))
1742 case OP_SPECIAL_JALR:
1744 case OP_SPECIAL_MFHI:
1748 /* Must use REG_HI if there is another MFHI target*/
1749 reg2 = get_mfhi_mflo_reg(block, i + 1, next,
1750 0, sync, mflo, true);
1751 if (reg2 > 0 && reg2 != REG_HI)
1754 if (!sync && !(old_mask & BIT(op->r.rd)))
1760 case OP_SPECIAL_MFLO:
1764 /* Must use REG_LO if there is another MFLO target*/
1765 reg2 = get_mfhi_mflo_reg(block, i + 1, next,
1766 0, sync, mflo, true);
1767 if (reg2 > 0 && reg2 != REG_LO)
1770 if (!sync && !(old_mask & BIT(op->r.rd)))
1789 static void lightrec_replace_lo_hi(struct block *block, u16 offset,
1795 /* This function will remove the following MFLO/MFHI. It must be called
1796 * only if get_mfhi_mflo_reg() returned a non-zero value. */
1798 for (i = offset; i < last; i++) {
1799 struct opcode *op = &block->opcode_list[i];
1807 /* TODO: handle backwards branches too */
1808 if (op_flag_local_branch(op->flags) && (s16)op->c.i.imm >= 0) {
1809 branch_offset = i + 1 + (s16)op->c.i.imm
1810 - !!op_flag_no_ds(op->flags);
1812 lightrec_replace_lo_hi(block, branch_offset, last, lo);
1813 lightrec_replace_lo_hi(block, i + 1, branch_offset, lo);
1818 if (lo && op->r.op == OP_SPECIAL_MFLO) {
1819 pr_debug("Removing MFLO opcode at offset 0x%x\n",
1823 } else if (!lo && op->r.op == OP_SPECIAL_MFHI) {
1824 pr_debug("Removing MFHI opcode at offset 0x%x\n",
1837 static bool lightrec_always_skip_div_check(void)
1846 static int lightrec_flag_mults_divs(struct lightrec_state *state, struct block *block)
1848 struct opcode *prev, *list = NULL;
1852 u32 values[32] = { 0 };
1854 for (i = 0; i < block->nb_ops - 1; i++) {
1856 list = &block->opcode_list[i];
1859 known = lightrec_propagate_consts(list, prev, known, values);
1861 switch (list->i.op) {
1863 switch (list->r.op) {
1864 case OP_SPECIAL_DIV:
1865 case OP_SPECIAL_DIVU:
1866 /* If we are dividing by a non-zero constant, don't
1867 * emit the div-by-zero check. */
1868 if (lightrec_always_skip_div_check() ||
1869 ((known & BIT(list->c.r.rt)) && values[list->c.r.rt]))
1870 list->flags |= LIGHTREC_NO_DIV_CHECK;
1872 case OP_SPECIAL_MULT:
1873 case OP_SPECIAL_MULTU:
1880 case OP_META_MULTU2:
1886 /* Don't support opcodes in delay slots */
1887 if ((i && has_delay_slot(block->opcode_list[i - 1].c)) ||
1888 op_flag_no_ds(list->flags)) {
1892 reg_lo = get_mfhi_mflo_reg(block, i + 1, NULL, 0, false, true, false);
1894 pr_debug("Mark MULT(U)/DIV(U) opcode at offset 0x%x as"
1895 " not writing LO\n", i << 2);
1896 list->flags |= LIGHTREC_NO_LO;
1899 reg_hi = get_mfhi_mflo_reg(block, i + 1, NULL, 0, false, false, false);
1901 pr_debug("Mark MULT(U)/DIV(U) opcode at offset 0x%x as"
1902 " not writing HI\n", i << 2);
1903 list->flags |= LIGHTREC_NO_HI;
1906 if (!reg_lo && !reg_hi) {
1907 pr_debug("Both LO/HI unused in this block, they will "
1908 "probably be used in parent block - removing "
1910 list->flags &= ~(LIGHTREC_NO_LO | LIGHTREC_NO_HI);
1913 if (reg_lo > 0 && reg_lo != REG_LO) {
1914 pr_debug("Found register %s to hold LO (rs = %u, rt = %u)\n",
1915 lightrec_reg_name(reg_lo), list->r.rs, list->r.rt);
1917 lightrec_replace_lo_hi(block, i + 1, block->nb_ops, true);
1918 list->r.rd = reg_lo;
1923 if (reg_hi > 0 && reg_hi != REG_HI) {
1924 pr_debug("Found register %s to hold HI (rs = %u, rt = %u)\n",
1925 lightrec_reg_name(reg_hi), list->r.rs, list->r.rt);
1927 lightrec_replace_lo_hi(block, i + 1, block->nb_ops, false);
1928 list->r.imm = reg_hi;
1937 static bool remove_div_sequence(struct block *block, unsigned int offset)
1940 unsigned int i, found = 0;
1943 * Scan for the zero-checking sequence that GCC automatically introduced
1944 * after most DIV/DIVU opcodes. This sequence checks the value of the
1945 * divisor, and if zero, executes a BREAK opcode, causing the BIOS
1946 * handler to crash the PS1.
1948 * For DIV opcodes, this sequence additionally checks that the signed
1949 * operation does not overflow.
1951 * With the assumption that the games never crashed the PS1, we can
1952 * therefore assume that the games never divided by zero or overflowed,
1953 * and these sequences can be removed.
1956 for (i = offset; i < block->nb_ops; i++) {
1957 op = &block->opcode_list[i];
1960 if (op->i.op == OP_SPECIAL &&
1961 (op->r.op == OP_SPECIAL_DIV || op->r.op == OP_SPECIAL_DIVU))
1964 if ((op->opcode & 0xfc1fffff) == 0x14000002) {
1965 /* BNE ???, zero, +8 */
1970 } else if (found == 1 && !op->opcode) {
1973 } else if (found == 2 && op->opcode == 0x0007000d) {
1976 } else if (found == 3 && op->opcode == 0x2401ffff) {
1979 } else if (found == 4 && (op->opcode & 0xfc1fffff) == 0x14010004) {
1980 /* BNE ???, at, +16 */
1982 } else if (found == 5 && op->opcode == 0x3c018000) {
1983 /* LUI at, 0x8000 */
1985 } else if (found == 6 && (op->opcode & 0x141fffff) == 0x14010002) {
1986 /* BNE ???, at, +16 */
1988 } else if (found == 7 && !op->opcode) {
1991 } else if (found == 8 && op->opcode == 0x0006000d) {
2004 pr_debug("Removing DIV%s sequence at offset 0x%x\n",
2005 found == 9 ? "" : "U", offset << 2);
2007 for (i = 0; i < found; i++)
2008 block->opcode_list[offset + i].opcode = 0;
2016 static int lightrec_remove_div_by_zero_check_sequence(struct lightrec_state *state,
2017 struct block *block)
2022 for (i = 0; i < block->nb_ops; i++) {
2023 op = &block->opcode_list[i];
2025 if (op->i.op == OP_SPECIAL &&
2026 (op->r.op == OP_SPECIAL_DIVU || op->r.op == OP_SPECIAL_DIV) &&
2027 remove_div_sequence(block, i + 1))
2028 op->flags |= LIGHTREC_NO_DIV_CHECK;
2034 static const u32 memset_code[] = {
2035 0x10a00006, // beqz a1, 2f
2036 0x24a2ffff, // addiu v0,a1,-1
2037 0x2403ffff, // li v1,-1
2038 0xac800000, // 1: sw zero,0(a0)
2039 0x2442ffff, // addiu v0,v0,-1
2040 0x1443fffd, // bne v0,v1, 1b
2041 0x24840004, // addiu a0,a0,4
2042 0x03e00008, // 2: jr ra
2046 static int lightrec_replace_memset(struct lightrec_state *state, struct block *block)
2051 for (i = 0; i < block->nb_ops; i++) {
2052 c = block->opcode_list[i].c;
2054 if (c.opcode != memset_code[i])
2057 if (i == ARRAY_SIZE(memset_code) - 1) {
2059 pr_debug("Block at PC 0x%x is a memset\n", block->pc);
2060 block_set_flags(block,
2061 BLOCK_IS_MEMSET | BLOCK_NEVER_COMPILE);
2063 /* Return non-zero to skip other optimizers. */
2071 static int (*lightrec_optimizers[])(struct lightrec_state *state, struct block *) = {
2072 IF_OPT(OPT_REMOVE_DIV_BY_ZERO_SEQ, &lightrec_remove_div_by_zero_check_sequence),
2073 IF_OPT(OPT_REPLACE_MEMSET, &lightrec_replace_memset),
2074 IF_OPT(OPT_DETECT_IMPOSSIBLE_BRANCHES, &lightrec_detect_impossible_branches),
2075 IF_OPT(OPT_TRANSFORM_OPS, &lightrec_transform_branches),
2076 IF_OPT(OPT_LOCAL_BRANCHES, &lightrec_local_branches),
2077 IF_OPT(OPT_TRANSFORM_OPS, &lightrec_transform_ops),
2078 IF_OPT(OPT_SWITCH_DELAY_SLOTS, &lightrec_switch_delay_slots),
2079 IF_OPT(OPT_FLAG_IO || OPT_FLAG_STORES, &lightrec_flag_io),
2080 IF_OPT(OPT_FLAG_MULT_DIV, &lightrec_flag_mults_divs),
2081 IF_OPT(OPT_EARLY_UNLOAD, &lightrec_early_unload),
2084 int lightrec_optimize(struct lightrec_state *state, struct block *block)
2089 for (i = 0; i < ARRAY_SIZE(lightrec_optimizers); i++) {
2090 if (lightrec_optimizers[i]) {
2091 ret = (*lightrec_optimizers[i])(state, block);