1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - gr4300.c *
3 * Mupen64Plus homepage: http://code.google.com/p/mupen64plus/ *
4 * Copyright (C) 2007 Richard Goedeken (Richard42) *
5 * Copyright (C) 2002 Hacktarux *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
21 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
25 #include "interpret.h"
27 #include "api/debugger.h"
29 #include "r4300/r4300.h"
30 #include "r4300/macros.h"
31 #include "r4300/interupt.h"
32 #include "r4300/ops.h"
33 #include "r4300/recomph.h"
34 #include "r4300/exception.h"
36 #include "memory/memory.h"
38 #if !defined(offsetof)
39 # define offsetof(TYPE,MEMBER) ((unsigned int) &((TYPE*)0)->MEMBER)
42 #if defined(COUNT_INSTR)
43 unsigned int instr_count[132];
44 char instr_name[][10] =
46 "reserved", "NI", "J", "JAL", "BEQ", "BNE", "BLEZ", "BGTZ",
47 "ADDI", "ADDIU", "SLTI", "SLTIU", "ANDI", "ORI", "XORI", "LUI",
48 "BEQL", "BNEL", "BLEZL", "BGTZL", "DADDI", "DADDIU", "LDL", "LDR",
49 "LB", "LH", "LW", "LWL", "LBU", "LHU", "LWU", "LWR",
50 "SB", "SH", "SW", "SWL", "SWR", "SDL", "SDR", "LWC1",
51 "LDC1", "LD", "LL", "SWC1", "SDC1", "SD", "SC", "BLTZ",
52 "BGEZ", "BLTZL", "BGEZL", "BLTZAL", "BGEZAL", "BLTZALL", "BGEZALL", "SLL",
53 "SRL", "SRA", "SLLV", "SRLV", "SRAV", "JR", "JALR", "SYSCALL",
54 "MFHI", "MTHI", "MFLO", "MTLO", "DSLLV", "DSRLV", "DSRAV", "MULT",
55 "MULTU", "DIV", "DIVU", "DMULT", "DMULTU", "DDIV", "DDIVU", "ADD",
56 "ADDU", "SUB", "SUBU", "AND", "OR", "XOR", "NOR", "SLT",
57 "SLTU", "DADD", "DADDU", "DSUB", "DSUBU", "DSLL", "DSRL", "DSRA",
58 "TEQ", "DSLL32", "DSRL32", "DSRA32", "BC1F", "BC1T", "BC1FL", "BC1TL",
59 "TLBWI", "TLBP", "TLBR", "TLBWR", "ERET", "MFC0", "MTC0", "MFC1",
60 "DMFC1", "CFC1", "MTC1", "DMTC1", "CTC1", "f.CVT", "f.CMP", "f.ADD",
61 "f.SUB", "f.MUL", "f.DIV", "f.SQRT", "f.ABS", "f.MOV", "f.NEG", "f.ROUND",
62 "f.TRUNC", "f.CEIL", "f.FLOOR"
64 unsigned int instr_type[131] = { 9, 10, 6, 6, 7, 7, 7, 7, 3, 3, 4, 4, 3, 4, 4, 0,
65 7, 7, 7, 7, 4, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
66 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 7,
67 7, 7, 7, 7, 7, 7, 7, 3, 3, 3, 3, 3, 3, 6, 6, 10,
68 2, 2, 2, 2, 4, 4, 4, 3, 3, 3, 3, 4, 4, 4, 4, 3,
69 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
70 8, 4, 4, 4, 7, 7, 7, 7, 10, 10, 10, 10, 8, 2, 2, 2,
71 2, 2, 2, 2, 2, 2, 5, 5, 5, 5, 5, 5, 5, 2, 5, 5,
73 char instr_typename[][20] = { "Load", "Store", "Data move/convert", "32-bit math", "64-bit math", "Float Math",
74 "Jump", "Branch", "Exceptions", "Reserved", "Other" };
77 extern unsigned int op;
79 static precomp_instr fake_instr;
81 static long long debug_reg_storage[8];
86 /* static functions */
88 static void genupdate_count(unsigned int addr)
90 #if !defined(COMPARE_CORE) && !defined(DBG)
91 mov_reg32_imm32(EAX, addr);
92 sub_xreg32_m32rel(EAX, (unsigned int*)(&last_addr));
93 shr_reg32_imm8(EAX, 1);
94 add_m32rel_xreg32((unsigned int*)(&Count), EAX);
96 mov_reg64_imm64(RAX, (unsigned long long) (dst+1));
97 mov_m64rel_xreg64((unsigned long long *)(&PC), RAX);
98 mov_reg64_imm64(RAX, (unsigned long long)update_count);
103 static void gencheck_interupt(unsigned long long instr_structure)
105 mov_xreg32_m32rel(EAX, (void*)(&next_interupt));
106 cmp_xreg32_m32rel(EAX, (void*)&Count);
110 mov_reg64_imm64(RAX, (unsigned long long) instr_structure);
111 mov_m64rel_xreg64((unsigned long long *)(&PC), RAX);
112 mov_reg64_imm64(RAX, (unsigned long long) gen_interupt);
118 static void gencheck_interupt_out(unsigned int addr)
120 mov_xreg32_m32rel(EAX, (void*)(&next_interupt));
121 cmp_xreg32_m32rel(EAX, (void*)&Count);
125 mov_m32rel_imm32((unsigned int*)(&fake_instr.addr), addr);
126 mov_reg64_imm64(RAX, (unsigned long long) (&fake_instr));
127 mov_m64rel_xreg64((unsigned long long *)(&PC), RAX);
128 mov_reg64_imm64(RAX, (unsigned long long) gen_interupt);
134 static void genbeq_test(void)
136 int rs_64bit = is64((unsigned int *)dst->f.i.rs);
137 int rt_64bit = is64((unsigned int *)dst->f.i.rt);
139 if (rs_64bit == 0 && rt_64bit == 0)
141 int rs = allocate_register_32((unsigned int *)dst->f.i.rs);
142 int rt = allocate_register_32((unsigned int *)dst->f.i.rt);
144 cmp_reg32_reg32(rs, rt);
145 sete_m8rel((unsigned char *) &branch_taken);
147 else if (rs_64bit == -1)
149 int rt = allocate_register_64((unsigned long long *)dst->f.i.rt);
151 cmp_xreg64_m64rel(rt, (unsigned long long *) dst->f.i.rs);
152 sete_m8rel((unsigned char *) &branch_taken);
154 else if (rt_64bit == -1)
156 int rs = allocate_register_64((unsigned long long *)dst->f.i.rs);
158 cmp_xreg64_m64rel(rs, (unsigned long long *)dst->f.i.rt);
159 sete_m8rel((unsigned char *) &branch_taken);
163 int rs = allocate_register_64((unsigned long long *)dst->f.i.rs);
164 int rt = allocate_register_64((unsigned long long *)dst->f.i.rt);
165 cmp_reg64_reg64(rs, rt);
166 sete_m8rel((unsigned char *) &branch_taken);
170 static void genbne_test(void)
172 int rs_64bit = is64((unsigned int *)dst->f.i.rs);
173 int rt_64bit = is64((unsigned int *)dst->f.i.rt);
175 if (rs_64bit == 0 && rt_64bit == 0)
177 int rs = allocate_register_32((unsigned int *)dst->f.i.rs);
178 int rt = allocate_register_32((unsigned int *)dst->f.i.rt);
180 cmp_reg32_reg32(rs, rt);
181 setne_m8rel((unsigned char *) &branch_taken);
183 else if (rs_64bit == -1)
185 int rt = allocate_register_64((unsigned long long *) dst->f.i.rt);
187 cmp_xreg64_m64rel(rt, (unsigned long long *)dst->f.i.rs);
188 setne_m8rel((unsigned char *) &branch_taken);
190 else if (rt_64bit == -1)
192 int rs = allocate_register_64((unsigned long long *) dst->f.i.rs);
194 cmp_xreg64_m64rel(rs, (unsigned long long *)dst->f.i.rt);
195 setne_m8rel((unsigned char *) &branch_taken);
199 int rs = allocate_register_64((unsigned long long *)dst->f.i.rs);
200 int rt = allocate_register_64((unsigned long long *)dst->f.i.rt);
202 cmp_reg64_reg64(rs, rt);
203 setne_m8rel((unsigned char *) &branch_taken);
207 static void genblez_test(void)
209 int rs_64bit = is64((unsigned int *)dst->f.i.rs);
213 int rs = allocate_register_32((unsigned int *)dst->f.i.rs);
215 cmp_reg32_imm32(rs, 0);
216 setle_m8rel((unsigned char *) &branch_taken);
220 int rs = allocate_register_64((unsigned long long *)dst->f.i.rs);
222 cmp_reg64_imm8(rs, 0);
223 setle_m8rel((unsigned char *) &branch_taken);
227 static void genbgtz_test(void)
229 int rs_64bit = is64((unsigned int *)dst->f.i.rs);
233 int rs = allocate_register_32((unsigned int *)dst->f.i.rs);
235 cmp_reg32_imm32(rs, 0);
236 setg_m8rel((unsigned char *) &branch_taken);
240 int rs = allocate_register_64((unsigned long long *)dst->f.i.rs);
242 cmp_reg64_imm8(rs, 0);
243 setg_m8rel((unsigned char *) &branch_taken);
247 static void ld_register_alloc(int *pGpr1, int *pGpr2, int *pBase1, int *pBase2)
249 int gpr1, gpr2, base1, base2 = 0;
252 free_registers_move_start(); // to maintain parity with 32-bit core
255 if (dst->f.i.rs == dst->f.i.rt)
257 allocate_register_32((unsigned int*)dst->f.r.rs); // tell regcache we need to read RS register here
258 gpr1 = allocate_register_32_w((unsigned int*)dst->f.r.rt); // tell regcache we will modify RT register during this instruction
259 gpr2 = lock_register(lru_register()); // free and lock least recently used register for usage here
260 add_reg32_imm32(gpr1, (int)dst->f.i.immediate);
261 mov_reg32_reg32(gpr2, gpr1);
265 gpr2 = allocate_register_32((unsigned int*)dst->f.r.rs); // tell regcache we need to read RS register here
266 gpr1 = allocate_register_32_w((unsigned int*)dst->f.r.rt); // tell regcache we will modify RT register during this instruction
267 free_register(gpr2); // write out gpr2 if dirty because I'm going to trash it right now
268 add_reg32_imm32(gpr2, (int)dst->f.i.immediate);
269 mov_reg32_reg32(gpr1, gpr2);
270 lock_register(gpr2); // lock the freed gpr2 it so it doesn't get returned in the lru query
272 base1 = lock_register(lru_base_register()); // get another lru register
275 base2 = lock_register(lru_base_register()); // and another one if necessary
276 unlock_register(base2);
278 unlock_register(base1); // unlock the locked registers (they are
279 unlock_register(gpr2);
280 set_register_state(gpr1, NULL, 0, 0); // clear gpr1 state because it hasn't been written yet -
281 // we don't want it to be pushed/popped around read_rdramX call
289 /* global functions */
291 void gennotcompiled(void)
293 free_registers_move_start();
295 mov_reg64_imm64(RAX, (unsigned long long) dst);
296 mov_memoffs64_rax((unsigned long long *) &PC); /* RIP-relative will not work here */
297 mov_reg64_imm64(RAX, (unsigned long long) cached_interpreter_table.NOTCOMPILED);
301 void genlink_subblock(void)
303 free_all_registers();
310 free_all_registers();
312 mov_memoffs64_rax((unsigned long long *) &debug_reg_storage);
313 mov_reg64_imm64(RAX, (unsigned long long) &debug_reg_storage);
314 mov_preg64pimm8_reg64(RAX, 8, RBX);
315 mov_preg64pimm8_reg64(RAX, 16, RCX);
316 mov_preg64pimm8_reg64(RAX, 24, RDX);
317 mov_preg64pimm8_reg64(RAX, 32, RSP);
318 mov_preg64pimm8_reg64(RAX, 40, RBP);
319 mov_preg64pimm8_reg64(RAX, 48, RSI);
320 mov_preg64pimm8_reg64(RAX, 56, RDI);
322 mov_reg64_imm64(RAX, (unsigned long long) dst);
323 mov_memoffs64_rax((unsigned long long *) &PC);
324 mov_reg32_imm32(EAX, (unsigned int) src);
325 mov_memoffs32_eax((unsigned int *) &op);
326 mov_reg64_imm64(RAX, (unsigned long long) CoreCompareCallback);
329 mov_reg64_imm64(RAX, (unsigned long long) &debug_reg_storage);
330 mov_reg64_preg64pimm8(RDI, RAX, 56);
331 mov_reg64_preg64pimm8(RSI, RAX, 48);
332 mov_reg64_preg64pimm8(RBP, RAX, 40);
333 mov_reg64_preg64pimm8(RSP, RAX, 32);
334 mov_reg64_preg64pimm8(RDX, RAX, 24);
335 mov_reg64_preg64pimm8(RCX, RAX, 16);
336 mov_reg64_preg64pimm8(RBX, RAX, 8);
337 mov_reg64_preg64(RAX, RAX);
341 void gencallinterp(unsigned long addr, int jump)
343 free_registers_move_start();
346 mov_m32rel_imm32((unsigned int*)(&dyna_interp), 1);
348 mov_reg64_imm64(RAX, (unsigned long long) dst);
349 mov_m64rel_xreg64((unsigned long long *)(&PC), RAX);
350 mov_reg64_imm64(RAX, addr);
355 mov_m32rel_imm32((unsigned int*)(&dyna_interp), 0);
356 mov_reg64_imm64(RAX, (unsigned long long)dyna_jump);
361 void gendelayslot(void)
363 mov_m32rel_imm32((void*)(&delay_slot), 1);
366 free_all_registers();
367 genupdate_count(dst->addr+4);
369 mov_m32rel_imm32((void*)(&delay_slot), 0);
374 #if defined(COUNT_INSTR)
375 inc_m32rel(&instr_count[1]);
377 gencallinterp((unsigned long long)cached_interpreter_table.NI, 0);
380 void genreserved(void)
382 #if defined(COUNT_INSTR)
383 inc_m32rel(&instr_count[0]);
385 gencallinterp((unsigned long long)cached_interpreter_table.RESERVED, 0);
388 void genfin_block(void)
390 gencallinterp((unsigned long long)cached_interpreter_table.FIN_BLOCK, 0);
393 void gencheck_interupt_reg(void) // addr is in EAX
395 mov_xreg32_m32rel(EBX, (void*)&next_interupt);
396 cmp_xreg32_m32rel(EBX, (void*)&Count);
400 mov_m32rel_xreg32((unsigned int*)(&fake_instr.addr), EAX);
401 mov_reg64_imm64(RAX, (unsigned long long) (&fake_instr));
402 mov_m64rel_xreg64((unsigned long long *)(&PC), RAX);
403 mov_reg64_imm64(RAX, (unsigned long long) gen_interupt);
415 #if defined(COUNT_INSTR)
416 inc_m32rel(&instr_count[2]);
419 gencallinterp((unsigned long long)cached_interpreter_table.J, 1);
423 if (((dst->addr & 0xFFF) == 0xFFC &&
424 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
426 gencallinterp((unsigned long long)cached_interpreter_table.J, 1);
431 naddr = ((dst-1)->f.j.inst_index<<2) | (dst->addr & 0xF0000000);
433 mov_m32rel_imm32((void*)(&last_addr), naddr);
434 gencheck_interupt((unsigned long long) &actual->block[(naddr-actual->start)/4]);
441 #if defined(COUNT_INSTR)
442 inc_m32rel(&instr_count[2]);
444 #ifdef INTERPRET_J_OUT
445 gencallinterp((unsigned long long)cached_interpreter_table.J_OUT, 1);
449 if (((dst->addr & 0xFFF) == 0xFFC &&
450 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
452 gencallinterp((unsigned long long)cached_interpreter_table.J_OUT, 1);
457 naddr = ((dst-1)->f.j.inst_index<<2) | (dst->addr & 0xF0000000);
459 mov_m32rel_imm32((void*)(&last_addr), naddr);
460 gencheck_interupt_out(naddr);
461 mov_m32rel_imm32(&jump_to_address, naddr);
462 mov_reg64_imm64(RAX, (unsigned long long) (dst+1));
463 mov_m64rel_xreg64((unsigned long long *)(&PC), RAX);
464 mov_reg64_imm64(RAX, (unsigned long long)jump_to_func);
471 #if defined(COUNT_INSTR)
472 inc_m32rel(&instr_count[2]);
474 #ifdef INTERPRET_J_IDLE
475 gencallinterp((unsigned long long)cached_interpreter_table.J_IDLE, 1);
477 if (((dst->addr & 0xFFF) == 0xFFC &&
478 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
480 gencallinterp((unsigned long long)cached_interpreter_table.J_IDLE, 1);
484 mov_xreg32_m32rel(EAX, (unsigned int *)(&next_interupt));
485 sub_xreg32_m32rel(EAX, (unsigned int *)(&Count));
486 cmp_reg32_imm8(EAX, 3);
489 and_eax_imm32(0xFFFFFFFC); // 5
490 add_m32rel_xreg32((unsigned int *)(&Count), EAX); // 7
498 #if defined(COUNT_INSTR)
499 inc_m32rel(&instr_count[3]);
502 gencallinterp((unsigned long long)cached_interpreter_table.JAL, 1);
506 if (((dst->addr & 0xFFF) == 0xFFC &&
507 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
509 gencallinterp((unsigned long long)cached_interpreter_table.JAL, 1);
515 mov_m32rel_imm32((unsigned int *)(reg + 31), dst->addr + 4);
516 if (((dst->addr + 4) & 0x80000000))
517 mov_m32rel_imm32((unsigned int *)(®[31])+1, 0xFFFFFFFF);
519 mov_m32rel_imm32((unsigned int *)(®[31])+1, 0);
521 naddr = ((dst-1)->f.j.inst_index<<2) | (dst->addr & 0xF0000000);
523 mov_m32rel_imm32((void*)(&last_addr), naddr);
524 gencheck_interupt((unsigned long long) &actual->block[(naddr-actual->start)/4]);
529 void genjal_out(void)
531 #if defined(COUNT_INSTR)
532 inc_m32rel(&instr_count[3]);
534 #ifdef INTERPRET_JAL_OUT
535 gencallinterp((unsigned long long)cached_interpreter_table.JAL_OUT, 1);
539 if (((dst->addr & 0xFFF) == 0xFFC &&
540 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
542 gencallinterp((unsigned long long)cached_interpreter_table.JAL_OUT, 1);
548 mov_m32rel_imm32((unsigned int *)(reg + 31), dst->addr + 4);
549 if (((dst->addr + 4) & 0x80000000))
550 mov_m32rel_imm32((unsigned int *)(®[31])+1, 0xFFFFFFFF);
552 mov_m32rel_imm32((unsigned int *)(®[31])+1, 0);
554 naddr = ((dst-1)->f.j.inst_index<<2) | (dst->addr & 0xF0000000);
556 mov_m32rel_imm32((void*)(&last_addr), naddr);
557 gencheck_interupt_out(naddr);
558 mov_m32rel_imm32(&jump_to_address, naddr);
559 mov_reg64_imm64(RAX, (unsigned long long) (dst+1));
560 mov_m64rel_xreg64((unsigned long long *)(&PC), RAX);
561 mov_reg64_imm64(RAX, (unsigned long long) jump_to_func);
566 void genjal_idle(void)
568 #if defined(COUNT_INSTR)
569 inc_m32rel(&instr_count[3]);
571 #ifdef INTERPRET_JAL_IDLE
572 gencallinterp((unsigned long long)cached_interpreter_table.JAL_IDLE, 1);
574 if (((dst->addr & 0xFFF) == 0xFFC &&
575 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
577 gencallinterp((unsigned long long)cached_interpreter_table.JAL_IDLE, 1);
581 mov_xreg32_m32rel(EAX, (unsigned int *)(&next_interupt));
582 sub_xreg32_m32rel(EAX, (unsigned int *)(&Count));
583 cmp_reg32_imm8(EAX, 3);
586 and_eax_imm32(0xFFFFFFFC); // 5
587 add_m32rel_xreg32((unsigned int *)(&Count), EAX); // 7
595 cmp_m32rel_imm32((unsigned int *)(&branch_taken), 0);
599 mov_m32rel_imm32((void*)(&last_addr), dst->addr + (dst-1)->f.i.immediate*4);
600 gencheck_interupt((unsigned long long) (dst + (dst-1)->f.i.immediate));
601 jmp(dst->addr + (dst-1)->f.i.immediate*4);
605 mov_m32rel_imm32((void*)(&last_addr), dst->addr + 4);
606 gencheck_interupt((unsigned long long)(dst + 1));
612 #if defined(COUNT_INSTR)
613 inc_m32rel(&instr_count[4]);
616 gencallinterp((unsigned long long)cached_interpreter_table.BEQ, 1);
618 if (((dst->addr & 0xFFF) == 0xFFC &&
619 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
621 gencallinterp((unsigned long long)cached_interpreter_table.BEQ, 1);
631 void gentest_out(void)
633 cmp_m32rel_imm32((unsigned int *)(&branch_taken), 0);
637 mov_m32rel_imm32((void*)(&last_addr), dst->addr + (dst-1)->f.i.immediate*4);
638 gencheck_interupt_out(dst->addr + (dst-1)->f.i.immediate*4);
639 mov_m32rel_imm32(&jump_to_address, dst->addr + (dst-1)->f.i.immediate*4);
640 mov_reg64_imm64(RAX, (unsigned long long) (dst+1));
641 mov_m64rel_xreg64((unsigned long long *)(&PC), RAX);
642 mov_reg64_imm64(RAX, (unsigned long long) jump_to_func);
646 mov_m32rel_imm32((void*)(&last_addr), dst->addr + 4);
647 gencheck_interupt((unsigned long long) (dst + 1));
651 void genbeq_out(void)
653 #if defined(COUNT_INSTR)
654 inc_m32rel(&instr_count[4]);
656 #ifdef INTERPRET_BEQ_OUT
657 gencallinterp((unsigned long long)cached_interpreter_table.BEQ_OUT, 1);
659 if (((dst->addr & 0xFFF) == 0xFFC &&
660 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
662 gencallinterp((unsigned long long)cached_interpreter_table.BEQ_OUT, 1);
672 void gentest_idle(void)
676 reg = lru_register();
679 cmp_m32rel_imm32((unsigned int *)(&branch_taken), 0);
683 mov_xreg32_m32rel(reg, (unsigned int *)(&next_interupt));
684 sub_xreg32_m32rel(reg, (unsigned int *)(&Count));
685 cmp_reg32_imm8(reg, 3);
689 and_reg32_imm32(reg, 0xFFFFFFFC);
690 add_m32rel_xreg32((unsigned int *)(&Count), reg);
696 void genbeq_idle(void)
698 #ifdef INTERPRET_BEQ_IDLE
699 gencallinterp((unsigned long long)cached_interpreter_table.BEQ_IDLE, 1);
701 if (((dst->addr & 0xFFF) == 0xFFC &&
702 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
704 gencallinterp((unsigned long long)cached_interpreter_table.BEQ_IDLE, 1);
716 #if defined(COUNT_INSTR)
717 inc_m32rel(&instr_count[5]);
720 gencallinterp((unsigned long long)cached_interpreter_table.BNE, 1);
722 if (((dst->addr & 0xFFF) == 0xFFC &&
723 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
725 gencallinterp((unsigned long long)cached_interpreter_table.BNE, 1);
735 void genbne_out(void)
737 #if defined(COUNT_INSTR)
738 inc_m32rel(&instr_count[5]);
740 #ifdef INTERPRET_BNE_OUT
741 gencallinterp((unsigned long long)cached_interpreter_table.BNE_OUT, 1);
743 if (((dst->addr & 0xFFF) == 0xFFC &&
744 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
746 gencallinterp((unsigned long long)cached_interpreter_table.BNE_OUT, 1);
756 void genbne_idle(void)
758 #ifdef INTERPRET_BNE_IDLE
759 gencallinterp((unsigned long long)cached_interpreter_table.BNE_IDLE, 1);
761 if (((dst->addr & 0xFFF) == 0xFFC &&
762 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
764 gencallinterp((unsigned long long)cached_interpreter_table.BNE_IDLE, 1);
776 #if defined(COUNT_INSTR)
777 inc_m32rel(&instr_count[6]);
779 #ifdef INTERPRET_BLEZ
780 gencallinterp((unsigned long long)cached_interpreter_table.BLEZ, 1);
782 if (((dst->addr & 0xFFF) == 0xFFC &&
783 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
785 gencallinterp((unsigned long long)cached_interpreter_table.BLEZ, 1);
795 void genblez_out(void)
797 #if defined(COUNT_INSTR)
798 inc_m32rel(&instr_count[6]);
800 #ifdef INTERPRET_BLEZ_OUT
801 gencallinterp((unsigned long long)cached_interpreter_table.BLEZ_OUT, 1);
803 if (((dst->addr & 0xFFF) == 0xFFC &&
804 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
806 gencallinterp((unsigned long long)cached_interpreter_table.BLEZ_OUT, 1);
816 void genblez_idle(void)
818 #ifdef INTERPRET_BLEZ_IDLE
819 gencallinterp((unsigned long long)cached_interpreter_table.BLEZ_IDLE, 1);
821 if (((dst->addr & 0xFFF) == 0xFFC &&
822 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
824 gencallinterp((unsigned long long)cached_interpreter_table.BLEZ_IDLE, 1);
836 #if defined(COUNT_INSTR)
837 inc_m32rel(&instr_count[7]);
839 #ifdef INTERPRET_BGTZ
840 gencallinterp((unsigned long long)cached_interpreter_table.BGTZ, 1);
842 if (((dst->addr & 0xFFF) == 0xFFC &&
843 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
845 gencallinterp((unsigned long long)cached_interpreter_table.BGTZ, 1);
855 void genbgtz_out(void)
857 #if defined(COUNT_INSTR)
858 inc_m32rel(&instr_count[7]);
860 #ifdef INTERPRET_BGTZ_OUT
861 gencallinterp((unsigned long long)cached_interpreter_table.BGTZ_OUT, 1);
863 if (((dst->addr & 0xFFF) == 0xFFC &&
864 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
866 gencallinterp((unsigned long long)cached_interpreter_table.BGTZ_OUT, 1);
876 void genbgtz_idle(void)
878 #ifdef INTERPRET_BGTZ_IDLE
879 gencallinterp((unsigned long long)cached_interpreter_table.BGTZ_IDLE, 1);
881 if (((dst->addr & 0xFFF) == 0xFFC &&
882 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
884 gencallinterp((unsigned long long)cached_interpreter_table.BGTZ_IDLE, 1);
896 #if defined(COUNT_INSTR)
897 inc_m32rel(&instr_count[8]);
899 #ifdef INTERPRET_ADDI
900 gencallinterp((unsigned long long)cached_interpreter_table.ADDI, 0);
902 int rs = allocate_register_32((unsigned int *)dst->f.i.rs);
903 int rt = allocate_register_32_w((unsigned int *)dst->f.i.rt);
905 mov_reg32_reg32(rt, rs);
906 add_reg32_imm32(rt,(int)dst->f.i.immediate);
912 #if defined(COUNT_INSTR)
913 inc_m32rel(&instr_count[9]);
915 #ifdef INTERPRET_ADDIU
916 gencallinterp((unsigned long long)cached_interpreter_table.ADDIU, 0);
918 int rs = allocate_register_32((unsigned int *)dst->f.i.rs);
919 int rt = allocate_register_32_w((unsigned int *)dst->f.i.rt);
921 mov_reg32_reg32(rt, rs);
922 add_reg32_imm32(rt,(int)dst->f.i.immediate);
928 #if defined(COUNT_INSTR)
929 inc_m32rel(&instr_count[10]);
931 #ifdef INTERPRET_SLTI
932 gencallinterp((unsigned long long)cached_interpreter_table.SLTI, 0);
934 int rs = allocate_register_64((unsigned long long *) dst->f.i.rs);
935 int rt = allocate_register_64_w((unsigned long long *) dst->f.i.rt);
936 int imm = (int) dst->f.i.immediate;
938 cmp_reg64_imm32(rs, imm);
940 and_reg64_imm8(rt, 1);
946 #if defined(COUNT_INSTR)
947 inc_m32rel(&instr_count[11]);
949 #ifdef INTERPRET_SLTIU
950 gencallinterp((unsigned long long)cached_interpreter_table.SLTIU, 0);
952 int rs = allocate_register_64((unsigned long long *)dst->f.i.rs);
953 int rt = allocate_register_64_w((unsigned long long *)dst->f.i.rt);
954 int imm = (int) dst->f.i.immediate;
956 cmp_reg64_imm32(rs, imm);
958 and_reg64_imm8(rt, 1);
964 #if defined(COUNT_INSTR)
965 inc_m32rel(&instr_count[12]);
967 #ifdef INTERPRET_ANDI
968 gencallinterp((unsigned long long)cached_interpreter_table.ANDI, 0);
970 int rs = allocate_register_64((unsigned long long *)dst->f.i.rs);
971 int rt = allocate_register_64_w((unsigned long long *)dst->f.i.rt);
973 mov_reg64_reg64(rt, rs);
974 and_reg64_imm32(rt, (unsigned short)dst->f.i.immediate);
980 #if defined(COUNT_INSTR)
981 inc_m32rel(&instr_count[13]);
984 gencallinterp((unsigned long long)cached_interpreter_table.ORI, 0);
986 int rs = allocate_register_64((unsigned long long *) dst->f.i.rs);
987 int rt = allocate_register_64_w((unsigned long long *) dst->f.i.rt);
989 mov_reg64_reg64(rt, rs);
990 or_reg64_imm32(rt, (unsigned short)dst->f.i.immediate);
996 #if defined(COUNT_INSTR)
997 inc_m32rel(&instr_count[14]);
999 #ifdef INTERPRET_XORI
1000 gencallinterp((unsigned long long)cached_interpreter_table.XORI, 0);
1002 int rs = allocate_register_64((unsigned long long *)dst->f.i.rs);
1003 int rt = allocate_register_64_w((unsigned long long *)dst->f.i.rt);
1005 mov_reg64_reg64(rt, rs);
1006 xor_reg64_imm32(rt, (unsigned short)dst->f.i.immediate);
1012 #if defined(COUNT_INSTR)
1013 inc_m32rel(&instr_count[15]);
1015 #ifdef INTERPRET_LUI
1016 gencallinterp((unsigned long long)cached_interpreter_table.LUI, 0);
1018 int rt = allocate_register_32_w((unsigned int *)dst->f.i.rt);
1020 mov_reg32_imm32(rt, (unsigned int)dst->f.i.immediate << 16);
1026 cmp_m32rel_imm32((unsigned int *)(&branch_taken), 0);
1031 mov_m32rel_imm32((void*)(&last_addr), dst->addr + (dst-1)->f.i.immediate*4);
1032 gencheck_interupt((unsigned long long) (dst + (dst-1)->f.i.immediate));
1033 jmp(dst->addr + (dst-1)->f.i.immediate*4);
1037 genupdate_count(dst->addr-4);
1038 mov_m32rel_imm32((void*)(&last_addr), dst->addr + 4);
1039 gencheck_interupt((unsigned long long) (dst + 1));
1045 #if defined(COUNT_INSTR)
1046 inc_m32rel(&instr_count[16]);
1048 #ifdef INTERPRET_BEQL
1049 gencallinterp((unsigned long long)cached_interpreter_table.BEQL, 1);
1051 if (((dst->addr & 0xFFF) == 0xFFC &&
1052 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1054 gencallinterp((unsigned long long)cached_interpreter_table.BEQL, 1);
1059 free_all_registers();
1064 void gentestl_out(void)
1066 cmp_m32rel_imm32((unsigned int *)(&branch_taken), 0);
1071 mov_m32rel_imm32((void*)(&last_addr), dst->addr + (dst-1)->f.i.immediate*4);
1072 gencheck_interupt_out(dst->addr + (dst-1)->f.i.immediate*4);
1073 mov_m32rel_imm32(&jump_to_address, dst->addr + (dst-1)->f.i.immediate*4);
1075 mov_reg64_imm64(RAX, (unsigned long long) (dst+1));
1076 mov_m64rel_xreg64((unsigned long long *)(&PC), RAX);
1077 mov_reg64_imm64(RAX, (unsigned long long) jump_to_func);
1082 genupdate_count(dst->addr-4);
1083 mov_m32rel_imm32((void*)(&last_addr), dst->addr + 4);
1084 gencheck_interupt((unsigned long long) (dst + 1));
1088 void genbeql_out(void)
1090 #if defined(COUNT_INSTR)
1091 inc_m32rel(&instr_count[16]);
1093 #ifdef INTERPRET_BEQL_OUT
1094 gencallinterp((unsigned long long)cached_interpreter_table.BEQL_OUT, 1);
1096 if (((dst->addr & 0xFFF) == 0xFFC &&
1097 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1099 gencallinterp((unsigned long long)cached_interpreter_table.BEQL_OUT, 1);
1104 free_all_registers();
1109 void genbeql_idle(void)
1111 #ifdef INTERPRET_BEQL_IDLE
1112 gencallinterp((unsigned long long)cached_interpreter_table.BEQL_IDLE, 1);
1114 if (((dst->addr & 0xFFF) == 0xFFC &&
1115 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1117 gencallinterp((unsigned long long)cached_interpreter_table.BEQL_IDLE, 1);
1129 #if defined(COUNT_INSTR)
1130 inc_m32rel(&instr_count[17]);
1132 #ifdef INTERPRET_BNEL
1133 gencallinterp((unsigned long long)cached_interpreter_table.BNEL, 1);
1135 if (((dst->addr & 0xFFF) == 0xFFC &&
1136 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1138 gencallinterp((unsigned long long)cached_interpreter_table.BNEL, 1);
1143 free_all_registers();
1148 void genbnel_out(void)
1150 #if defined(COUNT_INSTR)
1151 inc_m32rel(&instr_count[17]);
1153 #ifdef INTERPRET_BNEL_OUT
1154 gencallinterp((unsigned long long)cached_interpreter_table.BNEL_OUT, 1);
1156 if (((dst->addr & 0xFFF) == 0xFFC &&
1157 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1159 gencallinterp((unsigned long long)cached_interpreter_table.BNEL_OUT, 1);
1164 free_all_registers();
1169 void genbnel_idle(void)
1171 #ifdef INTERPRET_BNEL_IDLE
1172 gencallinterp((unsigned long long)cached_interpreter_table.BNEL_IDLE, 1);
1174 if (((dst->addr & 0xFFF) == 0xFFC &&
1175 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1177 gencallinterp((unsigned long long)cached_interpreter_table.BNEL_IDLE, 1);
1189 #if defined(COUNT_INSTR)
1190 inc_m32rel(&instr_count[18]);
1192 #ifdef INTERPRET_BLEZL
1193 gencallinterp((unsigned long long)cached_interpreter_table.BLEZL, 1);
1195 if (((dst->addr & 0xFFF) == 0xFFC &&
1196 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1198 gencallinterp((unsigned long long)cached_interpreter_table.BLEZL, 1);
1203 free_all_registers();
1208 void genblezl_out(void)
1210 #if defined(COUNT_INSTR)
1211 inc_m32rel(&instr_count[18]);
1213 #ifdef INTERPRET_BLEZL_OUT
1214 gencallinterp((unsigned long long)cached_interpreter_table.BLEZL_OUT, 1);
1216 if (((dst->addr & 0xFFF) == 0xFFC &&
1217 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1219 gencallinterp((unsigned long long)cached_interpreter_table.BLEZL_OUT, 1);
1224 free_all_registers();
1229 void genblezl_idle(void)
1231 #ifdef INTERPRET_BLEZL_IDLE
1232 gencallinterp((unsigned long long)cached_interpreter_table.BLEZL_IDLE, 1);
1234 if (((dst->addr & 0xFFF) == 0xFFC &&
1235 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1237 gencallinterp((unsigned long long)cached_interpreter_table.BLEZL_IDLE, 1);
1249 #if defined(COUNT_INSTR)
1250 inc_m32rel(&instr_count[19]);
1252 #ifdef INTERPRET_BGTZL
1253 gencallinterp((unsigned long long)cached_interpreter_table.BGTZL, 1);
1255 if (((dst->addr & 0xFFF) == 0xFFC &&
1256 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1258 gencallinterp((unsigned long long)cached_interpreter_table.BGTZL, 1);
1263 free_all_registers();
1268 void genbgtzl_out(void)
1270 #if defined(COUNT_INSTR)
1271 inc_m32rel(&instr_count[19]);
1273 #ifdef INTERPRET_BGTZL_OUT
1274 gencallinterp((unsigned long long)cached_interpreter_table.BGTZL_OUT, 1);
1276 if (((dst->addr & 0xFFF) == 0xFFC &&
1277 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1279 gencallinterp((unsigned long long)cached_interpreter_table.BGTZL_OUT, 1);
1284 free_all_registers();
1289 void genbgtzl_idle(void)
1291 #ifdef INTERPRET_BGTZL_IDLE
1292 gencallinterp((unsigned long long)cached_interpreter_table.BGTZL_IDLE, 1);
1294 if (((dst->addr & 0xFFF) == 0xFFC &&
1295 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1297 gencallinterp((unsigned long long)cached_interpreter_table.BGTZL_IDLE, 1);
1309 #if defined(COUNT_INSTR)
1310 inc_m32rel(&instr_count[20]);
1312 #ifdef INTERPRET_DADDI
1313 gencallinterp((unsigned long long)cached_interpreter_table.DADDI, 0);
1315 int rs = allocate_register_64((unsigned long long *)dst->f.i.rs);
1316 int rt = allocate_register_64_w((unsigned long long *)dst->f.i.rt);
1318 mov_reg64_reg64(rt, rs);
1319 add_reg64_imm32(rt, (int) dst->f.i.immediate);
1323 void gendaddiu(void)
1325 #ifdef INTERPRET_DADDIU
1326 gencallinterp((unsigned long long)cached_interpreter_table.DADDIU, 0);
1328 int rs = allocate_register_64((unsigned long long *)dst->f.i.rs);
1329 int rt = allocate_register_64_w((unsigned long long *)dst->f.i.rt);
1331 mov_reg64_reg64(rt, rs);
1332 add_reg64_imm32(rt, (int) dst->f.i.immediate);
1338 #if defined(COUNT_INSTR)
1339 inc_m32rel(&instr_count[22]);
1341 gencallinterp((unsigned long long)cached_interpreter_table.LDL, 0);
1346 #if defined(COUNT_INSTR)
1347 inc_m32rel(&instr_count[23]);
1349 gencallinterp((unsigned long long)cached_interpreter_table.LDR, 0);
1354 int gpr1, gpr2, base1, base2 = 0;
1355 #if defined(COUNT_INSTR)
1356 inc_m32rel(&instr_count[24]);
1359 gencallinterp((unsigned long long)cached_interpreter_table.LB, 0);
1361 free_registers_move_start();
1363 ld_register_alloc(&gpr1, &gpr2, &base1, &base2);
1365 mov_reg64_imm64(base1, (unsigned long long) readmemb);
1368 and_reg32_imm32(gpr1, 0xDF800000);
1369 cmp_reg32_imm32(gpr1, 0x80000000);
1373 mov_reg64_imm64(base2, (unsigned long long) read_rdramb);
1374 shr_reg32_imm8(gpr1, 16);
1375 mov_reg64_preg64x8preg64(gpr1, gpr1, base1);
1376 cmp_reg64_reg64(gpr1, base2);
1381 mov_reg64_imm64(gpr1, (unsigned long long) (dst+1));
1382 mov_m64rel_xreg64((unsigned long long *)(&PC), gpr1);
1383 mov_m32rel_xreg32((unsigned int *)(&address), gpr2);
1384 mov_reg64_imm64(gpr1, (unsigned long long) dst->f.i.rt);
1385 mov_m64rel_xreg64((unsigned long long *)(&rdword), gpr1);
1386 shr_reg32_imm8(gpr2, 16);
1387 mov_reg64_preg64x8preg64(gpr2, gpr2, base1);
1389 movsx_xreg32_m8rel(gpr1, (unsigned char *)dst->f.i.rt);
1393 mov_reg64_imm64(base1, (unsigned long long) rdram); // 10
1394 and_reg32_imm32(gpr2, 0x7FFFFF); // 6
1395 xor_reg8_imm8(gpr2, 3); // 4
1396 movsx_reg32_8preg64preg64(gpr1, gpr2, base1); // 4
1398 set_register_state(gpr1, (unsigned int*)dst->f.i.rt, 1, 0);
1404 int gpr1, gpr2, base1, base2 = 0;
1405 #if defined(COUNT_INSTR)
1406 inc_m32rel(&instr_count[25]);
1409 gencallinterp((unsigned long long)cached_interpreter_table.LH, 0);
1411 free_registers_move_start();
1413 ld_register_alloc(&gpr1, &gpr2, &base1, &base2);
1415 mov_reg64_imm64(base1, (unsigned long long) readmemh);
1418 and_reg32_imm32(gpr1, 0xDF800000);
1419 cmp_reg32_imm32(gpr1, 0x80000000);
1423 mov_reg64_imm64(base2, (unsigned long long) read_rdramh);
1424 shr_reg32_imm8(gpr1, 16);
1425 mov_reg64_preg64x8preg64(gpr1, gpr1, base1);
1426 cmp_reg64_reg64(gpr1, base2);
1431 mov_reg64_imm64(gpr1, (unsigned long long) (dst+1));
1432 mov_m64rel_xreg64((unsigned long long *)(&PC), gpr1);
1433 mov_m32rel_xreg32((unsigned int *)(&address), gpr2);
1434 mov_reg64_imm64(gpr1, (unsigned long long) dst->f.i.rt);
1435 mov_m64rel_xreg64((unsigned long long *)(&rdword), gpr1);
1436 shr_reg32_imm8(gpr2, 16);
1437 mov_reg64_preg64x8preg64(gpr2, gpr2, base1);
1439 movsx_xreg32_m16rel(gpr1, (unsigned short *)dst->f.i.rt);
1443 mov_reg64_imm64(base1, (unsigned long long) rdram); // 10
1444 and_reg32_imm32(gpr2, 0x7FFFFF); // 6
1445 xor_reg8_imm8(gpr2, 2); // 4
1446 movsx_reg32_16preg64preg64(gpr1, gpr2, base1); // 4
1448 set_register_state(gpr1, (unsigned int*)dst->f.i.rt, 1, 0);
1454 #if defined(COUNT_INSTR)
1455 inc_m32rel(&instr_count[27]);
1457 gencallinterp((unsigned long long)cached_interpreter_table.LWL, 0);
1462 int gpr1, gpr2, base1, base2 = 0;
1463 #if defined(COUNT_INSTR)
1464 inc_m32rel(&instr_count[26]);
1467 gencallinterp((unsigned long long)cached_interpreter_table.LW, 0);
1469 free_registers_move_start();
1471 ld_register_alloc(&gpr1, &gpr2, &base1, &base2);
1473 mov_reg64_imm64(base1, (unsigned long long) readmem);
1476 and_reg32_imm32(gpr1, 0xDF800000);
1477 cmp_reg32_imm32(gpr1, 0x80000000);
1481 mov_reg64_imm64(base2, (unsigned long long) read_rdram);
1482 shr_reg32_imm8(gpr1, 16);
1483 mov_reg64_preg64x8preg64(gpr1, gpr1, base1);
1484 cmp_reg64_reg64(gpr1, base2);
1488 mov_reg64_imm64(base1, (unsigned long long) rdram); // 10
1489 and_reg32_imm32(gpr2, 0x7FFFFF); // 6
1490 mov_reg32_preg64preg64(gpr1, gpr2, base1); // 3
1491 jmp_imm_short(0); // 2
1494 mov_reg64_imm64(gpr1, (unsigned long long) (dst+1));
1495 mov_m64rel_xreg64((unsigned long long *)(&PC), gpr1);
1496 mov_m32rel_xreg32((unsigned int *)(&address), gpr2);
1497 mov_reg64_imm64(gpr1, (unsigned long long) dst->f.i.rt);
1498 mov_m64rel_xreg64((unsigned long long *)(&rdword), gpr1);
1499 shr_reg32_imm8(gpr2, 16);
1500 mov_reg64_preg64x8preg64(gpr1, gpr2, base1);
1502 mov_xreg32_m32rel(gpr1, (unsigned int *)(dst->f.i.rt));
1506 set_register_state(gpr1, (unsigned int*)dst->f.i.rt, 1, 0); // set gpr1 state as dirty, and bound to r4300 reg RT
1512 int gpr1, gpr2, base1, base2 = 0;
1513 #if defined(COUNT_INSTR)
1514 inc_m32rel(&instr_count[28]);
1516 #ifdef INTERPRET_LBU
1517 gencallinterp((unsigned long long)cached_interpreter_table.LBU, 0);
1519 free_registers_move_start();
1521 ld_register_alloc(&gpr1, &gpr2, &base1, &base2);
1523 mov_reg64_imm64(base1, (unsigned long long) readmemb);
1526 and_reg32_imm32(gpr1, 0xDF800000);
1527 cmp_reg32_imm32(gpr1, 0x80000000);
1531 mov_reg64_imm64(base2, (unsigned long long) read_rdramb);
1532 shr_reg32_imm8(gpr1, 16);
1533 mov_reg64_preg64x8preg64(gpr1, gpr1, base1);
1534 cmp_reg64_reg64(gpr1, base2);
1539 mov_reg64_imm64(gpr1, (unsigned long long) (dst+1));
1540 mov_m64rel_xreg64((unsigned long long *)(&PC), gpr1);
1541 mov_m32rel_xreg32((unsigned int *)(&address), gpr2);
1542 mov_reg64_imm64(gpr1, (unsigned long long) dst->f.i.rt);
1543 mov_m64rel_xreg64((unsigned long long *)(&rdword), gpr1);
1544 shr_reg32_imm8(gpr2, 16);
1545 mov_reg64_preg64x8preg64(gpr2, gpr2, base1);
1547 mov_xreg32_m32rel(gpr1, (unsigned int *)dst->f.i.rt);
1551 mov_reg64_imm64(base1, (unsigned long long) rdram); // 10
1552 and_reg32_imm32(gpr2, 0x7FFFFF); // 6
1553 xor_reg8_imm8(gpr2, 3); // 4
1554 mov_reg32_preg64preg64(gpr1, gpr2, base1); // 3
1556 and_reg32_imm32(gpr1, 0xFF);
1557 set_register_state(gpr1, (unsigned int*)dst->f.i.rt, 1, 0);
1563 int gpr1, gpr2, base1, base2 = 0;
1564 #if defined(COUNT_INSTR)
1565 inc_m32rel(&instr_count[29]);
1567 #ifdef INTERPRET_LHU
1568 gencallinterp((unsigned long long)cached_interpreter_table.LHU, 0);
1570 free_registers_move_start();
1572 ld_register_alloc(&gpr1, &gpr2, &base1, &base2);
1574 mov_reg64_imm64(base1, (unsigned long long) readmemh);
1577 and_reg32_imm32(gpr1, 0xDF800000);
1578 cmp_reg32_imm32(gpr1, 0x80000000);
1582 mov_reg64_imm64(base2, (unsigned long long) read_rdramh);
1583 shr_reg32_imm8(gpr1, 16);
1584 mov_reg64_preg64x8preg64(gpr1, gpr1, base1);
1585 cmp_reg64_reg64(gpr1, base2);
1590 mov_reg64_imm64(gpr1, (unsigned long long) (dst+1));
1591 mov_m64rel_xreg64((unsigned long long *)(&PC), gpr1);
1592 mov_m32rel_xreg32((unsigned int *)(&address), gpr2);
1593 mov_reg64_imm64(gpr1, (unsigned long long) dst->f.i.rt);
1594 mov_m64rel_xreg64((unsigned long long *)(&rdword), gpr1);
1595 shr_reg32_imm8(gpr2, 16);
1596 mov_reg64_preg64x8preg64(gpr2, gpr2, base1);
1598 mov_xreg32_m32rel(gpr1, (unsigned int *)dst->f.i.rt);
1602 mov_reg64_imm64(base1, (unsigned long long) rdram); // 10
1603 and_reg32_imm32(gpr2, 0x7FFFFF); // 6
1604 xor_reg8_imm8(gpr2, 2); // 4
1605 mov_reg32_preg64preg64(gpr1, gpr2, base1); // 3
1607 and_reg32_imm32(gpr1, 0xFFFF);
1608 set_register_state(gpr1, (unsigned int*)dst->f.i.rt, 1, 0);
1614 #if defined(COUNT_INSTR)
1615 inc_m32rel(&instr_count[31]);
1617 gencallinterp((unsigned long long)cached_interpreter_table.LWR, 0);
1622 int gpr1, gpr2, base1, base2 = 0;
1623 #if defined(COUNT_INSTR)
1624 inc_m32rel(&instr_count[30]);
1626 #ifdef INTERPRET_LWU
1627 gencallinterp((unsigned long long)cached_interpreter_table.LWU, 0);
1629 free_registers_move_start();
1631 ld_register_alloc(&gpr1, &gpr2, &base1, &base2);
1633 mov_reg64_imm64(base1, (unsigned long long) readmem);
1636 and_reg32_imm32(gpr1, 0xDF800000);
1637 cmp_reg32_imm32(gpr1, 0x80000000);
1641 mov_reg64_imm64(base2, (unsigned long long) read_rdram);
1642 shr_reg32_imm8(gpr1, 16);
1643 mov_reg64_preg64x8preg64(gpr1, gpr1, base1);
1644 cmp_reg64_reg64(gpr1, base2);
1649 mov_reg64_imm64(gpr1, (unsigned long long) (dst+1));
1650 mov_m64rel_xreg64((unsigned long long *)(&PC), gpr1);
1651 mov_m32rel_xreg32((unsigned int *)(&address), gpr2);
1652 mov_reg64_imm64(gpr1, (unsigned long long) dst->f.i.rt);
1653 mov_m64rel_xreg64((unsigned long long *)(&rdword), gpr1);
1654 shr_reg32_imm8(gpr2, 16);
1655 mov_reg64_preg64x8preg64(gpr2, gpr2, base1);
1657 mov_xreg32_m32rel(gpr1, (unsigned int *)dst->f.i.rt);
1661 mov_reg64_imm64(base1, (unsigned long long) rdram); // 10
1662 and_reg32_imm32(gpr2, 0x7FFFFF); // 6
1663 mov_reg32_preg64preg64(gpr1, gpr2, base1); // 3
1665 set_register_state(gpr1, (unsigned int*)dst->f.i.rt, 1, 1);
1671 #if defined(COUNT_INSTR)
1672 inc_m32rel(&instr_count[32]);
1675 gencallinterp((unsigned long long)cached_interpreter_table.SB, 0);
1677 free_registers_move_start();
1679 mov_xreg8_m8rel(CL, (unsigned char *)dst->f.i.rt);
1680 mov_xreg32_m32rel(EAX, (unsigned int *)dst->f.i.rs);
1681 add_eax_imm32((int)dst->f.i.immediate);
1682 mov_reg32_reg32(EBX, EAX);
1683 mov_reg64_imm64(RSI, (unsigned long long) writememb);
1686 and_eax_imm32(0xDF800000);
1687 cmp_eax_imm32(0x80000000);
1691 mov_reg64_imm64(RDI, (unsigned long long) write_rdramb);
1692 shr_reg32_imm8(EAX, 16);
1693 mov_reg64_preg64x8preg64(RAX, RAX, RSI);
1694 cmp_reg64_reg64(RAX, RDI);
1698 mov_reg64_imm64(RAX, (unsigned long long) (dst+1)); // 10
1699 mov_m64rel_xreg64((unsigned long long *)(&PC), RAX); // 7
1700 mov_m32rel_xreg32((unsigned int *)(&address), EBX); // 7
1701 mov_m8rel_xreg8((unsigned char *)(&cpu_byte), CL); // 7
1702 shr_reg32_imm8(EBX, 16); // 3
1703 mov_reg64_preg64x8preg64(RBX, RBX, RSI); // 4
1704 call_reg64(RBX); // 2
1705 mov_xreg32_m32rel(EAX, (unsigned int *)(&address)); // 7
1706 jmp_imm_short(25); // 2
1708 mov_reg64_imm64(RSI, (unsigned long long) rdram); // 10
1709 mov_reg32_reg32(EAX, EBX); // 2
1710 and_reg32_imm32(EBX, 0x7FFFFF); // 6
1711 xor_reg8_imm8(BL, 3); // 4
1712 mov_preg64preg64_reg8(RBX, RSI, CL); // 3
1714 mov_reg64_imm64(RSI, (unsigned long long) invalid_code);
1715 mov_reg32_reg32(EBX, EAX);
1716 shr_reg32_imm8(EBX, 12);
1717 cmp_preg64preg64_imm8(RBX, RSI, 0);
1720 mov_reg64_imm64(RDI, (unsigned long long) blocks); // 10
1721 mov_reg32_reg32(ECX, EBX); // 2
1722 mov_reg64_preg64x8preg64(RBX, RBX, RDI); // 4
1723 mov_reg64_preg64pimm32(RBX, RBX, (int) offsetof(precomp_block, block)); // 7
1724 mov_reg64_imm64(RDI, (unsigned long long) cached_interpreter_table.NOTCOMPILED); // 10
1725 and_eax_imm32(0xFFF); // 5
1726 shr_reg32_imm8(EAX, 2); // 3
1727 mov_reg32_imm32(EDX, sizeof(precomp_instr)); // 5
1728 mul_reg32(EDX); // 2
1729 mov_reg64_preg64preg64pimm32(RAX, RAX, RBX, (int) offsetof(precomp_instr, ops)); // 8
1730 cmp_reg64_reg64(RAX, RDI); // 3
1732 mov_preg64preg64_imm8(RCX, RSI, 1); // 4
1738 #if defined(COUNT_INSTR)
1739 inc_m32rel(&instr_count[33]);
1742 gencallinterp((unsigned long long)cached_interpreter_table.SH, 0);
1744 free_registers_move_start();
1746 mov_xreg16_m16rel(CX, (unsigned short *)dst->f.i.rt);
1747 mov_xreg32_m32rel(EAX, (unsigned int *)dst->f.i.rs);
1748 add_eax_imm32((int)dst->f.i.immediate);
1749 mov_reg32_reg32(EBX, EAX);
1750 mov_reg64_imm64(RSI, (unsigned long long) writememh);
1753 and_eax_imm32(0xDF800000);
1754 cmp_eax_imm32(0x80000000);
1758 mov_reg64_imm64(RDI, (unsigned long long) write_rdramh);
1759 shr_reg32_imm8(EAX, 16);
1760 mov_reg64_preg64x8preg64(RAX, RAX, RSI);
1761 cmp_reg64_reg64(RAX, RDI);
1765 mov_reg64_imm64(RAX, (unsigned long long) (dst+1)); // 10
1766 mov_m64rel_xreg64((unsigned long long *)(&PC), RAX); // 7
1767 mov_m32rel_xreg32((unsigned int *)(&address), EBX); // 7
1768 mov_m16rel_xreg16((unsigned short *)(&hword), CX); // 8
1769 shr_reg32_imm8(EBX, 16); // 3
1770 mov_reg64_preg64x8preg64(RBX, RBX, RSI); // 4
1771 call_reg64(RBX); // 2
1772 mov_xreg32_m32rel(EAX, (unsigned int *)(&address)); // 7
1773 jmp_imm_short(26); // 2
1775 mov_reg64_imm64(RSI, (unsigned long long) rdram); // 10
1776 mov_reg32_reg32(EAX, EBX); // 2
1777 and_reg32_imm32(EBX, 0x7FFFFF); // 6
1778 xor_reg8_imm8(BL, 2); // 4
1779 mov_preg64preg64_reg16(RBX, RSI, CX); // 4
1781 mov_reg64_imm64(RSI, (unsigned long long) invalid_code);
1782 mov_reg32_reg32(EBX, EAX);
1783 shr_reg32_imm8(EBX, 12);
1784 cmp_preg64preg64_imm8(RBX, RSI, 0);
1787 mov_reg64_imm64(RDI, (unsigned long long) blocks); // 10
1788 mov_reg32_reg32(ECX, EBX); // 2
1789 mov_reg64_preg64x8preg64(RBX, RBX, RDI); // 4
1790 mov_reg64_preg64pimm32(RBX, RBX, (int) offsetof(precomp_block, block)); // 7
1791 mov_reg64_imm64(RDI, (unsigned long long) cached_interpreter_table.NOTCOMPILED); // 10
1792 and_eax_imm32(0xFFF); // 5
1793 shr_reg32_imm8(EAX, 2); // 3
1794 mov_reg32_imm32(EDX, sizeof(precomp_instr)); // 5
1795 mul_reg32(EDX); // 2
1796 mov_reg64_preg64preg64pimm32(RAX, RAX, RBX, (int) offsetof(precomp_instr, ops)); // 8
1797 cmp_reg64_reg64(RAX, RDI); // 3
1799 mov_preg64preg64_imm8(RCX, RSI, 1); // 4
1805 #if defined(COUNT_INSTR)
1806 inc_m32rel(&instr_count[35]);
1808 gencallinterp((unsigned long long)cached_interpreter_table.SWL, 0);
1813 #if defined(COUNT_INSTR)
1814 inc_m32rel(&instr_count[34]);
1817 gencallinterp((unsigned long long)cached_interpreter_table.SW, 0);
1819 free_registers_move_start();
1821 mov_xreg32_m32rel(ECX, (unsigned int *)dst->f.i.rt);
1822 mov_xreg32_m32rel(EAX, (unsigned int *)dst->f.i.rs);
1823 add_eax_imm32((int)dst->f.i.immediate);
1824 mov_reg32_reg32(EBX, EAX);
1825 mov_reg64_imm64(RSI, (unsigned long long) writemem);
1828 and_eax_imm32(0xDF800000);
1829 cmp_eax_imm32(0x80000000);
1833 mov_reg64_imm64(RDI, (unsigned long long) write_rdram);
1834 shr_reg32_imm8(EAX, 16);
1835 mov_reg64_preg64x8preg64(RAX, RAX, RSI);
1836 cmp_reg64_reg64(RAX, RDI);
1840 mov_reg64_imm64(RAX, (unsigned long long) (dst+1)); // 10
1841 mov_m64rel_xreg64((unsigned long long *)(&PC), RAX); // 7
1842 mov_m32rel_xreg32((unsigned int *)(&address), EBX); // 7
1843 mov_m32rel_xreg32((unsigned int *)(&word), ECX); // 7
1844 shr_reg32_imm8(EBX, 16); // 3
1845 mov_reg64_preg64x8preg64(RBX, RBX, RSI); // 4
1846 call_reg64(RBX); // 2
1847 mov_xreg32_m32rel(EAX, (unsigned int *)(&address)); // 7
1848 jmp_imm_short(21); // 2
1850 mov_reg64_imm64(RSI, (unsigned long long) rdram); // 10
1851 mov_reg32_reg32(EAX, EBX); // 2
1852 and_reg32_imm32(EBX, 0x7FFFFF); // 6
1853 mov_preg64preg64_reg32(RBX, RSI, ECX); // 3
1855 mov_reg64_imm64(RSI, (unsigned long long) invalid_code);
1856 mov_reg32_reg32(EBX, EAX);
1857 shr_reg32_imm8(EBX, 12);
1858 cmp_preg64preg64_imm8(RBX, RSI, 0);
1861 mov_reg64_imm64(RDI, (unsigned long long) blocks); // 10
1862 mov_reg32_reg32(ECX, EBX); // 2
1863 mov_reg64_preg64x8preg64(RBX, RBX, RDI); // 4
1864 mov_reg64_preg64pimm32(RBX, RBX, (int) offsetof(precomp_block, block)); // 7
1865 mov_reg64_imm64(RDI, (unsigned long long) cached_interpreter_table.NOTCOMPILED); // 10
1866 and_eax_imm32(0xFFF); // 5
1867 shr_reg32_imm8(EAX, 2); // 3
1868 mov_reg32_imm32(EDX, sizeof(precomp_instr)); // 5
1869 mul_reg32(EDX); // 2
1870 mov_reg64_preg64preg64pimm32(RAX, RAX, RBX, (int) offsetof(precomp_instr, ops)); // 8
1871 cmp_reg64_reg64(RAX, RDI); // 3
1873 mov_preg64preg64_imm8(RCX, RSI, 1); // 4
1879 #if defined(COUNT_INSTR)
1880 inc_m32rel(&instr_count[37]);
1882 gencallinterp((unsigned long long)cached_interpreter_table.SDL, 0);
1887 #if defined(COUNT_INSTR)
1888 inc_m32rel(&instr_count[38]);
1890 gencallinterp((unsigned long long)cached_interpreter_table.SDR, 0);
1895 #if defined(COUNT_INSTR)
1896 inc_m32rel(&instr_count[36]);
1898 gencallinterp((unsigned long long)cached_interpreter_table.SWR, 0);
1901 void gencheck_cop1_unusable(void)
1903 free_registers_move_start();
1905 test_m32rel_imm32((unsigned int*)&Status, 0x20000000);
1909 gencallinterp((unsigned long long)check_cop1_unusable, 0);
1916 #if defined(COUNT_INSTR)
1917 inc_m32rel(&instr_count[39]);
1919 #ifdef INTERPRET_LWC1
1920 gencallinterp((unsigned long long)cached_interpreter_table.LWC1, 0);
1922 gencheck_cop1_unusable();
1924 mov_xreg32_m32rel(EAX, (unsigned int *)(®[dst->f.lf.base]));
1925 add_eax_imm32((int)dst->f.lf.offset);
1926 mov_reg32_reg32(EBX, EAX);
1927 mov_reg64_imm64(RSI, (unsigned long long) readmem);
1930 and_eax_imm32(0xDF800000);
1931 cmp_eax_imm32(0x80000000);
1935 mov_reg64_imm64(RDI, (unsigned long long) read_rdram);
1936 shr_reg32_imm8(EAX, 16);
1937 mov_reg64_preg64x8preg64(RAX, RAX, RSI);
1938 cmp_reg64_reg64(RAX, RDI);
1942 mov_reg64_imm64(RAX, (unsigned long long) (dst+1)); // 10
1943 mov_m64rel_xreg64((unsigned long long *)(&PC), RAX); // 7
1944 mov_m32rel_xreg32((unsigned int *)(&address), EBX); // 7
1945 mov_xreg64_m64rel(RDX, (unsigned long long *)(®_cop1_simple[dst->f.lf.ft])); // 7
1946 mov_m64rel_xreg64((unsigned long long *)(&rdword), RDX); // 7
1947 shr_reg32_imm8(EBX, 16); // 3
1948 mov_reg64_preg64x8preg64(RBX, RBX, RSI); // 4
1949 call_reg64(RBX); // 2
1950 jmp_imm_short(28); // 2
1952 mov_reg64_imm64(RSI, (unsigned long long) rdram); // 10
1953 and_reg32_imm32(EBX, 0x7FFFFF); // 6
1954 mov_reg32_preg64preg64(EAX, RBX, RSI); // 3
1955 mov_xreg64_m64rel(RBX, (unsigned long long *)(®_cop1_simple[dst->f.lf.ft])); // 7
1956 mov_preg64_reg32(RBX, EAX); // 2
1962 #if defined(COUNT_INSTR)
1963 inc_m32rel(&instr_count[40]);
1965 #ifdef INTERPRET_LDC1
1966 gencallinterp((unsigned long long)cached_interpreter_table.LDC1, 0);
1968 gencheck_cop1_unusable();
1970 mov_xreg32_m32rel(EAX, (unsigned int *)(®[dst->f.lf.base]));
1971 add_eax_imm32((int)dst->f.lf.offset);
1972 mov_reg32_reg32(EBX, EAX);
1973 mov_reg64_imm64(RSI, (unsigned long long) readmemd);
1976 and_eax_imm32(0xDF800000);
1977 cmp_eax_imm32(0x80000000);
1981 mov_reg64_imm64(RDI, (unsigned long long) read_rdramd);
1982 shr_reg32_imm8(EAX, 16);
1983 mov_reg64_preg64x8preg64(RAX, RAX, RSI);
1984 cmp_reg64_reg64(RAX, RDI);
1988 mov_reg64_imm64(RAX, (unsigned long long) (dst+1)); // 10
1989 mov_m64rel_xreg64((unsigned long long *)(&PC), RAX); // 7
1990 mov_m32rel_xreg32((unsigned int *)(&address), EBX); // 7
1991 mov_xreg64_m64rel(RDX, (unsigned long long *)(®_cop1_double[dst->f.lf.ft])); // 7
1992 mov_m64rel_xreg64((unsigned long long *)(&rdword), RDX); // 7
1993 shr_reg32_imm8(EBX, 16); // 3
1994 mov_reg64_preg64x8preg64(RBX, RBX, RSI); // 4
1995 call_reg64(RBX); // 2
1996 jmp_imm_short(39); // 2
1998 mov_reg64_imm64(RSI, (unsigned long long) rdram); // 10
1999 and_reg32_imm32(EBX, 0x7FFFFF); // 6
2000 mov_reg64_preg64preg64(RAX, RBX, RSI); // 4
2001 mov_xreg64_m64rel(RBX, (unsigned long long *)(®_cop1_double[dst->f.lf.ft])); // 7
2002 mov_preg64pimm32_reg32(RBX, 4, EAX); // 6
2003 shr_reg64_imm8(RAX, 32); // 4
2004 mov_preg64_reg32(RBX, EAX); // 2
2014 #if defined(COUNT_INSTR)
2015 inc_m32rel(&instr_count[41]);
2018 gencallinterp((unsigned long long)cached_interpreter_table.LD, 0);
2020 free_registers_move_start();
2022 mov_xreg32_m32rel(EAX, (unsigned int *)dst->f.i.rs);
2023 add_eax_imm32((int)dst->f.i.immediate);
2024 mov_reg32_reg32(EBX, EAX);
2025 mov_reg64_imm64(RSI, (unsigned long long) readmemd);
2028 and_eax_imm32(0xDF800000);
2029 cmp_eax_imm32(0x80000000);
2033 mov_reg64_imm64(RDI, (unsigned long long) read_rdramd);
2034 shr_reg32_imm8(EAX, 16);
2035 mov_reg64_preg64x8preg64(RAX, RAX, RSI);
2036 cmp_reg64_reg64(RAX, RDI);
2040 mov_reg64_imm64(RAX, (unsigned long long) (dst+1)); // 10
2041 mov_m64rel_xreg64((unsigned long long *)(&PC), RAX); // 7
2042 mov_m32rel_xreg32((unsigned int *)(&address), EBX); // 7
2043 mov_reg64_imm64(RAX, (unsigned long long) dst->f.i.rt); // 10
2044 mov_m64rel_xreg64((unsigned long long *)(&rdword), RAX); // 7
2045 shr_reg32_imm8(EBX, 16); // 3
2046 mov_reg64_preg64x8preg64(RBX, RBX, RSI); // 4
2047 call_reg64(RBX); // 2
2048 mov_xreg64_m64rel(RAX, (unsigned long long *)(dst->f.i.rt)); // 7
2049 jmp_imm_short(33); // 2
2051 mov_reg64_imm64(RSI, (unsigned long long) rdram); // 10
2052 and_reg32_imm32(EBX, 0x7FFFFF); // 6
2054 mov_reg32_preg64preg64(EAX, RBX, RSI); // 3
2055 mov_reg32_preg64preg64pimm32(EBX, RBX, RSI, 4); // 7
2056 shl_reg64_imm8(RAX, 32); // 4
2057 or_reg64_reg64(RAX, RBX); // 3
2059 set_register_state(RAX, (unsigned int*)dst->f.i.rt, 1, 1);
2065 #if defined(COUNT_INSTR)
2066 inc_m32rel(&instr_count[43]);
2068 #ifdef INTERPRET_SWC1
2069 gencallinterp((unsigned long long)cached_interpreter_table.SWC1, 0);
2071 gencheck_cop1_unusable();
2073 mov_xreg64_m64rel(RDX, (unsigned long long *)(®_cop1_simple[dst->f.lf.ft]));
2074 mov_reg32_preg64(ECX, RDX);
2075 mov_xreg32_m32rel(EAX, (unsigned int *)(®[dst->f.lf.base]));
2076 add_eax_imm32((int)dst->f.lf.offset);
2077 mov_reg32_reg32(EBX, EAX);
2078 mov_reg64_imm64(RSI, (unsigned long long) writemem);
2081 and_eax_imm32(0xDF800000);
2082 cmp_eax_imm32(0x80000000);
2086 mov_reg64_imm64(RDI, (unsigned long long) write_rdram);
2087 shr_reg32_imm8(EAX, 16);
2088 mov_reg64_preg64x8preg64(RAX, RAX, RSI);
2089 cmp_reg64_reg64(RAX, RDI);
2093 mov_reg64_imm64(RAX, (unsigned long long) (dst+1)); // 10
2094 mov_m64rel_xreg64((unsigned long long *)(&PC), RAX); // 7
2095 mov_m32rel_xreg32((unsigned int *)(&address), EBX); // 7
2096 mov_m32rel_xreg32((unsigned int *)(&word), ECX); // 7
2097 shr_reg32_imm8(EBX, 16); // 3
2098 mov_reg64_preg64x8preg64(RBX, RBX, RSI); // 4
2099 call_reg64(RBX); // 2
2100 mov_xreg32_m32rel(EAX, (unsigned int *)(&address)); // 7
2101 jmp_imm_short(21); // 2
2103 mov_reg64_imm64(RSI, (unsigned long long) rdram); // 10
2104 mov_reg32_reg32(EAX, EBX); // 2
2105 and_reg32_imm32(EBX, 0x7FFFFF); // 6
2106 mov_preg64preg64_reg32(RBX, RSI, ECX); // 3
2108 mov_reg64_imm64(RSI, (unsigned long long) invalid_code);
2109 mov_reg32_reg32(EBX, EAX);
2110 shr_reg32_imm8(EBX, 12);
2111 cmp_preg64preg64_imm8(RBX, RSI, 0);
2114 mov_reg64_imm64(RDI, (unsigned long long) blocks); // 10
2115 mov_reg32_reg32(ECX, EBX); // 2
2116 mov_reg64_preg64x8preg64(RBX, RBX, RDI); // 4
2117 mov_reg64_preg64pimm32(RBX, RBX, (int) offsetof(precomp_block, block)); // 7
2118 mov_reg64_imm64(RDI, (unsigned long long) cached_interpreter_table.NOTCOMPILED); // 10
2119 and_eax_imm32(0xFFF); // 5
2120 shr_reg32_imm8(EAX, 2); // 3
2121 mov_reg32_imm32(EDX, sizeof(precomp_instr)); // 5
2122 mul_reg32(EDX); // 2
2123 mov_reg64_preg64preg64pimm32(RAX, RAX, RBX, (int) offsetof(precomp_instr, ops)); // 8
2124 cmp_reg64_reg64(RAX, RDI); // 3
2126 mov_preg64preg64_imm8(RCX, RSI, 1); // 4
2132 #if defined(COUNT_INSTR)
2133 inc_m32rel(&instr_count[44]);
2135 #ifdef INTERPRET_SDC1
2136 gencallinterp((unsigned long long)cached_interpreter_table.SDC1, 0);
2138 gencheck_cop1_unusable();
2140 mov_xreg64_m64rel(RSI, (unsigned long long *)(®_cop1_double[dst->f.lf.ft]));
2141 mov_reg32_preg64(ECX, RSI);
2142 mov_reg32_preg64pimm32(EDX, RSI, 4);
2143 mov_xreg32_m32rel(EAX, (unsigned int *)(®[dst->f.lf.base]));
2144 add_eax_imm32((int)dst->f.lf.offset);
2145 mov_reg32_reg32(EBX, EAX);
2146 mov_reg64_imm64(RSI, (unsigned long long) writememd);
2149 and_eax_imm32(0xDF800000);
2150 cmp_eax_imm32(0x80000000);
2154 mov_reg64_imm64(RDI, (unsigned long long) write_rdramd);
2155 shr_reg32_imm8(EAX, 16);
2156 mov_reg64_preg64x8preg64(RAX, RAX, RSI);
2157 cmp_reg64_reg64(RAX, RDI);
2161 mov_reg64_imm64(RAX, (unsigned long long) (dst+1)); // 10
2162 mov_m64rel_xreg64((unsigned long long *)(&PC), RAX); // 7
2163 mov_m32rel_xreg32((unsigned int *)(&address), EBX); // 7
2164 mov_m32rel_xreg32((unsigned int *)(&dword), ECX); // 7
2165 mov_m32rel_xreg32((unsigned int *)(&dword)+1, EDX); // 7
2166 shr_reg32_imm8(EBX, 16); // 3
2167 mov_reg64_preg64x8preg64(RBX, RBX, RSI); // 4
2168 call_reg64(RBX); // 2
2169 mov_xreg32_m32rel(EAX, (unsigned int *)(&address)); // 7
2170 jmp_imm_short(28); // 2
2172 mov_reg64_imm64(RSI, (unsigned long long) rdram); // 10
2173 mov_reg32_reg32(EAX, EBX); // 2
2174 and_reg32_imm32(EBX, 0x7FFFFF); // 6
2175 mov_preg64preg64pimm32_reg32(RBX, RSI, 4, ECX); // 7
2176 mov_preg64preg64_reg32(RBX, RSI, EDX); // 3
2178 mov_reg64_imm64(RSI, (unsigned long long) invalid_code);
2179 mov_reg32_reg32(EBX, EAX);
2180 shr_reg32_imm8(EBX, 12);
2181 cmp_preg64preg64_imm8(RBX, RSI, 0);
2184 mov_reg64_imm64(RDI, (unsigned long long) blocks); // 10
2185 mov_reg32_reg32(ECX, EBX); // 2
2186 mov_reg64_preg64x8preg64(RBX, RBX, RDI); // 4
2187 mov_reg64_preg64pimm32(RBX, RBX, (int) offsetof(precomp_block, block)); // 7
2188 mov_reg64_imm64(RDI, (unsigned long long) cached_interpreter_table.NOTCOMPILED); // 10
2189 and_eax_imm32(0xFFF); // 5
2190 shr_reg32_imm8(EAX, 2); // 3
2191 mov_reg32_imm32(EDX, sizeof(precomp_instr)); // 5
2192 mul_reg32(EDX); // 2
2193 mov_reg64_preg64preg64pimm32(RAX, RAX, RBX, (int) offsetof(precomp_instr, ops)); // 8
2194 cmp_reg64_reg64(RAX, RDI); // 3
2196 mov_preg64preg64_imm8(RCX, RSI, 1); // 4
2202 #if defined(COUNT_INSTR)
2203 inc_m32rel(&instr_count[45]);
2206 gencallinterp((unsigned long long)cached_interpreter_table.SD, 0);
2208 free_registers_move_start();
2210 mov_xreg32_m32rel(ECX, (unsigned int *)dst->f.i.rt);
2211 mov_xreg32_m32rel(EDX, ((unsigned int *)dst->f.i.rt)+1);
2212 mov_xreg32_m32rel(EAX, (unsigned int *)dst->f.i.rs);
2213 add_eax_imm32((int)dst->f.i.immediate);
2214 mov_reg32_reg32(EBX, EAX);
2215 mov_reg64_imm64(RSI, (unsigned long long) writememd);
2218 and_eax_imm32(0xDF800000);
2219 cmp_eax_imm32(0x80000000);
2223 mov_reg64_imm64(RDI, (unsigned long long) write_rdramd);
2224 shr_reg32_imm8(EAX, 16);
2225 mov_reg64_preg64x8preg64(RAX, RAX, RSI);
2226 cmp_reg64_reg64(RAX, RDI);
2230 mov_reg64_imm64(RAX, (unsigned long long) (dst+1)); // 10
2231 mov_m64rel_xreg64((unsigned long long *)(&PC), RAX); // 7
2232 mov_m32rel_xreg32((unsigned int *)(&address), EBX); // 7
2233 mov_m32rel_xreg32((unsigned int *)(&dword), ECX); // 7
2234 mov_m32rel_xreg32((unsigned int *)(&dword)+1, EDX); // 7
2235 shr_reg32_imm8(EBX, 16); // 3
2236 mov_reg64_preg64x8preg64(RBX, RBX, RSI); // 4
2237 call_reg64(RBX); // 2
2238 mov_xreg32_m32rel(EAX, (unsigned int *)(&address)); // 7
2239 jmp_imm_short(28); // 2
2241 mov_reg64_imm64(RSI, (unsigned long long) rdram); // 10
2242 mov_reg32_reg32(EAX, EBX); // 2
2243 and_reg32_imm32(EBX, 0x7FFFFF); // 6
2244 mov_preg64preg64pimm32_reg32(RBX, RSI, 4, ECX); // 7
2245 mov_preg64preg64_reg32(RBX, RSI, EDX); // 3
2247 mov_reg64_imm64(RSI, (unsigned long long) invalid_code);
2248 mov_reg32_reg32(EBX, EAX);
2249 shr_reg32_imm8(EBX, 12);
2250 cmp_preg64preg64_imm8(RBX, RSI, 0);
2253 mov_reg64_imm64(RDI, (unsigned long long) blocks); // 10
2254 mov_reg32_reg32(ECX, EBX); // 2
2255 mov_reg64_preg64x8preg64(RBX, RBX, RDI); // 4
2256 mov_reg64_preg64pimm32(RBX, RBX, (int) offsetof(precomp_block, block)); // 7
2257 mov_reg64_imm64(RDI, (unsigned long long) cached_interpreter_table.NOTCOMPILED); // 10
2258 and_eax_imm32(0xFFF); // 5
2259 shr_reg32_imm8(EAX, 2); // 3
2260 mov_reg32_imm32(EDX, sizeof(precomp_instr)); // 5
2261 mul_reg32(EDX); // 2
2262 mov_reg64_preg64preg64pimm32(RAX, RAX, RBX, (int) offsetof(precomp_instr, ops)); // 8
2263 cmp_reg64_reg64(RAX, RDI); // 3
2265 mov_preg64preg64_imm8(RCX, RSI, 1); // 4
2271 #if defined(COUNT_INSTR)
2272 inc_m32rel(&instr_count[42]);
2274 gencallinterp((unsigned long long)cached_interpreter_table.LL, 0);
2279 #if defined(COUNT_INSTR)
2280 inc_m32rel(&instr_count[46]);
2282 gencallinterp((unsigned long long)cached_interpreter_table.SC, 0);