1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus/PCSX - assem_arm.c *
3 * Copyright (C) 2009-2011 Ari64 *
4 * Copyright (C) 2010-2011 GraÅžvydas "notaz" Ignotas *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
20 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include "../../gte.h"
24 #include "../../gte.h"
26 #include "../../gte_arm.h"
27 #include "../../gte_neon.h"
29 #include "arm_features.h"
31 #if defined(BASE_ADDR_FIXED)
32 #elif defined(BASE_ADDR_DYNAMIC)
33 char *translation_cache;
35 char translation_cache[1 << TARGET_SIZE_2] __attribute__((aligned(4096)));
39 #define CALLER_SAVE_REGS 0x100f
41 #define CALLER_SAVE_REGS 0x120f
44 #define unused __attribute__((unused))
46 extern int cycle_count;
47 extern int last_count;
49 extern int pending_exception;
50 extern int branch_target;
51 extern uint64_t readmem_dword;
52 extern void *dynarec_local;
53 extern u_int mini_ht[32][2];
55 void indirect_jump_indexed();
68 void jump_vaddr_r10();
69 void jump_vaddr_r12();
71 const u_int jump_vaddr_reg[16] = {
89 void invalidate_addr_r0();
90 void invalidate_addr_r1();
91 void invalidate_addr_r2();
92 void invalidate_addr_r3();
93 void invalidate_addr_r4();
94 void invalidate_addr_r5();
95 void invalidate_addr_r6();
96 void invalidate_addr_r7();
97 void invalidate_addr_r8();
98 void invalidate_addr_r9();
99 void invalidate_addr_r10();
100 void invalidate_addr_r12();
102 const u_int invalidate_addr_reg[16] = {
103 (int)invalidate_addr_r0,
104 (int)invalidate_addr_r1,
105 (int)invalidate_addr_r2,
106 (int)invalidate_addr_r3,
107 (int)invalidate_addr_r4,
108 (int)invalidate_addr_r5,
109 (int)invalidate_addr_r6,
110 (int)invalidate_addr_r7,
111 (int)invalidate_addr_r8,
112 (int)invalidate_addr_r9,
113 (int)invalidate_addr_r10,
115 (int)invalidate_addr_r12,
120 static u_int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
124 static void set_jump_target(int addr,u_int target)
126 u_char *ptr=(u_char *)addr;
127 u_int *ptr2=(u_int *)ptr;
129 assert((target-(u_int)ptr2-8)<1024);
131 assert((target&3)==0);
132 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>2)|0xF00;
133 //printf("target=%x addr=%x insn=%x\n",target,addr,*ptr2);
135 else if(ptr[3]==0x72) {
136 // generated by emit_jno_unlikely
137 if((target-(u_int)ptr2-8)<1024) {
139 assert((target&3)==0);
140 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>2)|0xF00;
142 else if((target-(u_int)ptr2-8)<4096&&!((target-(u_int)ptr2-8)&15)) {
144 assert((target&3)==0);
145 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>4)|0xE00;
147 else *ptr2=(0x7A000000)|(((target-(u_int)ptr2-8)<<6)>>8);
150 assert((ptr[3]&0x0e)==0xa);
151 *ptr2=(*ptr2&0xFF000000)|(((target-(u_int)ptr2-8)<<6)>>8);
155 // This optionally copies the instruction from the target of the branch into
156 // the space before the branch. Works, but the difference in speed is
157 // usually insignificant.
159 static void set_jump_target_fillslot(int addr,u_int target,int copy)
161 u_char *ptr=(u_char *)addr;
162 u_int *ptr2=(u_int *)ptr;
163 assert(!copy||ptr2[-1]==0xe28dd000);
166 assert((target-(u_int)ptr2-8)<4096);
167 *ptr2=(*ptr2&0xFFFFF000)|(target-(u_int)ptr2-8);
170 assert((ptr[3]&0x0e)==0xa);
171 u_int target_insn=*(u_int *)target;
172 if((target_insn&0x0e100000)==0) { // ALU, no immediate, no flags
175 if((target_insn&0x0c100000)==0x04100000) { // Load
178 if(target_insn&0x08000000) {
182 ptr2[-1]=target_insn;
185 *ptr2=(*ptr2&0xFF000000)|(((target-(u_int)ptr2-8)<<6)>>8);
191 static void add_literal(int addr,int val)
193 assert(literalcount<sizeof(literals)/sizeof(literals[0]));
194 literals[literalcount][0]=addr;
195 literals[literalcount][1]=val;
199 // from a pointer to external jump stub (which was produced by emit_extjump2)
200 // find where the jumping insn is
201 static void *find_extjump_insn(void *stub)
203 int *ptr=(int *)(stub+4);
204 assert((*ptr&0x0fff0000)==0x059f0000); // ldr rx, [pc, #ofs]
205 u_int offset=*ptr&0xfff;
206 void **l_ptr=(void *)ptr+offset+8;
210 // find where external branch is liked to using addr of it's stub:
211 // get address that insn one after stub loads (dyna_linker arg1),
212 // treat it as a pointer to branch insn,
213 // return addr where that branch jumps to
214 static int get_pointer(void *stub)
216 //printf("get_pointer(%x)\n",(int)stub);
217 int *i_ptr=find_extjump_insn(stub);
218 assert((*i_ptr&0x0f000000)==0x0a000000);
219 return (int)i_ptr+((*i_ptr<<8)>>6)+8;
222 // Find the "clean" entry point from a "dirty" entry point
223 // by skipping past the call to verify_code
224 static u_int get_clean_addr(int addr)
226 int *ptr=(int *)addr;
232 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
233 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
235 if((*ptr&0xFF000000)==0xea000000) {
236 return (int)ptr+((*ptr<<8)>>6)+8; // follow jump
241 static int verify_dirty(u_int *ptr)
244 // get from literal pool
245 assert((*ptr&0xFFFF0000)==0xe59f0000);
246 u_int offset=*ptr&0xfff;
247 u_int *l_ptr=(void *)ptr+offset+8;
248 u_int source=l_ptr[0];
254 assert((*ptr&0xFFF00000)==0xe3000000);
255 u_int source=(ptr[0]&0xFFF)+((ptr[0]>>4)&0xF000)+((ptr[2]<<16)&0xFFF0000)+((ptr[2]<<12)&0xF0000000);
256 u_int copy=(ptr[1]&0xFFF)+((ptr[1]>>4)&0xF000)+((ptr[3]<<16)&0xFFF0000)+((ptr[3]<<12)&0xF0000000);
257 u_int len=(ptr[4]&0xFFF)+((ptr[4]>>4)&0xF000);
260 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
261 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
262 //printf("verify_dirty: %x %x %x\n",source,copy,len);
263 return !memcmp((void *)source,(void *)copy,len);
266 // This doesn't necessarily find all clean entry points, just
267 // guarantees that it's not dirty
268 static int isclean(int addr)
271 u_int *ptr=((u_int *)addr)+4;
273 u_int *ptr=((u_int *)addr)+6;
275 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
276 if((*ptr&0xFF000000)!=0xeb000000) return 1; // bl instruction
277 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code) return 0;
278 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code_vm) return 0;
279 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code_ds) return 0;
283 // get source that block at addr was compiled from (host pointers)
284 static void get_bounds(int addr,u_int *start,u_int *end)
286 u_int *ptr=(u_int *)addr;
288 // get from literal pool
289 assert((*ptr&0xFFFF0000)==0xe59f0000);
290 u_int offset=*ptr&0xfff;
291 u_int *l_ptr=(void *)ptr+offset+8;
292 u_int source=l_ptr[0];
293 //u_int copy=l_ptr[1];
298 assert((*ptr&0xFFF00000)==0xe3000000);
299 u_int source=(ptr[0]&0xFFF)+((ptr[0]>>4)&0xF000)+((ptr[2]<<16)&0xFFF0000)+((ptr[2]<<12)&0xF0000000);
300 //u_int copy=(ptr[1]&0xFFF)+((ptr[1]>>4)&0xF000)+((ptr[3]<<16)&0xFFF0000)+((ptr[3]<<12)&0xF0000000);
301 u_int len=(ptr[4]&0xFFF)+((ptr[4]>>4)&0xF000);
304 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
305 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
310 /* Register allocation */
312 // Note: registers are allocated clean (unmodified state)
313 // if you intend to modify the register, you must call dirty_reg().
314 static void alloc_reg(struct regstat *cur,int i,signed char reg)
317 int preferred_reg = (reg&7);
318 if(reg==CCREG) preferred_reg=HOST_CCREG;
319 if(reg==PTEMP||reg==FTEMP) preferred_reg=12;
321 // Don't allocate unused registers
322 if((cur->u>>reg)&1) return;
324 // see if it's already allocated
325 for(hr=0;hr<HOST_REGS;hr++)
327 if(cur->regmap[hr]==reg) return;
330 // Keep the same mapping if the register was already allocated in a loop
331 preferred_reg = loop_reg(i,reg,preferred_reg);
333 // Try to allocate the preferred register
334 if(cur->regmap[preferred_reg]==-1) {
335 cur->regmap[preferred_reg]=reg;
336 cur->dirty&=~(1<<preferred_reg);
337 cur->isconst&=~(1<<preferred_reg);
340 r=cur->regmap[preferred_reg];
341 if(r<64&&((cur->u>>r)&1)) {
342 cur->regmap[preferred_reg]=reg;
343 cur->dirty&=~(1<<preferred_reg);
344 cur->isconst&=~(1<<preferred_reg);
347 if(r>=64&&((cur->uu>>(r&63))&1)) {
348 cur->regmap[preferred_reg]=reg;
349 cur->dirty&=~(1<<preferred_reg);
350 cur->isconst&=~(1<<preferred_reg);
354 // Clear any unneeded registers
355 // We try to keep the mapping consistent, if possible, because it
356 // makes branches easier (especially loops). So we try to allocate
357 // first (see above) before removing old mappings. If this is not
358 // possible then go ahead and clear out the registers that are no
360 for(hr=0;hr<HOST_REGS;hr++)
365 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
369 if((cur->uu>>(r&63))&1) {cur->regmap[hr]=-1;break;}
373 // Try to allocate any available register, but prefer
374 // registers that have not been used recently.
376 for(hr=0;hr<HOST_REGS;hr++) {
377 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
378 if(regs[i-1].regmap[hr]!=rs1[i-1]&®s[i-1].regmap[hr]!=rs2[i-1]&®s[i-1].regmap[hr]!=rt1[i-1]&®s[i-1].regmap[hr]!=rt2[i-1]) {
380 cur->dirty&=~(1<<hr);
381 cur->isconst&=~(1<<hr);
387 // Try to allocate any available register
388 for(hr=0;hr<HOST_REGS;hr++) {
389 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
391 cur->dirty&=~(1<<hr);
392 cur->isconst&=~(1<<hr);
397 // Ok, now we have to evict someone
398 // Pick a register we hopefully won't need soon
399 u_char hsn[MAXREG+1];
400 memset(hsn,10,sizeof(hsn));
402 lsn(hsn,i,&preferred_reg);
403 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
404 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
406 // Don't evict the cycle count at entry points, otherwise the entry
407 // stub will have to write it.
408 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
409 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
412 // Alloc preferred register if available
413 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
414 for(hr=0;hr<HOST_REGS;hr++) {
415 // Evict both parts of a 64-bit register
416 if((cur->regmap[hr]&63)==r) {
418 cur->dirty&=~(1<<hr);
419 cur->isconst&=~(1<<hr);
422 cur->regmap[preferred_reg]=reg;
425 for(r=1;r<=MAXREG;r++)
427 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
428 for(hr=0;hr<HOST_REGS;hr++) {
429 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
430 if(cur->regmap[hr]==r+64) {
432 cur->dirty&=~(1<<hr);
433 cur->isconst&=~(1<<hr);
438 for(hr=0;hr<HOST_REGS;hr++) {
439 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
440 if(cur->regmap[hr]==r) {
442 cur->dirty&=~(1<<hr);
443 cur->isconst&=~(1<<hr);
454 for(r=1;r<=MAXREG;r++)
457 for(hr=0;hr<HOST_REGS;hr++) {
458 if(cur->regmap[hr]==r+64) {
460 cur->dirty&=~(1<<hr);
461 cur->isconst&=~(1<<hr);
465 for(hr=0;hr<HOST_REGS;hr++) {
466 if(cur->regmap[hr]==r) {
468 cur->dirty&=~(1<<hr);
469 cur->isconst&=~(1<<hr);
476 SysPrintf("This shouldn't happen (alloc_reg)");exit(1);
479 static void alloc_reg64(struct regstat *cur,int i,signed char reg)
481 int preferred_reg = 8+(reg&1);
484 // allocate the lower 32 bits
485 alloc_reg(cur,i,reg);
487 // Don't allocate unused registers
488 if((cur->uu>>reg)&1) return;
490 // see if the upper half is already allocated
491 for(hr=0;hr<HOST_REGS;hr++)
493 if(cur->regmap[hr]==reg+64) return;
496 // Keep the same mapping if the register was already allocated in a loop
497 preferred_reg = loop_reg(i,reg,preferred_reg);
499 // Try to allocate the preferred register
500 if(cur->regmap[preferred_reg]==-1) {
501 cur->regmap[preferred_reg]=reg|64;
502 cur->dirty&=~(1<<preferred_reg);
503 cur->isconst&=~(1<<preferred_reg);
506 r=cur->regmap[preferred_reg];
507 if(r<64&&((cur->u>>r)&1)) {
508 cur->regmap[preferred_reg]=reg|64;
509 cur->dirty&=~(1<<preferred_reg);
510 cur->isconst&=~(1<<preferred_reg);
513 if(r>=64&&((cur->uu>>(r&63))&1)) {
514 cur->regmap[preferred_reg]=reg|64;
515 cur->dirty&=~(1<<preferred_reg);
516 cur->isconst&=~(1<<preferred_reg);
520 // Clear any unneeded registers
521 // We try to keep the mapping consistent, if possible, because it
522 // makes branches easier (especially loops). So we try to allocate
523 // first (see above) before removing old mappings. If this is not
524 // possible then go ahead and clear out the registers that are no
526 for(hr=HOST_REGS-1;hr>=0;hr--)
531 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
535 if((cur->uu>>(r&63))&1) {cur->regmap[hr]=-1;break;}
539 // Try to allocate any available register, but prefer
540 // registers that have not been used recently.
542 for(hr=0;hr<HOST_REGS;hr++) {
543 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
544 if(regs[i-1].regmap[hr]!=rs1[i-1]&®s[i-1].regmap[hr]!=rs2[i-1]&®s[i-1].regmap[hr]!=rt1[i-1]&®s[i-1].regmap[hr]!=rt2[i-1]) {
545 cur->regmap[hr]=reg|64;
546 cur->dirty&=~(1<<hr);
547 cur->isconst&=~(1<<hr);
553 // Try to allocate any available register
554 for(hr=0;hr<HOST_REGS;hr++) {
555 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
556 cur->regmap[hr]=reg|64;
557 cur->dirty&=~(1<<hr);
558 cur->isconst&=~(1<<hr);
563 // Ok, now we have to evict someone
564 // Pick a register we hopefully won't need soon
565 u_char hsn[MAXREG+1];
566 memset(hsn,10,sizeof(hsn));
568 lsn(hsn,i,&preferred_reg);
569 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
570 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
572 // Don't evict the cycle count at entry points, otherwise the entry
573 // stub will have to write it.
574 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
575 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
578 // Alloc preferred register if available
579 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
580 for(hr=0;hr<HOST_REGS;hr++) {
581 // Evict both parts of a 64-bit register
582 if((cur->regmap[hr]&63)==r) {
584 cur->dirty&=~(1<<hr);
585 cur->isconst&=~(1<<hr);
588 cur->regmap[preferred_reg]=reg|64;
591 for(r=1;r<=MAXREG;r++)
593 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
594 for(hr=0;hr<HOST_REGS;hr++) {
595 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
596 if(cur->regmap[hr]==r+64) {
597 cur->regmap[hr]=reg|64;
598 cur->dirty&=~(1<<hr);
599 cur->isconst&=~(1<<hr);
604 for(hr=0;hr<HOST_REGS;hr++) {
605 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
606 if(cur->regmap[hr]==r) {
607 cur->regmap[hr]=reg|64;
608 cur->dirty&=~(1<<hr);
609 cur->isconst&=~(1<<hr);
620 for(r=1;r<=MAXREG;r++)
623 for(hr=0;hr<HOST_REGS;hr++) {
624 if(cur->regmap[hr]==r+64) {
625 cur->regmap[hr]=reg|64;
626 cur->dirty&=~(1<<hr);
627 cur->isconst&=~(1<<hr);
631 for(hr=0;hr<HOST_REGS;hr++) {
632 if(cur->regmap[hr]==r) {
633 cur->regmap[hr]=reg|64;
634 cur->dirty&=~(1<<hr);
635 cur->isconst&=~(1<<hr);
642 SysPrintf("This shouldn't happen");exit(1);
645 // Allocate a temporary register. This is done without regard to
646 // dirty status or whether the register we request is on the unneeded list
647 // Note: This will only allocate one register, even if called multiple times
648 static void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
651 int preferred_reg = -1;
653 // see if it's already allocated
654 for(hr=0;hr<HOST_REGS;hr++)
656 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
659 // Try to allocate any available register
660 for(hr=HOST_REGS-1;hr>=0;hr--) {
661 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
663 cur->dirty&=~(1<<hr);
664 cur->isconst&=~(1<<hr);
669 // Find an unneeded register
670 for(hr=HOST_REGS-1;hr>=0;hr--)
676 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
678 cur->dirty&=~(1<<hr);
679 cur->isconst&=~(1<<hr);
686 if((cur->uu>>(r&63))&1) {
687 if(i==0||((unneeded_reg_upper[i-1]>>(r&63))&1)) {
689 cur->dirty&=~(1<<hr);
690 cur->isconst&=~(1<<hr);
698 // Ok, now we have to evict someone
699 // Pick a register we hopefully won't need soon
700 // TODO: we might want to follow unconditional jumps here
701 // TODO: get rid of dupe code and make this into a function
702 u_char hsn[MAXREG+1];
703 memset(hsn,10,sizeof(hsn));
705 lsn(hsn,i,&preferred_reg);
706 //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
708 // Don't evict the cycle count at entry points, otherwise the entry
709 // stub will have to write it.
710 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
711 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
714 for(r=1;r<=MAXREG;r++)
716 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
717 for(hr=0;hr<HOST_REGS;hr++) {
718 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
719 if(cur->regmap[hr]==r+64) {
721 cur->dirty&=~(1<<hr);
722 cur->isconst&=~(1<<hr);
727 for(hr=0;hr<HOST_REGS;hr++) {
728 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
729 if(cur->regmap[hr]==r) {
731 cur->dirty&=~(1<<hr);
732 cur->isconst&=~(1<<hr);
743 for(r=1;r<=MAXREG;r++)
746 for(hr=0;hr<HOST_REGS;hr++) {
747 if(cur->regmap[hr]==r+64) {
749 cur->dirty&=~(1<<hr);
750 cur->isconst&=~(1<<hr);
754 for(hr=0;hr<HOST_REGS;hr++) {
755 if(cur->regmap[hr]==r) {
757 cur->dirty&=~(1<<hr);
758 cur->isconst&=~(1<<hr);
765 SysPrintf("This shouldn't happen");exit(1);
768 // Allocate a specific ARM register.
769 static void alloc_arm_reg(struct regstat *cur,int i,signed char reg,int hr)
774 // see if it's already allocated (and dealloc it)
775 for(n=0;n<HOST_REGS;n++)
777 if(n!=EXCLUDE_REG&&cur->regmap[n]==reg) {
778 dirty=(cur->dirty>>n)&1;
784 cur->dirty&=~(1<<hr);
785 cur->dirty|=dirty<<hr;
786 cur->isconst&=~(1<<hr);
789 // Alloc cycle count into dedicated register
790 static void alloc_cc(struct regstat *cur,int i)
792 alloc_arm_reg(cur,i,CCREG,HOST_CCREG);
800 static unused char regname[16][4] = {
818 static void output_w32(u_int word)
820 *((u_int *)out)=word;
824 static u_int rd_rn_rm(u_int rd, u_int rn, u_int rm)
829 return((rn<<16)|(rd<<12)|rm);
832 static u_int rd_rn_imm_shift(u_int rd, u_int rn, u_int imm, u_int shift)
837 assert((shift&1)==0);
838 return((rn<<16)|(rd<<12)|(((32-shift)&30)<<7)|imm);
841 static u_int genimm(u_int imm,u_int *encoded)
849 *encoded=((i&30)<<7)|imm;
852 imm=(imm>>2)|(imm<<30);i-=2;
857 static void genimm_checked(u_int imm,u_int *encoded)
859 u_int ret=genimm(imm,encoded);
864 static u_int genjmp(u_int addr)
866 int offset=addr-(int)out-8;
867 if(offset<-33554432||offset>=33554432) {
869 SysPrintf("genjmp: out of range: %08x\n", offset);
874 return ((u_int)offset>>2)&0xffffff;
877 static void emit_mov(int rs,int rt)
879 assem_debug("mov %s,%s\n",regname[rt],regname[rs]);
880 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs));
883 static void emit_movs(int rs,int rt)
885 assem_debug("movs %s,%s\n",regname[rt],regname[rs]);
886 output_w32(0xe1b00000|rd_rn_rm(rt,0,rs));
889 static void emit_add(int rs1,int rs2,int rt)
891 assem_debug("add %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
892 output_w32(0xe0800000|rd_rn_rm(rt,rs1,rs2));
895 static void emit_adds(int rs1,int rs2,int rt)
897 assem_debug("adds %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
898 output_w32(0xe0900000|rd_rn_rm(rt,rs1,rs2));
901 static void emit_adcs(int rs1,int rs2,int rt)
903 assem_debug("adcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
904 output_w32(0xe0b00000|rd_rn_rm(rt,rs1,rs2));
907 static void emit_sbc(int rs1,int rs2,int rt)
909 assem_debug("sbc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
910 output_w32(0xe0c00000|rd_rn_rm(rt,rs1,rs2));
913 static void emit_sbcs(int rs1,int rs2,int rt)
915 assem_debug("sbcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
916 output_w32(0xe0d00000|rd_rn_rm(rt,rs1,rs2));
919 static void emit_neg(int rs, int rt)
921 assem_debug("rsb %s,%s,#0\n",regname[rt],regname[rs]);
922 output_w32(0xe2600000|rd_rn_rm(rt,rs,0));
925 static void emit_negs(int rs, int rt)
927 assem_debug("rsbs %s,%s,#0\n",regname[rt],regname[rs]);
928 output_w32(0xe2700000|rd_rn_rm(rt,rs,0));
931 static void emit_sub(int rs1,int rs2,int rt)
933 assem_debug("sub %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
934 output_w32(0xe0400000|rd_rn_rm(rt,rs1,rs2));
937 static void emit_subs(int rs1,int rs2,int rt)
939 assem_debug("subs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
940 output_w32(0xe0500000|rd_rn_rm(rt,rs1,rs2));
943 static void emit_zeroreg(int rt)
945 assem_debug("mov %s,#0\n",regname[rt]);
946 output_w32(0xe3a00000|rd_rn_rm(rt,0,0));
949 static void emit_loadlp(u_int imm,u_int rt)
951 add_literal((int)out,imm);
952 assem_debug("ldr %s,pc+? [=%x]\n",regname[rt],imm);
953 output_w32(0xe5900000|rd_rn_rm(rt,15,0));
956 static void emit_movw(u_int imm,u_int rt)
959 assem_debug("movw %s,#%d (0x%x)\n",regname[rt],imm,imm);
960 output_w32(0xe3000000|rd_rn_rm(rt,0,0)|(imm&0xfff)|((imm<<4)&0xf0000));
963 static void emit_movt(u_int imm,u_int rt)
965 assem_debug("movt %s,#%d (0x%x)\n",regname[rt],imm&0xffff0000,imm&0xffff0000);
966 output_w32(0xe3400000|rd_rn_rm(rt,0,0)|((imm>>16)&0xfff)|((imm>>12)&0xf0000));
969 static void emit_movimm(u_int imm,u_int rt)
972 if(genimm(imm,&armval)) {
973 assem_debug("mov %s,#%d\n",regname[rt],imm);
974 output_w32(0xe3a00000|rd_rn_rm(rt,0,0)|armval);
975 }else if(genimm(~imm,&armval)) {
976 assem_debug("mvn %s,#%d\n",regname[rt],imm);
977 output_w32(0xe3e00000|rd_rn_rm(rt,0,0)|armval);
978 }else if(imm<65536) {
980 assem_debug("mov %s,#%d\n",regname[rt],imm&0xFF00);
981 output_w32(0xe3a00000|rd_rn_imm_shift(rt,0,imm>>8,8));
982 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
983 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
991 emit_movw(imm&0x0000FFFF,rt);
992 emit_movt(imm&0xFFFF0000,rt);
997 static void emit_pcreladdr(u_int rt)
999 assem_debug("add %s,pc,#?\n",regname[rt]);
1000 output_w32(0xe2800000|rd_rn_rm(rt,15,0));
1003 static void emit_loadreg(int r, int hr)
1006 SysPrintf("64bit load in 32bit mode!\n");
1013 int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
1014 if((r&63)==HIREG) addr=(int)&hi+((r&64)>>4);
1015 if((r&63)==LOREG) addr=(int)&lo+((r&64)>>4);
1016 if(r==CCREG) addr=(int)&cycle_count;
1017 if(r==CSREG) addr=(int)&Status;
1018 if(r==FSREG) addr=(int)&FCR31;
1019 if(r==INVCP) addr=(int)&invc_ptr;
1020 u_int offset = addr-(u_int)&dynarec_local;
1021 assert(offset<4096);
1022 assem_debug("ldr %s,fp+%d\n",regname[hr],offset);
1023 output_w32(0xe5900000|rd_rn_rm(hr,FP,0)|offset);
1027 static void emit_storereg(int r, int hr)
1030 SysPrintf("64bit store in 32bit mode!\n");
1034 int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
1035 if((r&63)==HIREG) addr=(int)&hi+((r&64)>>4);
1036 if((r&63)==LOREG) addr=(int)&lo+((r&64)>>4);
1037 if(r==CCREG) addr=(int)&cycle_count;
1038 if(r==FSREG) addr=(int)&FCR31;
1039 u_int offset = addr-(u_int)&dynarec_local;
1040 assert(offset<4096);
1041 assem_debug("str %s,fp+%d\n",regname[hr],offset);
1042 output_w32(0xe5800000|rd_rn_rm(hr,FP,0)|offset);
1045 static void emit_test(int rs, int rt)
1047 assem_debug("tst %s,%s\n",regname[rs],regname[rt]);
1048 output_w32(0xe1100000|rd_rn_rm(0,rs,rt));
1051 static void emit_testimm(int rs,int imm)
1054 assem_debug("tst %s,#%d\n",regname[rs],imm);
1055 genimm_checked(imm,&armval);
1056 output_w32(0xe3100000|rd_rn_rm(0,rs,0)|armval);
1059 static void emit_testeqimm(int rs,int imm)
1062 assem_debug("tsteq %s,$%d\n",regname[rs],imm);
1063 genimm_checked(imm,&armval);
1064 output_w32(0x03100000|rd_rn_rm(0,rs,0)|armval);
1067 static void emit_not(int rs,int rt)
1069 assem_debug("mvn %s,%s\n",regname[rt],regname[rs]);
1070 output_w32(0xe1e00000|rd_rn_rm(rt,0,rs));
1073 static void emit_mvnmi(int rs,int rt)
1075 assem_debug("mvnmi %s,%s\n",regname[rt],regname[rs]);
1076 output_w32(0x41e00000|rd_rn_rm(rt,0,rs));
1079 static void emit_and(u_int rs1,u_int rs2,u_int rt)
1081 assem_debug("and %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1082 output_w32(0xe0000000|rd_rn_rm(rt,rs1,rs2));
1085 static void emit_or(u_int rs1,u_int rs2,u_int rt)
1087 assem_debug("orr %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1088 output_w32(0xe1800000|rd_rn_rm(rt,rs1,rs2));
1091 static void emit_or_and_set_flags(int rs1,int rs2,int rt)
1093 assem_debug("orrs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1094 output_w32(0xe1900000|rd_rn_rm(rt,rs1,rs2));
1097 static void emit_orrshl_imm(u_int rs,u_int imm,u_int rt)
1102 assem_debug("orr %s,%s,%s,lsl #%d\n",regname[rt],regname[rt],regname[rs],imm);
1103 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|(imm<<7));
1106 static void emit_orrshr_imm(u_int rs,u_int imm,u_int rt)
1111 assem_debug("orr %s,%s,%s,lsr #%d\n",regname[rt],regname[rt],regname[rs],imm);
1112 output_w32(0xe1800020|rd_rn_rm(rt,rt,rs)|(imm<<7));
1115 static void emit_xor(u_int rs1,u_int rs2,u_int rt)
1117 assem_debug("eor %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1118 output_w32(0xe0200000|rd_rn_rm(rt,rs1,rs2));
1121 static void emit_addimm(u_int rs,int imm,u_int rt)
1127 if(genimm(imm,&armval)) {
1128 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rs],imm);
1129 output_w32(0xe2800000|rd_rn_rm(rt,rs,0)|armval);
1130 }else if(genimm(-imm,&armval)) {
1131 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],-imm);
1132 output_w32(0xe2400000|rd_rn_rm(rt,rs,0)|armval);
1134 }else if(rt!=rs&&(u_int)imm<65536) {
1135 emit_movw(imm&0x0000ffff,rt);
1137 }else if(rt!=rs&&(u_int)-imm<65536) {
1138 emit_movw(-imm&0x0000ffff,rt);
1141 }else if((u_int)-imm<65536) {
1142 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],(-imm)&0xFF00);
1143 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF);
1144 output_w32(0xe2400000|rd_rn_imm_shift(rt,rs,(-imm)>>8,8));
1145 output_w32(0xe2400000|rd_rn_imm_shift(rt,rt,(-imm)&0xff,0));
1148 int shift = (ffs(imm) - 1) & ~1;
1149 int imm8 = imm & (0xff << shift);
1150 genimm_checked(imm8,&armval);
1151 assem_debug("add %s,%s,#0x%x\n",regname[rt],regname[rs],imm8);
1152 output_w32(0xe2800000|rd_rn_rm(rt,rs,0)|armval);
1159 else if(rs!=rt) emit_mov(rs,rt);
1162 static void emit_addimm_and_set_flags(int imm,int rt)
1164 assert(imm>-65536&&imm<65536);
1166 if(genimm(imm,&armval)) {
1167 assem_debug("adds %s,%s,#%d\n",regname[rt],regname[rt],imm);
1168 output_w32(0xe2900000|rd_rn_rm(rt,rt,0)|armval);
1169 }else if(genimm(-imm,&armval)) {
1170 assem_debug("subs %s,%s,#%d\n",regname[rt],regname[rt],imm);
1171 output_w32(0xe2500000|rd_rn_rm(rt,rt,0)|armval);
1173 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF00);
1174 assem_debug("subs %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF);
1175 output_w32(0xe2400000|rd_rn_imm_shift(rt,rt,(-imm)>>8,8));
1176 output_w32(0xe2500000|rd_rn_imm_shift(rt,rt,(-imm)&0xff,0));
1178 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF00);
1179 assem_debug("adds %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
1180 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm>>8,8));
1181 output_w32(0xe2900000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1185 static void emit_addimm_no_flags(u_int imm,u_int rt)
1187 emit_addimm(rt,imm,rt);
1190 static void emit_addnop(u_int r)
1193 assem_debug("add %s,%s,#0 (nop)\n",regname[r],regname[r]);
1194 output_w32(0xe2800000|rd_rn_rm(r,r,0));
1197 static void emit_adcimm(u_int rs,int imm,u_int rt)
1200 genimm_checked(imm,&armval);
1201 assem_debug("adc %s,%s,#%d\n",regname[rt],regname[rs],imm);
1202 output_w32(0xe2a00000|rd_rn_rm(rt,rs,0)|armval);
1205 static void emit_rscimm(int rs,int imm,u_int rt)
1209 genimm_checked(imm,&armval);
1210 assem_debug("rsc %s,%s,#%d\n",regname[rt],regname[rs],imm);
1211 output_w32(0xe2e00000|rd_rn_rm(rt,rs,0)|armval);
1214 static void emit_addimm64_32(int rsh,int rsl,int imm,int rth,int rtl)
1216 // TODO: if(genimm(imm,&armval)) ...
1218 emit_movimm(imm,HOST_TEMPREG);
1219 emit_adds(HOST_TEMPREG,rsl,rtl);
1220 emit_adcimm(rsh,0,rth);
1223 static void emit_andimm(int rs,int imm,int rt)
1228 }else if(genimm(imm,&armval)) {
1229 assem_debug("and %s,%s,#%d\n",regname[rt],regname[rs],imm);
1230 output_w32(0xe2000000|rd_rn_rm(rt,rs,0)|armval);
1231 }else if(genimm(~imm,&armval)) {
1232 assem_debug("bic %s,%s,#%d\n",regname[rt],regname[rs],imm);
1233 output_w32(0xe3c00000|rd_rn_rm(rt,rs,0)|armval);
1234 }else if(imm==65535) {
1236 assem_debug("bic %s,%s,#FF000000\n",regname[rt],regname[rs]);
1237 output_w32(0xe3c00000|rd_rn_rm(rt,rs,0)|0x4FF);
1238 assem_debug("bic %s,%s,#00FF0000\n",regname[rt],regname[rt]);
1239 output_w32(0xe3c00000|rd_rn_rm(rt,rt,0)|0x8FF);
1241 assem_debug("uxth %s,%s\n",regname[rt],regname[rs]);
1242 output_w32(0xe6ff0070|rd_rn_rm(rt,0,rs));
1245 assert(imm>0&&imm<65535);
1247 assem_debug("mov r14,#%d\n",imm&0xFF00);
1248 output_w32(0xe3a00000|rd_rn_imm_shift(HOST_TEMPREG,0,imm>>8,8));
1249 assem_debug("add r14,r14,#%d\n",imm&0xFF);
1250 output_w32(0xe2800000|rd_rn_imm_shift(HOST_TEMPREG,HOST_TEMPREG,imm&0xff,0));
1252 emit_movw(imm,HOST_TEMPREG);
1254 assem_debug("and %s,%s,r14\n",regname[rt],regname[rs]);
1255 output_w32(0xe0000000|rd_rn_rm(rt,rs,HOST_TEMPREG));
1259 static void emit_orimm(int rs,int imm,int rt)
1263 if(rs!=rt) emit_mov(rs,rt);
1264 }else if(genimm(imm,&armval)) {
1265 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1266 output_w32(0xe3800000|rd_rn_rm(rt,rs,0)|armval);
1268 assert(imm>0&&imm<65536);
1269 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1270 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF);
1271 output_w32(0xe3800000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1272 output_w32(0xe3800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1276 static void emit_xorimm(int rs,int imm,int rt)
1280 if(rs!=rt) emit_mov(rs,rt);
1281 }else if(genimm(imm,&armval)) {
1282 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm);
1283 output_w32(0xe2200000|rd_rn_rm(rt,rs,0)|armval);
1285 assert(imm>0&&imm<65536);
1286 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1287 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF);
1288 output_w32(0xe2200000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1289 output_w32(0xe2200000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1293 static void emit_shlimm(int rs,u_int imm,int rt)
1298 assem_debug("lsl %s,%s,#%d\n",regname[rt],regname[rs],imm);
1299 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1302 static void emit_lsls_imm(int rs,int imm,int rt)
1306 assem_debug("lsls %s,%s,#%d\n",regname[rt],regname[rs],imm);
1307 output_w32(0xe1b00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1310 static unused void emit_lslpls_imm(int rs,int imm,int rt)
1314 assem_debug("lslpls %s,%s,#%d\n",regname[rt],regname[rs],imm);
1315 output_w32(0x51b00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1318 static void emit_shrimm(int rs,u_int imm,int rt)
1322 assem_debug("lsr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1323 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
1326 static void emit_sarimm(int rs,u_int imm,int rt)
1330 assem_debug("asr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1331 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x40|(imm<<7));
1334 static void emit_rorimm(int rs,u_int imm,int rt)
1338 assem_debug("ror %s,%s,#%d\n",regname[rt],regname[rs],imm);
1339 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x60|(imm<<7));
1342 static void emit_shldimm(int rs,int rs2,u_int imm,int rt)
1344 assem_debug("shld %%%s,%%%s,%d\n",regname[rt],regname[rs2],imm);
1348 assem_debug("lsl %s,%s,#%d\n",regname[rt],regname[rs],imm);
1349 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1350 assem_debug("orr %s,%s,%s,lsr #%d\n",regname[rt],regname[rt],regname[rs2],32-imm);
1351 output_w32(0xe1800020|rd_rn_rm(rt,rt,rs2)|((32-imm)<<7));
1354 static void emit_shrdimm(int rs,int rs2,u_int imm,int rt)
1356 assem_debug("shrd %%%s,%%%s,%d\n",regname[rt],regname[rs2],imm);
1360 assem_debug("lsr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1361 output_w32(0xe1a00020|rd_rn_rm(rt,0,rs)|(imm<<7));
1362 assem_debug("orr %s,%s,%s,lsl #%d\n",regname[rt],regname[rt],regname[rs2],32-imm);
1363 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs2)|((32-imm)<<7));
1366 static void emit_signextend16(int rs,int rt)
1369 emit_shlimm(rs,16,rt);
1370 emit_sarimm(rt,16,rt);
1372 assem_debug("sxth %s,%s\n",regname[rt],regname[rs]);
1373 output_w32(0xe6bf0070|rd_rn_rm(rt,0,rs));
1377 static void emit_signextend8(int rs,int rt)
1380 emit_shlimm(rs,24,rt);
1381 emit_sarimm(rt,24,rt);
1383 assem_debug("sxtb %s,%s\n",regname[rt],regname[rs]);
1384 output_w32(0xe6af0070|rd_rn_rm(rt,0,rs));
1388 static void emit_shl(u_int rs,u_int shift,u_int rt)
1394 assem_debug("lsl %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1395 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x10|(shift<<8));
1398 static void emit_shr(u_int rs,u_int shift,u_int rt)
1403 assem_debug("lsr %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1404 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x30|(shift<<8));
1407 static void emit_sar(u_int rs,u_int shift,u_int rt)
1412 assem_debug("asr %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1413 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x50|(shift<<8));
1416 static void emit_orrshl(u_int rs,u_int shift,u_int rt)
1421 assem_debug("orr %s,%s,%s,lsl %s\n",regname[rt],regname[rt],regname[rs],regname[shift]);
1422 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|0x10|(shift<<8));
1425 static void emit_orrshr(u_int rs,u_int shift,u_int rt)
1430 assem_debug("orr %s,%s,%s,lsr %s\n",regname[rt],regname[rt],regname[rs],regname[shift]);
1431 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|0x30|(shift<<8));
1434 static void emit_cmpimm(int rs,int imm)
1437 if(genimm(imm,&armval)) {
1438 assem_debug("cmp %s,#%d\n",regname[rs],imm);
1439 output_w32(0xe3500000|rd_rn_rm(0,rs,0)|armval);
1440 }else if(genimm(-imm,&armval)) {
1441 assem_debug("cmn %s,#%d\n",regname[rs],imm);
1442 output_w32(0xe3700000|rd_rn_rm(0,rs,0)|armval);
1445 emit_movimm(imm,HOST_TEMPREG);
1446 assem_debug("cmp %s,r14\n",regname[rs]);
1447 output_w32(0xe1500000|rd_rn_rm(0,rs,HOST_TEMPREG));
1450 emit_movimm(-imm,HOST_TEMPREG);
1451 assem_debug("cmn %s,r14\n",regname[rs]);
1452 output_w32(0xe1700000|rd_rn_rm(0,rs,HOST_TEMPREG));
1456 static void emit_cmovne_imm(int imm,int rt)
1458 assem_debug("movne %s,#%d\n",regname[rt],imm);
1460 genimm_checked(imm,&armval);
1461 output_w32(0x13a00000|rd_rn_rm(rt,0,0)|armval);
1464 static void emit_cmovl_imm(int imm,int rt)
1466 assem_debug("movlt %s,#%d\n",regname[rt],imm);
1468 genimm_checked(imm,&armval);
1469 output_w32(0xb3a00000|rd_rn_rm(rt,0,0)|armval);
1472 static void emit_cmovb_imm(int imm,int rt)
1474 assem_debug("movcc %s,#%d\n",regname[rt],imm);
1476 genimm_checked(imm,&armval);
1477 output_w32(0x33a00000|rd_rn_rm(rt,0,0)|armval);
1480 static void emit_cmovs_imm(int imm,int rt)
1482 assem_debug("movmi %s,#%d\n",regname[rt],imm);
1484 genimm_checked(imm,&armval);
1485 output_w32(0x43a00000|rd_rn_rm(rt,0,0)|armval);
1488 static void emit_cmove_reg(int rs,int rt)
1490 assem_debug("moveq %s,%s\n",regname[rt],regname[rs]);
1491 output_w32(0x01a00000|rd_rn_rm(rt,0,rs));
1494 static void emit_cmovne_reg(int rs,int rt)
1496 assem_debug("movne %s,%s\n",regname[rt],regname[rs]);
1497 output_w32(0x11a00000|rd_rn_rm(rt,0,rs));
1500 static void emit_cmovl_reg(int rs,int rt)
1502 assem_debug("movlt %s,%s\n",regname[rt],regname[rs]);
1503 output_w32(0xb1a00000|rd_rn_rm(rt,0,rs));
1506 static void emit_cmovs_reg(int rs,int rt)
1508 assem_debug("movmi %s,%s\n",regname[rt],regname[rs]);
1509 output_w32(0x41a00000|rd_rn_rm(rt,0,rs));
1512 static void emit_slti32(int rs,int imm,int rt)
1514 if(rs!=rt) emit_zeroreg(rt);
1515 emit_cmpimm(rs,imm);
1516 if(rs==rt) emit_movimm(0,rt);
1517 emit_cmovl_imm(1,rt);
1520 static void emit_sltiu32(int rs,int imm,int rt)
1522 if(rs!=rt) emit_zeroreg(rt);
1523 emit_cmpimm(rs,imm);
1524 if(rs==rt) emit_movimm(0,rt);
1525 emit_cmovb_imm(1,rt);
1528 static void emit_slti64_32(int rsh,int rsl,int imm,int rt)
1531 emit_slti32(rsl,imm,rt);
1535 emit_cmovne_imm(0,rt);
1536 emit_cmovs_imm(1,rt);
1540 emit_cmpimm(rsh,-1);
1541 emit_cmovne_imm(0,rt);
1542 emit_cmovl_imm(1,rt);
1546 static void emit_sltiu64_32(int rsh,int rsl,int imm,int rt)
1549 emit_sltiu32(rsl,imm,rt);
1553 emit_cmovne_imm(0,rt);
1557 emit_cmpimm(rsh,-1);
1558 emit_cmovne_imm(1,rt);
1562 static void emit_cmp(int rs,int rt)
1564 assem_debug("cmp %s,%s\n",regname[rs],regname[rt]);
1565 output_w32(0xe1500000|rd_rn_rm(0,rs,rt));
1568 static void emit_set_gz32(int rs, int rt)
1570 //assem_debug("set_gz32\n");
1573 emit_cmovl_imm(0,rt);
1576 static void emit_set_nz32(int rs, int rt)
1578 //assem_debug("set_nz32\n");
1579 if(rs!=rt) emit_movs(rs,rt);
1580 else emit_test(rs,rs);
1581 emit_cmovne_imm(1,rt);
1584 static void emit_set_gz64_32(int rsh, int rsl, int rt)
1586 //assem_debug("set_gz64\n");
1587 emit_set_gz32(rsl,rt);
1589 emit_cmovne_imm(1,rt);
1590 emit_cmovs_imm(0,rt);
1593 static void emit_set_nz64_32(int rsh, int rsl, int rt)
1595 //assem_debug("set_nz64\n");
1596 emit_or_and_set_flags(rsh,rsl,rt);
1597 emit_cmovne_imm(1,rt);
1600 static void emit_set_if_less32(int rs1, int rs2, int rt)
1602 //assem_debug("set if less (%%%s,%%%s),%%%s\n",regname[rs1],regname[rs2],regname[rt]);
1603 if(rs1!=rt&&rs2!=rt) emit_zeroreg(rt);
1605 if(rs1==rt||rs2==rt) emit_movimm(0,rt);
1606 emit_cmovl_imm(1,rt);
1609 static void emit_set_if_carry32(int rs1, int rs2, int rt)
1611 //assem_debug("set if carry (%%%s,%%%s),%%%s\n",regname[rs1],regname[rs2],regname[rt]);
1612 if(rs1!=rt&&rs2!=rt) emit_zeroreg(rt);
1614 if(rs1==rt||rs2==rt) emit_movimm(0,rt);
1615 emit_cmovb_imm(1,rt);
1618 static void emit_set_if_less64_32(int u1, int l1, int u2, int l2, int rt)
1620 //assem_debug("set if less64 (%%%s,%%%s,%%%s,%%%s),%%%s\n",regname[u1],regname[l1],regname[u2],regname[l2],regname[rt]);
1625 emit_sbcs(u1,u2,HOST_TEMPREG);
1626 emit_cmovl_imm(1,rt);
1629 static void emit_set_if_carry64_32(int u1, int l1, int u2, int l2, int rt)
1631 //assem_debug("set if carry64 (%%%s,%%%s,%%%s,%%%s),%%%s\n",regname[u1],regname[l1],regname[u2],regname[l2],regname[rt]);
1636 emit_sbcs(u1,u2,HOST_TEMPREG);
1637 emit_cmovb_imm(1,rt);
1640 static void emit_call(int a)
1642 assem_debug("bl %x (%x+%x)\n",a,(int)out,a-(int)out-8);
1643 u_int offset=genjmp(a);
1644 output_w32(0xeb000000|offset);
1647 static void emit_jmp(int a)
1649 assem_debug("b %x (%x+%x)\n",a,(int)out,a-(int)out-8);
1650 u_int offset=genjmp(a);
1651 output_w32(0xea000000|offset);
1654 static void emit_jne(int a)
1656 assem_debug("bne %x\n",a);
1657 u_int offset=genjmp(a);
1658 output_w32(0x1a000000|offset);
1661 static void emit_jeq(int a)
1663 assem_debug("beq %x\n",a);
1664 u_int offset=genjmp(a);
1665 output_w32(0x0a000000|offset);
1668 static void emit_js(int a)
1670 assem_debug("bmi %x\n",a);
1671 u_int offset=genjmp(a);
1672 output_w32(0x4a000000|offset);
1675 static void emit_jns(int a)
1677 assem_debug("bpl %x\n",a);
1678 u_int offset=genjmp(a);
1679 output_w32(0x5a000000|offset);
1682 static void emit_jl(int a)
1684 assem_debug("blt %x\n",a);
1685 u_int offset=genjmp(a);
1686 output_w32(0xba000000|offset);
1689 static void emit_jge(int a)
1691 assem_debug("bge %x\n",a);
1692 u_int offset=genjmp(a);
1693 output_w32(0xaa000000|offset);
1696 static void emit_jno(int a)
1698 assem_debug("bvc %x\n",a);
1699 u_int offset=genjmp(a);
1700 output_w32(0x7a000000|offset);
1703 static void emit_jc(int a)
1705 assem_debug("bcs %x\n",a);
1706 u_int offset=genjmp(a);
1707 output_w32(0x2a000000|offset);
1710 static void emit_jcc(int a)
1712 assem_debug("bcc %x\n",a);
1713 u_int offset=genjmp(a);
1714 output_w32(0x3a000000|offset);
1717 static void emit_callreg(u_int r)
1720 assem_debug("blx %s\n",regname[r]);
1721 output_w32(0xe12fff30|r);
1724 static void emit_jmpreg(u_int r)
1726 assem_debug("mov pc,%s\n",regname[r]);
1727 output_w32(0xe1a00000|rd_rn_rm(15,0,r));
1730 static void emit_readword_indexed(int offset, int rs, int rt)
1732 assert(offset>-4096&&offset<4096);
1733 assem_debug("ldr %s,%s+%d\n",regname[rt],regname[rs],offset);
1735 output_w32(0xe5900000|rd_rn_rm(rt,rs,0)|offset);
1737 output_w32(0xe5100000|rd_rn_rm(rt,rs,0)|(-offset));
1741 static void emit_readword_dualindexedx4(int rs1, int rs2, int rt)
1743 assem_debug("ldr %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1744 output_w32(0xe7900000|rd_rn_rm(rt,rs1,rs2)|0x100);
1747 static void emit_ldrcc_dualindexed(int rs1, int rs2, int rt)
1749 assem_debug("ldrcc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1750 output_w32(0x37900000|rd_rn_rm(rt,rs1,rs2));
1753 static void emit_ldrccb_dualindexed(int rs1, int rs2, int rt)
1755 assem_debug("ldrccb %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1756 output_w32(0x37d00000|rd_rn_rm(rt,rs1,rs2));
1759 static void emit_ldrccsb_dualindexed(int rs1, int rs2, int rt)
1761 assem_debug("ldrccsb %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1762 output_w32(0x319000d0|rd_rn_rm(rt,rs1,rs2));
1765 static void emit_ldrcch_dualindexed(int rs1, int rs2, int rt)
1767 assem_debug("ldrcch %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1768 output_w32(0x319000b0|rd_rn_rm(rt,rs1,rs2));
1771 static void emit_ldrccsh_dualindexed(int rs1, int rs2, int rt)
1773 assem_debug("ldrccsh %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1774 output_w32(0x319000f0|rd_rn_rm(rt,rs1,rs2));
1777 static void emit_readword_indexed_tlb(int addr, int rs, int map, int rt)
1779 if(map<0) emit_readword_indexed(addr, rs, rt);
1782 emit_readword_dualindexedx4(rs, map, rt);
1786 static void emit_readdword_indexed_tlb(int addr, int rs, int map, int rh, int rl)
1789 if(rh>=0) emit_readword_indexed(addr, rs, rh);
1790 emit_readword_indexed(addr+4, rs, rl);
1793 if(rh>=0) emit_readword_indexed_tlb(addr, rs, map, rh);
1794 emit_addimm(map,1,map);
1795 emit_readword_indexed_tlb(addr, rs, map, rl);
1799 static void emit_movsbl_indexed(int offset, int rs, int rt)
1801 assert(offset>-256&&offset<256);
1802 assem_debug("ldrsb %s,%s+%d\n",regname[rt],regname[rs],offset);
1804 output_w32(0xe1d000d0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1806 output_w32(0xe15000d0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1810 static void emit_movsbl_indexed_tlb(int addr, int rs, int map, int rt)
1812 if(map<0) emit_movsbl_indexed(addr, rs, rt);
1815 emit_shlimm(map,2,map);
1816 assem_debug("ldrsb %s,%s+%s\n",regname[rt],regname[rs],regname[map]);
1817 output_w32(0xe19000d0|rd_rn_rm(rt,rs,map));
1819 assert(addr>-256&&addr<256);
1820 assem_debug("add %s,%s,%s,lsl #2\n",regname[rt],regname[rs],regname[map]);
1821 output_w32(0xe0800000|rd_rn_rm(rt,rs,map)|(2<<7));
1822 emit_movsbl_indexed(addr, rt, rt);
1827 static void emit_movswl_indexed(int offset, int rs, int rt)
1829 assert(offset>-256&&offset<256);
1830 assem_debug("ldrsh %s,%s+%d\n",regname[rt],regname[rs],offset);
1832 output_w32(0xe1d000f0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1834 output_w32(0xe15000f0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1838 static void emit_movzbl_indexed(int offset, int rs, int rt)
1840 assert(offset>-4096&&offset<4096);
1841 assem_debug("ldrb %s,%s+%d\n",regname[rt],regname[rs],offset);
1843 output_w32(0xe5d00000|rd_rn_rm(rt,rs,0)|offset);
1845 output_w32(0xe5500000|rd_rn_rm(rt,rs,0)|(-offset));
1849 static void emit_movzbl_dualindexedx4(int rs1, int rs2, int rt)
1851 assem_debug("ldrb %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1852 output_w32(0xe7d00000|rd_rn_rm(rt,rs1,rs2)|0x100);
1855 static void emit_movzbl_indexed_tlb(int addr, int rs, int map, int rt)
1857 if(map<0) emit_movzbl_indexed(addr, rs, rt);
1860 emit_movzbl_dualindexedx4(rs, map, rt);
1862 emit_addimm(rs,addr,rt);
1863 emit_movzbl_dualindexedx4(rt, map, rt);
1868 static void emit_movzwl_indexed(int offset, int rs, int rt)
1870 assert(offset>-256&&offset<256);
1871 assem_debug("ldrh %s,%s+%d\n",regname[rt],regname[rs],offset);
1873 output_w32(0xe1d000b0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1875 output_w32(0xe15000b0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1879 static void emit_ldrd(int offset, int rs, int rt)
1881 assert(offset>-256&&offset<256);
1882 assem_debug("ldrd %s,%s+%d\n",regname[rt],regname[rs],offset);
1884 output_w32(0xe1c000d0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1886 output_w32(0xe14000d0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1890 static void emit_readword(int addr, int rt)
1892 u_int offset = addr-(u_int)&dynarec_local;
1893 assert(offset<4096);
1894 assem_debug("ldr %s,fp+%d\n",regname[rt],offset);
1895 output_w32(0xe5900000|rd_rn_rm(rt,FP,0)|offset);
1898 static unused void emit_movsbl(int addr, int rt)
1900 u_int offset = addr-(u_int)&dynarec_local;
1902 assem_debug("ldrsb %s,fp+%d\n",regname[rt],offset);
1903 output_w32(0xe1d000d0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1906 static unused void emit_movswl(int addr, int rt)
1908 u_int offset = addr-(u_int)&dynarec_local;
1910 assem_debug("ldrsh %s,fp+%d\n",regname[rt],offset);
1911 output_w32(0xe1d000f0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1914 static unused void emit_movzbl(int addr, int rt)
1916 u_int offset = addr-(u_int)&dynarec_local;
1917 assert(offset<4096);
1918 assem_debug("ldrb %s,fp+%d\n",regname[rt],offset);
1919 output_w32(0xe5d00000|rd_rn_rm(rt,FP,0)|offset);
1922 static unused void emit_movzwl(int addr, int rt)
1924 u_int offset = addr-(u_int)&dynarec_local;
1926 assem_debug("ldrh %s,fp+%d\n",regname[rt],offset);
1927 output_w32(0xe1d000b0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1930 static void emit_writeword_indexed(int rt, int offset, int rs)
1932 assert(offset>-4096&&offset<4096);
1933 assem_debug("str %s,%s+%d\n",regname[rt],regname[rs],offset);
1935 output_w32(0xe5800000|rd_rn_rm(rt,rs,0)|offset);
1937 output_w32(0xe5000000|rd_rn_rm(rt,rs,0)|(-offset));
1941 static void emit_writeword_dualindexedx4(int rt, int rs1, int rs2)
1943 assem_debug("str %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1944 output_w32(0xe7800000|rd_rn_rm(rt,rs1,rs2)|0x100);
1947 static void emit_writeword_indexed_tlb(int rt, int addr, int rs, int map, int temp)
1949 if(map<0) emit_writeword_indexed(rt, addr, rs);
1952 emit_writeword_dualindexedx4(rt, rs, map);
1956 static void emit_writedword_indexed_tlb(int rh, int rl, int addr, int rs, int map, int temp)
1959 if(rh>=0) emit_writeword_indexed(rh, addr, rs);
1960 emit_writeword_indexed(rl, addr+4, rs);
1963 if(temp!=rs) emit_addimm(map,1,temp);
1964 emit_writeword_indexed_tlb(rh, addr, rs, map, temp);
1965 if(temp!=rs) emit_writeword_indexed_tlb(rl, addr, rs, temp, temp);
1967 emit_addimm(rs,4,rs);
1968 emit_writeword_indexed_tlb(rl, addr, rs, map, temp);
1973 static void emit_writehword_indexed(int rt, int offset, int rs)
1975 assert(offset>-256&&offset<256);
1976 assem_debug("strh %s,%s+%d\n",regname[rt],regname[rs],offset);
1978 output_w32(0xe1c000b0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1980 output_w32(0xe14000b0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1984 static void emit_writebyte_indexed(int rt, int offset, int rs)
1986 assert(offset>-4096&&offset<4096);
1987 assem_debug("strb %s,%s+%d\n",regname[rt],regname[rs],offset);
1989 output_w32(0xe5c00000|rd_rn_rm(rt,rs,0)|offset);
1991 output_w32(0xe5400000|rd_rn_rm(rt,rs,0)|(-offset));
1995 static void emit_writebyte_dualindexedx4(int rt, int rs1, int rs2)
1997 assem_debug("strb %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1998 output_w32(0xe7c00000|rd_rn_rm(rt,rs1,rs2)|0x100);
2001 static void emit_writebyte_indexed_tlb(int rt, int addr, int rs, int map, int temp)
2003 if(map<0) emit_writebyte_indexed(rt, addr, rs);
2006 emit_writebyte_dualindexedx4(rt, rs, map);
2008 emit_addimm(rs,addr,temp);
2009 emit_writebyte_dualindexedx4(rt, temp, map);
2014 static void emit_strcc_dualindexed(int rs1, int rs2, int rt)
2016 assem_debug("strcc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2017 output_w32(0x37800000|rd_rn_rm(rt,rs1,rs2));
2020 static void emit_strccb_dualindexed(int rs1, int rs2, int rt)
2022 assem_debug("strccb %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2023 output_w32(0x37c00000|rd_rn_rm(rt,rs1,rs2));
2026 static void emit_strcch_dualindexed(int rs1, int rs2, int rt)
2028 assem_debug("strcch %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2029 output_w32(0x318000b0|rd_rn_rm(rt,rs1,rs2));
2032 static void emit_writeword(int rt, int addr)
2034 u_int offset = addr-(u_int)&dynarec_local;
2035 assert(offset<4096);
2036 assem_debug("str %s,fp+%d\n",regname[rt],offset);
2037 output_w32(0xe5800000|rd_rn_rm(rt,FP,0)|offset);
2040 static unused void emit_writehword(int rt, int addr)
2042 u_int offset = addr-(u_int)&dynarec_local;
2044 assem_debug("strh %s,fp+%d\n",regname[rt],offset);
2045 output_w32(0xe1c000b0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
2048 static unused void emit_writebyte(int rt, int addr)
2050 u_int offset = addr-(u_int)&dynarec_local;
2051 assert(offset<4096);
2052 assem_debug("strb %s,fp+%d\n",regname[rt],offset);
2053 output_w32(0xe5c00000|rd_rn_rm(rt,FP,0)|offset);
2056 static void emit_umull(u_int rs1, u_int rs2, u_int hi, u_int lo)
2058 assem_debug("umull %s, %s, %s, %s\n",regname[lo],regname[hi],regname[rs1],regname[rs2]);
2063 output_w32(0xe0800090|(hi<<16)|(lo<<12)|(rs2<<8)|rs1);
2066 static void emit_smull(u_int rs1, u_int rs2, u_int hi, u_int lo)
2068 assem_debug("smull %s, %s, %s, %s\n",regname[lo],regname[hi],regname[rs1],regname[rs2]);
2073 output_w32(0xe0c00090|(hi<<16)|(lo<<12)|(rs2<<8)|rs1);
2076 static void emit_clz(int rs,int rt)
2078 assem_debug("clz %s,%s\n",regname[rt],regname[rs]);
2079 output_w32(0xe16f0f10|rd_rn_rm(rt,0,rs));
2082 static void emit_subcs(int rs1,int rs2,int rt)
2084 assem_debug("subcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2085 output_w32(0x20400000|rd_rn_rm(rt,rs1,rs2));
2088 static void emit_shrcc_imm(int rs,u_int imm,int rt)
2092 assem_debug("lsrcc %s,%s,#%d\n",regname[rt],regname[rs],imm);
2093 output_w32(0x31a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
2096 static void emit_shrne_imm(int rs,u_int imm,int rt)
2100 assem_debug("lsrne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2101 output_w32(0x11a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
2104 static void emit_negmi(int rs, int rt)
2106 assem_debug("rsbmi %s,%s,#0\n",regname[rt],regname[rs]);
2107 output_w32(0x42600000|rd_rn_rm(rt,rs,0));
2110 static void emit_negsmi(int rs, int rt)
2112 assem_debug("rsbsmi %s,%s,#0\n",regname[rt],regname[rs]);
2113 output_w32(0x42700000|rd_rn_rm(rt,rs,0));
2116 static void emit_orreq(u_int rs1,u_int rs2,u_int rt)
2118 assem_debug("orreq %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2119 output_w32(0x01800000|rd_rn_rm(rt,rs1,rs2));
2122 static void emit_orrne(u_int rs1,u_int rs2,u_int rt)
2124 assem_debug("orrne %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2125 output_w32(0x11800000|rd_rn_rm(rt,rs1,rs2));
2128 static void emit_bic_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2130 assem_debug("bic %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2131 output_w32(0xe1C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2134 static void emit_biceq_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2136 assem_debug("biceq %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2137 output_w32(0x01C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2140 static void emit_bicne_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2142 assem_debug("bicne %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2143 output_w32(0x11C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2146 static void emit_bic_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2148 assem_debug("bic %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2149 output_w32(0xe1C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2152 static void emit_biceq_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2154 assem_debug("biceq %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2155 output_w32(0x01C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2158 static void emit_bicne_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2160 assem_debug("bicne %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2161 output_w32(0x11C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2164 static void emit_teq(int rs, int rt)
2166 assem_debug("teq %s,%s\n",regname[rs],regname[rt]);
2167 output_w32(0xe1300000|rd_rn_rm(0,rs,rt));
2170 static void emit_rsbimm(int rs, int imm, int rt)
2173 genimm_checked(imm,&armval);
2174 assem_debug("rsb %s,%s,#%d\n",regname[rt],regname[rs],imm);
2175 output_w32(0xe2600000|rd_rn_rm(rt,rs,0)|armval);
2178 // Load 2 immediates optimizing for small code size
2179 static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
2181 emit_movimm(imm1,rt1);
2183 if(genimm(imm2-imm1,&armval)) {
2184 assem_debug("add %s,%s,#%d\n",regname[rt2],regname[rt1],imm2-imm1);
2185 output_w32(0xe2800000|rd_rn_rm(rt2,rt1,0)|armval);
2186 }else if(genimm(imm1-imm2,&armval)) {
2187 assem_debug("sub %s,%s,#%d\n",regname[rt2],regname[rt1],imm1-imm2);
2188 output_w32(0xe2400000|rd_rn_rm(rt2,rt1,0)|armval);
2190 else emit_movimm(imm2,rt2);
2193 // Conditionally select one of two immediates, optimizing for small code size
2194 // This will only be called if HAVE_CMOV_IMM is defined
2195 static void emit_cmov2imm_e_ne_compact(int imm1,int imm2,u_int rt)
2198 if(genimm(imm2-imm1,&armval)) {
2199 emit_movimm(imm1,rt);
2200 assem_debug("addne %s,%s,#%d\n",regname[rt],regname[rt],imm2-imm1);
2201 output_w32(0x12800000|rd_rn_rm(rt,rt,0)|armval);
2202 }else if(genimm(imm1-imm2,&armval)) {
2203 emit_movimm(imm1,rt);
2204 assem_debug("subne %s,%s,#%d\n",regname[rt],regname[rt],imm1-imm2);
2205 output_w32(0x12400000|rd_rn_rm(rt,rt,0)|armval);
2209 emit_movimm(imm1,rt);
2210 add_literal((int)out,imm2);
2211 assem_debug("ldrne %s,pc+? [=%x]\n",regname[rt],imm2);
2212 output_w32(0x15900000|rd_rn_rm(rt,15,0));
2214 emit_movw(imm1&0x0000FFFF,rt);
2215 if((imm1&0xFFFF)!=(imm2&0xFFFF)) {
2216 assem_debug("movwne %s,#%d (0x%x)\n",regname[rt],imm2&0xFFFF,imm2&0xFFFF);
2217 output_w32(0x13000000|rd_rn_rm(rt,0,0)|(imm2&0xfff)|((imm2<<4)&0xf0000));
2219 emit_movt(imm1&0xFFFF0000,rt);
2220 if((imm1&0xFFFF0000)!=(imm2&0xFFFF0000)) {
2221 assem_debug("movtne %s,#%d (0x%x)\n",regname[rt],imm2&0xffff0000,imm2&0xffff0000);
2222 output_w32(0x13400000|rd_rn_rm(rt,0,0)|((imm2>>16)&0xfff)|((imm2>>12)&0xf0000));
2228 // special case for checking invalid_code
2229 static void emit_cmpmem_indexedsr12_reg(int base,int r,int imm)
2231 assert(imm<128&&imm>=0);
2233 assem_debug("ldrb lr,%s,%s lsr #12\n",regname[base],regname[r]);
2234 output_w32(0xe7d00000|rd_rn_rm(HOST_TEMPREG,base,r)|0x620);
2235 emit_cmpimm(HOST_TEMPREG,imm);
2238 static void emit_callne(int a)
2240 assem_debug("blne %x\n",a);
2241 u_int offset=genjmp(a);
2242 output_w32(0x1b000000|offset);
2245 // Used to preload hash table entries
2246 static unused void emit_prefetchreg(int r)
2248 assem_debug("pld %s\n",regname[r]);
2249 output_w32(0xf5d0f000|rd_rn_rm(0,r,0));
2252 // Special case for mini_ht
2253 static void emit_ldreq_indexed(int rs, u_int offset, int rt)
2255 assert(offset<4096);
2256 assem_debug("ldreq %s,[%s, #%d]\n",regname[rt],regname[rs],offset);
2257 output_w32(0x05900000|rd_rn_rm(rt,rs,0)|offset);
2260 static unused void emit_bicne_imm(int rs,int imm,int rt)
2263 genimm_checked(imm,&armval);
2264 assem_debug("bicne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2265 output_w32(0x13c00000|rd_rn_rm(rt,rs,0)|armval);
2268 static unused void emit_biccs_imm(int rs,int imm,int rt)
2271 genimm_checked(imm,&armval);
2272 assem_debug("biccs %s,%s,#%d\n",regname[rt],regname[rs],imm);
2273 output_w32(0x23c00000|rd_rn_rm(rt,rs,0)|armval);
2276 static unused void emit_bicvc_imm(int rs,int imm,int rt)
2279 genimm_checked(imm,&armval);
2280 assem_debug("bicvc %s,%s,#%d\n",regname[rt],regname[rs],imm);
2281 output_w32(0x73c00000|rd_rn_rm(rt,rs,0)|armval);
2284 static unused void emit_bichi_imm(int rs,int imm,int rt)
2287 genimm_checked(imm,&armval);
2288 assem_debug("bichi %s,%s,#%d\n",regname[rt],regname[rs],imm);
2289 output_w32(0x83c00000|rd_rn_rm(rt,rs,0)|armval);
2292 static unused void emit_orrvs_imm(int rs,int imm,int rt)
2295 genimm_checked(imm,&armval);
2296 assem_debug("orrvs %s,%s,#%d\n",regname[rt],regname[rs],imm);
2297 output_w32(0x63800000|rd_rn_rm(rt,rs,0)|armval);
2300 static void emit_orrne_imm(int rs,int imm,int rt)
2303 genimm_checked(imm,&armval);
2304 assem_debug("orrne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2305 output_w32(0x13800000|rd_rn_rm(rt,rs,0)|armval);
2308 static void emit_andne_imm(int rs,int imm,int rt)
2311 genimm_checked(imm,&armval);
2312 assem_debug("andne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2313 output_w32(0x12000000|rd_rn_rm(rt,rs,0)|armval);
2316 static unused void emit_addpl_imm(int rs,int imm,int rt)
2319 genimm_checked(imm,&armval);
2320 assem_debug("addpl %s,%s,#%d\n",regname[rt],regname[rs],imm);
2321 output_w32(0x52800000|rd_rn_rm(rt,rs,0)|armval);
2324 static void emit_jno_unlikely(int a)
2327 assem_debug("addvc pc,pc,#? (%x)\n",/*a-(int)out-8,*/a);
2328 output_w32(0x72800000|rd_rn_rm(15,15,0));
2331 static void save_regs_all(u_int reglist)
2334 if(!reglist) return;
2335 assem_debug("stmia fp,{");
2338 assem_debug("r%d,",i);
2340 output_w32(0xe88b0000|reglist);
2343 static void restore_regs_all(u_int reglist)
2346 if(!reglist) return;
2347 assem_debug("ldmia fp,{");
2350 assem_debug("r%d,",i);
2352 output_w32(0xe89b0000|reglist);
2355 // Save registers before function call
2356 static void save_regs(u_int reglist)
2358 reglist&=CALLER_SAVE_REGS; // only save the caller-save registers, r0-r3, r12
2359 save_regs_all(reglist);
2362 // Restore registers after function call
2363 static void restore_regs(u_int reglist)
2365 reglist&=CALLER_SAVE_REGS;
2366 restore_regs_all(reglist);
2369 /* Stubs/epilogue */
2371 static void literal_pool(int n)
2373 if(!literalcount) return;
2375 if((int)out-literals[0][0]<4096-n) return;
2379 for(i=0;i<literalcount;i++)
2381 u_int l_addr=(u_int)out;
2384 if(literals[j][1]==literals[i][1]) {
2385 //printf("dup %08x\n",literals[i][1]);
2386 l_addr=literals[j][0];
2390 ptr=(u_int *)literals[i][0];
2391 u_int offset=l_addr-(u_int)ptr-8;
2392 assert(offset<4096);
2393 assert(!(offset&3));
2395 if(l_addr==(u_int)out) {
2396 literals[i][0]=l_addr; // remember for dupes
2397 output_w32(literals[i][1]);
2403 static void literal_pool_jumpover(int n)
2405 if(!literalcount) return;
2407 if((int)out-literals[0][0]<4096-n) return;
2412 set_jump_target(jaddr,(int)out);
2415 static void emit_extjump2(u_int addr, int target, int linker)
2417 u_char *ptr=(u_char *)addr;
2418 assert((ptr[3]&0x0e)==0xa);
2421 emit_loadlp(target,0);
2422 emit_loadlp(addr,1);
2423 assert(addr>=BASE_ADDR&&addr<(BASE_ADDR+(1<<TARGET_SIZE_2)));
2424 //assert((target>=0x80000000&&target<0x80800000)||(target>0xA4000000&&target<0xA4001000));
2426 #ifdef DEBUG_CYCLE_COUNT
2427 emit_readword((int)&last_count,ECX);
2428 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2429 emit_readword((int)&next_interupt,ECX);
2430 emit_writeword(HOST_CCREG,(int)&Count);
2431 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
2432 emit_writeword(ECX,(int)&last_count);
2438 static void emit_extjump(int addr, int target)
2440 emit_extjump2(addr, target, (int)dyna_linker);
2443 static void emit_extjump_ds(int addr, int target)
2445 emit_extjump2(addr, target, (int)dyna_linker_ds);
2448 // put rt_val into rt, potentially making use of rs with value rs_val
2449 static void emit_movimm_from(u_int rs_val,int rs,u_int rt_val,int rt)
2453 if(genimm(rt_val,&armval)) {
2454 assem_debug("mov %s,#%d\n",regname[rt],rt_val);
2455 output_w32(0xe3a00000|rd_rn_rm(rt,0,0)|armval);
2458 if(genimm(~rt_val,&armval)) {
2459 assem_debug("mvn %s,#%d\n",regname[rt],rt_val);
2460 output_w32(0xe3e00000|rd_rn_rm(rt,0,0)|armval);
2464 if(genimm(diff,&armval)) {
2465 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rs],diff);
2466 output_w32(0xe2800000|rd_rn_rm(rt,rs,0)|armval);
2468 }else if(genimm(-diff,&armval)) {
2469 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],-diff);
2470 output_w32(0xe2400000|rd_rn_rm(rt,rs,0)|armval);
2473 emit_movimm(rt_val,rt);
2476 // return 1 if above function can do it's job cheaply
2477 static int is_similar_value(u_int v1,u_int v2)
2481 if(v1==v2) return 1;
2483 for(xs=diff;xs!=0&&(xs&3)==0;xs>>=2)
2485 if(xs<0x100) return 1;
2486 for(xs=-diff;xs!=0&&(xs&3)==0;xs>>=2)
2488 if(xs<0x100) return 1;
2493 static void pass_args(int a0, int a1)
2497 emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
2499 else if(a0!=0&&a1==0) {
2501 if (a0>=0) emit_mov(a0,0);
2504 if(a0>=0&&a0!=0) emit_mov(a0,0);
2505 if(a1>=0&&a1!=1) emit_mov(a1,1);
2509 static void mov_loadtype_adj(int type,int rs,int rt)
2512 case LOADB_STUB: emit_signextend8(rs,rt); break;
2513 case LOADBU_STUB: emit_andimm(rs,0xff,rt); break;
2514 case LOADH_STUB: emit_signextend16(rs,rt); break;
2515 case LOADHU_STUB: emit_andimm(rs,0xffff,rt); break;
2516 case LOADW_STUB: if(rs!=rt) emit_mov(rs,rt); break;
2521 #include "../backends/psx/pcsxmem.h"
2522 #include "../backends/psx/pcsxmem_inline.c"
2524 static void do_readstub(int n)
2526 assem_debug("do_readstub %x\n",start+stubs[n][3]*4);
2528 set_jump_target(stubs[n][1],(int)out);
2529 int type=stubs[n][0];
2532 struct regstat *i_regs=(struct regstat *)stubs[n][5];
2533 u_int reglist=stubs[n][7];
2534 signed char *i_regmap=i_regs->regmap;
2536 if(itype[i]==C1LS||itype[i]==C2LS||itype[i]==LOADLR) {
2537 rt=get_reg(i_regmap,FTEMP);
2539 rt=get_reg(i_regmap,rt1[i]);
2542 int r,temp=-1,temp2=HOST_TEMPREG,regs_saved=0,restore_jump=0;
2544 for(r=0;r<=12;r++) {
2545 if(((1<<r)&0x13ff)&&((1<<r)®list)==0) {
2549 if(rt>=0&&rt1[i]!=0)
2556 if((regs_saved||(reglist&2)==0)&&temp!=1&&rs!=1)
2558 emit_readword((int)&mem_rtab,temp);
2559 emit_shrimm(rs,12,temp2);
2560 emit_readword_dualindexedx4(temp,temp2,temp2);
2561 emit_lsls_imm(temp2,1,temp2);
2562 if(itype[i]==C1LS||itype[i]==C2LS||(rt>=0&&rt1[i]!=0)) {
2564 case LOADB_STUB: emit_ldrccsb_dualindexed(temp2,rs,rt); break;
2565 case LOADBU_STUB: emit_ldrccb_dualindexed(temp2,rs,rt); break;
2566 case LOADH_STUB: emit_ldrccsh_dualindexed(temp2,rs,rt); break;
2567 case LOADHU_STUB: emit_ldrcch_dualindexed(temp2,rs,rt); break;
2568 case LOADW_STUB: emit_ldrcc_dualindexed(temp2,rs,rt); break;
2572 restore_jump=(int)out;
2573 emit_jcc(0); // jump to reg restore
2576 emit_jcc(stubs[n][2]); // return address
2581 if(type==LOADB_STUB||type==LOADBU_STUB)
2582 handler=(int)jump_handler_read8;
2583 if(type==LOADH_STUB||type==LOADHU_STUB)
2584 handler=(int)jump_handler_read16;
2585 if(type==LOADW_STUB)
2586 handler=(int)jump_handler_read32;
2588 pass_args(rs,temp2);
2589 int cc=get_reg(i_regmap,CCREG);
2591 emit_loadreg(CCREG,2);
2592 emit_addimm(cc<0?2:cc,CLOCK_ADJUST((int)stubs[n][6]+1),2);
2594 if(itype[i]==C1LS||itype[i]==C2LS||(rt>=0&&rt1[i]!=0)) {
2595 mov_loadtype_adj(type,0,rt);
2598 set_jump_target(restore_jump,(int)out);
2599 restore_regs(reglist);
2600 emit_jmp(stubs[n][2]); // return address
2603 // return memhandler, or get directly accessable address and return 0
2604 static u_int get_direct_memhandler(void *table,u_int addr,int type,u_int *addr_host)
2607 l1=((u_int *)table)[addr>>12];
2608 if((l1&(1<<31))==0) {
2615 if(type==LOADB_STUB||type==LOADBU_STUB||type==STOREB_STUB)
2616 l2=((u_int *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
2617 else if(type==LOADH_STUB||type==LOADHU_STUB||type==STOREH_STUB)
2618 l2=((u_int *)l1)[0x1000/4 + (addr&0xfff)/2];
2620 l2=((u_int *)l1)[(addr&0xfff)/4];
2621 if((l2&(1<<31))==0) {
2623 *addr_host=v+(addr&0xfff);
2630 static void inline_readstub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
2632 int rs=get_reg(regmap,target);
2633 int rt=get_reg(regmap,target);
2634 if(rs<0) rs=get_reg(regmap,-1);
2636 u_int handler,host_addr=0,is_dynamic,far_call=0;
2637 int cc=get_reg(regmap,CCREG);
2638 if(pcsx_direct_read(type,addr,CLOCK_ADJUST(adj+1),cc,target?rs:-1,rt))
2640 handler=get_direct_memhandler(mem_rtab,addr,type,&host_addr);
2645 emit_movimm_from(addr,rs,host_addr,rs);
2647 case LOADB_STUB: emit_movsbl_indexed(0,rs,rt); break;
2648 case LOADBU_STUB: emit_movzbl_indexed(0,rs,rt); break;
2649 case LOADH_STUB: emit_movswl_indexed(0,rs,rt); break;
2650 case LOADHU_STUB: emit_movzwl_indexed(0,rs,rt); break;
2651 case LOADW_STUB: emit_readword_indexed(0,rs,rt); break;
2656 is_dynamic=pcsxmem_is_handler_dynamic(addr);
2658 if(type==LOADB_STUB||type==LOADBU_STUB)
2659 handler=(int)jump_handler_read8;
2660 if(type==LOADH_STUB||type==LOADHU_STUB)
2661 handler=(int)jump_handler_read16;
2662 if(type==LOADW_STUB)
2663 handler=(int)jump_handler_read32;
2666 // call a memhandler
2667 if(rt>=0&&rt1[i]!=0)
2671 emit_movimm(addr,0);
2674 int offset=(int)handler-(int)out-8;
2675 if(offset<-33554432||offset>=33554432) {
2676 // unreachable memhandler, a plugin func perhaps
2677 emit_movimm(handler,12);
2681 emit_loadreg(CCREG,2);
2683 emit_movimm(((u_int *)mem_rtab)[addr>>12]<<1,1);
2684 emit_addimm(cc<0?2:cc,CLOCK_ADJUST(adj+1),2);
2687 emit_readword((int)&last_count,3);
2688 emit_addimm(cc<0?2:cc,CLOCK_ADJUST(adj+1),2);
2690 emit_writeword(2,(int)&Count);
2698 if(rt>=0&&rt1[i]!=0) {
2700 case LOADB_STUB: emit_signextend8(0,rt); break;
2701 case LOADBU_STUB: emit_andimm(0,0xff,rt); break;
2702 case LOADH_STUB: emit_signextend16(0,rt); break;
2703 case LOADHU_STUB: emit_andimm(0,0xffff,rt); break;
2704 case LOADW_STUB: if(rt!=0) emit_mov(0,rt); break;
2708 restore_regs(reglist);
2711 static void do_writestub(int n)
2713 assem_debug("do_writestub %x\n",start+stubs[n][3]*4);
2715 set_jump_target(stubs[n][1],(int)out);
2716 int type=stubs[n][0];
2719 struct regstat *i_regs=(struct regstat *)stubs[n][5];
2720 u_int reglist=stubs[n][7];
2721 signed char *i_regmap=i_regs->regmap;
2723 if(itype[i]==C1LS||itype[i]==C2LS) {
2724 rt=get_reg(i_regmap,r=FTEMP);
2726 rt=get_reg(i_regmap,r=rs2[i]);
2730 int rtmp,temp=-1,temp2=HOST_TEMPREG,regs_saved=0,restore_jump=0,ra;
2731 int reglist2=reglist|(1<<rs)|(1<<rt);
2732 for(rtmp=0;rtmp<=12;rtmp++) {
2733 if(((1<<rtmp)&0x13ff)&&((1<<rtmp)®list2)==0) {
2740 for(rtmp=0;rtmp<=3;rtmp++)
2741 if(rtmp!=rs&&rtmp!=rt)
2744 if((regs_saved||(reglist2&8)==0)&&temp!=3&&rs!=3&&rt!=3)
2746 emit_readword((int)&mem_wtab,temp);
2747 emit_shrimm(rs,12,temp2);
2748 emit_readword_dualindexedx4(temp,temp2,temp2);
2749 emit_lsls_imm(temp2,1,temp2);
2751 case STOREB_STUB: emit_strccb_dualindexed(temp2,rs,rt); break;
2752 case STOREH_STUB: emit_strcch_dualindexed(temp2,rs,rt); break;
2753 case STOREW_STUB: emit_strcc_dualindexed(temp2,rs,rt); break;
2757 restore_jump=(int)out;
2758 emit_jcc(0); // jump to reg restore
2761 emit_jcc(stubs[n][2]); // return address (invcode check)
2767 case STOREB_STUB: handler=(int)jump_handler_write8; break;
2768 case STOREH_STUB: handler=(int)jump_handler_write16; break;
2769 case STOREW_STUB: handler=(int)jump_handler_write32; break;
2775 int cc=get_reg(i_regmap,CCREG);
2777 emit_loadreg(CCREG,2);
2778 emit_addimm(cc<0?2:cc,CLOCK_ADJUST((int)stubs[n][6]+1),2);
2779 // returns new cycle_count
2781 emit_addimm(0,-CLOCK_ADJUST((int)stubs[n][6]+1),cc<0?2:cc);
2783 emit_storereg(CCREG,2);
2785 set_jump_target(restore_jump,(int)out);
2786 restore_regs(reglist);
2791 static void inline_writestub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
2793 int rs=get_reg(regmap,-1);
2794 int rt=get_reg(regmap,target);
2797 u_int handler,host_addr=0;
2798 handler=get_direct_memhandler(mem_wtab,addr,type,&host_addr);
2801 emit_movimm_from(addr,rs,host_addr,rs);
2803 case STOREB_STUB: emit_writebyte_indexed(rt,0,rs); break;
2804 case STOREH_STUB: emit_writehword_indexed(rt,0,rs); break;
2805 case STOREW_STUB: emit_writeword_indexed(rt,0,rs); break;
2811 // call a memhandler
2814 int cc=get_reg(regmap,CCREG);
2816 emit_loadreg(CCREG,2);
2817 emit_addimm(cc<0?2:cc,CLOCK_ADJUST(adj+1),2);
2818 emit_movimm(handler,3);
2819 // returns new cycle_count
2820 emit_call((int)jump_handler_write_h);
2821 emit_addimm(0,-CLOCK_ADJUST(adj+1),cc<0?2:cc);
2823 emit_storereg(CCREG,2);
2824 restore_regs(reglist);
2827 static void do_unalignedwritestub(int n)
2829 assem_debug("do_unalignedwritestub %x\n",start+stubs[n][3]*4);
2831 set_jump_target(stubs[n][1],(int)out);
2834 struct regstat *i_regs=(struct regstat *)stubs[n][4];
2835 int addr=stubs[n][5];
2836 u_int reglist=stubs[n][7];
2837 signed char *i_regmap=i_regs->regmap;
2838 int temp2=get_reg(i_regmap,FTEMP);
2840 rt=get_reg(i_regmap,rs2[i]);
2843 assert(opcode[i]==0x2a||opcode[i]==0x2e); // SWL/SWR only implemented
2845 reglist&=~(1<<temp2);
2848 // don't bother with it and call write handler
2851 int cc=get_reg(i_regmap,CCREG);
2853 emit_loadreg(CCREG,2);
2854 emit_addimm(cc<0?2:cc,CLOCK_ADJUST((int)stubs[n][6]+1),2);
2855 emit_call((int)(opcode[i]==0x2a?jump_handle_swl:jump_handle_swr));
2856 emit_addimm(0,-CLOCK_ADJUST((int)stubs[n][6]+1),cc<0?2:cc);
2858 emit_storereg(CCREG,2);
2859 restore_regs(reglist);
2860 emit_jmp(stubs[n][2]); // return address
2862 emit_andimm(addr,0xfffffffc,temp2);
2863 emit_writeword(temp2,(int)&address);
2866 emit_shrimm(addr,16,1);
2867 int cc=get_reg(i_regmap,CCREG);
2869 emit_loadreg(CCREG,2);
2871 emit_movimm((u_int)readmem,0);
2872 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
2873 emit_call((int)&indirect_jump_indexed);
2874 restore_regs(reglist);
2876 emit_readword((int)&readmem_dword,temp2);
2877 int temp=addr; //hmh
2878 emit_shlimm(addr,3,temp);
2879 emit_andimm(temp,24,temp);
2880 #ifdef BIG_ENDIAN_MIPS
2881 if (opcode[i]==0x2e) // SWR
2883 if (opcode[i]==0x2a) // SWL
2885 emit_xorimm(temp,24,temp);
2886 emit_movimm(-1,HOST_TEMPREG);
2887 if (opcode[i]==0x2a) { // SWL
2888 emit_bic_lsr(temp2,HOST_TEMPREG,temp,temp2);
2889 emit_orrshr(rt,temp,temp2);
2891 emit_bic_lsl(temp2,HOST_TEMPREG,temp,temp2);
2892 emit_orrshl(rt,temp,temp2);
2894 emit_readword((int)&address,addr);
2895 emit_writeword(temp2,(int)&word);
2896 //save_regs(reglist); // don't need to, no state changes
2897 emit_shrimm(addr,16,1);
2898 emit_movimm((u_int)writemem,0);
2899 //emit_call((int)&indirect_jump_indexed);
2901 emit_readword_dualindexedx4(0,1,15);
2902 emit_readword((int)&Count,HOST_TEMPREG);
2903 emit_readword((int)&next_interupt,2);
2904 emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
2905 emit_writeword(2,(int)&last_count);
2906 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2908 emit_storereg(CCREG,HOST_TEMPREG);
2910 restore_regs(reglist);
2911 emit_jmp(stubs[n][2]); // return address
2915 static void do_invstub(int n)
2918 u_int reglist=stubs[n][3];
2919 set_jump_target(stubs[n][1],(int)out);
2921 if(stubs[n][4]!=0) emit_mov(stubs[n][4],0);
2922 emit_call((int)&invalidate_addr);
2923 restore_regs(reglist);
2924 emit_jmp(stubs[n][2]); // return address
2927 int do_dirty_stub(int i)
2929 assem_debug("do_dirty_stub %x\n",start+i*4);
2930 u_int addr=(u_int)source;
2931 // Careful about the code output here, verify_dirty needs to parse it.
2933 emit_loadlp(addr,1);
2934 emit_loadlp((int)copy,2);
2935 emit_loadlp(slen*4,3);
2937 emit_movw(addr&0x0000FFFF,1);
2938 emit_movw(((u_int)copy)&0x0000FFFF,2);
2939 emit_movt(addr&0xFFFF0000,1);
2940 emit_movt(((u_int)copy)&0xFFFF0000,2);
2941 emit_movw(slen*4,3);
2943 emit_movimm(start+i*4,0);
2944 emit_call((int)start<(int)0xC0000000?(int)&verify_code:(int)&verify_code_vm);
2947 if(entry==(int)out) entry=instr_addr[i];
2948 emit_jmp(instr_addr[i]);
2952 static void do_dirty_stub_ds()
2954 // Careful about the code output here, verify_dirty needs to parse it.
2956 emit_loadlp((int)start<(int)0xC0000000?(int)source:(int)start,1);
2957 emit_loadlp((int)copy,2);
2958 emit_loadlp(slen*4,3);
2960 emit_movw(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0x0000FFFF,1);
2961 emit_movw(((u_int)copy)&0x0000FFFF,2);
2962 emit_movt(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0xFFFF0000,1);
2963 emit_movt(((u_int)copy)&0xFFFF0000,2);
2964 emit_movw(slen*4,3);
2966 emit_movimm(start+1,0);
2967 emit_call((int)&verify_code_ds);
2970 static void do_cop1stub(int n)
2973 assem_debug("do_cop1stub %x\n",start+stubs[n][3]*4);
2974 set_jump_target(stubs[n][1],(int)out);
2976 // int rs=stubs[n][4];
2977 struct regstat *i_regs=(struct regstat *)stubs[n][5];
2980 load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
2981 //if(i_regs!=®s[i]) printf("oops: regs[i]=%x i_regs=%x",(int)®s[i],(int)i_regs);
2983 //else {printf("fp exception in delay slot\n");}
2984 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty);
2985 if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
2986 emit_movimm(start+(i-ds)*4,EAX); // Get PC
2987 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
2988 emit_jmp(ds?(int)fp_exception_ds:(int)fp_exception);
2993 static void shift_assemble_arm(int i,struct regstat *i_regs)
2996 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
2998 signed char s,t,shift;
2999 t=get_reg(i_regs->regmap,rt1[i]);
3000 s=get_reg(i_regs->regmap,rs1[i]);
3001 shift=get_reg(i_regs->regmap,rs2[i]);
3010 if(s!=t) emit_mov(s,t);
3014 emit_andimm(shift,31,HOST_TEMPREG);
3015 if(opcode2[i]==4) // SLLV
3017 emit_shl(s,HOST_TEMPREG,t);
3019 if(opcode2[i]==6) // SRLV
3021 emit_shr(s,HOST_TEMPREG,t);
3023 if(opcode2[i]==7) // SRAV
3025 emit_sar(s,HOST_TEMPREG,t);
3029 } else { // DSLLV/DSRLV/DSRAV
3030 signed char sh,sl,th,tl,shift;
3031 th=get_reg(i_regs->regmap,rt1[i]|64);
3032 tl=get_reg(i_regs->regmap,rt1[i]);
3033 sh=get_reg(i_regs->regmap,rs1[i]|64);
3034 sl=get_reg(i_regs->regmap,rs1[i]);
3035 shift=get_reg(i_regs->regmap,rs2[i]);
3040 if(th>=0) emit_zeroreg(th);
3045 if(sl!=tl) emit_mov(sl,tl);
3046 if(th>=0&&sh!=th) emit_mov(sh,th);
3050 // FIXME: What if shift==tl ?
3052 int temp=get_reg(i_regs->regmap,-1);
3054 if(th<0&&opcode2[i]!=0x14) {th=temp;} // DSLLV doesn't need a temporary register
3057 emit_andimm(shift,31,HOST_TEMPREG);
3058 if(opcode2[i]==0x14) // DSLLV
3060 if(th>=0) emit_shl(sh,HOST_TEMPREG,th);
3061 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3062 emit_orrshr(sl,HOST_TEMPREG,th);
3063 emit_andimm(shift,31,HOST_TEMPREG);
3064 emit_testimm(shift,32);
3065 emit_shl(sl,HOST_TEMPREG,tl);
3066 if(th>=0) emit_cmovne_reg(tl,th);
3067 emit_cmovne_imm(0,tl);
3069 if(opcode2[i]==0x16) // DSRLV
3072 emit_shr(sl,HOST_TEMPREG,tl);
3073 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3074 emit_orrshl(sh,HOST_TEMPREG,tl);
3075 emit_andimm(shift,31,HOST_TEMPREG);
3076 emit_testimm(shift,32);
3077 emit_shr(sh,HOST_TEMPREG,th);
3078 emit_cmovne_reg(th,tl);
3079 if(real_th>=0) emit_cmovne_imm(0,th);
3081 if(opcode2[i]==0x17) // DSRAV
3084 emit_shr(sl,HOST_TEMPREG,tl);
3085 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3088 emit_sarimm(th,31,temp);
3090 emit_orrshl(sh,HOST_TEMPREG,tl);
3091 emit_andimm(shift,31,HOST_TEMPREG);
3092 emit_testimm(shift,32);
3093 emit_sar(sh,HOST_TEMPREG,th);
3094 emit_cmovne_reg(th,tl);
3095 if(real_th>=0) emit_cmovne_reg(temp,th);
3103 static void speculate_mov(int rs,int rt)
3106 smrv_strong_next|=1<<rt;
3111 static void speculate_mov_weak(int rs,int rt)
3114 smrv_weak_next|=1<<rt;
3119 static void speculate_register_values(int i)
3122 memcpy(smrv,psxRegs.GPR.r,sizeof(smrv));
3123 // gp,sp are likely to stay the same throughout the block
3124 smrv_strong_next=(1<<28)|(1<<29)|(1<<30);
3125 smrv_weak_next=~smrv_strong_next;
3126 //printf(" llr %08x\n", smrv[4]);
3128 smrv_strong=smrv_strong_next;
3129 smrv_weak=smrv_weak_next;
3132 if ((smrv_strong>>rs1[i])&1) speculate_mov(rs1[i],rt1[i]);
3133 else if((smrv_strong>>rs2[i])&1) speculate_mov(rs2[i],rt1[i]);
3134 else if((smrv_weak>>rs1[i])&1) speculate_mov_weak(rs1[i],rt1[i]);
3135 else if((smrv_weak>>rs2[i])&1) speculate_mov_weak(rs2[i],rt1[i]);
3137 smrv_strong_next&=~(1<<rt1[i]);
3138 smrv_weak_next&=~(1<<rt1[i]);
3142 smrv_strong_next&=~(1<<rt1[i]);
3143 smrv_weak_next&=~(1<<rt1[i]);
3146 if(rt1[i]&&is_const(®s[i],rt1[i])) {
3147 int value,hr=get_reg(regs[i].regmap,rt1[i]);
3149 if(get_final_value(hr,i,&value))
3151 else smrv[rt1[i]]=constmap[i][hr];
3152 smrv_strong_next|=1<<rt1[i];
3156 if ((smrv_strong>>rs1[i])&1) speculate_mov(rs1[i],rt1[i]);
3157 else if((smrv_weak>>rs1[i])&1) speculate_mov_weak(rs1[i],rt1[i]);
3161 if(start<0x2000&&(rt1[i]==26||(smrv[rt1[i]]>>24)==0xa0)) {
3162 // special case for BIOS
3163 smrv[rt1[i]]=0xa0000000;
3164 smrv_strong_next|=1<<rt1[i];
3171 smrv_strong_next&=~(1<<rt1[i]);
3172 smrv_weak_next&=~(1<<rt1[i]);
3176 if(opcode2[i]==0||opcode2[i]==2) { // MFC/CFC
3177 smrv_strong_next&=~(1<<rt1[i]);
3178 smrv_weak_next&=~(1<<rt1[i]);
3182 if (opcode[i]==0x32) { // LWC2
3183 smrv_strong_next&=~(1<<rt1[i]);
3184 smrv_weak_next&=~(1<<rt1[i]);
3190 printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4,
3191 ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst);
3203 static int get_ptr_mem_type(u_int a)
3205 if(a < 0x00200000) {
3206 if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0))
3207 // return wrong, must use memhandler for BIOS self-test to pass
3208 // 007 does similar stuff from a00 mirror, weird stuff
3212 if(0x1f800000 <= a && a < 0x1f801000)
3214 if(0x80200000 <= a && a < 0x80800000)
3216 if(0xa0000000 <= a && a < 0xa0200000)
3221 static int emit_fastpath_cmp_jump(int i,int addr,int *addr_reg_override)
3225 if(((smrv_strong|smrv_weak)>>mr)&1) {
3226 type=get_ptr_mem_type(smrv[mr]);
3227 //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type);
3230 // use the mirror we are running on
3231 type=get_ptr_mem_type(start);
3232 //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type);
3235 if(type==MTYPE_8020) { // RAM 80200000+ mirror
3236 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
3237 addr=*addr_reg_override=HOST_TEMPREG;
3240 else if(type==MTYPE_0000) { // RAM 0 mirror
3241 emit_orimm(addr,0x80000000,HOST_TEMPREG);
3242 addr=*addr_reg_override=HOST_TEMPREG;
3245 else if(type==MTYPE_A000) { // RAM A mirror
3246 emit_andimm(addr,~0x20000000,HOST_TEMPREG);
3247 addr=*addr_reg_override=HOST_TEMPREG;
3250 else if(type==MTYPE_1F80) { // scratchpad
3251 if (psxH == (void *)0x1f800000) {
3252 emit_addimm(addr,-0x1f800000,HOST_TEMPREG);
3253 emit_cmpimm(HOST_TEMPREG,0x1000);
3258 // do usual RAM check, jump will go to the right handler
3265 emit_cmpimm(addr,RAM_SIZE);
3267 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3268 // Hint to branch predictor that the branch is unlikely to be taken
3270 emit_jno_unlikely(0);
3275 emit_addimm(addr,ram_offset,HOST_TEMPREG);
3276 addr=*addr_reg_override=HOST_TEMPREG;
3283 #define shift_assemble shift_assemble_arm
3285 static void loadlr_assemble_arm(int i,struct regstat *i_regs)
3287 int s,th,tl,temp,temp2,addr,map=-1;
3290 int memtarget=0,c=0;
3291 int fastload_reg_override=0;
3293 th=get_reg(i_regs->regmap,rt1[i]|64);
3294 tl=get_reg(i_regs->regmap,rt1[i]);
3295 s=get_reg(i_regs->regmap,rs1[i]);
3296 temp=get_reg(i_regs->regmap,-1);
3297 temp2=get_reg(i_regs->regmap,FTEMP);
3298 addr=get_reg(i_regs->regmap,AGEN1+(i&1));
3301 for(hr=0;hr<HOST_REGS;hr++) {
3302 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3305 if(offset||s<0||c) addr=temp2;
3308 c=(i_regs->wasconst>>s)&1;
3310 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3315 map=get_reg(i_regs->regmap,ROREG);
3316 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3318 emit_shlimm(addr,3,temp);
3319 if (opcode[i]==0x22||opcode[i]==0x26) {
3320 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
3322 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
3324 jaddr=emit_fastpath_cmp_jump(i,temp2,&fastload_reg_override);
3327 if(ram_offset&&memtarget) {
3328 emit_addimm(temp2,ram_offset,HOST_TEMPREG);
3329 fastload_reg_override=HOST_TEMPREG;
3331 if (opcode[i]==0x22||opcode[i]==0x26) {
3332 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
3334 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
3337 if (opcode[i]==0x22||opcode[i]==0x26) { // LWL/LWR
3340 if(fastload_reg_override) a=fastload_reg_override;
3341 //emit_readword_indexed((int)rdram-0x80000000,temp2,temp2);
3342 emit_readword_indexed_tlb(0,a,map,temp2);
3343 if(jaddr) add_stub(LOADW_STUB,jaddr,(int)out,i,temp2,(int)i_regs,ccadj[i],reglist);
3346 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj[i],reglist);
3349 emit_andimm(temp,24,temp);
3350 #ifdef BIG_ENDIAN_MIPS
3351 if (opcode[i]==0x26) // LWR
3353 if (opcode[i]==0x22) // LWL
3355 emit_xorimm(temp,24,temp);
3356 emit_movimm(-1,HOST_TEMPREG);
3357 if (opcode[i]==0x26) {
3358 emit_shr(temp2,temp,temp2);
3359 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
3361 emit_shl(temp2,temp,temp2);
3362 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
3364 emit_or(temp2,tl,tl);
3366 //emit_storereg(rt1[i],tl); // DEBUG
3368 if (opcode[i]==0x1A||opcode[i]==0x1B) { // LDL/LDR
3369 // FIXME: little endian, fastload_reg_override
3370 int temp2h=get_reg(i_regs->regmap,FTEMP|64);
3372 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,temp2,temp2h);
3373 //emit_readword_indexed((int)rdram-0x7FFFFFFC,temp2,temp2);
3374 emit_readdword_indexed_tlb(0,temp2,map,temp2h,temp2);
3375 if(jaddr) add_stub(LOADD_STUB,jaddr,(int)out,i,temp2,(int)i_regs,ccadj[i],reglist);
3378 inline_readstub(LOADD_STUB,i,(constmap[i][s]+offset)&0xFFFFFFF8,i_regs->regmap,FTEMP,ccadj[i],reglist);
3382 emit_testimm(temp,32);
3383 emit_andimm(temp,24,temp);
3384 if (opcode[i]==0x1A) { // LDL
3385 emit_rsbimm(temp,32,HOST_TEMPREG);
3386 emit_shl(temp2h,temp,temp2h);
3387 emit_orrshr(temp2,HOST_TEMPREG,temp2h);
3388 emit_movimm(-1,HOST_TEMPREG);
3389 emit_shl(temp2,temp,temp2);
3390 emit_cmove_reg(temp2h,th);
3391 emit_biceq_lsl(tl,HOST_TEMPREG,temp,tl);
3392 emit_bicne_lsl(th,HOST_TEMPREG,temp,th);
3393 emit_orreq(temp2,tl,tl);
3394 emit_orrne(temp2,th,th);
3396 if (opcode[i]==0x1B) { // LDR
3397 emit_xorimm(temp,24,temp);
3398 emit_rsbimm(temp,32,HOST_TEMPREG);
3399 emit_shr(temp2,temp,temp2);
3400 emit_orrshl(temp2h,HOST_TEMPREG,temp2);
3401 emit_movimm(-1,HOST_TEMPREG);
3402 emit_shr(temp2h,temp,temp2h);
3403 emit_cmovne_reg(temp2,tl);
3404 emit_bicne_lsr(th,HOST_TEMPREG,temp,th);
3405 emit_biceq_lsr(tl,HOST_TEMPREG,temp,tl);
3406 emit_orrne(temp2h,th,th);
3407 emit_orreq(temp2h,tl,tl);
3412 #define loadlr_assemble loadlr_assemble_arm
3414 static void cop0_assemble(int i,struct regstat *i_regs)
3416 if(opcode2[i]==0) // MFC0
3418 signed char t=get_reg(i_regs->regmap,rt1[i]);
3419 char copr=(source[i]>>11)&0x1f;
3420 //assert(t>=0); // Why does this happen? OOT is weird
3421 if(t>=0&&rt1[i]!=0) {
3422 emit_readword((int)®_cop0+copr*4,t);
3425 else if(opcode2[i]==4) // MTC0
3427 signed char s=get_reg(i_regs->regmap,rs1[i]);
3428 char copr=(source[i]>>11)&0x1f;
3430 wb_register(rs1[i],i_regs->regmap,i_regs->dirty,i_regs->is32);
3431 if(copr==9||copr==11||copr==12||copr==13) {
3432 emit_readword((int)&last_count,HOST_TEMPREG);
3433 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3434 emit_add(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3435 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
3436 emit_writeword(HOST_CCREG,(int)&Count);
3438 // What a mess. The status register (12) can enable interrupts,
3439 // so needs a special case to handle a pending interrupt.
3440 // The interrupt must be taken immediately, because a subsequent
3441 // instruction might disable interrupts again.
3442 if(copr==12||copr==13) {
3444 // burn cycles to cause cc_interrupt, which will
3445 // reschedule next_interupt. Relies on CCREG from above.
3446 assem_debug("MTC0 DS %d\n", copr);
3447 emit_writeword(HOST_CCREG,(int)&last_count);
3448 emit_movimm(0,HOST_CCREG);
3449 emit_storereg(CCREG,HOST_CCREG);
3450 emit_loadreg(rs1[i],1);
3451 emit_movimm(copr,0);
3452 emit_call((int)pcsx_mtc0_ds);
3453 emit_loadreg(rs1[i],s);
3456 emit_movimm(start+i*4+4,HOST_TEMPREG);
3457 emit_writeword(HOST_TEMPREG,(int)&pcaddr);
3458 emit_movimm(0,HOST_TEMPREG);
3459 emit_writeword(HOST_TEMPREG,(int)&pending_exception);
3461 //else if(copr==12&&is_delayslot) emit_call((int)MTC0_R12);
3464 emit_loadreg(rs1[i],1);
3467 emit_movimm(copr,0);
3468 emit_call((int)pcsx_mtc0);
3469 if(copr==9||copr==11||copr==12||copr==13) {
3470 emit_readword((int)&Count,HOST_CCREG);
3471 emit_readword((int)&next_interupt,HOST_TEMPREG);
3472 emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
3473 emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3474 emit_writeword(HOST_TEMPREG,(int)&last_count);
3475 emit_storereg(CCREG,HOST_CCREG);
3477 if(copr==12||copr==13) {
3478 assert(!is_delayslot);
3479 emit_readword((int)&pending_exception,14);
3481 emit_jne((int)&do_interrupt);
3483 emit_loadreg(rs1[i],s);
3484 if(get_reg(i_regs->regmap,rs1[i]|64)>=0)
3485 emit_loadreg(rs1[i]|64,get_reg(i_regs->regmap,rs1[i]|64));
3490 assert(opcode2[i]==0x10);
3491 if((source[i]&0x3f)==0x10) // RFE
3493 emit_readword((int)&Status,0);
3494 emit_andimm(0,0x3c,1);
3495 emit_andimm(0,~0xf,0);
3496 emit_orrshr_imm(1,2,0);
3497 emit_writeword(0,(int)&Status);
3502 static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3512 emit_readword((int)®_cop2d[copr],tl);
3513 emit_signextend16(tl,tl);
3514 emit_writeword(tl,(int)®_cop2d[copr]); // hmh
3521 emit_readword((int)®_cop2d[copr],tl);
3522 emit_andimm(tl,0xffff,tl);
3523 emit_writeword(tl,(int)®_cop2d[copr]);
3526 emit_readword((int)®_cop2d[14],tl); // SXY2
3527 emit_writeword(tl,(int)®_cop2d[copr]);
3531 emit_readword((int)®_cop2d[9],temp);
3532 emit_testimm(temp,0x8000); // do we need this?
3533 emit_andimm(temp,0xf80,temp);
3534 emit_andne_imm(temp,0,temp);
3535 emit_shrimm(temp,7,tl);
3536 emit_readword((int)®_cop2d[10],temp);
3537 emit_testimm(temp,0x8000);
3538 emit_andimm(temp,0xf80,temp);
3539 emit_andne_imm(temp,0,temp);
3540 emit_orrshr_imm(temp,2,tl);
3541 emit_readword((int)®_cop2d[11],temp);
3542 emit_testimm(temp,0x8000);
3543 emit_andimm(temp,0xf80,temp);
3544 emit_andne_imm(temp,0,temp);
3545 emit_orrshl_imm(temp,3,tl);
3546 emit_writeword(tl,(int)®_cop2d[copr]);
3549 emit_readword((int)®_cop2d[copr],tl);
3554 static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3558 emit_readword((int)®_cop2d[13],temp); // SXY1
3559 emit_writeword(sl,(int)®_cop2d[copr]);
3560 emit_writeword(temp,(int)®_cop2d[12]); // SXY0
3561 emit_readword((int)®_cop2d[14],temp); // SXY2
3562 emit_writeword(sl,(int)®_cop2d[14]);
3563 emit_writeword(temp,(int)®_cop2d[13]); // SXY1
3566 emit_andimm(sl,0x001f,temp);
3567 emit_shlimm(temp,7,temp);
3568 emit_writeword(temp,(int)®_cop2d[9]);
3569 emit_andimm(sl,0x03e0,temp);
3570 emit_shlimm(temp,2,temp);
3571 emit_writeword(temp,(int)®_cop2d[10]);
3572 emit_andimm(sl,0x7c00,temp);
3573 emit_shrimm(temp,3,temp);
3574 emit_writeword(temp,(int)®_cop2d[11]);
3575 emit_writeword(sl,(int)®_cop2d[28]);
3579 emit_mvnmi(temp,temp);
3581 emit_clz(temp,temp);
3583 emit_movs(temp,HOST_TEMPREG);
3584 emit_movimm(0,temp);
3585 emit_jeq((int)out+4*4);
3586 emit_addpl_imm(temp,1,temp);
3587 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3588 emit_jns((int)out-2*4);
3590 emit_writeword(sl,(int)®_cop2d[30]);
3591 emit_writeword(temp,(int)®_cop2d[31]);
3596 emit_writeword(sl,(int)®_cop2d[copr]);
3601 static void cop2_assemble(int i,struct regstat *i_regs)
3603 u_int copr=(source[i]>>11)&0x1f;
3604 signed char temp=get_reg(i_regs->regmap,-1);
3605 if (opcode2[i]==0) { // MFC2
3606 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3607 if(tl>=0&&rt1[i]!=0)
3608 cop2_get_dreg(copr,tl,temp);
3610 else if (opcode2[i]==4) { // MTC2
3611 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3612 cop2_put_dreg(copr,sl,temp);
3614 else if (opcode2[i]==2) // CFC2
3616 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3617 if(tl>=0&&rt1[i]!=0)
3618 emit_readword((int)®_cop2c[copr],tl);
3620 else if (opcode2[i]==6) // CTC2
3622 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3631 emit_signextend16(sl,temp);
3634 //value = value & 0x7ffff000;
3635 //if (value & 0x7f87e000) value |= 0x80000000;
3636 emit_shrimm(sl,12,temp);
3637 emit_shlimm(temp,12,temp);
3638 emit_testimm(temp,0x7f000000);
3639 emit_testeqimm(temp,0x00870000);
3640 emit_testeqimm(temp,0x0000e000);
3641 emit_orrne_imm(temp,0x80000000,temp);
3647 emit_writeword(temp,(int)®_cop2c[copr]);
3652 static void c2op_prologue(u_int op,u_int reglist)
3654 save_regs_all(reglist);
3657 emit_call((int)pcnt_gte_start);
3659 emit_addimm(FP,(int)&psxRegs.CP2D.r[0]-(int)&dynarec_local,0); // cop2 regs
3662 static void c2op_epilogue(u_int op,u_int reglist)
3666 emit_call((int)pcnt_gte_end);
3668 restore_regs_all(reglist);
3671 static void c2op_call_MACtoIR(int lm,int need_flags)
3674 emit_call((int)(lm?gteMACtoIR_lm1:gteMACtoIR_lm0));
3676 emit_call((int)(lm?gteMACtoIR_lm1_nf:gteMACtoIR_lm0_nf));
3679 static void c2op_call_rgb_func(void *func,int lm,int need_ir,int need_flags)
3681 emit_call((int)func);
3682 // func is C code and trashes r0
3683 emit_addimm(FP,(int)&psxRegs.CP2D.r[0]-(int)&dynarec_local,0);
3684 if(need_flags||need_ir)
3685 c2op_call_MACtoIR(lm,need_flags);
3686 emit_call((int)(need_flags?gteMACtoRGB:gteMACtoRGB_nf));
3689 static void c2op_assemble(int i,struct regstat *i_regs)
3691 u_int c2op=source[i]&0x3f;
3692 u_int hr,reglist_full=0,reglist;
3693 int need_flags,need_ir;
3694 for(hr=0;hr<HOST_REGS;hr++) {
3695 if(i_regs->regmap[hr]>=0) reglist_full|=1<<hr;
3697 reglist=reglist_full&CALLER_SAVE_REGS;
3699 if (gte_handlers[c2op]!=NULL) {
3700 need_flags=!(gte_unneeded[i+1]>>63); // +1 because of how liveness detection works
3701 need_ir=(gte_unneeded[i+1]&0xe00)!=0xe00;
3702 assem_debug("gte op %08x, unneeded %016llx, need_flags %d, need_ir %d\n",
3703 source[i],gte_unneeded[i+1],need_flags,need_ir);
3704 if(new_dynarec_hacks&NDHACK_GTE_NO_FLAGS)
3706 int shift = (source[i] >> 19) & 1;
3707 int lm = (source[i] >> 10) & 1;
3712 int v = (source[i] >> 15) & 3;
3713 int cv = (source[i] >> 13) & 3;
3714 int mx = (source[i] >> 17) & 3;
3715 reglist=reglist_full&(CALLER_SAVE_REGS|0xf0); // +{r4-r7}
3716 c2op_prologue(c2op,reglist);
3717 /* r4,r5 = VXYZ(v) packed; r6 = &MX11(mx); r7 = &CV1(cv) */
3721 emit_movzwl_indexed(9*4,0,4); // gteIR
3722 emit_movzwl_indexed(10*4,0,6);
3723 emit_movzwl_indexed(11*4,0,5);
3724 emit_orrshl_imm(6,16,4);
3727 emit_addimm(0,32*4+mx*8*4,6);
3729 emit_readword((int)&zeromem_ptr,6);
3731 emit_addimm(0,32*4+(cv*8+5)*4,7);
3733 emit_readword((int)&zeromem_ptr,7);
3735 emit_movimm(source[i],1); // opcode
3736 emit_call((int)gteMVMVA_part_neon);
3739 emit_call((int)gteMACtoIR_flags_neon);
3743 emit_call((int)gteMVMVA_part_cv3sh12_arm);
3745 emit_movimm(shift,1);
3746 emit_call((int)(need_flags?gteMVMVA_part_arm:gteMVMVA_part_nf_arm));
3748 if(need_flags||need_ir)
3749 c2op_call_MACtoIR(lm,need_flags);
3751 #else /* if not HAVE_ARMV5 */
3752 c2op_prologue(c2op,reglist);
3753 emit_movimm(source[i],1); // opcode
3754 emit_writeword(1,(int)&psxRegs.code);
3755 emit_call((int)(need_flags?gte_handlers[c2op]:gte_handlers_nf[c2op]));
3760 c2op_prologue(c2op,reglist);
3761 emit_call((int)(shift?gteOP_part_shift:gteOP_part_noshift));
3762 if(need_flags||need_ir) {
3763 emit_addimm(FP,(int)&psxRegs.CP2D.r[0]-(int)&dynarec_local,0);
3764 c2op_call_MACtoIR(lm,need_flags);
3768 c2op_prologue(c2op,reglist);
3769 c2op_call_rgb_func(shift?gteDPCS_part_shift:gteDPCS_part_noshift,lm,need_ir,need_flags);
3772 c2op_prologue(c2op,reglist);
3773 c2op_call_rgb_func(shift?gteINTPL_part_shift:gteINTPL_part_noshift,lm,need_ir,need_flags);
3776 c2op_prologue(c2op,reglist);
3777 emit_call((int)(shift?gteSQR_part_shift:gteSQR_part_noshift));
3778 if(need_flags||need_ir) {
3779 emit_addimm(FP,(int)&psxRegs.CP2D.r[0]-(int)&dynarec_local,0);
3780 c2op_call_MACtoIR(lm,need_flags);
3784 c2op_prologue(c2op,reglist);
3785 c2op_call_rgb_func(gteDCPL_part,lm,need_ir,need_flags);
3788 c2op_prologue(c2op,reglist);
3789 c2op_call_rgb_func(shift?gteGPF_part_shift:gteGPF_part_noshift,lm,need_ir,need_flags);
3792 c2op_prologue(c2op,reglist);
3793 c2op_call_rgb_func(shift?gteGPL_part_shift:gteGPL_part_noshift,lm,need_ir,need_flags);
3797 c2op_prologue(c2op,reglist);
3799 emit_movimm(source[i],1); // opcode
3800 emit_writeword(1,(int)&psxRegs.code);
3802 emit_call((int)(need_flags?gte_handlers[c2op]:gte_handlers_nf[c2op]));
3805 c2op_epilogue(c2op,reglist);
3809 static void cop1_unusable(int i,struct regstat *i_regs)
3811 // XXX: should just just do the exception instead
3815 add_stub(FP_STUB,jaddr,(int)out,i,0,(int)i_regs,is_delayslot,0);
3820 static void cop1_assemble(int i,struct regstat *i_regs)
3822 cop1_unusable(i, i_regs);
3825 static void fconv_assemble_arm(int i,struct regstat *i_regs)
3827 cop1_unusable(i, i_regs);
3829 #define fconv_assemble fconv_assemble_arm
3831 static void fcomp_assemble(int i,struct regstat *i_regs)
3833 cop1_unusable(i, i_regs);
3836 static void float_assemble(int i,struct regstat *i_regs)
3838 cop1_unusable(i, i_regs);
3841 static void multdiv_assemble_arm(int i,struct regstat *i_regs)
3848 // case 0x1D: DMULTU
3853 if((opcode2[i]&4)==0) // 32-bit
3855 if(opcode2[i]==0x18) // MULT
3857 signed char m1=get_reg(i_regs->regmap,rs1[i]);
3858 signed char m2=get_reg(i_regs->regmap,rs2[i]);
3859 signed char hi=get_reg(i_regs->regmap,HIREG);
3860 signed char lo=get_reg(i_regs->regmap,LOREG);
3865 emit_smull(m1,m2,hi,lo);
3867 if(opcode2[i]==0x19) // MULTU
3869 signed char m1=get_reg(i_regs->regmap,rs1[i]);
3870 signed char m2=get_reg(i_regs->regmap,rs2[i]);
3871 signed char hi=get_reg(i_regs->regmap,HIREG);
3872 signed char lo=get_reg(i_regs->regmap,LOREG);
3877 emit_umull(m1,m2,hi,lo);
3879 if(opcode2[i]==0x1A) // DIV
3881 signed char d1=get_reg(i_regs->regmap,rs1[i]);
3882 signed char d2=get_reg(i_regs->regmap,rs2[i]);
3885 signed char quotient=get_reg(i_regs->regmap,LOREG);
3886 signed char remainder=get_reg(i_regs->regmap,HIREG);
3887 assert(quotient>=0);
3888 assert(remainder>=0);
3889 emit_movs(d1,remainder);
3890 emit_movimm(0xffffffff,quotient);
3891 emit_negmi(quotient,quotient); // .. quotient and ..
3892 emit_negmi(remainder,remainder); // .. remainder for div0 case (will be negated back after jump)
3893 emit_movs(d2,HOST_TEMPREG);
3894 emit_jeq((int)out+52); // Division by zero
3895 emit_negsmi(HOST_TEMPREG,HOST_TEMPREG);
3897 emit_clz(HOST_TEMPREG,quotient);
3898 emit_shl(HOST_TEMPREG,quotient,HOST_TEMPREG);
3900 emit_movimm(0,quotient);
3901 emit_addpl_imm(quotient,1,quotient);
3902 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3903 emit_jns((int)out-2*4);
3905 emit_orimm(quotient,1<<31,quotient);
3906 emit_shr(quotient,quotient,quotient);
3907 emit_cmp(remainder,HOST_TEMPREG);
3908 emit_subcs(remainder,HOST_TEMPREG,remainder);
3909 emit_adcs(quotient,quotient,quotient);
3910 emit_shrimm(HOST_TEMPREG,1,HOST_TEMPREG);
3911 emit_jcc((int)out-16); // -4
3913 emit_negmi(quotient,quotient);
3915 emit_negmi(remainder,remainder);
3917 if(opcode2[i]==0x1B) // DIVU
3919 signed char d1=get_reg(i_regs->regmap,rs1[i]); // dividend
3920 signed char d2=get_reg(i_regs->regmap,rs2[i]); // divisor
3923 signed char quotient=get_reg(i_regs->regmap,LOREG);
3924 signed char remainder=get_reg(i_regs->regmap,HIREG);
3925 assert(quotient>=0);
3926 assert(remainder>=0);
3927 emit_mov(d1,remainder);
3928 emit_movimm(0xffffffff,quotient); // div0 case
3930 emit_jeq((int)out+40); // Division by zero
3932 emit_clz(d2,HOST_TEMPREG);
3933 emit_movimm(1<<31,quotient);
3934 emit_shl(d2,HOST_TEMPREG,d2);
3936 emit_movimm(0,HOST_TEMPREG);
3937 emit_addpl_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3938 emit_lslpls_imm(d2,1,d2);
3939 emit_jns((int)out-2*4);
3940 emit_movimm(1<<31,quotient);
3942 emit_shr(quotient,HOST_TEMPREG,quotient);
3943 emit_cmp(remainder,d2);
3944 emit_subcs(remainder,d2,remainder);
3945 emit_adcs(quotient,quotient,quotient);
3946 emit_shrcc_imm(d2,1,d2);
3947 emit_jcc((int)out-16); // -4
3955 // Multiply by zero is zero.
3956 // MIPS does not have a divide by zero exception.
3957 // The result is undefined, we return zero.
3958 signed char hr=get_reg(i_regs->regmap,HIREG);
3959 signed char lr=get_reg(i_regs->regmap,LOREG);
3960 if(hr>=0) emit_zeroreg(hr);
3961 if(lr>=0) emit_zeroreg(lr);
3964 #define multdiv_assemble multdiv_assemble_arm
3966 static void do_preload_rhash(int r) {
3967 // Don't need this for ARM. On x86, this puts the value 0xf8 into the
3968 // register. On ARM the hash can be done with a single instruction (below)
3971 static void do_preload_rhtbl(int ht) {
3972 emit_addimm(FP,(int)&mini_ht-(int)&dynarec_local,ht);
3975 static void do_rhash(int rs,int rh) {
3976 emit_andimm(rs,0xf8,rh);
3979 static void do_miniht_load(int ht,int rh) {
3980 assem_debug("ldr %s,[%s,%s]!\n",regname[rh],regname[ht],regname[rh]);
3981 output_w32(0xe7b00000|rd_rn_rm(rh,ht,rh));
3984 static void do_miniht_jump(int rs,int rh,int ht) {
3986 emit_ldreq_indexed(ht,4,15);
3987 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3989 emit_jmp(jump_vaddr_reg[7]);
3991 emit_jmp(jump_vaddr_reg[rs]);
3995 static void do_miniht_insert(u_int return_address,int rt,int temp) {
3997 emit_movimm(return_address,rt); // PC into link register
3998 add_to_linker((int)out,return_address,1);
3999 emit_pcreladdr(temp);
4000 emit_writeword(rt,(int)&mini_ht[(return_address&0xFF)>>3][0]);
4001 emit_writeword(temp,(int)&mini_ht[(return_address&0xFF)>>3][1]);
4003 emit_movw(return_address&0x0000FFFF,rt);
4004 add_to_linker((int)out,return_address,1);
4005 emit_pcreladdr(temp);
4006 emit_writeword(temp,(int)&mini_ht[(return_address&0xFF)>>3][1]);
4007 emit_movt(return_address&0xFFFF0000,rt);
4008 emit_writeword(rt,(int)&mini_ht[(return_address&0xFF)>>3][0]);
4012 static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t is32_pre,uint64_t u,uint64_t uu)
4014 //if(dirty_pre==dirty) return;
4016 for(hr=0;hr<HOST_REGS;hr++) {
4017 if(hr!=EXCLUDE_REG) {
4019 if(((~u)>>(reg&63))&1) {
4021 if(((dirty_pre&~dirty)>>hr)&1) {
4023 emit_storereg(reg,hr);
4024 if( ((is32_pre&~uu)>>reg)&1 ) {
4025 emit_sarimm(hr,31,HOST_TEMPREG);
4026 emit_storereg(reg|64,HOST_TEMPREG);
4030 emit_storereg(reg,hr);
4040 /* using strd could possibly help but you'd have to allocate registers in pairs
4041 static void wb_invalidate_arm(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,uint64_t u,uint64_t uu)
4045 for(hr=HOST_REGS-1;hr>=0;hr--) {
4046 if(hr!=EXCLUDE_REG) {
4047 if(pre[hr]!=entry[hr]) {
4050 if(get_reg(entry,pre[hr])<0) {
4052 if(!((u>>pre[hr])&1)) {
4053 if(hr<10&&(~hr&1)&&(pre[hr+1]<0||wrote==hr+1)) {
4054 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4055 emit_sarimm(hr,31,hr+1);
4056 emit_strdreg(pre[hr],hr);
4059 emit_storereg(pre[hr],hr);
4061 emit_storereg(pre[hr],hr);
4062 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4063 emit_sarimm(hr,31,hr);
4064 emit_storereg(pre[hr]|64,hr);
4069 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
4070 emit_storereg(pre[hr],hr);
4080 for(hr=0;hr<HOST_REGS;hr++) {
4081 if(hr!=EXCLUDE_REG) {
4082 if(pre[hr]!=entry[hr]) {
4085 if((nr=get_reg(entry,pre[hr]))>=0) {
4093 #define wb_invalidate wb_invalidate_arm
4096 static void mark_clear_cache(void *target)
4098 u_long offset = (char *)target - (char *)BASE_ADDR;
4099 u_int mask = 1u << ((offset >> 12) & 31);
4100 if (!(needs_clear_cache[offset >> 17] & mask)) {
4101 char *start = (char *)((u_long)target & ~4095ul);
4102 start_tcache_write(start, start + 4096);
4103 needs_clear_cache[offset >> 17] |= mask;
4107 // Clearing the cache is rather slow on ARM Linux, so mark the areas
4108 // that need to be cleared, and then only clear these areas once.
4109 static void do_clear_cache()
4112 for (i=0;i<(1<<(TARGET_SIZE_2-17));i++)
4114 u_int bitmap=needs_clear_cache[i];
4120 start=(u_int)BASE_ADDR+i*131072+j*4096;
4128 end_tcache_write((void *)start,(void *)end);
4134 needs_clear_cache[i]=0;
4139 // CPU-architecture-specific initialization
4140 static void arch_init() {
4143 // vim:shiftwidth=2:expandtab