1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * linkage_arm.s for PCSX *
3 * Copyright (C) 2009-2011 Ari64 *
4 * Copyright (C) 2010-2013 GraÅžvydas "notaz" Ignotas *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
20 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include "arm_features.h"
23 #include "../new_dynarec_config.h"
24 #include "linkage_offsets.h"
28 #define dynarec_local ESYM(dynarec_local)
29 #define add_link ESYM(add_link)
30 #define new_recompile_block ESYM(new_recompile_block)
31 #define get_addr ESYM(get_addr)
32 #define get_addr_ht ESYM(get_addr_ht)
33 #define clean_blocks ESYM(clean_blocks)
34 #define gen_interupt ESYM(gen_interupt)
35 #define psxException ESYM(psxException)
36 #define execI ESYM(execI)
37 #define invalidate_addr ESYM(invalidate_addr)
43 .type dynarec_local, %object
44 .size dynarec_local, LO_dynarec_local_size
46 .space LO_dynarec_local_size
48 #define DRC_VAR_(name, vname, size_) \
49 vname = dynarec_local + LO_##name; \
51 .type vname, %object; \
54 #define DRC_VAR(name, size_) \
55 DRC_VAR_(name, ESYM(name), size_)
57 DRC_VAR(next_interupt, 4)
58 DRC_VAR(cycle_count, 4)
59 DRC_VAR(last_count, 4)
60 DRC_VAR(pending_exception, 4)
64 DRC_VAR(psxRegs, LO_psxRegs_end - LO_psxRegs)
70 DRC_VAR(reg_cop0, 128)
71 DRC_VAR(reg_cop2d, 128)
72 DRC_VAR(reg_cop2c, 128)
76 @DRC_VAR(interrupt, 4)
77 @DRC_VAR(intCycle, 256)
83 DRC_VAR(zeromem_ptr, 4)
84 DRC_VAR(inv_code_start, 4)
85 DRC_VAR(inv_code_end, 4)
86 DRC_VAR(branch_target, 4)
87 DRC_VAR(scratch_buf_ptr, 4)
88 @DRC_VAR(align0, 12) /* unused/alignment */
90 DRC_VAR(restore_candidate, 512)
102 .word ESYM(jump_dirty)
104 .word ESYM(hash_table)
119 .macro load_varadr reg var
120 #if defined(HAVE_ARMV7) && !defined(__PIC__)
121 movw \reg, #:lower16:\var
122 movt \reg, #:upper16:\var
123 #elif defined(HAVE_ARMV7) && defined(__MACH__)
124 movw \reg, #:lower16:(\var-(1678f+8))
125 movt \reg, #:upper16:(\var-(1678f+8))
133 .macro load_varadr_ext reg var
134 #if defined(HAVE_ARMV7) && defined(__MACH__) && defined(__PIC__)
135 movw \reg, #:lower16:(ptr_\var-(1678f+8))
136 movt \reg, #:upper16:(ptr_\var-(1678f+8))
140 load_varadr \reg \var
144 .macro mov_16 reg imm
148 mov \reg, #(\imm & 0x00ff)
149 orr \reg, #(\imm & 0xff00)
153 .macro mov_24 reg imm
155 movw \reg, #(\imm & 0xffff)
156 movt \reg, #(\imm >> 16)
158 mov \reg, #(\imm & 0x0000ff)
159 orr \reg, #(\imm & 0x00ff00)
160 orr \reg, #(\imm & 0xff0000)
164 /* r0 = virtual target address */
165 /* r1 = instruction to patch */
166 .macro dyna_linker_main
167 #ifndef NO_WRITE_EXEC
168 load_varadr_ext r3, jump_in
181 ldr r5, [r3, r2, lsl #2]
183 add r6, r1, r12, asr #6
189 ldr r3, [r5] /* ll_entry .vaddr */
190 ldrd r4, r5, [r4, #8] /* ll_entry .next, .addr */
194 moveq pc, r4 /* Stale i-cache */
196 b 1b /* jump_in may have dupes, continue search */
199 beq 3f /* r0 not in jump_in */
205 and r1, r7, #0xff000000
208 add r1, r1, r2, lsr #8
212 /* hash_table lookup */
214 load_varadr_ext r3, jump_dirty
215 eor r4, r0, r0, lsl #16
217 load_varadr_ext r6, hash_table
221 ldr r5, [r3, r2, lsl #2]
228 /* jump_dirty lookup */
238 /* hash_table insert */
248 /* XXX: should be able to do better than this... */
255 FUNCTION(dyna_linker):
256 /* r0 = virtual target address */
257 /* r1 = instruction to patch */
262 bl new_recompile_block
270 .size dyna_linker, .-dyna_linker
272 FUNCTION(exec_pagefault):
273 /* r0 = instruction pointer */
274 /* r1 = fault address */
276 ldr r3, [fp, #LO_reg_cop0+48] /* Status */
278 ldr r4, [fp, #LO_reg_cop0+16] /* Context */
279 bic r6, r6, #0x0F800000
280 str r0, [fp, #LO_reg_cop0+56] /* EPC */
282 str r1, [fp, #LO_reg_cop0+32] /* BadVAddr */
284 str r3, [fp, #LO_reg_cop0+48] /* Status */
285 and r5, r6, r1, lsr #9
286 str r2, [fp, #LO_reg_cop0+52] /* Cause */
287 and r1, r1, r6, lsl #9
288 str r1, [fp, #LO_reg_cop0+40] /* EntryHi */
290 str r4, [fp, #LO_reg_cop0+16] /* Context */
294 .size exec_pagefault, .-exec_pagefault
296 /* Special dynamic linker for the case where a page fault
297 may occur in a branch delay slot */
298 FUNCTION(dyna_linker_ds):
299 /* r0 = virtual target address */
300 /* r1 = instruction to patch */
307 bl new_recompile_block
314 mov r2, #0x80000008 /* High bit set indicates pagefault in delay slot */
317 .size dyna_linker_ds, .-dyna_linker_ds
321 FUNCTION(jump_vaddr_r0):
322 eor r2, r0, r0, lsl #16
324 .size jump_vaddr_r0, .-jump_vaddr_r0
325 FUNCTION(jump_vaddr_r1):
326 eor r2, r1, r1, lsl #16
329 .size jump_vaddr_r1, .-jump_vaddr_r1
330 FUNCTION(jump_vaddr_r2):
332 eor r2, r2, r2, lsl #16
334 .size jump_vaddr_r2, .-jump_vaddr_r2
335 FUNCTION(jump_vaddr_r3):
336 eor r2, r3, r3, lsl #16
339 .size jump_vaddr_r3, .-jump_vaddr_r3
340 FUNCTION(jump_vaddr_r4):
341 eor r2, r4, r4, lsl #16
344 .size jump_vaddr_r4, .-jump_vaddr_r4
345 FUNCTION(jump_vaddr_r5):
346 eor r2, r5, r5, lsl #16
349 .size jump_vaddr_r5, .-jump_vaddr_r5
350 FUNCTION(jump_vaddr_r6):
351 eor r2, r6, r6, lsl #16
354 .size jump_vaddr_r6, .-jump_vaddr_r6
355 FUNCTION(jump_vaddr_r8):
356 eor r2, r8, r8, lsl #16
359 .size jump_vaddr_r8, .-jump_vaddr_r8
360 FUNCTION(jump_vaddr_r9):
361 eor r2, r9, r9, lsl #16
364 .size jump_vaddr_r9, .-jump_vaddr_r9
365 FUNCTION(jump_vaddr_r10):
366 eor r2, r10, r10, lsl #16
369 .size jump_vaddr_r10, .-jump_vaddr_r10
370 FUNCTION(jump_vaddr_r12):
371 eor r2, r12, r12, lsl #16
374 .size jump_vaddr_r12, .-jump_vaddr_r12
375 FUNCTION(jump_vaddr_r7):
376 eor r2, r7, r7, lsl #16
378 .size jump_vaddr_r7, .-jump_vaddr_r7
379 FUNCTION(jump_vaddr):
380 load_varadr_ext r1, hash_table
382 and r2, r3, r2, lsr #12
389 str r10, [fp, #LO_cycle_count]
391 ldr r10, [fp, #LO_cycle_count]
393 .size jump_vaddr, .-jump_vaddr
397 FUNCTION(verify_code_ds):
398 str r8, [fp, #LO_branch_target]
399 FUNCTION(verify_code_vm):
400 FUNCTION(verify_code):
428 ldr r8, [fp, #LO_branch_target]
433 .size verify_code, .-verify_code
434 .size verify_code_vm, .-verify_code_vm
437 FUNCTION(cc_interrupt):
438 ldr r0, [fp, #LO_last_count]
442 str r1, [fp, #LO_pending_exception]
443 and r2, r2, r10, lsr #17
444 add r3, fp, #LO_restore_candidate
445 str r10, [fp, #LO_cycle] /* PCSX cycles */
446 @@ str r10, [fp, #LO_reg_cop0+36] /* Count */
454 ldr r10, [fp, #LO_cycle]
455 ldr r0, [fp, #LO_next_interupt]
456 ldr r1, [fp, #LO_pending_exception]
457 ldr r2, [fp, #LO_stop]
458 str r0, [fp, #LO_last_count]
461 ldmfdne sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
465 ldr r0, [fp, #LO_pcaddr]
469 /* Move 'dirty' blocks to the 'clean' list */
480 .size cc_interrupt, .-cc_interrupt
483 FUNCTION(do_interrupt):
484 ldr r0, [fp, #LO_pcaddr]
488 .size do_interrupt, .-do_interrupt
491 FUNCTION(fp_exception):
494 ldr r1, [fp, #LO_reg_cop0+48] /* Status */
496 str r0, [fp, #LO_reg_cop0+56] /* EPC */
499 str r1, [fp, #LO_reg_cop0+48] /* Status */
500 str r2, [fp, #LO_reg_cop0+52] /* Cause */
504 .size fp_exception, .-fp_exception
506 FUNCTION(fp_exception_ds):
507 mov r2, #0x90000000 /* Set high bit if delay slot */
509 .size fp_exception_ds, .-fp_exception_ds
512 FUNCTION(jump_syscall):
513 ldr r1, [fp, #LO_reg_cop0+48] /* Status */
515 str r0, [fp, #LO_reg_cop0+56] /* EPC */
518 str r1, [fp, #LO_reg_cop0+48] /* Status */
519 str r2, [fp, #LO_reg_cop0+52] /* Cause */
523 .size jump_syscall, .-jump_syscall
527 FUNCTION(jump_syscall_hle):
528 str r0, [fp, #LO_pcaddr] /* PC must be set to EPC for psxException */
529 ldr r2, [fp, #LO_last_count]
530 mov r1, #0 /* in delay slot */
532 mov r0, #0x20 /* cause */
533 str r2, [fp, #LO_cycle] /* PCSX cycle counter */
536 /* note: psxException might do recursive recompiler call from it's HLE code,
537 * so be ready for this */
539 ldr r1, [fp, #LO_next_interupt]
540 ldr r10, [fp, #LO_cycle]
541 ldr r0, [fp, #LO_pcaddr]
543 str r1, [fp, #LO_last_count]
546 .size jump_syscall_hle, .-jump_syscall_hle
549 FUNCTION(jump_hlecall):
550 ldr r2, [fp, #LO_last_count]
551 str r0, [fp, #LO_pcaddr]
554 str r2, [fp, #LO_cycle] /* PCSX cycle counter */
556 .size jump_hlecall, .-jump_hlecall
559 FUNCTION(jump_intcall):
560 ldr r2, [fp, #LO_last_count]
561 str r0, [fp, #LO_pcaddr]
564 str r2, [fp, #LO_cycle] /* PCSX cycle counter */
566 .size jump_hlecall, .-jump_hlecall
569 FUNCTION(new_dyna_leave):
570 ldr r0, [fp, #LO_last_count]
573 str r10, [fp, #LO_cycle]
574 ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
575 .size new_dyna_leave, .-new_dyna_leave
578 FUNCTION(invalidate_addr_r0):
579 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
580 b invalidate_addr_call
581 .size invalidate_addr_r0, .-invalidate_addr_r0
583 FUNCTION(invalidate_addr_r1):
584 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
586 b invalidate_addr_call
587 .size invalidate_addr_r1, .-invalidate_addr_r1
589 FUNCTION(invalidate_addr_r2):
590 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
592 b invalidate_addr_call
593 .size invalidate_addr_r2, .-invalidate_addr_r2
595 FUNCTION(invalidate_addr_r3):
596 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
598 b invalidate_addr_call
599 .size invalidate_addr_r3, .-invalidate_addr_r3
601 FUNCTION(invalidate_addr_r4):
602 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
604 b invalidate_addr_call
605 .size invalidate_addr_r4, .-invalidate_addr_r4
607 FUNCTION(invalidate_addr_r5):
608 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
610 b invalidate_addr_call
611 .size invalidate_addr_r5, .-invalidate_addr_r5
613 FUNCTION(invalidate_addr_r6):
614 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
616 b invalidate_addr_call
617 .size invalidate_addr_r6, .-invalidate_addr_r6
619 FUNCTION(invalidate_addr_r7):
620 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
622 b invalidate_addr_call
623 .size invalidate_addr_r7, .-invalidate_addr_r7
625 FUNCTION(invalidate_addr_r8):
626 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
628 b invalidate_addr_call
629 .size invalidate_addr_r8, .-invalidate_addr_r8
631 FUNCTION(invalidate_addr_r9):
632 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
634 b invalidate_addr_call
635 .size invalidate_addr_r9, .-invalidate_addr_r9
637 FUNCTION(invalidate_addr_r10):
638 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
640 b invalidate_addr_call
641 .size invalidate_addr_r10, .-invalidate_addr_r10
643 FUNCTION(invalidate_addr_r12):
644 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
646 .size invalidate_addr_r12, .-invalidate_addr_r12
648 invalidate_addr_call:
649 ldr r12, [fp, #LO_inv_code_start]
650 ldr lr, [fp, #LO_inv_code_end]
654 ldmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, pc}
655 .size invalidate_addr_call, .-invalidate_addr_call
658 FUNCTION(new_dyna_start):
659 /* ip is stored to conform EABI alignment */
660 stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
661 load_varadr fp, dynarec_local
662 ldr r0, [fp, #LO_pcaddr]
664 ldr r1, [fp, #LO_next_interupt]
665 ldr r10, [fp, #LO_cycle]
666 str r1, [fp, #LO_last_count]
669 .size new_dyna_start, .-new_dyna_start
671 /* --------------------------------------- */
675 .macro pcsx_read_mem readop tab_shift
676 /* r0 = address, r1 = handler_tab, r2 = cycles */
678 lsr r3, #(20+\tab_shift)
679 ldr r12, [fp, #LO_last_count]
680 ldr r1, [r1, r3, lsl #2]
687 \readop r0, [r1, r3, lsl #\tab_shift]
690 str r2, [fp, #LO_cycle]
694 FUNCTION(jump_handler_read8):
695 add r1, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part
696 pcsx_read_mem ldrbcc, 0
698 FUNCTION(jump_handler_read16):
699 add r1, #0x1000/4*4 @ shift to r16 part
700 pcsx_read_mem ldrhcc, 1
702 FUNCTION(jump_handler_read32):
703 pcsx_read_mem ldrcc, 2
706 .macro pcsx_write_mem wrtop tab_shift
707 /* r0 = address, r1 = data, r2 = cycles, r3 = handler_tab */
709 lsr r12, #(20+\tab_shift)
710 ldr r3, [r3, r12, lsl #2]
711 str r0, [fp, #LO_address] @ some handlers still need it..
713 mov r0, r2 @ cycle return in case of direct store
718 \wrtop r1, [r3, r12, lsl #\tab_shift]
721 ldr r12, [fp, #LO_last_count]
725 str r2, [fp, #LO_cycle]
728 ldr r0, [fp, #LO_next_interupt]
730 str r0, [fp, #LO_last_count]
735 FUNCTION(jump_handler_write8):
736 add r3, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part
737 pcsx_write_mem strbcc, 0
739 FUNCTION(jump_handler_write16):
740 add r3, #0x1000/4*4 @ shift to r16 part
741 pcsx_write_mem strhcc, 1
743 FUNCTION(jump_handler_write32):
744 pcsx_write_mem strcc, 2
746 FUNCTION(jump_handler_write_h):
747 /* r0 = address, r1 = data, r2 = cycles, r3 = handler */
748 ldr r12, [fp, #LO_last_count]
749 str r0, [fp, #LO_address] @ some handlers still need it..
753 str r2, [fp, #LO_cycle]
756 ldr r0, [fp, #LO_next_interupt]
758 str r0, [fp, #LO_last_count]
762 FUNCTION(jump_handle_swl):
763 /* r0 = address, r1 = data, r2 = cycles */
764 ldr r3, [fp, #LO_mem_wtab]
766 ldr r3, [r3, r12, lsl #2]
787 lsreq r12, r1, #24 @ 0
797 FUNCTION(jump_handle_swr):
798 /* r0 = address, r1 = data, r2 = cycles */
799 ldr r3, [fp, #LO_mem_wtab]
801 ldr r3, [r3, r12, lsl #2]
823 .macro rcntx_read_mode0 num
824 /* r0 = address, r2 = cycles */
825 ldr r3, [fp, #LO_rcnts+6*4+7*4*\num] @ cycleStart
827 sub r0, r0, r3, lsl #16
832 FUNCTION(rcnt0_read_count_m0):
835 FUNCTION(rcnt1_read_count_m0):
838 FUNCTION(rcnt2_read_count_m0):
841 FUNCTION(rcnt0_read_count_m1):
842 /* r0 = address, r2 = cycles */
843 ldr r3, [fp, #LO_rcnts+6*4+7*4*0] @ cycleStart
846 mul r0, r1, r2 @ /= 5
850 FUNCTION(rcnt1_read_count_m1):
851 /* r0 = address, r2 = cycles */
852 ldr r3, [fp, #LO_rcnts+6*4+7*4*1]
855 umull r3, r0, r1, r2 @ ~ /= hsync_cycles, max ~0x1e6cdd
858 FUNCTION(rcnt2_read_count_m1):
859 /* r0 = address, r2 = cycles */
860 ldr r3, [fp, #LO_rcnts+6*4+7*4*2]
861 mov r0, r2, lsl #16-3
862 sub r0, r0, r3, lsl #16-3
866 @ vim:filetype=armasm