1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - assem_arm.c *
3 * Copyright (C) 2009-2010 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
21 extern int cycle_count;
22 extern int last_count;
24 extern int pending_exception;
25 extern int branch_target;
26 extern uint64_t readmem_dword;
28 extern precomp_instr fake_pc;
30 extern void *dynarec_local;
31 extern u_int memory_map[1048576];
32 extern u_int mini_ht[32][2];
33 extern u_int rounding_modes[4];
35 void indirect_jump_indexed();
48 void jump_vaddr_r10();
49 void jump_vaddr_r12();
51 const u_int jump_vaddr_reg[16] = {
73 void set_jump_target(int addr,u_int target)
75 u_char *ptr=(u_char *)addr;
76 u_int *ptr2=(u_int *)ptr;
78 assert((target-(u_int)ptr2-8)<1024);
80 assert((target&3)==0);
81 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>2)|0xF00;
82 //printf("target=%x addr=%x insn=%x\n",target,addr,*ptr2);
84 else if(ptr[3]==0x72) {
85 // generated by emit_jno_unlikely
86 if((target-(u_int)ptr2-8)<1024) {
88 assert((target&3)==0);
89 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>2)|0xF00;
91 else if((target-(u_int)ptr2-8)<4096&&!((target-(u_int)ptr2-8)&15)) {
93 assert((target&3)==0);
94 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>4)|0xE00;
96 else *ptr2=(0x7A000000)|(((target-(u_int)ptr2-8)<<6)>>8);
99 assert((ptr[3]&0x0e)==0xa);
100 *ptr2=(*ptr2&0xFF000000)|(((target-(u_int)ptr2-8)<<6)>>8);
104 // This optionally copies the instruction from the target of the branch into
105 // the space before the branch. Works, but the difference in speed is
106 // usually insignificant.
107 void set_jump_target_fillslot(int addr,u_int target,int copy)
109 u_char *ptr=(u_char *)addr;
110 u_int *ptr2=(u_int *)ptr;
111 assert(!copy||ptr2[-1]==0xe28dd000);
114 assert((target-(u_int)ptr2-8)<4096);
115 *ptr2=(*ptr2&0xFFFFF000)|(target-(u_int)ptr2-8);
118 assert((ptr[3]&0x0e)==0xa);
119 u_int target_insn=*(u_int *)target;
120 if((target_insn&0x0e100000)==0) { // ALU, no immediate, no flags
123 if((target_insn&0x0c100000)==0x04100000) { // Load
126 if(target_insn&0x08000000) {
130 ptr2[-1]=target_insn;
133 *ptr2=(*ptr2&0xFF000000)|(((target-(u_int)ptr2-8)<<6)>>8);
138 add_literal(int addr,int val)
140 literals[literalcount][0]=addr;
141 literals[literalcount][1]=val;
145 void *kill_pointer(void *stub)
147 int *ptr=(int *)(stub+4);
148 assert((*ptr&0x0ff00000)==0x05900000);
149 u_int offset=*ptr&0xfff;
150 int **l_ptr=(void *)ptr+offset+8;
152 set_jump_target((int)i_ptr,(int)stub);
156 int get_pointer(void *stub)
158 //printf("get_pointer(%x)\n",(int)stub);
159 int *ptr=(int *)(stub+4);
160 assert((*ptr&0x0ff00000)==0x05900000);
161 u_int offset=*ptr&0xfff;
162 int **l_ptr=(void *)ptr+offset+8;
164 assert((*i_ptr&0x0f000000)==0x0a000000);
165 return (int)i_ptr+((*i_ptr<<8)>>6)+8;
168 // Find the "clean" entry point from a "dirty" entry point
169 // by skipping past the call to verify_code
170 u_int get_clean_addr(int addr)
172 int *ptr=(int *)addr;
178 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
179 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
181 if((*ptr&0xFF000000)==0xea000000) {
182 return (int)ptr+((*ptr<<8)>>6)+8; // follow jump
187 int verify_dirty(int addr)
189 u_int *ptr=(u_int *)addr;
191 // get from literal pool
192 assert((*ptr&0xFFF00000)==0xe5900000);
193 u_int offset=*ptr&0xfff;
194 u_int *l_ptr=(void *)ptr+offset+8;
195 u_int source=l_ptr[0];
201 assert((*ptr&0xFFF00000)==0xe3000000);
202 u_int source=(ptr[0]&0xFFF)+((ptr[0]>>4)&0xF000)+((ptr[2]<<16)&0xFFF0000)+((ptr[2]<<12)&0xF0000000);
203 u_int copy=(ptr[1]&0xFFF)+((ptr[1]>>4)&0xF000)+((ptr[3]<<16)&0xFFF0000)+((ptr[3]<<12)&0xF0000000);
204 u_int len=(ptr[4]&0xFFF)+((ptr[4]>>4)&0xF000);
207 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
208 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
209 u_int verifier=(int)ptr+((signed int)(*ptr<<8)>>6)+8; // get target of bl
210 if(verifier==(u_int)verify_code_vm||verifier==(u_int)verify_code_ds) {
211 unsigned int page=source>>12;
212 unsigned int map_value=memory_map[page];
213 if(map_value>=0x80000000) return 0;
214 while(page<((source+len-1)>>12)) {
215 if((memory_map[++page]<<2)!=(map_value<<2)) return 0;
217 source = source+(map_value<<2);
219 //printf("verify_dirty: %x %x %x\n",source,copy,len);
220 return !memcmp((void *)source,(void *)copy,len);
223 // This doesn't necessarily find all clean entry points, just
224 // guarantees that it's not dirty
225 int isclean(int addr)
228 int *ptr=((u_int *)addr)+4;
230 int *ptr=((u_int *)addr)+6;
232 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
233 if((*ptr&0xFF000000)!=0xeb000000) return 1; // bl instruction
234 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code) return 0;
235 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code_vm) return 0;
236 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code_ds) return 0;
240 void get_bounds(int addr,u_int *start,u_int *end)
242 u_int *ptr=(u_int *)addr;
244 // get from literal pool
245 assert((*ptr&0xFFF00000)==0xe5900000);
246 u_int offset=*ptr&0xfff;
247 u_int *l_ptr=(void *)ptr+offset+8;
248 u_int source=l_ptr[0];
249 //u_int copy=l_ptr[1];
254 assert((*ptr&0xFFF00000)==0xe3000000);
255 u_int source=(ptr[0]&0xFFF)+((ptr[0]>>4)&0xF000)+((ptr[2]<<16)&0xFFF0000)+((ptr[2]<<12)&0xF0000000);
256 //u_int copy=(ptr[1]&0xFFF)+((ptr[1]>>4)&0xF000)+((ptr[3]<<16)&0xFFF0000)+((ptr[3]<<12)&0xF0000000);
257 u_int len=(ptr[4]&0xFFF)+((ptr[4]>>4)&0xF000);
260 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
261 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
262 u_int verifier=(int)ptr+((signed int)(*ptr<<8)>>6)+8; // get target of bl
263 if(verifier==(u_int)verify_code_vm||verifier==(u_int)verify_code_ds) {
264 if(memory_map[source>>12]>=0x80000000) source = 0;
265 else source = source+(memory_map[source>>12]<<2);
271 /* Register allocation */
273 // Note: registers are allocated clean (unmodified state)
274 // if you intend to modify the register, you must call dirty_reg().
275 void alloc_reg(struct regstat *cur,int i,signed char reg)
278 int preferred_reg = (reg&7);
279 if(reg==CCREG) preferred_reg=HOST_CCREG;
280 if(reg==PTEMP||reg==FTEMP) preferred_reg=12;
282 // Don't allocate unused registers
283 if((cur->u>>reg)&1) return;
285 // see if it's already allocated
286 for(hr=0;hr<HOST_REGS;hr++)
288 if(cur->regmap[hr]==reg) return;
291 // Keep the same mapping if the register was already allocated in a loop
292 preferred_reg = loop_reg(i,reg,preferred_reg);
294 // Try to allocate the preferred register
295 if(cur->regmap[preferred_reg]==-1) {
296 cur->regmap[preferred_reg]=reg;
297 cur->dirty&=~(1<<preferred_reg);
298 cur->isconst&=~(1<<preferred_reg);
301 r=cur->regmap[preferred_reg];
302 if(r<64&&((cur->u>>r)&1)) {
303 cur->regmap[preferred_reg]=reg;
304 cur->dirty&=~(1<<preferred_reg);
305 cur->isconst&=~(1<<preferred_reg);
308 if(r>=64&&((cur->uu>>(r&63))&1)) {
309 cur->regmap[preferred_reg]=reg;
310 cur->dirty&=~(1<<preferred_reg);
311 cur->isconst&=~(1<<preferred_reg);
315 // Clear any unneeded registers
316 // We try to keep the mapping consistent, if possible, because it
317 // makes branches easier (especially loops). So we try to allocate
318 // first (see above) before removing old mappings. If this is not
319 // possible then go ahead and clear out the registers that are no
321 for(hr=0;hr<HOST_REGS;hr++)
326 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
330 if((cur->uu>>(r&63))&1) {cur->regmap[hr]=-1;break;}
334 // Try to allocate any available register, but prefer
335 // registers that have not been used recently.
337 for(hr=0;hr<HOST_REGS;hr++) {
338 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
339 if(regs[i-1].regmap[hr]!=rs1[i-1]&®s[i-1].regmap[hr]!=rs2[i-1]&®s[i-1].regmap[hr]!=rt1[i-1]&®s[i-1].regmap[hr]!=rt2[i-1]) {
341 cur->dirty&=~(1<<hr);
342 cur->isconst&=~(1<<hr);
348 // Try to allocate any available register
349 for(hr=0;hr<HOST_REGS;hr++) {
350 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
352 cur->dirty&=~(1<<hr);
353 cur->isconst&=~(1<<hr);
358 // Ok, now we have to evict someone
359 // Pick a register we hopefully won't need soon
360 u_char hsn[MAXREG+1];
361 memset(hsn,10,sizeof(hsn));
363 lsn(hsn,i,&preferred_reg);
364 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
365 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
367 // Don't evict the cycle count at entry points, otherwise the entry
368 // stub will have to write it.
369 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
370 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
373 // Alloc preferred register if available
374 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
375 for(hr=0;hr<HOST_REGS;hr++) {
376 // Evict both parts of a 64-bit register
377 if((cur->regmap[hr]&63)==r) {
379 cur->dirty&=~(1<<hr);
380 cur->isconst&=~(1<<hr);
383 cur->regmap[preferred_reg]=reg;
386 for(r=1;r<=MAXREG;r++)
388 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
389 for(hr=0;hr<HOST_REGS;hr++) {
390 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
391 if(cur->regmap[hr]==r+64) {
393 cur->dirty&=~(1<<hr);
394 cur->isconst&=~(1<<hr);
399 for(hr=0;hr<HOST_REGS;hr++) {
400 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
401 if(cur->regmap[hr]==r) {
403 cur->dirty&=~(1<<hr);
404 cur->isconst&=~(1<<hr);
415 for(r=1;r<=MAXREG;r++)
418 for(hr=0;hr<HOST_REGS;hr++) {
419 if(cur->regmap[hr]==r+64) {
421 cur->dirty&=~(1<<hr);
422 cur->isconst&=~(1<<hr);
426 for(hr=0;hr<HOST_REGS;hr++) {
427 if(cur->regmap[hr]==r) {
429 cur->dirty&=~(1<<hr);
430 cur->isconst&=~(1<<hr);
437 printf("This shouldn't happen (alloc_reg)");exit(1);
440 void alloc_reg64(struct regstat *cur,int i,signed char reg)
442 int preferred_reg = 8+(reg&1);
445 // allocate the lower 32 bits
446 alloc_reg(cur,i,reg);
448 // Don't allocate unused registers
449 if((cur->uu>>reg)&1) return;
451 // see if the upper half is already allocated
452 for(hr=0;hr<HOST_REGS;hr++)
454 if(cur->regmap[hr]==reg+64) return;
457 // Keep the same mapping if the register was already allocated in a loop
458 preferred_reg = loop_reg(i,reg,preferred_reg);
460 // Try to allocate the preferred register
461 if(cur->regmap[preferred_reg]==-1) {
462 cur->regmap[preferred_reg]=reg|64;
463 cur->dirty&=~(1<<preferred_reg);
464 cur->isconst&=~(1<<preferred_reg);
467 r=cur->regmap[preferred_reg];
468 if(r<64&&((cur->u>>r)&1)) {
469 cur->regmap[preferred_reg]=reg|64;
470 cur->dirty&=~(1<<preferred_reg);
471 cur->isconst&=~(1<<preferred_reg);
474 if(r>=64&&((cur->uu>>(r&63))&1)) {
475 cur->regmap[preferred_reg]=reg|64;
476 cur->dirty&=~(1<<preferred_reg);
477 cur->isconst&=~(1<<preferred_reg);
481 // Clear any unneeded registers
482 // We try to keep the mapping consistent, if possible, because it
483 // makes branches easier (especially loops). So we try to allocate
484 // first (see above) before removing old mappings. If this is not
485 // possible then go ahead and clear out the registers that are no
487 for(hr=HOST_REGS-1;hr>=0;hr--)
492 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
496 if((cur->uu>>(r&63))&1) {cur->regmap[hr]=-1;break;}
500 // Try to allocate any available register, but prefer
501 // registers that have not been used recently.
503 for(hr=0;hr<HOST_REGS;hr++) {
504 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
505 if(regs[i-1].regmap[hr]!=rs1[i-1]&®s[i-1].regmap[hr]!=rs2[i-1]&®s[i-1].regmap[hr]!=rt1[i-1]&®s[i-1].regmap[hr]!=rt2[i-1]) {
506 cur->regmap[hr]=reg|64;
507 cur->dirty&=~(1<<hr);
508 cur->isconst&=~(1<<hr);
514 // Try to allocate any available register
515 for(hr=0;hr<HOST_REGS;hr++) {
516 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
517 cur->regmap[hr]=reg|64;
518 cur->dirty&=~(1<<hr);
519 cur->isconst&=~(1<<hr);
524 // Ok, now we have to evict someone
525 // Pick a register we hopefully won't need soon
526 u_char hsn[MAXREG+1];
527 memset(hsn,10,sizeof(hsn));
529 lsn(hsn,i,&preferred_reg);
530 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
531 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
533 // Don't evict the cycle count at entry points, otherwise the entry
534 // stub will have to write it.
535 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
536 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
539 // Alloc preferred register if available
540 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
541 for(hr=0;hr<HOST_REGS;hr++) {
542 // Evict both parts of a 64-bit register
543 if((cur->regmap[hr]&63)==r) {
545 cur->dirty&=~(1<<hr);
546 cur->isconst&=~(1<<hr);
549 cur->regmap[preferred_reg]=reg|64;
552 for(r=1;r<=MAXREG;r++)
554 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
555 for(hr=0;hr<HOST_REGS;hr++) {
556 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
557 if(cur->regmap[hr]==r+64) {
558 cur->regmap[hr]=reg|64;
559 cur->dirty&=~(1<<hr);
560 cur->isconst&=~(1<<hr);
565 for(hr=0;hr<HOST_REGS;hr++) {
566 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
567 if(cur->regmap[hr]==r) {
568 cur->regmap[hr]=reg|64;
569 cur->dirty&=~(1<<hr);
570 cur->isconst&=~(1<<hr);
581 for(r=1;r<=MAXREG;r++)
584 for(hr=0;hr<HOST_REGS;hr++) {
585 if(cur->regmap[hr]==r+64) {
586 cur->regmap[hr]=reg|64;
587 cur->dirty&=~(1<<hr);
588 cur->isconst&=~(1<<hr);
592 for(hr=0;hr<HOST_REGS;hr++) {
593 if(cur->regmap[hr]==r) {
594 cur->regmap[hr]=reg|64;
595 cur->dirty&=~(1<<hr);
596 cur->isconst&=~(1<<hr);
603 printf("This shouldn't happen");exit(1);
606 // Allocate a temporary register. This is done without regard to
607 // dirty status or whether the register we request is on the unneeded list
608 // Note: This will only allocate one register, even if called multiple times
609 void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
612 int preferred_reg = -1;
614 // see if it's already allocated
615 for(hr=0;hr<HOST_REGS;hr++)
617 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
620 // Try to allocate any available register
621 for(hr=HOST_REGS-1;hr>=0;hr--) {
622 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
624 cur->dirty&=~(1<<hr);
625 cur->isconst&=~(1<<hr);
630 // Find an unneeded register
631 for(hr=HOST_REGS-1;hr>=0;hr--)
637 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
639 cur->dirty&=~(1<<hr);
640 cur->isconst&=~(1<<hr);
647 if((cur->uu>>(r&63))&1) {
648 if(i==0||((unneeded_reg_upper[i-1]>>(r&63))&1)) {
650 cur->dirty&=~(1<<hr);
651 cur->isconst&=~(1<<hr);
659 // Ok, now we have to evict someone
660 // Pick a register we hopefully won't need soon
661 // TODO: we might want to follow unconditional jumps here
662 // TODO: get rid of dupe code and make this into a function
663 u_char hsn[MAXREG+1];
664 memset(hsn,10,sizeof(hsn));
666 lsn(hsn,i,&preferred_reg);
667 //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
669 // Don't evict the cycle count at entry points, otherwise the entry
670 // stub will have to write it.
671 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
672 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
675 for(r=1;r<=MAXREG;r++)
677 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
678 for(hr=0;hr<HOST_REGS;hr++) {
679 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
680 if(cur->regmap[hr]==r+64) {
682 cur->dirty&=~(1<<hr);
683 cur->isconst&=~(1<<hr);
688 for(hr=0;hr<HOST_REGS;hr++) {
689 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
690 if(cur->regmap[hr]==r) {
692 cur->dirty&=~(1<<hr);
693 cur->isconst&=~(1<<hr);
704 for(r=1;r<=MAXREG;r++)
707 for(hr=0;hr<HOST_REGS;hr++) {
708 if(cur->regmap[hr]==r+64) {
710 cur->dirty&=~(1<<hr);
711 cur->isconst&=~(1<<hr);
715 for(hr=0;hr<HOST_REGS;hr++) {
716 if(cur->regmap[hr]==r) {
718 cur->dirty&=~(1<<hr);
719 cur->isconst&=~(1<<hr);
726 printf("This shouldn't happen");exit(1);
728 // Allocate a specific ARM register.
729 void alloc_arm_reg(struct regstat *cur,int i,signed char reg,char hr)
733 // see if it's already allocated (and dealloc it)
734 for(n=0;n<HOST_REGS;n++)
736 if(n!=EXCLUDE_REG&&cur->regmap[n]==reg) {cur->regmap[n]=-1;}
740 cur->dirty&=~(1<<hr);
741 cur->isconst&=~(1<<hr);
744 // Alloc cycle count into dedicated register
745 alloc_cc(struct regstat *cur,int i)
747 alloc_arm_reg(cur,i,CCREG,HOST_CCREG);
755 char regname[16][4] = {
773 void output_byte(u_char byte)
777 void output_modrm(u_char mod,u_char rm,u_char ext)
782 u_char byte=(mod<<6)|(ext<<3)|rm;
785 void output_sib(u_char scale,u_char index,u_char base)
790 u_char byte=(scale<<6)|(index<<3)|base;
793 void output_w32(u_int word)
795 *((u_int *)out)=word;
798 u_int rd_rn_rm(u_int rd, u_int rn, u_int rm)
803 return((rn<<16)|(rd<<12)|rm);
805 u_int rd_rn_imm_shift(u_int rd, u_int rn, u_int imm, u_int shift)
810 assert((shift&1)==0);
811 return((rn<<16)|(rd<<12)|(((32-shift)&30)<<7)|imm);
813 u_int genimm(u_int imm,u_int *encoded)
815 if(imm==0) {*encoded=0;return 1;}
820 *encoded=((i&30)<<7)|imm;
823 imm=(imm>>2)|(imm<<30);i-=2;
827 u_int genjmp(u_int addr)
829 int offset=addr-(int)out-8;
830 if(offset<-33554432||offset>=33554432) {
832 printf("genjmp: out of range: %08x\n", offset);
837 return ((u_int)offset>>2)&0xffffff;
840 void emit_mov(int rs,int rt)
842 assem_debug("mov %s,%s\n",regname[rt],regname[rs]);
843 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs));
846 void emit_movs(int rs,int rt)
848 assem_debug("movs %s,%s\n",regname[rt],regname[rs]);
849 output_w32(0xe1b00000|rd_rn_rm(rt,0,rs));
852 void emit_add(int rs1,int rs2,int rt)
854 assem_debug("add %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
855 output_w32(0xe0800000|rd_rn_rm(rt,rs1,rs2));
858 void emit_adds(int rs1,int rs2,int rt)
860 assem_debug("adds %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
861 output_w32(0xe0900000|rd_rn_rm(rt,rs1,rs2));
864 void emit_adcs(int rs1,int rs2,int rt)
866 assem_debug("adcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
867 output_w32(0xe0b00000|rd_rn_rm(rt,rs1,rs2));
870 void emit_sbc(int rs1,int rs2,int rt)
872 assem_debug("sbc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
873 output_w32(0xe0c00000|rd_rn_rm(rt,rs1,rs2));
876 void emit_sbcs(int rs1,int rs2,int rt)
878 assem_debug("sbcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
879 output_w32(0xe0d00000|rd_rn_rm(rt,rs1,rs2));
882 void emit_neg(int rs, int rt)
884 assem_debug("rsb %s,%s,#0\n",regname[rt],regname[rs]);
885 output_w32(0xe2600000|rd_rn_rm(rt,rs,0));
888 void emit_negs(int rs, int rt)
890 assem_debug("rsbs %s,%s,#0\n",regname[rt],regname[rs]);
891 output_w32(0xe2700000|rd_rn_rm(rt,rs,0));
894 void emit_sub(int rs1,int rs2,int rt)
896 assem_debug("sub %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
897 output_w32(0xe0400000|rd_rn_rm(rt,rs1,rs2));
900 void emit_subs(int rs1,int rs2,int rt)
902 assem_debug("subs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
903 output_w32(0xe0500000|rd_rn_rm(rt,rs1,rs2));
906 void emit_zeroreg(int rt)
908 assem_debug("mov %s,#0\n",regname[rt]);
909 output_w32(0xe3a00000|rd_rn_rm(rt,0,0));
912 void emit_loadreg(int r, int hr)
916 printf("64bit load in 32bit mode!\n");
923 int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
924 if((r&63)==HIREG) addr=(int)&hi+((r&64)>>4);
925 if((r&63)==LOREG) addr=(int)&lo+((r&64)>>4);
926 if(r==CCREG) addr=(int)&cycle_count;
927 if(r==CSREG) addr=(int)&Status;
928 if(r==FSREG) addr=(int)&FCR31;
929 if(r==INVCP) addr=(int)&invc_ptr;
930 u_int offset = addr-(u_int)&dynarec_local;
932 assem_debug("ldr %s,fp+%d\n",regname[hr],offset);
933 output_w32(0xe5900000|rd_rn_rm(hr,FP,0)|offset);
936 void emit_storereg(int r, int hr)
940 printf("64bit store in 32bit mode!\n");
944 int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
945 if((r&63)==HIREG) addr=(int)&hi+((r&64)>>4);
946 if((r&63)==LOREG) addr=(int)&lo+((r&64)>>4);
947 if(r==CCREG) addr=(int)&cycle_count;
948 if(r==FSREG) addr=(int)&FCR31;
949 u_int offset = addr-(u_int)&dynarec_local;
951 assem_debug("str %s,fp+%d\n",regname[hr],offset);
952 output_w32(0xe5800000|rd_rn_rm(hr,FP,0)|offset);
955 void emit_test(int rs, int rt)
957 assem_debug("tst %s,%s\n",regname[rs],regname[rt]);
958 output_w32(0xe1100000|rd_rn_rm(0,rs,rt));
961 void emit_testimm(int rs,int imm)
964 assem_debug("tst %s,$%d\n",regname[rs],imm);
965 assert(genimm(imm,&armval));
966 output_w32(0xe3100000|rd_rn_rm(0,rs,0)|armval);
969 void emit_testeqimm(int rs,int imm)
972 assem_debug("tsteq %s,$%d\n",regname[rs],imm);
973 assert(genimm(imm,&armval));
974 output_w32(0x03100000|rd_rn_rm(0,rs,0)|armval);
977 void emit_not(int rs,int rt)
979 assem_debug("mvn %s,%s\n",regname[rt],regname[rs]);
980 output_w32(0xe1e00000|rd_rn_rm(rt,0,rs));
983 void emit_mvnmi(int rs,int rt)
985 assem_debug("mvnmi %s,%s\n",regname[rt],regname[rs]);
986 output_w32(0x41e00000|rd_rn_rm(rt,0,rs));
989 void emit_and(u_int rs1,u_int rs2,u_int rt)
991 assem_debug("and %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
992 output_w32(0xe0000000|rd_rn_rm(rt,rs1,rs2));
995 void emit_or(u_int rs1,u_int rs2,u_int rt)
997 assem_debug("orr %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
998 output_w32(0xe1800000|rd_rn_rm(rt,rs1,rs2));
1000 void emit_or_and_set_flags(int rs1,int rs2,int rt)
1002 assem_debug("orrs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1003 output_w32(0xe1900000|rd_rn_rm(rt,rs1,rs2));
1006 void emit_xor(u_int rs1,u_int rs2,u_int rt)
1008 assem_debug("eor %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1009 output_w32(0xe0200000|rd_rn_rm(rt,rs1,rs2));
1012 void emit_loadlp(u_int imm,u_int rt)
1014 add_literal((int)out,imm);
1015 assem_debug("ldr %s,pc+? [=%x]\n",regname[rt],imm);
1016 output_w32(0xe5900000|rd_rn_rm(rt,15,0));
1018 void emit_movw(u_int imm,u_int rt)
1021 assem_debug("movw %s,#%d (0x%x)\n",regname[rt],imm,imm);
1022 output_w32(0xe3000000|rd_rn_rm(rt,0,0)|(imm&0xfff)|((imm<<4)&0xf0000));
1024 void emit_movt(u_int imm,u_int rt)
1026 assem_debug("movt %s,#%d (0x%x)\n",regname[rt],imm&0xffff0000,imm&0xffff0000);
1027 output_w32(0xe3400000|rd_rn_rm(rt,0,0)|((imm>>16)&0xfff)|((imm>>12)&0xf0000));
1029 void emit_movimm(u_int imm,u_int rt)
1032 if(genimm(imm,&armval)) {
1033 assem_debug("mov %s,#%d\n",regname[rt],imm);
1034 output_w32(0xe3a00000|rd_rn_rm(rt,0,0)|armval);
1035 }else if(genimm(~imm,&armval)) {
1036 assem_debug("mvn %s,#%d\n",regname[rt],imm);
1037 output_w32(0xe3e00000|rd_rn_rm(rt,0,0)|armval);
1038 }else if(imm<65536) {
1040 assem_debug("mov %s,#%d\n",regname[rt],imm&0xFF00);
1041 output_w32(0xe3a00000|rd_rn_imm_shift(rt,0,imm>>8,8));
1042 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
1043 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1049 emit_loadlp(imm,rt);
1051 emit_movw(imm&0x0000FFFF,rt);
1052 emit_movt(imm&0xFFFF0000,rt);
1056 void emit_pcreladdr(u_int rt)
1058 assem_debug("add %s,pc,#?\n",regname[rt]);
1059 output_w32(0xe2800000|rd_rn_rm(rt,15,0));
1062 void emit_addimm(u_int rs,int imm,u_int rt)
1067 assert(imm>-65536&&imm<65536);
1069 if(genimm(imm,&armval)) {
1070 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rs],imm);
1071 output_w32(0xe2800000|rd_rn_rm(rt,rs,0)|armval);
1072 }else if(genimm(-imm,&armval)) {
1073 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],imm);
1074 output_w32(0xe2400000|rd_rn_rm(rt,rs,0)|armval);
1076 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],(-imm)&0xFF00);
1077 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF);
1078 output_w32(0xe2400000|rd_rn_imm_shift(rt,rs,(-imm)>>8,8));
1079 output_w32(0xe2400000|rd_rn_imm_shift(rt,rt,(-imm)&0xff,0));
1081 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1082 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
1083 output_w32(0xe2800000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1084 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1087 else if(rs!=rt) emit_mov(rs,rt);
1090 void emit_addimm_and_set_flags(int imm,int rt)
1092 assert(imm>-65536&&imm<65536);
1094 if(genimm(imm,&armval)) {
1095 assem_debug("adds %s,%s,#%d\n",regname[rt],regname[rt],imm);
1096 output_w32(0xe2900000|rd_rn_rm(rt,rt,0)|armval);
1097 }else if(genimm(-imm,&armval)) {
1098 assem_debug("subs %s,%s,#%d\n",regname[rt],regname[rt],imm);
1099 output_w32(0xe2500000|rd_rn_rm(rt,rt,0)|armval);
1101 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF00);
1102 assem_debug("subs %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF);
1103 output_w32(0xe2400000|rd_rn_imm_shift(rt,rt,(-imm)>>8,8));
1104 output_w32(0xe2500000|rd_rn_imm_shift(rt,rt,(-imm)&0xff,0));
1106 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF00);
1107 assem_debug("adds %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
1108 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm>>8,8));
1109 output_w32(0xe2900000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1112 void emit_addimm_no_flags(u_int imm,u_int rt)
1114 emit_addimm(rt,imm,rt);
1117 void emit_addnop(u_int r)
1120 assem_debug("add %s,%s,#0 (nop)\n",regname[r],regname[r]);
1121 output_w32(0xe2800000|rd_rn_rm(r,r,0));
1124 void emit_adcimm(u_int rs,int imm,u_int rt)
1127 assert(genimm(imm,&armval));
1128 assem_debug("adc %s,%s,#%d\n",regname[rt],regname[rs],imm);
1129 output_w32(0xe2a00000|rd_rn_rm(rt,rs,0)|armval);
1131 /*void emit_sbcimm(int imm,u_int rt)
1134 assert(genimm(imm,&armval));
1135 assem_debug("sbc %s,%s,#%d\n",regname[rt],regname[rt],imm);
1136 output_w32(0xe2c00000|rd_rn_rm(rt,rt,0)|armval);
1138 void emit_sbbimm(int imm,u_int rt)
1140 assem_debug("sbb $%d,%%%s\n",imm,regname[rt]);
1142 if(imm<128&&imm>=-128) {
1144 output_modrm(3,rt,3);
1150 output_modrm(3,rt,3);
1154 void emit_rscimm(int rs,int imm,u_int rt)
1158 assert(genimm(imm,&armval));
1159 assem_debug("rsc %s,%s,#%d\n",regname[rt],regname[rs],imm);
1160 output_w32(0xe2e00000|rd_rn_rm(rt,rs,0)|armval);
1163 void emit_addimm64_32(int rsh,int rsl,int imm,int rth,int rtl)
1165 // TODO: if(genimm(imm,&armval)) ...
1167 emit_movimm(imm,HOST_TEMPREG);
1168 emit_adds(HOST_TEMPREG,rsl,rtl);
1169 emit_adcimm(rsh,0,rth);
1172 void emit_sbb(int rs1,int rs2)
1174 assem_debug("sbb %%%s,%%%s\n",regname[rs2],regname[rs1]);
1176 output_modrm(3,rs1,rs2);
1179 void emit_andimm(int rs,int imm,int rt)
1182 if(genimm(imm,&armval)) {
1183 assem_debug("and %s,%s,#%d\n",regname[rt],regname[rs],imm);
1184 output_w32(0xe2000000|rd_rn_rm(rt,rs,0)|armval);
1185 }else if(genimm(~imm,&armval)) {
1186 assem_debug("bic %s,%s,#%d\n",regname[rt],regname[rs],imm);
1187 output_w32(0xe3c00000|rd_rn_rm(rt,rs,0)|armval);
1188 }else if(imm==65535) {
1190 assem_debug("bic %s,%s,#FF000000\n",regname[rt],regname[rs]);
1191 output_w32(0xe3c00000|rd_rn_rm(rt,rs,0)|0x4FF);
1192 assem_debug("bic %s,%s,#00FF0000\n",regname[rt],regname[rt]);
1193 output_w32(0xe3c00000|rd_rn_rm(rt,rt,0)|0x8FF);
1195 assem_debug("uxth %s,%s\n",regname[rt],regname[rs]);
1196 output_w32(0xe6ff0070|rd_rn_rm(rt,0,rs));
1199 assert(imm>0&&imm<65535);
1201 assem_debug("mov r14,#%d\n",imm&0xFF00);
1202 output_w32(0xe3a00000|rd_rn_imm_shift(HOST_TEMPREG,0,imm>>8,8));
1203 assem_debug("add r14,r14,#%d\n",imm&0xFF);
1204 output_w32(0xe2800000|rd_rn_imm_shift(HOST_TEMPREG,HOST_TEMPREG,imm&0xff,0));
1206 emit_movw(imm,HOST_TEMPREG);
1208 assem_debug("and %s,%s,r14\n",regname[rt],regname[rs]);
1209 output_w32(0xe0000000|rd_rn_rm(rt,rs,HOST_TEMPREG));
1213 void emit_orimm(int rs,int imm,int rt)
1216 if(genimm(imm,&armval)) {
1217 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1218 output_w32(0xe3800000|rd_rn_rm(rt,rs,0)|armval);
1220 assert(imm>0&&imm<65536);
1221 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1222 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF);
1223 output_w32(0xe3800000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1224 output_w32(0xe3800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1228 void emit_xorimm(int rs,int imm,int rt)
1231 if(genimm(imm,&armval)) {
1232 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm);
1233 output_w32(0xe2200000|rd_rn_rm(rt,rs,0)|armval);
1235 assert(imm>0&&imm<65536);
1236 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1237 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF);
1238 output_w32(0xe2200000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1239 output_w32(0xe2200000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1243 void emit_shlimm(int rs,u_int imm,int rt)
1248 assem_debug("lsl %s,%s,#%d\n",regname[rt],regname[rs],imm);
1249 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1252 void emit_shrimm(int rs,u_int imm,int rt)
1256 assem_debug("lsr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1257 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
1260 void emit_sarimm(int rs,u_int imm,int rt)
1264 assem_debug("asr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1265 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x40|(imm<<7));
1268 void emit_rorimm(int rs,u_int imm,int rt)
1272 assem_debug("ror %s,%s,#%d\n",regname[rt],regname[rs],imm);
1273 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x60|(imm<<7));
1276 void emit_shldimm(int rs,int rs2,u_int imm,int rt)
1278 assem_debug("shld %%%s,%%%s,%d\n",regname[rt],regname[rs2],imm);
1282 assem_debug("lsl %s,%s,#%d\n",regname[rt],regname[rs],imm);
1283 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1284 assem_debug("orr %s,%s,%s,lsr #%d\n",regname[rt],regname[rt],regname[rs2],32-imm);
1285 output_w32(0xe1800020|rd_rn_rm(rt,rt,rs2)|((32-imm)<<7));
1288 void emit_shrdimm(int rs,int rs2,u_int imm,int rt)
1290 assem_debug("shrd %%%s,%%%s,%d\n",regname[rt],regname[rs2],imm);
1294 assem_debug("lsr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1295 output_w32(0xe1a00020|rd_rn_rm(rt,0,rs)|(imm<<7));
1296 assem_debug("orr %s,%s,%s,lsl #%d\n",regname[rt],regname[rt],regname[rs2],32-imm);
1297 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs2)|((32-imm)<<7));
1300 void emit_signextend16(int rs,int rt)
1303 emit_shlimm(rs,16,rt);
1304 emit_sarimm(rt,16,rt);
1306 assem_debug("sxth %s,%s\n",regname[rt],regname[rs]);
1307 output_w32(0xe6bf0070|rd_rn_rm(rt,0,rs));
1311 void emit_shl(u_int rs,u_int shift,u_int rt)
1317 assem_debug("lsl %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1318 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x10|(shift<<8));
1320 void emit_shr(u_int rs,u_int shift,u_int rt)
1325 assem_debug("lsr %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1326 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x30|(shift<<8));
1328 void emit_sar(u_int rs,u_int shift,u_int rt)
1333 assem_debug("asr %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1334 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x50|(shift<<8));
1336 void emit_shlcl(int r)
1338 assem_debug("shl %%%s,%%cl\n",regname[r]);
1341 void emit_shrcl(int r)
1343 assem_debug("shr %%%s,%%cl\n",regname[r]);
1346 void emit_sarcl(int r)
1348 assem_debug("sar %%%s,%%cl\n",regname[r]);
1352 void emit_shldcl(int r1,int r2)
1354 assem_debug("shld %%%s,%%%s,%%cl\n",regname[r1],regname[r2]);
1357 void emit_shrdcl(int r1,int r2)
1359 assem_debug("shrd %%%s,%%%s,%%cl\n",regname[r1],regname[r2]);
1362 void emit_orrshl(u_int rs,u_int shift,u_int rt)
1367 assem_debug("orr %s,%s,%s,lsl %s\n",regname[rt],regname[rt],regname[rs],regname[shift]);
1368 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|0x10|(shift<<8));
1370 void emit_orrshr(u_int rs,u_int shift,u_int rt)
1375 assem_debug("orr %s,%s,%s,lsr %s\n",regname[rt],regname[rt],regname[rs],regname[shift]);
1376 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|0x30|(shift<<8));
1379 void emit_cmpimm(int rs,int imm)
1382 if(genimm(imm,&armval)) {
1383 assem_debug("cmp %s,$%d\n",regname[rs],imm);
1384 output_w32(0xe3500000|rd_rn_rm(0,rs,0)|armval);
1385 }else if(genimm(-imm,&armval)) {
1386 assem_debug("cmn %s,$%d\n",regname[rs],imm);
1387 output_w32(0xe3700000|rd_rn_rm(0,rs,0)|armval);
1391 emit_movimm(imm,HOST_TEMPREG);
1393 emit_movw(imm,HOST_TEMPREG);
1395 assem_debug("cmp %s,r14\n",regname[rs]);
1396 output_w32(0xe1500000|rd_rn_rm(0,rs,HOST_TEMPREG));
1400 emit_movimm(-imm,HOST_TEMPREG);
1402 emit_movw(-imm,HOST_TEMPREG);
1404 assem_debug("cmn %s,r14\n",regname[rs]);
1405 output_w32(0xe1700000|rd_rn_rm(0,rs,HOST_TEMPREG));
1409 void emit_cmovne(u_int *addr,int rt)
1411 assem_debug("cmovne %x,%%%s",(int)addr,regname[rt]);
1414 void emit_cmovl(u_int *addr,int rt)
1416 assem_debug("cmovl %x,%%%s",(int)addr,regname[rt]);
1419 void emit_cmovs(u_int *addr,int rt)
1421 assem_debug("cmovs %x,%%%s",(int)addr,regname[rt]);
1424 void emit_cmovne_imm(int imm,int rt)
1426 assem_debug("movne %s,#%d\n",regname[rt],imm);
1428 assert(genimm(imm,&armval));
1429 output_w32(0x13a00000|rd_rn_rm(rt,0,0)|armval);
1431 void emit_cmovl_imm(int imm,int rt)
1433 assem_debug("movlt %s,#%d\n",regname[rt],imm);
1435 assert(genimm(imm,&armval));
1436 output_w32(0xb3a00000|rd_rn_rm(rt,0,0)|armval);
1438 void emit_cmovb_imm(int imm,int rt)
1440 assem_debug("movcc %s,#%d\n",regname[rt],imm);
1442 assert(genimm(imm,&armval));
1443 output_w32(0x33a00000|rd_rn_rm(rt,0,0)|armval);
1445 void emit_cmovs_imm(int imm,int rt)
1447 assem_debug("movmi %s,#%d\n",regname[rt],imm);
1449 assert(genimm(imm,&armval));
1450 output_w32(0x43a00000|rd_rn_rm(rt,0,0)|armval);
1452 void emit_cmove_reg(int rs,int rt)
1454 assem_debug("moveq %s,%s\n",regname[rt],regname[rs]);
1455 output_w32(0x01a00000|rd_rn_rm(rt,0,rs));
1457 void emit_cmovne_reg(int rs,int rt)
1459 assem_debug("movne %s,%s\n",regname[rt],regname[rs]);
1460 output_w32(0x11a00000|rd_rn_rm(rt,0,rs));
1462 void emit_cmovl_reg(int rs,int rt)
1464 assem_debug("movlt %s,%s\n",regname[rt],regname[rs]);
1465 output_w32(0xb1a00000|rd_rn_rm(rt,0,rs));
1467 void emit_cmovs_reg(int rs,int rt)
1469 assem_debug("movmi %s,%s\n",regname[rt],regname[rs]);
1470 output_w32(0x41a00000|rd_rn_rm(rt,0,rs));
1473 void emit_slti32(int rs,int imm,int rt)
1475 if(rs!=rt) emit_zeroreg(rt);
1476 emit_cmpimm(rs,imm);
1477 if(rs==rt) emit_movimm(0,rt);
1478 emit_cmovl_imm(1,rt);
1480 void emit_sltiu32(int rs,int imm,int rt)
1482 if(rs!=rt) emit_zeroreg(rt);
1483 emit_cmpimm(rs,imm);
1484 if(rs==rt) emit_movimm(0,rt);
1485 emit_cmovb_imm(1,rt);
1487 void emit_slti64_32(int rsh,int rsl,int imm,int rt)
1490 emit_slti32(rsl,imm,rt);
1494 emit_cmovne_imm(0,rt);
1495 emit_cmovs_imm(1,rt);
1499 emit_cmpimm(rsh,-1);
1500 emit_cmovne_imm(0,rt);
1501 emit_cmovl_imm(1,rt);
1504 void emit_sltiu64_32(int rsh,int rsl,int imm,int rt)
1507 emit_sltiu32(rsl,imm,rt);
1511 emit_cmovne_imm(0,rt);
1515 emit_cmpimm(rsh,-1);
1516 emit_cmovne_imm(1,rt);
1520 void emit_cmp(int rs,int rt)
1522 assem_debug("cmp %s,%s\n",regname[rs],regname[rt]);
1523 output_w32(0xe1500000|rd_rn_rm(0,rs,rt));
1525 void emit_set_gz32(int rs, int rt)
1527 //assem_debug("set_gz32\n");
1530 emit_cmovl_imm(0,rt);
1532 void emit_set_nz32(int rs, int rt)
1534 //assem_debug("set_nz32\n");
1535 if(rs!=rt) emit_movs(rs,rt);
1536 else emit_test(rs,rs);
1537 emit_cmovne_imm(1,rt);
1539 void emit_set_gz64_32(int rsh, int rsl, int rt)
1541 //assem_debug("set_gz64\n");
1542 emit_set_gz32(rsl,rt);
1544 emit_cmovne_imm(1,rt);
1545 emit_cmovs_imm(0,rt);
1547 void emit_set_nz64_32(int rsh, int rsl, int rt)
1549 //assem_debug("set_nz64\n");
1550 emit_or_and_set_flags(rsh,rsl,rt);
1551 emit_cmovne_imm(1,rt);
1553 void emit_set_if_less32(int rs1, int rs2, int rt)
1555 //assem_debug("set if less (%%%s,%%%s),%%%s\n",regname[rs1],regname[rs2],regname[rt]);
1556 if(rs1!=rt&&rs2!=rt) emit_zeroreg(rt);
1558 if(rs1==rt||rs2==rt) emit_movimm(0,rt);
1559 emit_cmovl_imm(1,rt);
1561 void emit_set_if_carry32(int rs1, int rs2, int rt)
1563 //assem_debug("set if carry (%%%s,%%%s),%%%s\n",regname[rs1],regname[rs2],regname[rt]);
1564 if(rs1!=rt&&rs2!=rt) emit_zeroreg(rt);
1566 if(rs1==rt||rs2==rt) emit_movimm(0,rt);
1567 emit_cmovb_imm(1,rt);
1569 void emit_set_if_less64_32(int u1, int l1, int u2, int l2, int rt)
1571 //assem_debug("set if less64 (%%%s,%%%s,%%%s,%%%s),%%%s\n",regname[u1],regname[l1],regname[u2],regname[l2],regname[rt]);
1576 emit_sbcs(u1,u2,HOST_TEMPREG);
1577 emit_cmovl_imm(1,rt);
1579 void emit_set_if_carry64_32(int u1, int l1, int u2, int l2, int rt)
1581 //assem_debug("set if carry64 (%%%s,%%%s,%%%s,%%%s),%%%s\n",regname[u1],regname[l1],regname[u2],regname[l2],regname[rt]);
1586 emit_sbcs(u1,u2,HOST_TEMPREG);
1587 emit_cmovb_imm(1,rt);
1590 void emit_call(int a)
1592 assem_debug("bl %x (%x+%x)\n",a,(int)out,a-(int)out-8);
1593 u_int offset=genjmp(a);
1594 output_w32(0xeb000000|offset);
1596 void emit_jmp(int a)
1598 assem_debug("b %x (%x+%x)\n",a,(int)out,a-(int)out-8);
1599 u_int offset=genjmp(a);
1600 output_w32(0xea000000|offset);
1602 void emit_jne(int a)
1604 assem_debug("bne %x\n",a);
1605 u_int offset=genjmp(a);
1606 output_w32(0x1a000000|offset);
1608 void emit_jeq(int a)
1610 assem_debug("beq %x\n",a);
1611 u_int offset=genjmp(a);
1612 output_w32(0x0a000000|offset);
1616 assem_debug("bmi %x\n",a);
1617 u_int offset=genjmp(a);
1618 output_w32(0x4a000000|offset);
1620 void emit_jns(int a)
1622 assem_debug("bpl %x\n",a);
1623 u_int offset=genjmp(a);
1624 output_w32(0x5a000000|offset);
1628 assem_debug("blt %x\n",a);
1629 u_int offset=genjmp(a);
1630 output_w32(0xba000000|offset);
1632 void emit_jge(int a)
1634 assem_debug("bge %x\n",a);
1635 u_int offset=genjmp(a);
1636 output_w32(0xaa000000|offset);
1638 void emit_jno(int a)
1640 assem_debug("bvc %x\n",a);
1641 u_int offset=genjmp(a);
1642 output_w32(0x7a000000|offset);
1646 assem_debug("bcs %x\n",a);
1647 u_int offset=genjmp(a);
1648 output_w32(0x2a000000|offset);
1650 void emit_jcc(int a)
1652 assem_debug("bcc %x\n",a);
1653 u_int offset=genjmp(a);
1654 output_w32(0x3a000000|offset);
1657 void emit_pushimm(int imm)
1659 assem_debug("push $%x\n",imm);
1664 assem_debug("pusha\n");
1669 assem_debug("popa\n");
1672 void emit_pushreg(u_int r)
1674 assem_debug("push %%%s\n",regname[r]);
1677 void emit_popreg(u_int r)
1679 assem_debug("pop %%%s\n",regname[r]);
1682 void emit_callreg(u_int r)
1684 assem_debug("call *%%%s\n",regname[r]);
1687 void emit_jmpreg(u_int r)
1689 assem_debug("mov pc,%s\n",regname[r]);
1690 output_w32(0xe1a00000|rd_rn_rm(15,0,r));
1693 void emit_readword_indexed(int offset, int rs, int rt)
1695 assert(offset>-4096&&offset<4096);
1696 assem_debug("ldr %s,%s+%d\n",regname[rt],regname[rs],offset);
1698 output_w32(0xe5900000|rd_rn_rm(rt,rs,0)|offset);
1700 output_w32(0xe5100000|rd_rn_rm(rt,rs,0)|(-offset));
1703 void emit_readword_dualindexedx4(int rs1, int rs2, int rt)
1705 assem_debug("ldr %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1706 output_w32(0xe7900000|rd_rn_rm(rt,rs1,rs2)|0x100);
1708 void emit_readword_indexed_tlb(int addr, int rs, int map, int rt)
1710 if(map<0) emit_readword_indexed(addr, rs, rt);
1713 emit_readword_dualindexedx4(rs, map, rt);
1716 void emit_readdword_indexed_tlb(int addr, int rs, int map, int rh, int rl)
1719 if(rh>=0) emit_readword_indexed(addr, rs, rh);
1720 emit_readword_indexed(addr+4, rs, rl);
1723 if(rh>=0) emit_readword_indexed_tlb(addr, rs, map, rh);
1724 emit_addimm(map,1,map);
1725 emit_readword_indexed_tlb(addr, rs, map, rl);
1728 void emit_movsbl_indexed(int offset, int rs, int rt)
1730 assert(offset>-256&&offset<256);
1731 assem_debug("ldrsb %s,%s+%d\n",regname[rt],regname[rs],offset);
1733 output_w32(0xe1d000d0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1735 output_w32(0xe15000d0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1738 void emit_movsbl_indexed_tlb(int addr, int rs, int map, int rt)
1740 if(map<0) emit_movsbl_indexed(addr, rs, rt);
1743 emit_shlimm(map,2,map);
1744 assem_debug("ldrsb %s,%s+%s\n",regname[rt],regname[rs],regname[map]);
1745 output_w32(0xe19000d0|rd_rn_rm(rt,rs,map));
1747 assert(addr>-256&&addr<256);
1748 assem_debug("add %s,%s,%s,lsl #2\n",regname[rt],regname[rs],regname[map]);
1749 output_w32(0xe0800000|rd_rn_rm(rt,rs,map)|(2<<7));
1750 emit_movsbl_indexed(addr, rt, rt);
1754 void emit_movswl_indexed(int offset, int rs, int rt)
1756 assert(offset>-256&&offset<256);
1757 assem_debug("ldrsh %s,%s+%d\n",regname[rt],regname[rs],offset);
1759 output_w32(0xe1d000f0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1761 output_w32(0xe15000f0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1764 void emit_movzbl_indexed(int offset, int rs, int rt)
1766 assert(offset>-4096&&offset<4096);
1767 assem_debug("ldrb %s,%s+%d\n",regname[rt],regname[rs],offset);
1769 output_w32(0xe5d00000|rd_rn_rm(rt,rs,0)|offset);
1771 output_w32(0xe5500000|rd_rn_rm(rt,rs,0)|(-offset));
1774 void emit_movzbl_dualindexedx4(int rs1, int rs2, int rt)
1776 assem_debug("ldrb %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1777 output_w32(0xe7d00000|rd_rn_rm(rt,rs1,rs2)|0x100);
1779 void emit_movzbl_indexed_tlb(int addr, int rs, int map, int rt)
1781 if(map<0) emit_movzbl_indexed(addr, rs, rt);
1784 emit_movzbl_dualindexedx4(rs, map, rt);
1786 emit_addimm(rs,addr,rt);
1787 emit_movzbl_dualindexedx4(rt, map, rt);
1791 void emit_movzwl_indexed(int offset, int rs, int rt)
1793 assert(offset>-256&&offset<256);
1794 assem_debug("ldrh %s,%s+%d\n",regname[rt],regname[rs],offset);
1796 output_w32(0xe1d000b0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1798 output_w32(0xe15000b0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1801 void emit_readword(int addr, int rt)
1803 u_int offset = addr-(u_int)&dynarec_local;
1804 assert(offset<4096);
1805 assem_debug("ldr %s,fp+%d\n",regname[rt],offset);
1806 output_w32(0xe5900000|rd_rn_rm(rt,FP,0)|offset);
1808 void emit_movsbl(int addr, int rt)
1810 u_int offset = addr-(u_int)&dynarec_local;
1812 assem_debug("ldrsb %s,fp+%d\n",regname[rt],offset);
1813 output_w32(0xe1d000d0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1815 void emit_movswl(int addr, int rt)
1817 u_int offset = addr-(u_int)&dynarec_local;
1819 assem_debug("ldrsh %s,fp+%d\n",regname[rt],offset);
1820 output_w32(0xe1d000f0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1822 void emit_movzbl(int addr, int rt)
1824 u_int offset = addr-(u_int)&dynarec_local;
1825 assert(offset<4096);
1826 assem_debug("ldrb %s,fp+%d\n",regname[rt],offset);
1827 output_w32(0xe5d00000|rd_rn_rm(rt,FP,0)|offset);
1829 void emit_movzwl(int addr, int rt)
1831 u_int offset = addr-(u_int)&dynarec_local;
1833 assem_debug("ldrh %s,fp+%d\n",regname[rt],offset);
1834 output_w32(0xe1d000b0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1836 void emit_movzwl_reg(int rs, int rt)
1838 assem_debug("movzwl %%%s,%%%s\n",regname[rs]+1,regname[rt]);
1842 void emit_xchg(int rs, int rt)
1844 assem_debug("xchg %%%s,%%%s\n",regname[rs],regname[rt]);
1847 void emit_writeword_indexed(int rt, int offset, int rs)
1849 assert(offset>-4096&&offset<4096);
1850 assem_debug("str %s,%s+%d\n",regname[rt],regname[rs],offset);
1852 output_w32(0xe5800000|rd_rn_rm(rt,rs,0)|offset);
1854 output_w32(0xe5000000|rd_rn_rm(rt,rs,0)|(-offset));
1857 void emit_writeword_dualindexedx4(int rt, int rs1, int rs2)
1859 assem_debug("str %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1860 output_w32(0xe7800000|rd_rn_rm(rt,rs1,rs2)|0x100);
1862 void emit_writeword_indexed_tlb(int rt, int addr, int rs, int map, int temp)
1864 if(map<0) emit_writeword_indexed(rt, addr, rs);
1867 emit_writeword_dualindexedx4(rt, rs, map);
1870 void emit_writedword_indexed_tlb(int rh, int rl, int addr, int rs, int map, int temp)
1873 if(rh>=0) emit_writeword_indexed(rh, addr, rs);
1874 emit_writeword_indexed(rl, addr+4, rs);
1877 if(temp!=rs) emit_addimm(map,1,temp);
1878 emit_writeword_indexed_tlb(rh, addr, rs, map, temp);
1879 if(temp!=rs) emit_writeword_indexed_tlb(rl, addr, rs, temp, temp);
1881 emit_addimm(rs,4,rs);
1882 emit_writeword_indexed_tlb(rl, addr, rs, map, temp);
1886 void emit_writehword_indexed(int rt, int offset, int rs)
1888 assert(offset>-256&&offset<256);
1889 assem_debug("strh %s,%s+%d\n",regname[rt],regname[rs],offset);
1891 output_w32(0xe1c000b0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1893 output_w32(0xe14000b0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1896 void emit_writebyte_indexed(int rt, int offset, int rs)
1898 assert(offset>-4096&&offset<4096);
1899 assem_debug("strb %s,%s+%d\n",regname[rt],regname[rs],offset);
1901 output_w32(0xe5c00000|rd_rn_rm(rt,rs,0)|offset);
1903 output_w32(0xe5400000|rd_rn_rm(rt,rs,0)|(-offset));
1906 void emit_writebyte_dualindexedx4(int rt, int rs1, int rs2)
1908 assem_debug("strb %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1909 output_w32(0xe7c00000|rd_rn_rm(rt,rs1,rs2)|0x100);
1911 void emit_writebyte_indexed_tlb(int rt, int addr, int rs, int map, int temp)
1913 if(map<0) emit_writebyte_indexed(rt, addr, rs);
1916 emit_writebyte_dualindexedx4(rt, rs, map);
1918 emit_addimm(rs,addr,temp);
1919 emit_writebyte_dualindexedx4(rt, temp, map);
1923 void emit_writeword(int rt, int addr)
1925 u_int offset = addr-(u_int)&dynarec_local;
1926 assert(offset<4096);
1927 assem_debug("str %s,fp+%d\n",regname[rt],offset);
1928 output_w32(0xe5800000|rd_rn_rm(rt,FP,0)|offset);
1930 void emit_writehword(int rt, int addr)
1932 u_int offset = addr-(u_int)&dynarec_local;
1934 assem_debug("strh %s,fp+%d\n",regname[rt],offset);
1935 output_w32(0xe1c000b0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1937 void emit_writebyte(int rt, int addr)
1939 u_int offset = addr-(u_int)&dynarec_local;
1940 assert(offset<4096);
1941 assem_debug("str %s,fp+%d\n",regname[rt],offset);
1942 output_w32(0xe5c00000|rd_rn_rm(rt,FP,0)|offset);
1944 void emit_writeword_imm(int imm, int addr)
1946 assem_debug("movl $%x,%x\n",imm,addr);
1949 void emit_writebyte_imm(int imm, int addr)
1951 assem_debug("movb $%x,%x\n",imm,addr);
1955 void emit_mul(int rs)
1957 assem_debug("mul %%%s\n",regname[rs]);
1960 void emit_imul(int rs)
1962 assem_debug("imul %%%s\n",regname[rs]);
1965 void emit_umull(u_int rs1, u_int rs2, u_int hi, u_int lo)
1967 assem_debug("umull %s, %s, %s, %s\n",regname[lo],regname[hi],regname[rs1],regname[rs2]);
1972 output_w32(0xe0800090|(hi<<16)|(lo<<12)|(rs2<<8)|rs1);
1974 void emit_smull(u_int rs1, u_int rs2, u_int hi, u_int lo)
1976 assem_debug("smull %s, %s, %s, %s\n",regname[lo],regname[hi],regname[rs1],regname[rs2]);
1981 output_w32(0xe0c00090|(hi<<16)|(lo<<12)|(rs2<<8)|rs1);
1984 void emit_div(int rs)
1986 assem_debug("div %%%s\n",regname[rs]);
1989 void emit_idiv(int rs)
1991 assem_debug("idiv %%%s\n",regname[rs]);
1996 assem_debug("cdq\n");
2000 void emit_clz(int rs,int rt)
2002 assem_debug("clz %s,%s\n",regname[rt],regname[rs]);
2003 output_w32(0xe16f0f10|rd_rn_rm(rt,0,rs));
2006 void emit_subcs(int rs1,int rs2,int rt)
2008 assem_debug("subcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2009 output_w32(0x20400000|rd_rn_rm(rt,rs1,rs2));
2012 void emit_shrcc_imm(int rs,u_int imm,int rt)
2016 assem_debug("lsrcc %s,%s,#%d\n",regname[rt],regname[rs],imm);
2017 output_w32(0x31a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
2020 void emit_negmi(int rs, int rt)
2022 assem_debug("rsbmi %s,%s,#0\n",regname[rt],regname[rs]);
2023 output_w32(0x42600000|rd_rn_rm(rt,rs,0));
2026 void emit_negsmi(int rs, int rt)
2028 assem_debug("rsbsmi %s,%s,#0\n",regname[rt],regname[rs]);
2029 output_w32(0x42700000|rd_rn_rm(rt,rs,0));
2032 void emit_orreq(u_int rs1,u_int rs2,u_int rt)
2034 assem_debug("orreq %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2035 output_w32(0x01800000|rd_rn_rm(rt,rs1,rs2));
2038 void emit_orrne(u_int rs1,u_int rs2,u_int rt)
2040 assem_debug("orrne %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2041 output_w32(0x11800000|rd_rn_rm(rt,rs1,rs2));
2044 void emit_bic_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2046 assem_debug("bic %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2047 output_w32(0xe1C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2050 void emit_biceq_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2052 assem_debug("biceq %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2053 output_w32(0x01C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2056 void emit_bicne_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2058 assem_debug("bicne %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2059 output_w32(0x11C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2062 void emit_bic_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2064 assem_debug("bic %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2065 output_w32(0xe1C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2068 void emit_biceq_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2070 assem_debug("biceq %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2071 output_w32(0x01C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2074 void emit_bicne_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2076 assem_debug("bicne %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2077 output_w32(0x11C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2080 void emit_teq(int rs, int rt)
2082 assem_debug("teq %s,%s\n",regname[rs],regname[rt]);
2083 output_w32(0xe1300000|rd_rn_rm(0,rs,rt));
2086 void emit_rsbimm(int rs, int imm, int rt)
2089 assert(genimm(imm,&armval));
2090 assem_debug("rsb %s,%s,#%d\n",regname[rt],regname[rs],imm);
2091 output_w32(0xe2600000|rd_rn_rm(rt,rs,0)|armval);
2094 // Load 2 immediates optimizing for small code size
2095 void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
2097 emit_movimm(imm1,rt1);
2099 if(genimm(imm2-imm1,&armval)) {
2100 assem_debug("add %s,%s,#%d\n",regname[rt2],regname[rt1],imm2-imm1);
2101 output_w32(0xe2800000|rd_rn_rm(rt2,rt1,0)|armval);
2102 }else if(genimm(imm1-imm2,&armval)) {
2103 assem_debug("sub %s,%s,#%d\n",regname[rt2],regname[rt1],imm1-imm2);
2104 output_w32(0xe2400000|rd_rn_rm(rt2,rt1,0)|armval);
2106 else emit_movimm(imm2,rt2);
2109 // Conditionally select one of two immediates, optimizing for small code size
2110 // This will only be called if HAVE_CMOV_IMM is defined
2111 void emit_cmov2imm_e_ne_compact(int imm1,int imm2,u_int rt)
2114 if(genimm(imm2-imm1,&armval)) {
2115 emit_movimm(imm1,rt);
2116 assem_debug("addne %s,%s,#%d\n",regname[rt],regname[rt],imm2-imm1);
2117 output_w32(0x12800000|rd_rn_rm(rt,rt,0)|armval);
2118 }else if(genimm(imm1-imm2,&armval)) {
2119 emit_movimm(imm1,rt);
2120 assem_debug("subne %s,%s,#%d\n",regname[rt],regname[rt],imm1-imm2);
2121 output_w32(0x12400000|rd_rn_rm(rt,rt,0)|armval);
2125 emit_movimm(imm1,rt);
2126 add_literal((int)out,imm2);
2127 assem_debug("ldrne %s,pc+? [=%x]\n",regname[rt],imm2);
2128 output_w32(0x15900000|rd_rn_rm(rt,15,0));
2130 emit_movw(imm1&0x0000FFFF,rt);
2131 if((imm1&0xFFFF)!=(imm2&0xFFFF)) {
2132 assem_debug("movwne %s,#%d (0x%x)\n",regname[rt],imm2&0xFFFF,imm2&0xFFFF);
2133 output_w32(0x13000000|rd_rn_rm(rt,0,0)|(imm2&0xfff)|((imm2<<4)&0xf0000));
2135 emit_movt(imm1&0xFFFF0000,rt);
2136 if((imm1&0xFFFF0000)!=(imm2&0xFFFF0000)) {
2137 assem_debug("movtne %s,#%d (0x%x)\n",regname[rt],imm2&0xffff0000,imm2&0xffff0000);
2138 output_w32(0x13400000|rd_rn_rm(rt,0,0)|((imm2>>16)&0xfff)|((imm2>>12)&0xf0000));
2144 // special case for checking invalid_code
2145 void emit_cmpmem_indexedsr12_imm(int addr,int r,int imm)
2150 // special case for checking invalid_code
2151 void emit_cmpmem_indexedsr12_reg(int base,int r,int imm)
2153 assert(imm<128&&imm>=0);
2155 assem_debug("ldrb lr,%s,%s lsr #12\n",regname[base],regname[r]);
2156 output_w32(0xe7d00000|rd_rn_rm(HOST_TEMPREG,base,r)|0x620);
2157 emit_cmpimm(HOST_TEMPREG,imm);
2160 // special case for tlb mapping
2161 void emit_addsr12(int rs1,int rs2,int rt)
2163 assem_debug("add %s,%s,%s lsr #12\n",regname[rt],regname[rs1],regname[rs2]);
2164 output_w32(0xe0800620|rd_rn_rm(rt,rs1,rs2));
2167 // Used to preload hash table entries
2168 void emit_prefetch(void *addr)
2170 assem_debug("prefetch %x\n",(int)addr);
2173 output_modrm(0,5,1);
2174 output_w32((int)addr);
2176 void emit_prefetchreg(int r)
2178 assem_debug("pld %s\n",regname[r]);
2179 output_w32(0xf5d0f000|rd_rn_rm(0,r,0));
2182 // Special case for mini_ht
2183 void emit_ldreq_indexed(int rs, u_int offset, int rt)
2185 assert(offset<4096);
2186 assem_debug("ldreq %s,[%s, #%d]\n",regname[rt],regname[rs],offset);
2187 output_w32(0x05900000|rd_rn_rm(rt,rs,0)|offset);
2190 void emit_flds(int r,int sr)
2192 assem_debug("flds s%d,[%s]\n",sr,regname[r]);
2193 output_w32(0xed900a00|((sr&14)<<11)|((sr&1)<<22)|(r<<16));
2196 void emit_vldr(int r,int vr)
2198 assem_debug("vldr d%d,[%s]\n",vr,regname[r]);
2199 output_w32(0xed900b00|(vr<<12)|(r<<16));
2202 void emit_fsts(int sr,int r)
2204 assem_debug("fsts s%d,[%s]\n",sr,regname[r]);
2205 output_w32(0xed800a00|((sr&14)<<11)|((sr&1)<<22)|(r<<16));
2208 void emit_vstr(int vr,int r)
2210 assem_debug("vstr d%d,[%s]\n",vr,regname[r]);
2211 output_w32(0xed800b00|(vr<<12)|(r<<16));
2214 void emit_ftosizs(int s,int d)
2216 assem_debug("ftosizs s%d,s%d\n",d,s);
2217 output_w32(0xeebd0ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2220 void emit_ftosizd(int s,int d)
2222 assem_debug("ftosizd s%d,d%d\n",d,s);
2223 output_w32(0xeebd0bc0|((d&14)<<11)|((d&1)<<22)|(s&7));
2226 void emit_fsitos(int s,int d)
2228 assem_debug("fsitos s%d,s%d\n",d,s);
2229 output_w32(0xeeb80ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2232 void emit_fsitod(int s,int d)
2234 assem_debug("fsitod d%d,s%d\n",d,s);
2235 output_w32(0xeeb80bc0|((d&7)<<12)|((s&14)>>1)|((s&1)<<5));
2238 void emit_fcvtds(int s,int d)
2240 assem_debug("fcvtds d%d,s%d\n",d,s);
2241 output_w32(0xeeb70ac0|((d&7)<<12)|((s&14)>>1)|((s&1)<<5));
2244 void emit_fcvtsd(int s,int d)
2246 assem_debug("fcvtsd s%d,d%d\n",d,s);
2247 output_w32(0xeeb70bc0|((d&14)<<11)|((d&1)<<22)|(s&7));
2250 void emit_fsqrts(int s,int d)
2252 assem_debug("fsqrts d%d,s%d\n",d,s);
2253 output_w32(0xeeb10ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2256 void emit_fsqrtd(int s,int d)
2258 assem_debug("fsqrtd s%d,d%d\n",d,s);
2259 output_w32(0xeeb10bc0|((d&7)<<12)|(s&7));
2262 void emit_fabss(int s,int d)
2264 assem_debug("fabss d%d,s%d\n",d,s);
2265 output_w32(0xeeb00ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2268 void emit_fabsd(int s,int d)
2270 assem_debug("fabsd s%d,d%d\n",d,s);
2271 output_w32(0xeeb00bc0|((d&7)<<12)|(s&7));
2274 void emit_fnegs(int s,int d)
2276 assem_debug("fnegs d%d,s%d\n",d,s);
2277 output_w32(0xeeb10a40|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2280 void emit_fnegd(int s,int d)
2282 assem_debug("fnegd s%d,d%d\n",d,s);
2283 output_w32(0xeeb10b40|((d&7)<<12)|(s&7));
2286 void emit_fadds(int s1,int s2,int d)
2288 assem_debug("fadds s%d,s%d,s%d\n",d,s1,s2);
2289 output_w32(0xee300a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2292 void emit_faddd(int s1,int s2,int d)
2294 assem_debug("faddd d%d,d%d,d%d\n",d,s1,s2);
2295 output_w32(0xee300b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2298 void emit_fsubs(int s1,int s2,int d)
2300 assem_debug("fsubs s%d,s%d,s%d\n",d,s1,s2);
2301 output_w32(0xee300a40|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2304 void emit_fsubd(int s1,int s2,int d)
2306 assem_debug("fsubd d%d,d%d,d%d\n",d,s1,s2);
2307 output_w32(0xee300b40|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2310 void emit_fmuls(int s1,int s2,int d)
2312 assem_debug("fmuls s%d,s%d,s%d\n",d,s1,s2);
2313 output_w32(0xee200a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2316 void emit_fmuld(int s1,int s2,int d)
2318 assem_debug("fmuld d%d,d%d,d%d\n",d,s1,s2);
2319 output_w32(0xee200b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2322 void emit_fdivs(int s1,int s2,int d)
2324 assem_debug("fdivs s%d,s%d,s%d\n",d,s1,s2);
2325 output_w32(0xee800a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2328 void emit_fdivd(int s1,int s2,int d)
2330 assem_debug("fdivd d%d,d%d,d%d\n",d,s1,s2);
2331 output_w32(0xee800b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2334 void emit_fcmps(int x,int y)
2336 assem_debug("fcmps s14, s15\n");
2337 output_w32(0xeeb47a67);
2340 void emit_fcmpd(int x,int y)
2342 assem_debug("fcmpd d6, d7\n");
2343 output_w32(0xeeb46b47);
2348 assem_debug("fmstat\n");
2349 output_w32(0xeef1fa10);
2352 void emit_bicne_imm(int rs,int imm,int rt)
2355 assert(genimm(imm,&armval));
2356 assem_debug("bicne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2357 output_w32(0x13c00000|rd_rn_rm(rt,rs,0)|armval);
2360 void emit_biccs_imm(int rs,int imm,int rt)
2363 assert(genimm(imm,&armval));
2364 assem_debug("biccs %s,%s,#%d\n",regname[rt],regname[rs],imm);
2365 output_w32(0x23c00000|rd_rn_rm(rt,rs,0)|armval);
2368 void emit_bicvc_imm(int rs,int imm,int rt)
2371 assert(genimm(imm,&armval));
2372 assem_debug("bicvc %s,%s,#%d\n",regname[rt],regname[rs],imm);
2373 output_w32(0x73c00000|rd_rn_rm(rt,rs,0)|armval);
2376 void emit_bichi_imm(int rs,int imm,int rt)
2379 assert(genimm(imm,&armval));
2380 assem_debug("bichi %s,%s,#%d\n",regname[rt],regname[rs],imm);
2381 output_w32(0x83c00000|rd_rn_rm(rt,rs,0)|armval);
2384 void emit_orrvs_imm(int rs,int imm,int rt)
2387 assert(genimm(imm,&armval));
2388 assem_debug("orrvs %s,%s,#%d\n",regname[rt],regname[rs],imm);
2389 output_w32(0x63800000|rd_rn_rm(rt,rs,0)|armval);
2392 void emit_orrne_imm(int rs,int imm,int rt)
2395 assert(genimm(imm,&armval));
2396 assem_debug("orrne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2397 output_w32(0x13800000|rd_rn_rm(rt,rs,0)|armval);
2400 void emit_andne_imm(int rs,int imm,int rt)
2403 assert(genimm(imm,&armval));
2404 assem_debug("andne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2405 output_w32(0x12000000|rd_rn_rm(rt,rs,0)|armval);
2408 void emit_jno_unlikely(int a)
2411 assem_debug("addvc pc,pc,#? (%x)\n",/*a-(int)out-8,*/a);
2412 output_w32(0x72800000|rd_rn_rm(15,15,0));
2415 // Save registers before function call
2416 void save_regs(u_int reglist)
2418 reglist&=0x100f; // only save the caller-save registers, r0-r3, r12
2419 if(!reglist) return;
2420 assem_debug("stmia fp,{");
2421 if(reglist&1) assem_debug("r0, ");
2422 if(reglist&2) assem_debug("r1, ");
2423 if(reglist&4) assem_debug("r2, ");
2424 if(reglist&8) assem_debug("r3, ");
2425 if(reglist&0x1000) assem_debug("r12");
2427 output_w32(0xe88b0000|reglist);
2429 // Restore registers after function call
2430 void restore_regs(u_int reglist)
2432 reglist&=0x100f; // only restore the caller-save registers, r0-r3, r12
2433 if(!reglist) return;
2434 assem_debug("ldmia fp,{");
2435 if(reglist&1) assem_debug("r0, ");
2436 if(reglist&2) assem_debug("r1, ");
2437 if(reglist&4) assem_debug("r2, ");
2438 if(reglist&8) assem_debug("r3, ");
2439 if(reglist&0x1000) assem_debug("r12");
2441 output_w32(0xe89b0000|reglist);
2444 // Write back consts using r14 so we don't disturb the other registers
2445 void wb_consts(signed char i_regmap[],uint64_t i_is32,u_int i_dirty,int i)
2448 for(hr=0;hr<HOST_REGS;hr++) {
2449 if(hr!=EXCLUDE_REG&&i_regmap[hr]>=0&&((i_dirty>>hr)&1)) {
2450 if(((regs[i].isconst>>hr)&1)&&i_regmap[hr]>0) {
2451 if(i_regmap[hr]<64 || !((i_is32>>(i_regmap[hr]&63))&1) ) {
2452 int value=constmap[i][hr];
2454 emit_zeroreg(HOST_TEMPREG);
2457 emit_movimm(value,HOST_TEMPREG);
2459 emit_storereg(i_regmap[hr],HOST_TEMPREG);
2461 if((i_is32>>i_regmap[hr])&1) {
2462 if(value!=-1&&value!=0) emit_sarimm(HOST_TEMPREG,31,HOST_TEMPREG);
2463 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
2472 /* Stubs/epilogue */
2474 void literal_pool(int n)
2476 if(!literalcount) return;
2478 if((int)out-literals[0][0]<4096-n) return;
2482 for(i=0;i<literalcount;i++)
2484 ptr=(u_int *)literals[i][0];
2485 u_int offset=(u_int)out-(u_int)ptr-8;
2486 assert(offset<4096);
2487 assert(!(offset&3));
2489 output_w32(literals[i][1]);
2494 void literal_pool_jumpover(int n)
2496 if(!literalcount) return;
2498 if((int)out-literals[0][0]<4096-n) return;
2503 set_jump_target(jaddr,(int)out);
2506 emit_extjump2(int addr, int target, int linker)
2508 u_char *ptr=(u_char *)addr;
2509 assert((ptr[3]&0x0e)==0xa);
2510 emit_loadlp(target,0);
2511 emit_loadlp(addr,1);
2512 assert(addr>=BASE_ADDR&&addr<(BASE_ADDR+(1<<TARGET_SIZE_2)));
2513 //assert((target>=0x80000000&&target<0x80800000)||(target>0xA4000000&&target<0xA4001000));
2515 #ifdef DEBUG_CYCLE_COUNT
2516 emit_readword((int)&last_count,ECX);
2517 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2518 emit_readword((int)&next_interupt,ECX);
2519 emit_writeword(HOST_CCREG,(int)&Count);
2520 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
2521 emit_writeword(ECX,(int)&last_count);
2527 emit_extjump(int addr, int target)
2529 emit_extjump2(addr, target, (int)dyna_linker);
2531 emit_extjump_ds(int addr, int target)
2533 emit_extjump2(addr, target, (int)dyna_linker_ds);
2538 assem_debug("do_readstub %x\n",start+stubs[n][3]*4);
2540 set_jump_target(stubs[n][1],(int)out);
2541 int type=stubs[n][0];
2544 struct regstat *i_regs=(struct regstat *)stubs[n][5];
2545 u_int reglist=stubs[n][7];
2546 signed char *i_regmap=i_regs->regmap;
2547 int addr=get_reg(i_regmap,AGEN1+(i&1));
2550 if(itype[i]==C1LS||itype[i]==C2LS||itype[i]==LOADLR) {
2551 rth=get_reg(i_regmap,FTEMP|64);
2552 rt=get_reg(i_regmap,FTEMP);
2554 rth=get_reg(i_regmap,rt1[i]|64);
2555 rt=get_reg(i_regmap,rt1[i]);
2559 // assume forced dummy read
2560 rt=get_reg(i_regmap,-1);
2567 if(type==LOADB_STUB||type==LOADBU_STUB)
2568 ftable=(int)readmemb;
2569 if(type==LOADH_STUB||type==LOADHU_STUB)
2570 ftable=(int)readmemh;
2571 if(type==LOADW_STUB)
2572 ftable=(int)readmem;
2574 if(type==LOADD_STUB)
2575 ftable=(int)readmemd;
2578 emit_writeword(rs,(int)&address);
2581 ds=i_regs!=®s[i];
2582 int real_rs=(itype[i]==LOADLR)?-1:get_reg(i_regmap,rs1[i]);
2583 u_int cmask=ds?-1:(0x100f|~i_regs->wasconst);
2584 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&0x100f,i);
2585 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs)));
2586 if(!ds) wb_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&~0x100f,i);
2587 emit_shrimm(rs,16,1);
2588 int cc=get_reg(i_regmap,CCREG);
2590 emit_loadreg(CCREG,2);
2592 emit_movimm(ftable,0);
2593 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
2594 emit_movimm(start+stubs[n][3]*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
2595 //emit_readword((int)&last_count,temp);
2596 //emit_add(cc,temp,cc);
2597 //emit_writeword(cc,(int)&Count);
2599 emit_call((int)&indirect_jump_indexed);
2601 //emit_readword_dualindexedx4(rs,HOST_TEMPREG,15);
2602 // We really shouldn't need to update the count here,
2603 // but not doing so causes random crashes...
2604 emit_readword((int)&Count,HOST_TEMPREG);
2605 emit_readword((int)&next_interupt,2);
2606 emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
2607 emit_writeword(2,(int)&last_count);
2608 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2610 emit_storereg(CCREG,HOST_TEMPREG);
2613 restore_regs(reglist);
2614 //if((cc=get_reg(regmap,CCREG))>=0) {
2615 // emit_loadreg(CCREG,cc);
2617 if(type==LOADB_STUB)
2618 emit_movsbl((int)&readmem_dword,rt);
2619 if(type==LOADBU_STUB)
2620 emit_movzbl((int)&readmem_dword,rt);
2621 if(type==LOADH_STUB)
2622 emit_movswl((int)&readmem_dword,rt);
2623 if(type==LOADHU_STUB)
2624 emit_movzwl((int)&readmem_dword,rt);
2625 if(type==LOADW_STUB)
2626 emit_readword((int)&readmem_dword,rt);
2627 if(type==LOADD_STUB) {
2628 emit_readword((int)&readmem_dword,rt);
2629 if(rth>=0) emit_readword(((int)&readmem_dword)+4,rth);
2631 emit_jmp(stubs[n][2]); // return address
2634 inline_readstub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
2636 int rs=get_reg(regmap,target);
2637 int rth=get_reg(regmap,target|64);
2638 int rt=get_reg(regmap,target);
2642 if(type==LOADB_STUB||type==LOADBU_STUB)
2643 ftable=(int)readmemb;
2644 if(type==LOADH_STUB||type==LOADHU_STUB)
2645 ftable=(int)readmemh;
2646 if(type==LOADW_STUB)
2647 ftable=(int)readmem;
2649 if(type==LOADD_STUB)
2650 ftable=(int)readmemd;
2653 emit_writeword(rs,(int)&address);
2656 //emit_shrimm(rs,16,1);
2657 int cc=get_reg(regmap,CCREG);
2659 emit_loadreg(CCREG,2);
2661 //emit_movimm(ftable,0);
2662 emit_movimm(((u_int *)ftable)[addr>>16],0);
2663 //emit_readword((int)&last_count,12);
2664 emit_addimm(cc<0?2:cc,CLOCK_DIVIDER*(adj+1),2);
2665 if((signed int)addr>=(signed int)0xC0000000) {
2666 // Pagefault address
2667 int ds=regmap!=regs[i].regmap;
2668 emit_movimm(start+i*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
2671 //emit_writeword(2,(int)&Count);
2672 //emit_call(((u_int *)ftable)[addr>>16]);
2673 emit_call((int)&indirect_jump);
2674 // We really shouldn't need to update the count here,
2675 // but not doing so causes random crashes...
2676 emit_readword((int)&Count,HOST_TEMPREG);
2677 emit_readword((int)&next_interupt,2);
2678 emit_addimm(HOST_TEMPREG,-CLOCK_DIVIDER*(adj+1),HOST_TEMPREG);
2679 emit_writeword(2,(int)&last_count);
2680 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2682 emit_storereg(CCREG,HOST_TEMPREG);
2685 restore_regs(reglist);
2686 if(type==LOADB_STUB)
2687 emit_movsbl((int)&readmem_dword,rt);
2688 if(type==LOADBU_STUB)
2689 emit_movzbl((int)&readmem_dword,rt);
2690 if(type==LOADH_STUB)
2691 emit_movswl((int)&readmem_dword,rt);
2692 if(type==LOADHU_STUB)
2693 emit_movzwl((int)&readmem_dword,rt);
2694 if(type==LOADW_STUB)
2695 emit_readword((int)&readmem_dword,rt);
2696 if(type==LOADD_STUB) {
2697 emit_readword((int)&readmem_dword,rt);
2698 if(rth>=0) emit_readword(((int)&readmem_dword)+4,rth);
2704 assem_debug("do_writestub %x\n",start+stubs[n][3]*4);
2706 set_jump_target(stubs[n][1],(int)out);
2707 int type=stubs[n][0];
2710 struct regstat *i_regs=(struct regstat *)stubs[n][5];
2711 u_int reglist=stubs[n][7];
2712 signed char *i_regmap=i_regs->regmap;
2713 int addr=get_reg(i_regmap,AGEN1+(i&1));
2716 if(itype[i]==C1LS||itype[i]==C2LS) {
2717 rth=get_reg(i_regmap,FTEMP|64);
2718 rt=get_reg(i_regmap,r=FTEMP);
2720 rth=get_reg(i_regmap,rs2[i]|64);
2721 rt=get_reg(i_regmap,r=rs2[i]);
2725 if(addr<0) addr=get_reg(i_regmap,-1);
2728 if(type==STOREB_STUB)
2729 ftable=(int)writememb;
2730 if(type==STOREH_STUB)
2731 ftable=(int)writememh;
2732 if(type==STOREW_STUB)
2733 ftable=(int)writemem;
2735 if(type==STORED_STUB)
2736 ftable=(int)writememd;
2739 emit_writeword(rs,(int)&address);
2740 //emit_shrimm(rs,16,rs);
2741 //emit_movmem_indexedx4(ftable,rs,rs);
2742 if(type==STOREB_STUB)
2743 emit_writebyte(rt,(int)&byte);
2744 if(type==STOREH_STUB)
2745 emit_writehword(rt,(int)&hword);
2746 if(type==STOREW_STUB)
2747 emit_writeword(rt,(int)&word);
2748 if(type==STORED_STUB) {
2750 emit_writeword(rt,(int)&dword);
2751 emit_writeword(r?rth:rt,(int)&dword+4);
2753 printf("STORED_STUB\n");
2758 ds=i_regs!=®s[i];
2759 int real_rs=get_reg(i_regmap,rs1[i]);
2760 u_int cmask=ds?-1:(0x100f|~i_regs->wasconst);
2761 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&0x100f,i);
2762 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs)));
2763 if(!ds) wb_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&~0x100f,i);
2764 emit_shrimm(rs,16,1);
2765 int cc=get_reg(i_regmap,CCREG);
2767 emit_loadreg(CCREG,2);
2769 emit_movimm(ftable,0);
2770 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
2771 emit_movimm(start+stubs[n][3]*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
2772 //emit_readword((int)&last_count,temp);
2773 //emit_addimm(cc,2*stubs[n][5]+2,cc);
2774 //emit_add(cc,temp,cc);
2775 //emit_writeword(cc,(int)&Count);
2776 emit_call((int)&indirect_jump_indexed);
2778 emit_readword((int)&Count,HOST_TEMPREG);
2779 emit_readword((int)&next_interupt,2);
2780 emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
2781 emit_writeword(2,(int)&last_count);
2782 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2784 emit_storereg(CCREG,HOST_TEMPREG);
2787 restore_regs(reglist);
2788 //if((cc=get_reg(regmap,CCREG))>=0) {
2789 // emit_loadreg(CCREG,cc);
2791 emit_jmp(stubs[n][2]); // return address
2794 inline_writestub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
2796 int rs=get_reg(regmap,-1);
2797 int rth=get_reg(regmap,target|64);
2798 int rt=get_reg(regmap,target);
2802 if(type==STOREB_STUB)
2803 ftable=(int)writememb;
2804 if(type==STOREH_STUB)
2805 ftable=(int)writememh;
2806 if(type==STOREW_STUB)
2807 ftable=(int)writemem;
2809 if(type==STORED_STUB)
2810 ftable=(int)writememd;
2813 emit_writeword(rs,(int)&address);
2814 //emit_shrimm(rs,16,rs);
2815 //emit_movmem_indexedx4(ftable,rs,rs);
2816 if(type==STOREB_STUB)
2817 emit_writebyte(rt,(int)&byte);
2818 if(type==STOREH_STUB)
2819 emit_writehword(rt,(int)&hword);
2820 if(type==STOREW_STUB)
2821 emit_writeword(rt,(int)&word);
2822 if(type==STORED_STUB) {
2824 emit_writeword(rt,(int)&dword);
2825 emit_writeword(target?rth:rt,(int)&dword+4);
2827 printf("STORED_STUB\n");
2832 //emit_shrimm(rs,16,1);
2833 int cc=get_reg(regmap,CCREG);
2835 emit_loadreg(CCREG,2);
2837 //emit_movimm(ftable,0);
2838 emit_movimm(((u_int *)ftable)[addr>>16],0);
2839 //emit_readword((int)&last_count,12);
2840 emit_addimm(cc<0?2:cc,CLOCK_DIVIDER*(adj+1),2);
2841 if((signed int)addr>=(signed int)0xC0000000) {
2842 // Pagefault address
2843 int ds=regmap!=regs[i].regmap;
2844 emit_movimm(start+i*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
2847 //emit_writeword(2,(int)&Count);
2848 //emit_call(((u_int *)ftable)[addr>>16]);
2849 emit_call((int)&indirect_jump);
2850 emit_readword((int)&Count,HOST_TEMPREG);
2851 emit_readword((int)&next_interupt,2);
2852 emit_addimm(HOST_TEMPREG,-CLOCK_DIVIDER*(adj+1),HOST_TEMPREG);
2853 emit_writeword(2,(int)&last_count);
2854 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2856 emit_storereg(CCREG,HOST_TEMPREG);
2859 restore_regs(reglist);
2862 do_unalignedwritestub(int n)
2864 assem_debug("do_unalignedwritestub %x\n",start+stubs[n][3]*4);
2866 set_jump_target(stubs[n][1],(int)out);
2869 struct regstat *i_regs=(struct regstat *)stubs[n][4];
2870 int addr=stubs[n][5];
2871 u_int reglist=stubs[n][7];
2872 signed char *i_regmap=i_regs->regmap;
2873 int temp2=get_reg(i_regmap,FTEMP);
2876 rt=get_reg(i_regmap,rs2[i]);
2879 assert(opcode[i]==0x2a||opcode[i]==0x2e); // SWL/SWR only implemented
2881 reglist&=~(1<<temp2);
2883 emit_andimm(addr,0xfffffffc,temp2);
2884 emit_writeword(temp2,(int)&address);
2887 ds=i_regs!=®s[i];
2888 real_rs=get_reg(i_regmap,rs1[i]);
2889 u_int cmask=ds?-1:(0x100f|~i_regs->wasconst);
2890 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&0x100f,i);
2891 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs)));
2892 if(!ds) wb_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&~0x100f,i);
2893 emit_shrimm(addr,16,1);
2894 int cc=get_reg(i_regmap,CCREG);
2896 emit_loadreg(CCREG,2);
2898 emit_movimm((u_int)readmem,0);
2899 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
2900 emit_movimm(start+stubs[n][3]*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3); // XXX: can be rm'd?
2901 emit_call((int)&indirect_jump_indexed);
2902 restore_regs(reglist);
2904 emit_readword((int)&readmem_dword,temp2);
2905 int temp=addr; //hmh
2906 emit_shlimm(addr,3,temp);
2907 emit_andimm(temp,24,temp);
2908 #ifdef BIG_ENDIAN_MIPS
2909 if (opcode[i]==0x2e) // SWR
2911 if (opcode[i]==0x2a) // SWL
2913 emit_xorimm(temp,24,temp);
2914 emit_movimm(-1,HOST_TEMPREG);
2915 if (opcode[i]==0x2e) { // SWR
2916 emit_bic_lsr(temp2,HOST_TEMPREG,temp,temp2);
2917 emit_orrshr(rt,temp,temp2);
2919 emit_bic_lsl(temp2,HOST_TEMPREG,temp,temp2);
2920 emit_orrshl(rt,temp,temp2);
2922 emit_readword((int)&address,addr);
2923 emit_writeword(temp2,(int)&word);
2924 //save_regs(reglist); // don't need to, no state changes
2925 emit_shrimm(addr,16,1);
2926 emit_movimm((u_int)writemem,0);
2927 //emit_call((int)&indirect_jump_indexed);
2929 emit_readword_dualindexedx4(0,1,15);
2930 emit_readword((int)&Count,HOST_TEMPREG);
2931 emit_readword((int)&next_interupt,2);
2932 emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
2933 emit_writeword(2,(int)&last_count);
2934 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2936 emit_storereg(CCREG,HOST_TEMPREG);
2938 restore_regs(reglist);
2939 emit_jmp(stubs[n][2]); // return address
2942 void printregs(int edi,int esi,int ebp,int esp,int b,int d,int c,int a)
2944 printf("regs: %x %x %x %x %x %x %x (%x)\n",a,b,c,d,ebp,esi,edi,(&edi)[-1]);
2950 u_int reglist=stubs[n][3];
2951 set_jump_target(stubs[n][1],(int)out);
2953 if(stubs[n][4]!=0) emit_mov(stubs[n][4],0);
2954 emit_call((int)&invalidate_addr);
2955 restore_regs(reglist);
2956 emit_jmp(stubs[n][2]); // return address
2959 int do_dirty_stub(int i)
2961 assem_debug("do_dirty_stub %x\n",start+i*4);
2962 // Careful about the code output here, verify_dirty needs to parse it.
2964 emit_loadlp((int)start<(int)0xC0000000?(int)source:(int)start,1);
2965 emit_loadlp((int)copy,2);
2966 emit_loadlp(slen*4,3);
2968 emit_movw(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0x0000FFFF,1);
2969 emit_movw(((u_int)copy)&0x0000FFFF,2);
2970 emit_movt(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0xFFFF0000,1);
2971 emit_movt(((u_int)copy)&0xFFFF0000,2);
2972 emit_movw(slen*4,3);
2974 emit_movimm(start+i*4,0);
2975 emit_call((int)start<(int)0xC0000000?(int)&verify_code:(int)&verify_code_vm);
2978 if(entry==(int)out) entry=instr_addr[i];
2979 emit_jmp(instr_addr[i]);
2983 void do_dirty_stub_ds()
2985 // Careful about the code output here, verify_dirty needs to parse it.
2987 emit_loadlp((int)start<(int)0xC0000000?(int)source:(int)start,1);
2988 emit_loadlp((int)copy,2);
2989 emit_loadlp(slen*4,3);
2991 emit_movw(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0x0000FFFF,1);
2992 emit_movw(((u_int)copy)&0x0000FFFF,2);
2993 emit_movt(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0xFFFF0000,1);
2994 emit_movt(((u_int)copy)&0xFFFF0000,2);
2995 emit_movw(slen*4,3);
2997 emit_movimm(start+1,0);
2998 emit_call((int)&verify_code_ds);
3004 assem_debug("do_cop1stub %x\n",start+stubs[n][3]*4);
3005 set_jump_target(stubs[n][1],(int)out);
3007 // int rs=stubs[n][4];
3008 struct regstat *i_regs=(struct regstat *)stubs[n][5];
3011 load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
3012 //if(i_regs!=®s[i]) printf("oops: regs[i]=%x i_regs=%x",(int)®s[i],(int)i_regs);
3014 //else {printf("fp exception in delay slot\n");}
3015 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty);
3016 if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3017 emit_movimm(start+(i-ds)*4,EAX); // Get PC
3018 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3019 emit_jmp(ds?(int)fp_exception_ds:(int)fp_exception);
3024 int do_tlb_r(int s,int ar,int map,int x,int a,int shift,int c,u_int addr)
3027 if((signed int)addr>=(signed int)0xC0000000) {
3028 // address_generation already loaded the const
3029 emit_readword_dualindexedx4(FP,map,map);
3032 return -1; // No mapping
3036 emit_movimm(((int)memory_map-(int)&dynarec_local)>>2,map);
3037 emit_addsr12(map,s,map);
3038 // Schedule this while we wait on the load
3039 //if(x) emit_xorimm(s,x,ar);
3040 if(shift>=0) emit_shlimm(s,3,shift);
3041 if(~a) emit_andimm(s,a,ar);
3042 emit_readword_dualindexedx4(FP,map,map);
3046 int do_tlb_r_branch(int map, int c, u_int addr, int *jaddr)
3048 if(!c||(signed int)addr>=(signed int)0xC0000000) {
3056 int gen_tlb_addr_r(int ar, int map) {
3058 assem_debug("add %s,%s,%s lsl #2\n",regname[ar],regname[ar],regname[map]);
3059 output_w32(0xe0800100|rd_rn_rm(ar,ar,map));
3063 int do_tlb_w(int s,int ar,int map,int x,int c,u_int addr)
3066 if(addr<0x80800000||addr>=0xC0000000) {
3067 // address_generation already loaded the const
3068 emit_readword_dualindexedx4(FP,map,map);
3071 return -1; // No mapping
3075 emit_movimm(((int)memory_map-(int)&dynarec_local)>>2,map);
3076 emit_addsr12(map,s,map);
3077 // Schedule this while we wait on the load
3078 //if(x) emit_xorimm(s,x,ar);
3079 emit_readword_dualindexedx4(FP,map,map);
3083 int do_tlb_w_branch(int map, int c, u_int addr, int *jaddr)
3085 if(!c||addr<0x80800000||addr>=0xC0000000) {
3086 emit_testimm(map,0x40000000);
3092 int gen_tlb_addr_w(int ar, int map) {
3094 assem_debug("add %s,%s,%s lsl #2\n",regname[ar],regname[ar],regname[map]);
3095 output_w32(0xe0800100|rd_rn_rm(ar,ar,map));
3099 // Generate the address of the memory_map entry, relative to dynarec_local
3100 generate_map_const(u_int addr,int reg) {
3101 //printf("generate_map_const(%x,%s)\n",addr,regname[reg]);
3102 emit_movimm((addr>>12)+(((u_int)memory_map-(u_int)&dynarec_local)>>2),reg);
3107 void shift_assemble_arm(int i,struct regstat *i_regs)
3110 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
3112 signed char s,t,shift;
3113 t=get_reg(i_regs->regmap,rt1[i]);
3114 s=get_reg(i_regs->regmap,rs1[i]);
3115 shift=get_reg(i_regs->regmap,rs2[i]);
3124 if(s!=t) emit_mov(s,t);
3128 emit_andimm(shift,31,HOST_TEMPREG);
3129 if(opcode2[i]==4) // SLLV
3131 emit_shl(s,HOST_TEMPREG,t);
3133 if(opcode2[i]==6) // SRLV
3135 emit_shr(s,HOST_TEMPREG,t);
3137 if(opcode2[i]==7) // SRAV
3139 emit_sar(s,HOST_TEMPREG,t);
3143 } else { // DSLLV/DSRLV/DSRAV
3144 signed char sh,sl,th,tl,shift;
3145 th=get_reg(i_regs->regmap,rt1[i]|64);
3146 tl=get_reg(i_regs->regmap,rt1[i]);
3147 sh=get_reg(i_regs->regmap,rs1[i]|64);
3148 sl=get_reg(i_regs->regmap,rs1[i]);
3149 shift=get_reg(i_regs->regmap,rs2[i]);
3154 if(th>=0) emit_zeroreg(th);
3159 if(sl!=tl) emit_mov(sl,tl);
3160 if(th>=0&&sh!=th) emit_mov(sh,th);
3164 // FIXME: What if shift==tl ?
3166 int temp=get_reg(i_regs->regmap,-1);
3168 if(th<0&&opcode2[i]!=0x14) {th=temp;} // DSLLV doesn't need a temporary register
3171 emit_andimm(shift,31,HOST_TEMPREG);
3172 if(opcode2[i]==0x14) // DSLLV
3174 if(th>=0) emit_shl(sh,HOST_TEMPREG,th);
3175 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3176 emit_orrshr(sl,HOST_TEMPREG,th);
3177 emit_andimm(shift,31,HOST_TEMPREG);
3178 emit_testimm(shift,32);
3179 emit_shl(sl,HOST_TEMPREG,tl);
3180 if(th>=0) emit_cmovne_reg(tl,th);
3181 emit_cmovne_imm(0,tl);
3183 if(opcode2[i]==0x16) // DSRLV
3186 emit_shr(sl,HOST_TEMPREG,tl);
3187 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3188 emit_orrshl(sh,HOST_TEMPREG,tl);
3189 emit_andimm(shift,31,HOST_TEMPREG);
3190 emit_testimm(shift,32);
3191 emit_shr(sh,HOST_TEMPREG,th);
3192 emit_cmovne_reg(th,tl);
3193 if(real_th>=0) emit_cmovne_imm(0,th);
3195 if(opcode2[i]==0x17) // DSRAV
3198 emit_shr(sl,HOST_TEMPREG,tl);
3199 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3202 emit_sarimm(th,31,temp);
3204 emit_orrshl(sh,HOST_TEMPREG,tl);
3205 emit_andimm(shift,31,HOST_TEMPREG);
3206 emit_testimm(shift,32);
3207 emit_sar(sh,HOST_TEMPREG,th);
3208 emit_cmovne_reg(th,tl);
3209 if(real_th>=0) emit_cmovne_reg(temp,th);
3216 #define shift_assemble shift_assemble_arm
3218 void loadlr_assemble_arm(int i,struct regstat *i_regs)
3220 int s,th,tl,temp,temp2,addr,map=-1;
3225 th=get_reg(i_regs->regmap,rt1[i]|64);
3226 tl=get_reg(i_regs->regmap,rt1[i]);
3227 s=get_reg(i_regs->regmap,rs1[i]);
3228 temp=get_reg(i_regs->regmap,-1);
3229 temp2=get_reg(i_regs->regmap,FTEMP);
3230 addr=get_reg(i_regs->regmap,AGEN1+(i&1));
3233 for(hr=0;hr<HOST_REGS;hr++) {
3234 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3237 if(offset||s<0||c) addr=temp2;
3240 c=(i_regs->wasconst>>s)&1;
3241 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
3242 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3249 emit_shlimm(addr,3,temp);
3250 if (opcode[i]==0x22||opcode[i]==0x26) {
3251 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
3253 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
3255 emit_cmpimm(addr,0x800000);
3260 if (opcode[i]==0x22||opcode[i]==0x26) {
3261 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
3263 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
3270 }else if (opcode[i]==0x22||opcode[i]==0x26) {
3271 a=0xFFFFFFFC; // LWL/LWR
3273 a=0xFFFFFFF8; // LDL/LDR
3275 map=get_reg(i_regs->regmap,TLREG);
3277 map=do_tlb_r(addr,temp2,map,0,a,c?-1:temp,c,constmap[i][s]+offset);
3279 if (opcode[i]==0x22||opcode[i]==0x26) {
3280 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
3282 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
3285 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
3287 if (opcode[i]==0x22||opcode[i]==0x26) { // LWL/LWR
3289 //emit_readword_indexed((int)rdram-0x80000000,temp2,temp2);
3290 emit_readword_indexed_tlb((int)rdram-0x80000000,temp2,map,temp2);
3291 if(jaddr) add_stub(LOADW_STUB,jaddr,(int)out,i,temp2,(int)i_regs,ccadj[i],reglist);
3294 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj[i],reglist);
3295 emit_andimm(temp,24,temp);
3296 #ifdef BIG_ENDIAN_MIPS
3297 if (opcode[i]==0x26) // LWR
3299 if (opcode[i]==0x22) // LWL
3301 emit_xorimm(temp,24,temp);
3302 emit_movimm(-1,HOST_TEMPREG);
3303 if (opcode[i]==0x26) {
3304 emit_shr(temp2,temp,temp2);
3305 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
3307 emit_shl(temp2,temp,temp2);
3308 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
3310 emit_or(temp2,tl,tl);
3311 //emit_storereg(rt1[i],tl); // DEBUG
3313 if (opcode[i]==0x1A||opcode[i]==0x1B) { // LDL/LDR
3314 // FIXME: little endian
3315 int temp2h=get_reg(i_regs->regmap,FTEMP|64);
3317 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,temp2,temp2h);
3318 //emit_readword_indexed((int)rdram-0x7FFFFFFC,temp2,temp2);
3319 emit_readdword_indexed_tlb((int)rdram-0x80000000,temp2,map,temp2h,temp2);
3320 if(jaddr) add_stub(LOADD_STUB,jaddr,(int)out,i,temp2,(int)i_regs,ccadj[i],reglist);
3323 inline_readstub(LOADD_STUB,i,(constmap[i][s]+offset)&0xFFFFFFF8,i_regs->regmap,FTEMP,ccadj[i],reglist);
3324 emit_testimm(temp,32);
3325 emit_andimm(temp,24,temp);
3326 if (opcode[i]==0x1A) { // LDL
3327 emit_rsbimm(temp,32,HOST_TEMPREG);
3328 emit_shl(temp2h,temp,temp2h);
3329 emit_orrshr(temp2,HOST_TEMPREG,temp2h);
3330 emit_movimm(-1,HOST_TEMPREG);
3331 emit_shl(temp2,temp,temp2);
3332 emit_cmove_reg(temp2h,th);
3333 emit_biceq_lsl(tl,HOST_TEMPREG,temp,tl);
3334 emit_bicne_lsl(th,HOST_TEMPREG,temp,th);
3335 emit_orreq(temp2,tl,tl);
3336 emit_orrne(temp2,th,th);
3338 if (opcode[i]==0x1B) { // LDR
3339 emit_xorimm(temp,24,temp);
3340 emit_rsbimm(temp,32,HOST_TEMPREG);
3341 emit_shr(temp2,temp,temp2);
3342 emit_orrshl(temp2h,HOST_TEMPREG,temp2);
3343 emit_movimm(-1,HOST_TEMPREG);
3344 emit_shr(temp2h,temp,temp2h);
3345 emit_cmovne_reg(temp2,tl);
3346 emit_bicne_lsr(th,HOST_TEMPREG,temp,th);
3347 emit_biceq_lsr(tl,HOST_TEMPREG,temp,tl);
3348 emit_orrne(temp2h,th,th);
3349 emit_orreq(temp2h,tl,tl);
3354 #define loadlr_assemble loadlr_assemble_arm
3356 void cop0_assemble(int i,struct regstat *i_regs)
3358 if(opcode2[i]==0) // MFC0
3360 signed char t=get_reg(i_regs->regmap,rt1[i]);
3361 char copr=(source[i]>>11)&0x1f;
3362 //assert(t>=0); // Why does this happen? OOT is weird
3365 emit_addimm(FP,(int)&fake_pc-(int)&dynarec_local,0);
3366 emit_movimm((source[i]>>11)&0x1f,1);
3367 emit_writeword(0,(int)&PC);
3368 emit_writebyte(1,(int)&(fake_pc.f.r.nrd));
3370 emit_readword((int)&last_count,ECX);
3371 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3372 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3373 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3374 emit_writeword(HOST_CCREG,(int)&Count);
3376 emit_call((int)MFC0);
3377 emit_readword((int)&readmem_dword,t);
3379 emit_readword((int)®_cop0+copr*4,t);
3383 else if(opcode2[i]==4) // MTC0
3385 signed char s=get_reg(i_regs->regmap,rs1[i]);
3386 char copr=(source[i]>>11)&0x1f;
3388 emit_writeword(s,(int)&readmem_dword);
3389 wb_register(rs1[i],i_regs->regmap,i_regs->dirty,i_regs->is32);
3390 #ifdef MUPEN64 /// FIXME
3391 emit_addimm(FP,(int)&fake_pc-(int)&dynarec_local,0);
3392 emit_movimm((source[i]>>11)&0x1f,1);
3393 emit_writeword(0,(int)&PC);
3394 emit_writebyte(1,(int)&(fake_pc.f.r.nrd));
3397 emit_movimm(source[i],0);
3398 emit_writeword(0,(int)&psxRegs.code);
3400 if(copr==9||copr==11||copr==12||copr==13) {
3401 emit_readword((int)&last_count,ECX);
3402 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3403 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3404 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3405 emit_writeword(HOST_CCREG,(int)&Count);
3407 // What a mess. The status register (12) can enable interrupts,
3408 // so needs a special case to handle a pending interrupt.
3409 // The interrupt must be taken immediately, because a subsequent
3410 // instruction might disable interrupts again.
3411 if(copr==12||copr==13) {
3412 emit_movimm(start+i*4+4,0);
3414 emit_writeword(0,(int)&pcaddr);
3415 emit_writeword(1,(int)&pending_exception);
3417 //else if(copr==12&&is_delayslot) emit_call((int)MTC0_R12);
3419 emit_call((int)MTC0);
3420 if(copr==9||copr==11||copr==12||copr==13) {
3421 emit_readword((int)&Count,HOST_CCREG);
3422 emit_readword((int)&next_interupt,ECX);
3423 emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3424 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
3425 emit_writeword(ECX,(int)&last_count);
3426 emit_storereg(CCREG,HOST_CCREG);
3428 if(copr==12||copr==13) {
3429 assert(!is_delayslot);
3430 emit_readword((int)&pending_exception,14);
3432 emit_loadreg(rs1[i],s);
3433 if(get_reg(i_regs->regmap,rs1[i]|64)>=0)
3434 emit_loadreg(rs1[i]|64,get_reg(i_regs->regmap,rs1[i]|64));
3435 if(copr==12||copr==13) {
3437 emit_jne((int)&do_interrupt);
3443 assert(opcode2[i]==0x10);
3445 if((source[i]&0x3f)==0x01) // TLBR
3446 emit_call((int)TLBR);
3447 if((source[i]&0x3f)==0x02) // TLBWI
3448 emit_call((int)TLBWI_new);
3449 if((source[i]&0x3f)==0x06) { // TLBWR
3450 // The TLB entry written by TLBWR is dependent on the count,
3451 // so update the cycle count
3452 emit_readword((int)&last_count,ECX);
3453 if(i_regs->regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3454 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3455 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3456 emit_writeword(HOST_CCREG,(int)&Count);
3457 emit_call((int)TLBWR_new);
3459 if((source[i]&0x3f)==0x08) // TLBP
3460 emit_call((int)TLBP);
3462 if((source[i]&0x3f)==0x18) // ERET
3465 if(i_regs->regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3466 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*count,HOST_CCREG); // TODO: Should there be an extra cycle here?
3467 emit_jmp((int)jump_eret);
3472 static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3482 emit_readword((int)®_cop2d[copr],tl);
3483 emit_signextend16(tl,tl);
3484 emit_writeword(tl,(int)®_cop2d[copr]); // hmh
3491 emit_readword((int)®_cop2d[copr],tl);
3492 emit_andimm(tl,0xffff,tl);
3493 emit_writeword(tl,(int)®_cop2d[copr]);
3496 emit_readword((int)®_cop2d[14],tl); // SXY2
3497 emit_writeword(tl,(int)®_cop2d[copr]);
3504 emit_readword((int)®_cop2d[9],temp);
3505 emit_testimm(temp,0x8000); // do we need this?
3506 emit_andimm(temp,0xf80,temp);
3507 emit_andne_imm(temp,0,temp);
3508 emit_shr(temp,7,tl);
3509 emit_readword((int)®_cop2d[10],temp);
3510 emit_testimm(temp,0x8000);
3511 emit_andimm(temp,0xf80,temp);
3512 emit_andne_imm(temp,0,temp);
3513 emit_orrshr(temp,2,tl);
3514 emit_readword((int)®_cop2d[11],temp);
3515 emit_testimm(temp,0x8000);
3516 emit_andimm(temp,0xf80,temp);
3517 emit_andne_imm(temp,0,temp);
3518 emit_orrshl(temp,3,tl);
3519 emit_writeword(tl,(int)®_cop2d[copr]);
3522 emit_readword((int)®_cop2d[copr],tl);
3527 static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3531 emit_readword((int)®_cop2d[13],temp); // SXY1
3532 emit_writeword(sl,(int)®_cop2d[copr]);
3533 emit_writeword(temp,(int)®_cop2d[12]); // SXY0
3534 emit_readword((int)®_cop2d[14],temp); // SXY2
3535 emit_writeword(sl,(int)®_cop2d[14]);
3536 emit_writeword(temp,(int)®_cop2d[13]); // SXY1
3539 emit_andimm(sl,0x001f,temp);
3540 emit_shl(temp,7,temp);
3541 emit_writeword(temp,(int)®_cop2d[9]);
3542 emit_andimm(sl,0x03e0,temp);
3543 emit_shl(temp,2,temp);
3544 emit_writeword(temp,(int)®_cop2d[10]);
3545 emit_andimm(sl,0x7c00,temp);
3546 emit_shr(temp,3,temp);
3547 emit_writeword(temp,(int)®_cop2d[11]);
3548 emit_writeword(sl,(int)®_cop2d[28]);
3552 emit_mvnmi(temp,temp);
3553 emit_clz(temp,temp);
3554 emit_writeword(sl,(int)®_cop2d[30]);
3555 emit_writeword(temp,(int)®_cop2d[31]);
3562 emit_writeword(sl,(int)®_cop2d[copr]);
3567 void cop2_assemble(int i,struct regstat *i_regs)
3569 u_int copr=(source[i]>>11)&0x1f;
3570 signed char temp=get_reg(i_regs->regmap,-1);
3571 if (opcode2[i]==0) { // MFC2
3572 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3574 cop2_get_dreg(copr,tl,temp);
3576 else if (opcode2[i]==4) { // MTC2
3577 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3578 cop2_put_dreg(copr,sl,temp);
3580 else if (opcode2[i]==2) // CFC2
3582 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3584 emit_readword((int)®_cop2c[copr],tl);
3586 else if (opcode2[i]==6) // CTC2
3588 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3597 emit_signextend16(sl,temp);
3600 //value = value & 0x7ffff000;
3601 //if (value & 0x7f87e000) value |= 0x80000000;
3602 emit_shrimm(sl,12,temp);
3603 emit_shlimm(temp,12,temp);
3604 emit_testimm(temp,0x7f000000);
3605 emit_testeqimm(temp,0x00870000);
3606 emit_testeqimm(temp,0x0000e000);
3607 emit_orrne_imm(temp,0x80000000,temp);
3613 emit_writeword(temp,(int)®_cop2c[copr]);
3618 void c2op_assemble(int i,struct regstat *i_regs)
3620 signed char temp=get_reg(i_regs->regmap,-1);
3621 u_int c2op=source[i]&0x3f;
3623 for(hr=0;hr<HOST_REGS;hr++) {
3624 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3626 if(i==0||itype[i-1]!=C2OP)
3629 if (gte_handlers[c2op]!=NULL) {
3630 int cc=get_reg(i_regs->regmap,CCREG);
3631 emit_movimm(source[i],temp); // opcode
3632 if (cc>=0&>e_cycletab[c2op])
3633 emit_addimm(cc,gte_cycletab[c2op]/2,cc); // XXX: cound just adjust ccadj?
3634 emit_writeword(temp,(int)&psxRegs.code);
3635 emit_call((int)gte_handlers[c2op]);
3638 if(i>=slen-1||itype[i+1]!=C2OP)
3639 restore_regs(reglist);
3642 void cop1_unusable(int i,struct regstat *i_regs)
3644 // XXX: should just just do the exception instead
3648 add_stub(FP_STUB,jaddr,(int)out,i,0,(int)i_regs,is_delayslot,0);
3653 void cop1_assemble(int i,struct regstat *i_regs)
3655 #ifndef DISABLE_COP1
3656 // Check cop1 unusable
3658 signed char rs=get_reg(i_regs->regmap,CSREG);
3660 emit_testimm(rs,0x20000000);
3663 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3666 if (opcode2[i]==0) { // MFC1
3667 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3669 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],tl);
3670 emit_readword_indexed(0,tl,tl);
3673 else if (opcode2[i]==1) { // DMFC1
3674 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3675 signed char th=get_reg(i_regs->regmap,rt1[i]|64);
3677 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],tl);
3678 if(th>=0) emit_readword_indexed(4,tl,th);
3679 emit_readword_indexed(0,tl,tl);
3682 else if (opcode2[i]==4) { // MTC1
3683 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3684 signed char temp=get_reg(i_regs->regmap,-1);
3685 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
3686 emit_writeword_indexed(sl,0,temp);
3688 else if (opcode2[i]==5) { // DMTC1
3689 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3690 signed char sh=rs1[i]>0?get_reg(i_regs->regmap,rs1[i]|64):sl;
3691 signed char temp=get_reg(i_regs->regmap,-1);
3692 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
3693 emit_writeword_indexed(sh,4,temp);
3694 emit_writeword_indexed(sl,0,temp);
3696 else if (opcode2[i]==2) // CFC1
3698 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3700 u_int copr=(source[i]>>11)&0x1f;
3701 if(copr==0) emit_readword((int)&FCR0,tl);
3702 if(copr==31) emit_readword((int)&FCR31,tl);
3705 else if (opcode2[i]==6) // CTC1
3707 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3708 u_int copr=(source[i]>>11)&0x1f;
3712 emit_writeword(sl,(int)&FCR31);
3713 // Set the rounding mode
3715 //char temp=get_reg(i_regs->regmap,-1);
3716 //emit_andimm(sl,3,temp);
3717 //emit_fldcw_indexed((int)&rounding_modes,temp);
3721 cop1_unusable(i, i_regs);
3725 void fconv_assemble_arm(int i,struct regstat *i_regs)
3727 #ifndef DISABLE_COP1
3728 signed char temp=get_reg(i_regs->regmap,-1);
3730 // Check cop1 unusable
3732 signed char rs=get_reg(i_regs->regmap,CSREG);
3734 emit_testimm(rs,0x20000000);
3737 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3741 #if(defined(__VFP_FP__) && !defined(__SOFTFP__))
3742 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0d) { // trunc_w_s
3743 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
3745 emit_ftosizs(15,15); // float->int, truncate
3746 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f))
3747 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
3751 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0d) { // trunc_w_d
3752 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
3754 emit_ftosizd(7,13); // double->int, truncate
3755 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
3760 if(opcode2[i]==0x14&&(source[i]&0x3f)==0x20) { // cvt_s_w
3761 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
3763 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f))
3764 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
3769 if(opcode2[i]==0x14&&(source[i]&0x3f)==0x21) { // cvt_d_w
3770 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
3772 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
3778 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x21) { // cvt_d_s
3779 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
3781 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
3786 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x20) { // cvt_s_d
3787 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
3789 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
3799 for(hr=0;hr<HOST_REGS;hr++) {
3800 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3804 if(opcode2[i]==0x14&&(source[i]&0x3f)==0x20) {
3805 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3806 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3807 emit_call((int)cvt_s_w);
3809 if(opcode2[i]==0x14&&(source[i]&0x3f)==0x21) {
3810 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3811 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3812 emit_call((int)cvt_d_w);
3814 if(opcode2[i]==0x15&&(source[i]&0x3f)==0x20) {
3815 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3816 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3817 emit_call((int)cvt_s_l);
3819 if(opcode2[i]==0x15&&(source[i]&0x3f)==0x21) {
3820 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3821 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3822 emit_call((int)cvt_d_l);
3825 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x21) {
3826 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3827 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3828 emit_call((int)cvt_d_s);
3830 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x24) {
3831 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3832 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3833 emit_call((int)cvt_w_s);
3835 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x25) {
3836 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3837 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3838 emit_call((int)cvt_l_s);
3841 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x20) {
3842 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3843 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3844 emit_call((int)cvt_s_d);
3846 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x24) {
3847 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3848 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3849 emit_call((int)cvt_w_d);
3851 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x25) {
3852 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3853 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3854 emit_call((int)cvt_l_d);
3857 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x08) {
3858 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3859 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3860 emit_call((int)round_l_s);
3862 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x09) {
3863 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3864 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3865 emit_call((int)trunc_l_s);
3867 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0a) {
3868 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3869 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3870 emit_call((int)ceil_l_s);
3872 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0b) {
3873 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3874 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3875 emit_call((int)floor_l_s);
3877 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0c) {
3878 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3879 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3880 emit_call((int)round_w_s);
3882 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0d) {
3883 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3884 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3885 emit_call((int)trunc_w_s);
3887 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0e) {
3888 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3889 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3890 emit_call((int)ceil_w_s);
3892 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0f) {
3893 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3894 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3895 emit_call((int)floor_w_s);
3898 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x08) {
3899 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3900 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3901 emit_call((int)round_l_d);
3903 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x09) {
3904 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3905 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3906 emit_call((int)trunc_l_d);
3908 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0a) {
3909 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3910 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3911 emit_call((int)ceil_l_d);
3913 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0b) {
3914 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3915 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3916 emit_call((int)floor_l_d);
3918 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0c) {
3919 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3920 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3921 emit_call((int)round_w_d);
3923 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0d) {
3924 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3925 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3926 emit_call((int)trunc_w_d);
3928 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0e) {
3929 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3930 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3931 emit_call((int)ceil_w_d);
3933 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0f) {
3934 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3935 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3936 emit_call((int)floor_w_d);
3939 restore_regs(reglist);
3941 cop1_unusable(i, i_regs);
3944 #define fconv_assemble fconv_assemble_arm
3946 void fcomp_assemble(int i,struct regstat *i_regs)
3948 #ifndef DISABLE_COP1
3949 signed char fs=get_reg(i_regs->regmap,FSREG);
3950 signed char temp=get_reg(i_regs->regmap,-1);
3952 // Check cop1 unusable
3954 signed char cs=get_reg(i_regs->regmap,CSREG);
3956 emit_testimm(cs,0x20000000);
3959 add_stub(FP_STUB,jaddr,(int)out,i,cs,(int)i_regs,is_delayslot,0);
3963 if((source[i]&0x3f)==0x30) {
3964 emit_andimm(fs,~0x800000,fs);
3968 if((source[i]&0x3e)==0x38) {
3969 // sf/ngle - these should throw exceptions for NaNs
3970 emit_andimm(fs,~0x800000,fs);
3974 #if(defined(__VFP_FP__) && !defined(__SOFTFP__))
3975 if(opcode2[i]==0x10) {
3976 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
3977 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],HOST_TEMPREG);
3978 emit_orimm(fs,0x800000,fs);
3980 emit_flds(HOST_TEMPREG,15);
3983 if((source[i]&0x3f)==0x31) emit_bicvc_imm(fs,0x800000,fs); // c_un_s
3984 if((source[i]&0x3f)==0x32) emit_bicne_imm(fs,0x800000,fs); // c_eq_s
3985 if((source[i]&0x3f)==0x33) {emit_bicne_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ueq_s
3986 if((source[i]&0x3f)==0x34) emit_biccs_imm(fs,0x800000,fs); // c_olt_s
3987 if((source[i]&0x3f)==0x35) {emit_biccs_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ult_s
3988 if((source[i]&0x3f)==0x36) emit_bichi_imm(fs,0x800000,fs); // c_ole_s
3989 if((source[i]&0x3f)==0x37) {emit_bichi_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ule_s
3990 if((source[i]&0x3f)==0x3a) emit_bicne_imm(fs,0x800000,fs); // c_seq_s
3991 if((source[i]&0x3f)==0x3b) emit_bicne_imm(fs,0x800000,fs); // c_ngl_s
3992 if((source[i]&0x3f)==0x3c) emit_biccs_imm(fs,0x800000,fs); // c_lt_s
3993 if((source[i]&0x3f)==0x3d) emit_biccs_imm(fs,0x800000,fs); // c_nge_s
3994 if((source[i]&0x3f)==0x3e) emit_bichi_imm(fs,0x800000,fs); // c_le_s
3995 if((source[i]&0x3f)==0x3f) emit_bichi_imm(fs,0x800000,fs); // c_ngt_s
3998 if(opcode2[i]==0x11) {
3999 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
4000 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],HOST_TEMPREG);
4001 emit_orimm(fs,0x800000,fs);
4003 emit_vldr(HOST_TEMPREG,7);
4006 if((source[i]&0x3f)==0x31) emit_bicvc_imm(fs,0x800000,fs); // c_un_d
4007 if((source[i]&0x3f)==0x32) emit_bicne_imm(fs,0x800000,fs); // c_eq_d
4008 if((source[i]&0x3f)==0x33) {emit_bicne_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ueq_d
4009 if((source[i]&0x3f)==0x34) emit_biccs_imm(fs,0x800000,fs); // c_olt_d
4010 if((source[i]&0x3f)==0x35) {emit_biccs_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ult_d
4011 if((source[i]&0x3f)==0x36) emit_bichi_imm(fs,0x800000,fs); // c_ole_d
4012 if((source[i]&0x3f)==0x37) {emit_bichi_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ule_d
4013 if((source[i]&0x3f)==0x3a) emit_bicne_imm(fs,0x800000,fs); // c_seq_d
4014 if((source[i]&0x3f)==0x3b) emit_bicne_imm(fs,0x800000,fs); // c_ngl_d
4015 if((source[i]&0x3f)==0x3c) emit_biccs_imm(fs,0x800000,fs); // c_lt_d
4016 if((source[i]&0x3f)==0x3d) emit_biccs_imm(fs,0x800000,fs); // c_nge_d
4017 if((source[i]&0x3f)==0x3e) emit_bichi_imm(fs,0x800000,fs); // c_le_d
4018 if((source[i]&0x3f)==0x3f) emit_bichi_imm(fs,0x800000,fs); // c_ngt_d
4026 for(hr=0;hr<HOST_REGS;hr++) {
4027 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
4031 if(opcode2[i]==0x10) {
4032 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4033 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],ARG2_REG);
4034 if((source[i]&0x3f)==0x30) emit_call((int)c_f_s);
4035 if((source[i]&0x3f)==0x31) emit_call((int)c_un_s);
4036 if((source[i]&0x3f)==0x32) emit_call((int)c_eq_s);
4037 if((source[i]&0x3f)==0x33) emit_call((int)c_ueq_s);
4038 if((source[i]&0x3f)==0x34) emit_call((int)c_olt_s);
4039 if((source[i]&0x3f)==0x35) emit_call((int)c_ult_s);
4040 if((source[i]&0x3f)==0x36) emit_call((int)c_ole_s);
4041 if((source[i]&0x3f)==0x37) emit_call((int)c_ule_s);
4042 if((source[i]&0x3f)==0x38) emit_call((int)c_sf_s);
4043 if((source[i]&0x3f)==0x39) emit_call((int)c_ngle_s);
4044 if((source[i]&0x3f)==0x3a) emit_call((int)c_seq_s);
4045 if((source[i]&0x3f)==0x3b) emit_call((int)c_ngl_s);
4046 if((source[i]&0x3f)==0x3c) emit_call((int)c_lt_s);
4047 if((source[i]&0x3f)==0x3d) emit_call((int)c_nge_s);
4048 if((source[i]&0x3f)==0x3e) emit_call((int)c_le_s);
4049 if((source[i]&0x3f)==0x3f) emit_call((int)c_ngt_s);
4051 if(opcode2[i]==0x11) {
4052 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4053 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],ARG2_REG);
4054 if((source[i]&0x3f)==0x30) emit_call((int)c_f_d);
4055 if((source[i]&0x3f)==0x31) emit_call((int)c_un_d);
4056 if((source[i]&0x3f)==0x32) emit_call((int)c_eq_d);
4057 if((source[i]&0x3f)==0x33) emit_call((int)c_ueq_d);
4058 if((source[i]&0x3f)==0x34) emit_call((int)c_olt_d);
4059 if((source[i]&0x3f)==0x35) emit_call((int)c_ult_d);
4060 if((source[i]&0x3f)==0x36) emit_call((int)c_ole_d);
4061 if((source[i]&0x3f)==0x37) emit_call((int)c_ule_d);
4062 if((source[i]&0x3f)==0x38) emit_call((int)c_sf_d);
4063 if((source[i]&0x3f)==0x39) emit_call((int)c_ngle_d);
4064 if((source[i]&0x3f)==0x3a) emit_call((int)c_seq_d);
4065 if((source[i]&0x3f)==0x3b) emit_call((int)c_ngl_d);
4066 if((source[i]&0x3f)==0x3c) emit_call((int)c_lt_d);
4067 if((source[i]&0x3f)==0x3d) emit_call((int)c_nge_d);
4068 if((source[i]&0x3f)==0x3e) emit_call((int)c_le_d);
4069 if((source[i]&0x3f)==0x3f) emit_call((int)c_ngt_d);
4071 restore_regs(reglist);
4072 emit_loadreg(FSREG,fs);
4074 cop1_unusable(i, i_regs);
4078 void float_assemble(int i,struct regstat *i_regs)
4080 #ifndef DISABLE_COP1
4081 signed char temp=get_reg(i_regs->regmap,-1);
4083 // Check cop1 unusable
4085 signed char cs=get_reg(i_regs->regmap,CSREG);
4087 emit_testimm(cs,0x20000000);
4090 add_stub(FP_STUB,jaddr,(int)out,i,cs,(int)i_regs,is_delayslot,0);
4094 #if(defined(__VFP_FP__) && !defined(__SOFTFP__))
4095 if((source[i]&0x3f)==6) // mov
4097 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4098 if(opcode2[i]==0x10) {
4099 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
4100 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],HOST_TEMPREG);
4101 emit_readword_indexed(0,temp,temp);
4102 emit_writeword_indexed(temp,0,HOST_TEMPREG);
4104 if(opcode2[i]==0x11) {
4105 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
4106 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],HOST_TEMPREG);
4108 emit_vstr(7,HOST_TEMPREG);
4114 if((source[i]&0x3f)>3)
4116 if(opcode2[i]==0x10) {
4117 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
4119 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4120 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
4122 if((source[i]&0x3f)==4) // sqrt
4124 if((source[i]&0x3f)==5) // abs
4126 if((source[i]&0x3f)==7) // neg
4130 if(opcode2[i]==0x11) {
4131 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
4133 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4134 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
4136 if((source[i]&0x3f)==4) // sqrt
4138 if((source[i]&0x3f)==5) // abs
4140 if((source[i]&0x3f)==7) // neg
4146 if((source[i]&0x3f)<4)
4148 if(opcode2[i]==0x10) {
4149 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
4151 if(opcode2[i]==0x11) {
4152 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
4154 if(((source[i]>>11)&0x1f)!=((source[i]>>16)&0x1f)) {
4155 if(opcode2[i]==0x10) {
4156 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],HOST_TEMPREG);
4158 emit_flds(HOST_TEMPREG,13);
4159 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4160 if(((source[i]>>16)&0x1f)!=((source[i]>>6)&0x1f)) {
4161 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
4164 if((source[i]&0x3f)==0) emit_fadds(15,13,15);
4165 if((source[i]&0x3f)==1) emit_fsubs(15,13,15);
4166 if((source[i]&0x3f)==2) emit_fmuls(15,13,15);
4167 if((source[i]&0x3f)==3) emit_fdivs(15,13,15);
4168 if(((source[i]>>16)&0x1f)==((source[i]>>6)&0x1f)) {
4169 emit_fsts(15,HOST_TEMPREG);
4174 else if(opcode2[i]==0x11) {
4175 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],HOST_TEMPREG);
4177 emit_vldr(HOST_TEMPREG,6);
4178 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4179 if(((source[i]>>16)&0x1f)!=((source[i]>>6)&0x1f)) {
4180 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
4183 if((source[i]&0x3f)==0) emit_faddd(7,6,7);
4184 if((source[i]&0x3f)==1) emit_fsubd(7,6,7);
4185 if((source[i]&0x3f)==2) emit_fmuld(7,6,7);
4186 if((source[i]&0x3f)==3) emit_fdivd(7,6,7);
4187 if(((source[i]>>16)&0x1f)==((source[i]>>6)&0x1f)) {
4188 emit_vstr(7,HOST_TEMPREG);
4195 if(opcode2[i]==0x10) {
4197 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4198 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
4200 if((source[i]&0x3f)==0) emit_fadds(15,15,15);
4201 if((source[i]&0x3f)==1) emit_fsubs(15,15,15);
4202 if((source[i]&0x3f)==2) emit_fmuls(15,15,15);
4203 if((source[i]&0x3f)==3) emit_fdivs(15,15,15);
4206 else if(opcode2[i]==0x11) {
4208 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4209 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
4211 if((source[i]&0x3f)==0) emit_faddd(7,7,7);
4212 if((source[i]&0x3f)==1) emit_fsubd(7,7,7);
4213 if((source[i]&0x3f)==2) emit_fmuld(7,7,7);
4214 if((source[i]&0x3f)==3) emit_fdivd(7,7,7);
4223 for(hr=0;hr<HOST_REGS;hr++) {
4224 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
4226 if(opcode2[i]==0x10) { // Single precision
4228 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4229 if((source[i]&0x3f)<4) {
4230 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],ARG2_REG);
4231 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG3_REG);
4233 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4235 switch(source[i]&0x3f)
4237 case 0x00: emit_call((int)add_s);break;
4238 case 0x01: emit_call((int)sub_s);break;
4239 case 0x02: emit_call((int)mul_s);break;
4240 case 0x03: emit_call((int)div_s);break;
4241 case 0x04: emit_call((int)sqrt_s);break;
4242 case 0x05: emit_call((int)abs_s);break;
4243 case 0x06: emit_call((int)mov_s);break;
4244 case 0x07: emit_call((int)neg_s);break;
4246 restore_regs(reglist);
4248 if(opcode2[i]==0x11) { // Double precision
4250 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4251 if((source[i]&0x3f)<4) {
4252 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],ARG2_REG);
4253 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG3_REG);
4255 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4257 switch(source[i]&0x3f)
4259 case 0x00: emit_call((int)add_d);break;
4260 case 0x01: emit_call((int)sub_d);break;
4261 case 0x02: emit_call((int)mul_d);break;
4262 case 0x03: emit_call((int)div_d);break;
4263 case 0x04: emit_call((int)sqrt_d);break;
4264 case 0x05: emit_call((int)abs_d);break;
4265 case 0x06: emit_call((int)mov_d);break;
4266 case 0x07: emit_call((int)neg_d);break;
4268 restore_regs(reglist);
4271 cop1_unusable(i, i_regs);
4275 void multdiv_assemble_arm(int i,struct regstat *i_regs)
4282 // case 0x1D: DMULTU
4287 if((opcode2[i]&4)==0) // 32-bit
4289 if(opcode2[i]==0x18) // MULT
4291 signed char m1=get_reg(i_regs->regmap,rs1[i]);
4292 signed char m2=get_reg(i_regs->regmap,rs2[i]);
4293 signed char hi=get_reg(i_regs->regmap,HIREG);
4294 signed char lo=get_reg(i_regs->regmap,LOREG);
4299 emit_smull(m1,m2,hi,lo);
4301 if(opcode2[i]==0x19) // MULTU
4303 signed char m1=get_reg(i_regs->regmap,rs1[i]);
4304 signed char m2=get_reg(i_regs->regmap,rs2[i]);
4305 signed char hi=get_reg(i_regs->regmap,HIREG);
4306 signed char lo=get_reg(i_regs->regmap,LOREG);
4311 emit_umull(m1,m2,hi,lo);
4313 if(opcode2[i]==0x1A) // DIV
4315 signed char d1=get_reg(i_regs->regmap,rs1[i]);
4316 signed char d2=get_reg(i_regs->regmap,rs2[i]);
4319 signed char quotient=get_reg(i_regs->regmap,LOREG);
4320 signed char remainder=get_reg(i_regs->regmap,HIREG);
4321 assert(quotient>=0);
4322 assert(remainder>=0);
4323 emit_movs(d1,remainder);
4324 emit_negmi(remainder,remainder);
4325 emit_movs(d2,HOST_TEMPREG);
4326 emit_jeq((int)out+52); // Division by zero
4327 emit_negmi(HOST_TEMPREG,HOST_TEMPREG);
4328 emit_clz(HOST_TEMPREG,quotient);
4329 emit_shl(HOST_TEMPREG,quotient,HOST_TEMPREG);
4330 emit_orimm(quotient,1<<31,quotient);
4331 emit_shr(quotient,quotient,quotient);
4332 emit_cmp(remainder,HOST_TEMPREG);
4333 emit_subcs(remainder,HOST_TEMPREG,remainder);
4334 emit_adcs(quotient,quotient,quotient);
4335 emit_shrimm(HOST_TEMPREG,1,HOST_TEMPREG);
4336 emit_jcc((int)out-16); // -4
4338 emit_negmi(quotient,quotient);
4340 emit_negmi(remainder,remainder);
4342 if(opcode2[i]==0x1B) // DIVU
4344 signed char d1=get_reg(i_regs->regmap,rs1[i]); // dividend
4345 signed char d2=get_reg(i_regs->regmap,rs2[i]); // divisor
4348 signed char quotient=get_reg(i_regs->regmap,LOREG);
4349 signed char remainder=get_reg(i_regs->regmap,HIREG);
4350 assert(quotient>=0);
4351 assert(remainder>=0);
4353 emit_jeq((int)out+44); // Division by zero
4354 emit_clz(d2,HOST_TEMPREG);
4355 emit_movimm(1<<31,quotient);
4356 emit_shl(d2,HOST_TEMPREG,d2);
4357 emit_mov(d1,remainder);
4358 emit_shr(quotient,HOST_TEMPREG,quotient);
4359 emit_cmp(remainder,d2);
4360 emit_subcs(remainder,d2,remainder);
4361 emit_adcs(quotient,quotient,quotient);
4362 emit_shrcc_imm(d2,1,d2);
4363 emit_jcc((int)out-16); // -4
4368 if(opcode2[i]==0x1C) // DMULT
4370 assert(opcode2[i]!=0x1C);
4371 signed char m1h=get_reg(i_regs->regmap,rs1[i]|64);
4372 signed char m1l=get_reg(i_regs->regmap,rs1[i]);
4373 signed char m2h=get_reg(i_regs->regmap,rs2[i]|64);
4374 signed char m2l=get_reg(i_regs->regmap,rs2[i]);
4383 emit_call((int)&mult64);
4388 signed char hih=get_reg(i_regs->regmap,HIREG|64);
4389 signed char hil=get_reg(i_regs->regmap,HIREG);
4390 if(hih>=0) emit_loadreg(HIREG|64,hih);
4391 if(hil>=0) emit_loadreg(HIREG,hil);
4392 signed char loh=get_reg(i_regs->regmap,LOREG|64);
4393 signed char lol=get_reg(i_regs->regmap,LOREG);
4394 if(loh>=0) emit_loadreg(LOREG|64,loh);
4395 if(lol>=0) emit_loadreg(LOREG,lol);
4397 if(opcode2[i]==0x1D) // DMULTU
4399 signed char m1h=get_reg(i_regs->regmap,rs1[i]|64);
4400 signed char m1l=get_reg(i_regs->regmap,rs1[i]);
4401 signed char m2h=get_reg(i_regs->regmap,rs2[i]|64);
4402 signed char m2l=get_reg(i_regs->regmap,rs2[i]);
4408 if(m1l!=0) emit_mov(m1l,0);
4409 if(m1h==0) emit_readword((int)&dynarec_local,1);
4410 else if(m1h>1) emit_mov(m1h,1);
4411 if(m2l<2) emit_readword((int)&dynarec_local+m2l*4,2);
4412 else if(m2l>2) emit_mov(m2l,2);
4413 if(m2h<3) emit_readword((int)&dynarec_local+m2h*4,3);
4414 else if(m2h>3) emit_mov(m2h,3);
4415 emit_call((int)&multu64);
4416 restore_regs(0x100f);
4417 signed char hih=get_reg(i_regs->regmap,HIREG|64);
4418 signed char hil=get_reg(i_regs->regmap,HIREG);
4419 signed char loh=get_reg(i_regs->regmap,LOREG|64);
4420 signed char lol=get_reg(i_regs->regmap,LOREG);
4421 /*signed char temp=get_reg(i_regs->regmap,-1);
4422 signed char rh=get_reg(i_regs->regmap,HIREG|64);
4423 signed char rl=get_reg(i_regs->regmap,HIREG);
4429 //emit_mov(m1l,EAX);
4431 emit_umull(rl,rh,m1l,m2l);
4432 emit_storereg(LOREG,rl);
4434 //emit_mov(m1h,EAX);
4436 emit_umull(rl,rh,m1h,m2l);
4437 emit_adds(rl,temp,temp);
4438 emit_adcimm(rh,0,rh);
4439 emit_storereg(HIREG,rh);
4440 //emit_mov(m2h,EAX);
4442 emit_umull(rl,rh,m1l,m2h);
4443 emit_adds(rl,temp,temp);
4444 emit_adcimm(rh,0,rh);
4445 emit_storereg(LOREG|64,temp);
4447 //emit_mov(m2h,EAX);
4449 emit_umull(rl,rh,m1h,m2h);
4450 emit_adds(rl,temp,rl);
4451 emit_loadreg(HIREG,temp);
4452 emit_adcimm(rh,0,rh);
4453 emit_adds(rl,temp,rl);
4454 emit_adcimm(rh,0,rh);
4461 emit_call((int)&multu64);
4466 signed char hih=get_reg(i_regs->regmap,HIREG|64);
4467 signed char hil=get_reg(i_regs->regmap,HIREG);
4468 if(hih>=0) emit_loadreg(HIREG|64,hih); // DEBUG
4469 if(hil>=0) emit_loadreg(HIREG,hil); // DEBUG
4471 // Shouldn't be necessary
4472 //char loh=get_reg(i_regs->regmap,LOREG|64);
4473 //char lol=get_reg(i_regs->regmap,LOREG);
4474 //if(loh>=0) emit_loadreg(LOREG|64,loh);
4475 //if(lol>=0) emit_loadreg(LOREG,lol);
4477 if(opcode2[i]==0x1E) // DDIV
4479 signed char d1h=get_reg(i_regs->regmap,rs1[i]|64);
4480 signed char d1l=get_reg(i_regs->regmap,rs1[i]);
4481 signed char d2h=get_reg(i_regs->regmap,rs2[i]|64);
4482 signed char d2l=get_reg(i_regs->regmap,rs2[i]);
4488 if(d1l!=0) emit_mov(d1l,0);
4489 if(d1h==0) emit_readword((int)&dynarec_local,1);
4490 else if(d1h>1) emit_mov(d1h,1);
4491 if(d2l<2) emit_readword((int)&dynarec_local+d2l*4,2);
4492 else if(d2l>2) emit_mov(d2l,2);
4493 if(d2h<3) emit_readword((int)&dynarec_local+d2h*4,3);
4494 else if(d2h>3) emit_mov(d2h,3);
4495 emit_call((int)&div64);
4496 restore_regs(0x100f);
4497 signed char hih=get_reg(i_regs->regmap,HIREG|64);
4498 signed char hil=get_reg(i_regs->regmap,HIREG);
4499 signed char loh=get_reg(i_regs->regmap,LOREG|64);
4500 signed char lol=get_reg(i_regs->regmap,LOREG);
4501 if(hih>=0) emit_loadreg(HIREG|64,hih);
4502 if(hil>=0) emit_loadreg(HIREG,hil);
4503 if(loh>=0) emit_loadreg(LOREG|64,loh);
4504 if(lol>=0) emit_loadreg(LOREG,lol);
4506 if(opcode2[i]==0x1F) // DDIVU
4508 //u_int hr,reglist=0;
4509 //for(hr=0;hr<HOST_REGS;hr++) {
4510 // if(i_regs->regmap[hr]>=0 && (i_regs->regmap[hr]&62)!=HIREG) reglist|=1<<hr;
4512 signed char d1h=get_reg(i_regs->regmap,rs1[i]|64);
4513 signed char d1l=get_reg(i_regs->regmap,rs1[i]);
4514 signed char d2h=get_reg(i_regs->regmap,rs2[i]|64);
4515 signed char d2l=get_reg(i_regs->regmap,rs2[i]);
4521 if(d1l!=0) emit_mov(d1l,0);
4522 if(d1h==0) emit_readword((int)&dynarec_local,1);
4523 else if(d1h>1) emit_mov(d1h,1);
4524 if(d2l<2) emit_readword((int)&dynarec_local+d2l*4,2);
4525 else if(d2l>2) emit_mov(d2l,2);
4526 if(d2h<3) emit_readword((int)&dynarec_local+d2h*4,3);
4527 else if(d2h>3) emit_mov(d2h,3);
4528 emit_call((int)&divu64);
4529 restore_regs(0x100f);
4530 signed char hih=get_reg(i_regs->regmap,HIREG|64);
4531 signed char hil=get_reg(i_regs->regmap,HIREG);
4532 signed char loh=get_reg(i_regs->regmap,LOREG|64);
4533 signed char lol=get_reg(i_regs->regmap,LOREG);
4534 if(hih>=0) emit_loadreg(HIREG|64,hih);
4535 if(hil>=0) emit_loadreg(HIREG,hil);
4536 if(loh>=0) emit_loadreg(LOREG|64,loh);
4537 if(lol>=0) emit_loadreg(LOREG,lol);
4543 // Multiply by zero is zero.
4544 // MIPS does not have a divide by zero exception.
4545 // The result is undefined, we return zero.
4546 signed char hr=get_reg(i_regs->regmap,HIREG);
4547 signed char lr=get_reg(i_regs->regmap,LOREG);
4548 if(hr>=0) emit_zeroreg(hr);
4549 if(lr>=0) emit_zeroreg(lr);
4552 #define multdiv_assemble multdiv_assemble_arm
4554 void do_preload_rhash(int r) {
4555 // Don't need this for ARM. On x86, this puts the value 0xf8 into the
4556 // register. On ARM the hash can be done with a single instruction (below)
4559 void do_preload_rhtbl(int ht) {
4560 emit_addimm(FP,(int)&mini_ht-(int)&dynarec_local,ht);
4563 void do_rhash(int rs,int rh) {
4564 emit_andimm(rs,0xf8,rh);
4567 void do_miniht_load(int ht,int rh) {
4568 assem_debug("ldr %s,[%s,%s]!\n",regname[rh],regname[ht],regname[rh]);
4569 output_w32(0xe7b00000|rd_rn_rm(rh,ht,rh));
4572 void do_miniht_jump(int rs,int rh,int ht) {
4574 emit_ldreq_indexed(ht,4,15);
4575 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
4577 emit_jmp(jump_vaddr_reg[7]);
4579 emit_jmp(jump_vaddr_reg[rs]);
4583 void do_miniht_insert(u_int return_address,int rt,int temp) {
4585 emit_movimm(return_address,rt); // PC into link register
4586 add_to_linker((int)out,return_address,1);
4587 emit_pcreladdr(temp);
4588 emit_writeword(rt,(int)&mini_ht[(return_address&0xFF)>>3][0]);
4589 emit_writeword(temp,(int)&mini_ht[(return_address&0xFF)>>3][1]);
4591 emit_movw(return_address&0x0000FFFF,rt);
4592 add_to_linker((int)out,return_address,1);
4593 emit_pcreladdr(temp);
4594 emit_writeword(temp,(int)&mini_ht[(return_address&0xFF)>>3][1]);
4595 emit_movt(return_address&0xFFFF0000,rt);
4596 emit_writeword(rt,(int)&mini_ht[(return_address&0xFF)>>3][0]);
4600 // Sign-extend to 64 bits and write out upper half of a register
4601 // This is useful where we have a 32-bit value in a register, and want to
4602 // keep it in a 32-bit register, but can't guarantee that it won't be read
4603 // as a 64-bit value later.
4604 void wb_sx(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32_pre,uint64_t is32,uint64_t u,uint64_t uu)
4607 if(is32_pre==is32) return;
4609 for(hr=0;hr<HOST_REGS;hr++) {
4610 if(hr!=EXCLUDE_REG) {
4611 //if(pre[hr]==entry[hr]) {
4612 if((reg=pre[hr])>=0) {
4614 if( ((is32_pre&~is32&~uu)>>reg)&1 ) {
4615 emit_sarimm(hr,31,HOST_TEMPREG);
4616 emit_storereg(reg|64,HOST_TEMPREG);
4626 void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t is32_pre,uint64_t u,uint64_t uu)
4628 //if(dirty_pre==dirty) return;
4630 for(hr=0;hr<HOST_REGS;hr++) {
4631 if(hr!=EXCLUDE_REG) {
4633 if(((~u)>>(reg&63))&1) {
4634 if(reg==entry[hr]||(reg>0&&entry[hr]<0)) {
4635 if(((dirty_pre&~dirty)>>hr)&1) {
4637 emit_storereg(reg,hr);
4638 if( ((is32_pre&~uu)>>reg)&1 ) {
4639 emit_sarimm(hr,31,HOST_TEMPREG);
4640 emit_storereg(reg|64,HOST_TEMPREG);
4644 emit_storereg(reg,hr);
4648 else // Check if register moved to a different register
4649 if((new_hr=get_reg(entry,reg))>=0) {
4650 if((dirty_pre>>hr)&(~dirty>>new_hr)&1) {
4652 emit_storereg(reg,hr);
4653 if( ((is32_pre&~uu)>>reg)&1 ) {
4654 emit_sarimm(hr,31,HOST_TEMPREG);
4655 emit_storereg(reg|64,HOST_TEMPREG);
4659 emit_storereg(reg,hr);
4669 /* using strd could possibly help but you'd have to allocate registers in pairs
4670 void wb_invalidate_arm(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,uint64_t u,uint64_t uu)
4674 for(hr=HOST_REGS-1;hr>=0;hr--) {
4675 if(hr!=EXCLUDE_REG) {
4676 if(pre[hr]!=entry[hr]) {
4679 if(get_reg(entry,pre[hr])<0) {
4681 if(!((u>>pre[hr])&1)) {
4682 if(hr<10&&(~hr&1)&&(pre[hr+1]<0||wrote==hr+1)) {
4683 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4684 emit_sarimm(hr,31,hr+1);
4685 emit_strdreg(pre[hr],hr);
4688 emit_storereg(pre[hr],hr);
4690 emit_storereg(pre[hr],hr);
4691 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4692 emit_sarimm(hr,31,hr);
4693 emit_storereg(pre[hr]|64,hr);
4698 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
4699 emit_storereg(pre[hr],hr);
4709 for(hr=0;hr<HOST_REGS;hr++) {
4710 if(hr!=EXCLUDE_REG) {
4711 if(pre[hr]!=entry[hr]) {
4714 if((nr=get_reg(entry,pre[hr]))>=0) {
4722 #define wb_invalidate wb_invalidate_arm
4725 // CPU-architecture-specific initialization
4727 #ifndef DISABLE_COP1
4728 rounding_modes[0]=0x0<<22; // round
4729 rounding_modes[1]=0x3<<22; // trunc
4730 rounding_modes[2]=0x1<<22; // ceil
4731 rounding_modes[3]=0x2<<22; // floor
4735 // vim:shiftwidth=2:expandtab