1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * linkage_arm.s for PCSX *
3 * Copyright (C) 2009-2011 Ari64 *
4 * Copyright (C) 2010-2013 GraÅžvydas "notaz" Ignotas *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
20 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include "arm_features.h"
23 #include "new_dynarec_config.h"
24 #include "linkage_offsets.h"
28 #define dynarec_local ESYM(dynarec_local)
29 #define add_link ESYM(add_link)
30 #define new_recompile_block ESYM(new_recompile_block)
31 #define get_addr ESYM(get_addr)
32 #define get_addr_ht ESYM(get_addr_ht)
33 #define clean_blocks ESYM(clean_blocks)
34 #define gen_interupt ESYM(gen_interupt)
35 #define psxException ESYM(psxException)
36 #define execI ESYM(execI)
37 #define invalidate_addr ESYM(invalidate_addr)
43 .type dynarec_local, %object
44 .size dynarec_local, LO_dynarec_local_size
46 .space LO_dynarec_local_size
48 #define DRC_VAR_(name, vname, size_) \
49 vname = dynarec_local + LO_##name; \
51 .type vname, %object; \
54 #define DRC_VAR(name, size_) \
55 DRC_VAR_(name, ESYM(name), size_)
57 DRC_VAR(next_interupt, 4)
58 DRC_VAR(cycle_count, 4)
59 DRC_VAR(last_count, 4)
60 DRC_VAR(pending_exception, 4)
62 DRC_VAR(branch_target, 4)
64 @DRC_VAR(align0, 4) /* unused/alignment */
65 DRC_VAR(psxRegs, LO_psxRegs_end - LO_psxRegs)
71 DRC_VAR(reg_cop0, 128)
72 DRC_VAR(reg_cop2d, 128)
73 DRC_VAR(reg_cop2c, 128)
77 @DRC_VAR(interrupt, 4)
78 @DRC_VAR(intCycle, 256)
81 DRC_VAR(inv_code_start, 4)
82 DRC_VAR(inv_code_end, 4)
86 DRC_VAR(zeromem_ptr, 4)
88 DRC_VAR(scratch_buf_ptr, 4)
89 @DRC_VAR(align1, 8) /* unused/alignment */
91 DRC_VAR(restore_candidate, 512)
94 #ifdef TEXRELS_FORBIDDEN
100 .word ESYM(jump_dirty)
102 .word ESYM(hash_table)
117 .macro load_varadr reg var
118 #if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN)
119 movw \reg, #:lower16:(\var-(1678f+8))
120 movt \reg, #:upper16:(\var-(1678f+8))
123 #elif defined(HAVE_ARMV7) && !defined(__PIC__)
124 movw \reg, #:lower16:\var
125 movt \reg, #:upper16:\var
131 .macro load_varadr_ext reg var
132 #if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN)
133 movw \reg, #:lower16:(ptr_\var-(1678f+8))
134 movt \reg, #:upper16:(ptr_\var-(1678f+8))
138 load_varadr \reg \var
142 .macro mov_16 reg imm
146 mov \reg, #(\imm & 0x00ff)
147 orr \reg, #(\imm & 0xff00)
151 .macro mov_24 reg imm
153 movw \reg, #(\imm & 0xffff)
154 movt \reg, #(\imm >> 16)
156 mov \reg, #(\imm & 0x0000ff)
157 orr \reg, #(\imm & 0x00ff00)
158 orr \reg, #(\imm & 0xff0000)
162 /* r0 = virtual target address */
163 /* r1 = instruction to patch */
164 .macro dyna_linker_main
165 #ifndef NO_WRITE_EXEC
166 load_varadr_ext r3, jump_in
179 ldr r5, [r3, r2, lsl #2]
181 add r6, r1, r12, asr #6
187 ldr r3, [r5] /* ll_entry .vaddr */
188 ldrd r4, r5, [r4, #8] /* ll_entry .next, .addr */
192 moveq pc, r4 /* Stale i-cache */
194 b 1b /* jump_in may have dupes, continue search */
197 beq 3f /* r0 not in jump_in */
203 and r1, r7, #0xff000000
206 add r1, r1, r2, lsr #8
210 /* hash_table lookup */
212 load_varadr_ext r3, jump_dirty
213 eor r4, r0, r0, lsl #16
215 load_varadr_ext r6, hash_table
219 ldr r5, [r3, r2, lsl #2]
226 /* jump_dirty lookup */
236 /* hash_table insert */
246 /* XXX: should be able to do better than this... */
253 FUNCTION(dyna_linker):
254 /* r0 = virtual target address */
255 /* r1 = instruction to patch */
260 bl new_recompile_block
268 .size dyna_linker, .-dyna_linker
270 FUNCTION(exec_pagefault):
271 /* r0 = instruction pointer */
272 /* r1 = fault address */
274 ldr r3, [fp, #LO_reg_cop0+48] /* Status */
276 ldr r4, [fp, #LO_reg_cop0+16] /* Context */
277 bic r6, r6, #0x0F800000
278 str r0, [fp, #LO_reg_cop0+56] /* EPC */
280 str r1, [fp, #LO_reg_cop0+32] /* BadVAddr */
282 str r3, [fp, #LO_reg_cop0+48] /* Status */
283 and r5, r6, r1, lsr #9
284 str r2, [fp, #LO_reg_cop0+52] /* Cause */
285 and r1, r1, r6, lsl #9
286 str r1, [fp, #LO_reg_cop0+40] /* EntryHi */
288 str r4, [fp, #LO_reg_cop0+16] /* Context */
292 .size exec_pagefault, .-exec_pagefault
294 /* Special dynamic linker for the case where a page fault
295 may occur in a branch delay slot */
296 FUNCTION(dyna_linker_ds):
297 /* r0 = virtual target address */
298 /* r1 = instruction to patch */
305 bl new_recompile_block
312 mov r2, #0x80000008 /* High bit set indicates pagefault in delay slot */
315 .size dyna_linker_ds, .-dyna_linker_ds
319 FUNCTION(jump_vaddr_r0):
320 eor r2, r0, r0, lsl #16
322 .size jump_vaddr_r0, .-jump_vaddr_r0
323 FUNCTION(jump_vaddr_r1):
324 eor r2, r1, r1, lsl #16
327 .size jump_vaddr_r1, .-jump_vaddr_r1
328 FUNCTION(jump_vaddr_r2):
330 eor r2, r2, r2, lsl #16
332 .size jump_vaddr_r2, .-jump_vaddr_r2
333 FUNCTION(jump_vaddr_r3):
334 eor r2, r3, r3, lsl #16
337 .size jump_vaddr_r3, .-jump_vaddr_r3
338 FUNCTION(jump_vaddr_r4):
339 eor r2, r4, r4, lsl #16
342 .size jump_vaddr_r4, .-jump_vaddr_r4
343 FUNCTION(jump_vaddr_r5):
344 eor r2, r5, r5, lsl #16
347 .size jump_vaddr_r5, .-jump_vaddr_r5
348 FUNCTION(jump_vaddr_r6):
349 eor r2, r6, r6, lsl #16
352 .size jump_vaddr_r6, .-jump_vaddr_r6
353 FUNCTION(jump_vaddr_r8):
354 eor r2, r8, r8, lsl #16
357 .size jump_vaddr_r8, .-jump_vaddr_r8
358 FUNCTION(jump_vaddr_r9):
359 eor r2, r9, r9, lsl #16
362 .size jump_vaddr_r9, .-jump_vaddr_r9
363 FUNCTION(jump_vaddr_r10):
364 eor r2, r10, r10, lsl #16
367 .size jump_vaddr_r10, .-jump_vaddr_r10
368 FUNCTION(jump_vaddr_r12):
369 eor r2, r12, r12, lsl #16
372 .size jump_vaddr_r12, .-jump_vaddr_r12
373 FUNCTION(jump_vaddr_r7):
374 eor r2, r7, r7, lsl #16
376 .size jump_vaddr_r7, .-jump_vaddr_r7
377 FUNCTION(jump_vaddr):
378 load_varadr_ext r1, hash_table
380 and r2, r3, r2, lsr #12
387 str r10, [fp, #LO_cycle_count]
389 ldr r10, [fp, #LO_cycle_count]
391 .size jump_vaddr, .-jump_vaddr
395 FUNCTION(verify_code_ds):
396 str r8, [fp, #LO_branch_target]
397 FUNCTION(verify_code):
425 ldr r8, [fp, #LO_branch_target]
430 .size verify_code, .-verify_code
431 .size verify_code_ds, .-verify_code_ds
434 FUNCTION(cc_interrupt):
435 ldr r0, [fp, #LO_last_count]
439 str r1, [fp, #LO_pending_exception]
440 and r2, r2, r10, lsr #17
441 add r3, fp, #LO_restore_candidate
442 str r10, [fp, #LO_cycle] /* PCSX cycles */
443 @@ str r10, [fp, #LO_reg_cop0+36] /* Count */
451 ldr r10, [fp, #LO_cycle]
452 ldr r0, [fp, #LO_next_interupt]
453 ldr r1, [fp, #LO_pending_exception]
454 ldr r2, [fp, #LO_stop]
455 str r0, [fp, #LO_last_count]
458 ldmfdne sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
462 ldr r0, [fp, #LO_pcaddr]
466 /* Move 'dirty' blocks to the 'clean' list */
477 .size cc_interrupt, .-cc_interrupt
480 FUNCTION(fp_exception):
483 ldr r1, [fp, #LO_reg_cop0+48] /* Status */
485 str r0, [fp, #LO_reg_cop0+56] /* EPC */
488 str r1, [fp, #LO_reg_cop0+48] /* Status */
489 str r2, [fp, #LO_reg_cop0+52] /* Cause */
493 .size fp_exception, .-fp_exception
495 FUNCTION(fp_exception_ds):
496 mov r2, #0x90000000 /* Set high bit if delay slot */
498 .size fp_exception_ds, .-fp_exception_ds
501 FUNCTION(jump_syscall):
502 ldr r1, [fp, #LO_reg_cop0+48] /* Status */
504 str r0, [fp, #LO_reg_cop0+56] /* EPC */
507 str r1, [fp, #LO_reg_cop0+48] /* Status */
508 str r2, [fp, #LO_reg_cop0+52] /* Cause */
512 .size jump_syscall, .-jump_syscall
516 FUNCTION(jump_syscall_hle):
517 str r0, [fp, #LO_pcaddr] /* PC must be set to EPC for psxException */
518 ldr r2, [fp, #LO_last_count]
519 mov r1, #0 /* in delay slot */
521 mov r0, #0x20 /* cause */
522 str r2, [fp, #LO_cycle] /* PCSX cycle counter */
525 /* note: psxException might do recursive recompiler call from it's HLE code,
526 * so be ready for this */
528 ldr r1, [fp, #LO_next_interupt]
529 ldr r10, [fp, #LO_cycle]
530 ldr r0, [fp, #LO_pcaddr]
532 str r1, [fp, #LO_last_count]
535 .size jump_syscall_hle, .-jump_syscall_hle
538 FUNCTION(jump_hlecall):
539 ldr r2, [fp, #LO_last_count]
540 str r0, [fp, #LO_pcaddr]
543 str r2, [fp, #LO_cycle] /* PCSX cycle counter */
545 .size jump_hlecall, .-jump_hlecall
548 FUNCTION(jump_intcall):
549 ldr r2, [fp, #LO_last_count]
550 str r0, [fp, #LO_pcaddr]
553 str r2, [fp, #LO_cycle] /* PCSX cycle counter */
555 .size jump_hlecall, .-jump_hlecall
558 FUNCTION(new_dyna_leave):
559 ldr r0, [fp, #LO_last_count]
562 str r10, [fp, #LO_cycle]
563 ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
564 .size new_dyna_leave, .-new_dyna_leave
567 FUNCTION(invalidate_addr_r0):
568 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
569 b invalidate_addr_call
570 .size invalidate_addr_r0, .-invalidate_addr_r0
572 FUNCTION(invalidate_addr_r1):
573 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
575 b invalidate_addr_call
576 .size invalidate_addr_r1, .-invalidate_addr_r1
578 FUNCTION(invalidate_addr_r2):
579 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
581 b invalidate_addr_call
582 .size invalidate_addr_r2, .-invalidate_addr_r2
584 FUNCTION(invalidate_addr_r3):
585 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
587 b invalidate_addr_call
588 .size invalidate_addr_r3, .-invalidate_addr_r3
590 FUNCTION(invalidate_addr_r4):
591 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
593 b invalidate_addr_call
594 .size invalidate_addr_r4, .-invalidate_addr_r4
596 FUNCTION(invalidate_addr_r5):
597 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
599 b invalidate_addr_call
600 .size invalidate_addr_r5, .-invalidate_addr_r5
602 FUNCTION(invalidate_addr_r6):
603 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
605 b invalidate_addr_call
606 .size invalidate_addr_r6, .-invalidate_addr_r6
608 FUNCTION(invalidate_addr_r7):
609 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
611 b invalidate_addr_call
612 .size invalidate_addr_r7, .-invalidate_addr_r7
614 FUNCTION(invalidate_addr_r8):
615 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
617 b invalidate_addr_call
618 .size invalidate_addr_r8, .-invalidate_addr_r8
620 FUNCTION(invalidate_addr_r9):
621 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
623 b invalidate_addr_call
624 .size invalidate_addr_r9, .-invalidate_addr_r9
626 FUNCTION(invalidate_addr_r10):
627 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
629 b invalidate_addr_call
630 .size invalidate_addr_r10, .-invalidate_addr_r10
632 FUNCTION(invalidate_addr_r12):
633 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
635 .size invalidate_addr_r12, .-invalidate_addr_r12
637 invalidate_addr_call:
638 ldr r12, [fp, #LO_inv_code_start]
639 ldr lr, [fp, #LO_inv_code_end]
643 ldmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, pc}
644 .size invalidate_addr_call, .-invalidate_addr_call
647 FUNCTION(new_dyna_start):
648 /* ip is stored to conform EABI alignment */
649 stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
650 mov fp, r0 /* dynarec_local */
651 ldr r0, [fp, #LO_pcaddr]
653 ldr r1, [fp, #LO_next_interupt]
654 ldr r10, [fp, #LO_cycle]
655 str r1, [fp, #LO_last_count]
658 .size new_dyna_start, .-new_dyna_start
660 /* --------------------------------------- */
664 .macro pcsx_read_mem readop tab_shift
665 /* r0 = address, r1 = handler_tab, r2 = cycles */
667 lsr r3, #(20+\tab_shift)
668 ldr r12, [fp, #LO_last_count]
669 ldr r1, [r1, r3, lsl #2]
676 \readop r0, [r1, r3, lsl #\tab_shift]
679 str r2, [fp, #LO_cycle]
683 FUNCTION(jump_handler_read8):
684 add r1, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part
685 pcsx_read_mem ldrbcc, 0
687 FUNCTION(jump_handler_read16):
688 add r1, #0x1000/4*4 @ shift to r16 part
689 pcsx_read_mem ldrhcc, 1
691 FUNCTION(jump_handler_read32):
692 pcsx_read_mem ldrcc, 2
695 .macro pcsx_write_mem wrtop tab_shift
696 /* r0 = address, r1 = data, r2 = cycles, r3 = handler_tab */
698 lsr r12, #(20+\tab_shift)
699 ldr r3, [r3, r12, lsl #2]
700 str r0, [fp, #LO_address] @ some handlers still need it..
702 mov r0, r2 @ cycle return in case of direct store
707 \wrtop r1, [r3, r12, lsl #\tab_shift]
710 ldr r12, [fp, #LO_last_count]
714 str r2, [fp, #LO_cycle]
717 ldr r0, [fp, #LO_next_interupt]
719 str r0, [fp, #LO_last_count]
724 FUNCTION(jump_handler_write8):
725 add r3, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part
726 pcsx_write_mem strbcc, 0
728 FUNCTION(jump_handler_write16):
729 add r3, #0x1000/4*4 @ shift to r16 part
730 pcsx_write_mem strhcc, 1
732 FUNCTION(jump_handler_write32):
733 pcsx_write_mem strcc, 2
735 FUNCTION(jump_handler_write_h):
736 /* r0 = address, r1 = data, r2 = cycles, r3 = handler */
737 ldr r12, [fp, #LO_last_count]
738 str r0, [fp, #LO_address] @ some handlers still need it..
742 str r2, [fp, #LO_cycle]
745 ldr r0, [fp, #LO_next_interupt]
747 str r0, [fp, #LO_last_count]
751 FUNCTION(jump_handle_swl):
752 /* r0 = address, r1 = data, r2 = cycles */
753 ldr r3, [fp, #LO_mem_wtab]
755 ldr r3, [r3, r12, lsl #2]
776 lsreq r12, r1, #24 @ 0
786 FUNCTION(jump_handle_swr):
787 /* r0 = address, r1 = data, r2 = cycles */
788 ldr r3, [fp, #LO_mem_wtab]
790 ldr r3, [r3, r12, lsl #2]
812 .macro rcntx_read_mode0 num
813 /* r0 = address, r2 = cycles */
814 ldr r3, [fp, #LO_rcnts+6*4+7*4*\num] @ cycleStart
816 sub r0, r0, r3, lsl #16
821 FUNCTION(rcnt0_read_count_m0):
824 FUNCTION(rcnt1_read_count_m0):
827 FUNCTION(rcnt2_read_count_m0):
830 FUNCTION(rcnt0_read_count_m1):
831 /* r0 = address, r2 = cycles */
832 ldr r3, [fp, #LO_rcnts+6*4+7*4*0] @ cycleStart
835 mul r0, r1, r2 @ /= 5
839 FUNCTION(rcnt1_read_count_m1):
840 /* r0 = address, r2 = cycles */
841 ldr r3, [fp, #LO_rcnts+6*4+7*4*1]
844 umull r3, r0, r1, r2 @ ~ /= hsync_cycles, max ~0x1e6cdd
847 FUNCTION(rcnt2_read_count_m1):
848 /* r0 = address, r2 = cycles */
849 ldr r3, [fp, #LO_rcnts+6*4+7*4*2]
850 mov r0, r2, lsl #16-3
851 sub r0, r0, r3, lsl #16-3
855 @ vim:filetype=armasm