1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * linkage_arm.s for PCSX *
3 * Copyright (C) 2009-2011 Ari64 *
4 * Copyright (C) 2010-2013 GraÅžvydas "notaz" Ignotas *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
20 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include "arm_features.h"
23 #include "new_dynarec_config.h"
24 #include "linkage_offsets.h"
28 #define dynarec_local ESYM(dynarec_local)
29 #define add_jump_out ESYM(add_jump_out)
30 #define new_recompile_block ESYM(new_recompile_block)
31 #define get_addr ESYM(get_addr)
32 #define get_addr_ht ESYM(get_addr_ht)
33 #define clean_blocks ESYM(clean_blocks)
34 #define gen_interupt ESYM(gen_interupt)
35 #define invalidate_addr ESYM(invalidate_addr)
36 #define gteCheckStallRaw ESYM(gteCheckStallRaw)
42 .type dynarec_local, %object
43 .size dynarec_local, LO_dynarec_local_size
45 .space LO_dynarec_local_size
47 #define DRC_VAR_(name, vname, size_) \
48 vname = dynarec_local + LO_##name; \
50 .type vname, %object; \
53 #define DRC_VAR(name, size_) \
54 DRC_VAR_(name, ESYM(name), size_)
56 DRC_VAR(next_interupt, 4)
57 DRC_VAR(cycle_count, 4)
58 DRC_VAR(last_count, 4)
59 DRC_VAR(pending_exception, 4)
61 DRC_VAR(branch_target, 4)
63 @DRC_VAR(align0, 4) /* unused/alignment */
64 DRC_VAR(psxRegs, LO_psxRegs_end - LO_psxRegs)
70 DRC_VAR(reg_cop0, 128)
71 DRC_VAR(reg_cop2d, 128)
72 DRC_VAR(reg_cop2c, 128)
76 @DRC_VAR(interrupt, 4)
77 @DRC_VAR(intCycle, 256)
80 DRC_VAR(inv_code_start, 4)
81 DRC_VAR(inv_code_end, 4)
85 DRC_VAR(zeromem_ptr, 4)
87 DRC_VAR(scratch_buf_ptr, 4)
88 DRC_VAR(ram_offset, 4)
90 DRC_VAR(restore_candidate, 512)
93 #ifdef TEXRELS_FORBIDDEN
99 .word ESYM(jump_dirty)
101 .word ESYM(hash_table)
116 .macro load_varadr reg var
117 #if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN)
118 movw \reg, #:lower16:(\var-(1678f+8))
119 movt \reg, #:upper16:(\var-(1678f+8))
122 #elif defined(HAVE_ARMV7) && !defined(__PIC__)
123 movw \reg, #:lower16:\var
124 movt \reg, #:upper16:\var
130 .macro load_varadr_ext reg var
131 #if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN)
132 movw \reg, #:lower16:(ptr_\var-(1678f+8))
133 movt \reg, #:upper16:(ptr_\var-(1678f+8))
137 load_varadr \reg \var
141 .macro mov_16 reg imm
145 mov \reg, #(\imm & 0x00ff)
146 orr \reg, #(\imm & 0xff00)
150 .macro mov_24 reg imm
152 movw \reg, #(\imm & 0xffff)
153 movt \reg, #(\imm >> 16)
155 mov \reg, #(\imm & 0x0000ff)
156 orr \reg, #(\imm & 0x00ff00)
157 orr \reg, #(\imm & 0xff0000)
161 /* r0 = virtual target address */
162 /* r1 = instruction to patch */
163 .macro dyna_linker_main
164 #ifndef NO_WRITE_EXEC
165 load_varadr_ext r3, jump_in
178 ldr r5, [r3, r2, lsl #2]
180 add r6, r1, r12, asr #6 /* old target */
186 ldr r3, [r5] /* ll_entry .vaddr */
187 ldrd r4, r5, [r4, #8] /* ll_entry .next, .addr */
191 moveq pc, r4 /* Stale i-cache */
193 b 1b /* jump_in may have dupes, continue search */
196 beq 3f /* r0 not in jump_in */
202 and r1, r7, #0xff000000
205 add r1, r1, r2, lsr #8
209 /* hash_table lookup */
211 load_varadr_ext r3, jump_dirty
212 eor r4, r0, r0, lsl #16
214 load_varadr_ext r6, hash_table
218 ldr r5, [r3, r2, lsl #2]
225 /* jump_dirty lookup */
235 /* hash_table insert */
245 /* XXX: should be able to do better than this... */
252 FUNCTION(dyna_linker):
253 /* r0 = virtual target address */
254 /* r1 = instruction to patch */
259 bl new_recompile_block
267 .size dyna_linker, .-dyna_linker
269 FUNCTION(exec_pagefault):
270 /* r0 = instruction pointer */
271 /* r1 = fault address */
273 ldr r3, [fp, #LO_reg_cop0+48] /* Status */
275 ldr r4, [fp, #LO_reg_cop0+16] /* Context */
276 bic r6, r6, #0x0F800000
277 str r0, [fp, #LO_reg_cop0+56] /* EPC */
279 str r1, [fp, #LO_reg_cop0+32] /* BadVAddr */
281 str r3, [fp, #LO_reg_cop0+48] /* Status */
282 and r5, r6, r1, lsr #9
283 str r2, [fp, #LO_reg_cop0+52] /* Cause */
284 and r1, r1, r6, lsl #9
285 str r1, [fp, #LO_reg_cop0+40] /* EntryHi */
287 str r4, [fp, #LO_reg_cop0+16] /* Context */
291 .size exec_pagefault, .-exec_pagefault
293 /* Special dynamic linker for the case where a page fault
294 may occur in a branch delay slot */
295 FUNCTION(dyna_linker_ds):
296 /* r0 = virtual target address */
297 /* r1 = instruction to patch */
304 bl new_recompile_block
311 mov r2, #0x80000008 /* High bit set indicates pagefault in delay slot */
314 .size dyna_linker_ds, .-dyna_linker_ds
318 FUNCTION(jump_vaddr_r0):
319 eor r2, r0, r0, lsl #16
321 .size jump_vaddr_r0, .-jump_vaddr_r0
322 FUNCTION(jump_vaddr_r1):
323 eor r2, r1, r1, lsl #16
326 .size jump_vaddr_r1, .-jump_vaddr_r1
327 FUNCTION(jump_vaddr_r2):
329 eor r2, r2, r2, lsl #16
331 .size jump_vaddr_r2, .-jump_vaddr_r2
332 FUNCTION(jump_vaddr_r3):
333 eor r2, r3, r3, lsl #16
336 .size jump_vaddr_r3, .-jump_vaddr_r3
337 FUNCTION(jump_vaddr_r4):
338 eor r2, r4, r4, lsl #16
341 .size jump_vaddr_r4, .-jump_vaddr_r4
342 FUNCTION(jump_vaddr_r5):
343 eor r2, r5, r5, lsl #16
346 .size jump_vaddr_r5, .-jump_vaddr_r5
347 FUNCTION(jump_vaddr_r6):
348 eor r2, r6, r6, lsl #16
351 .size jump_vaddr_r6, .-jump_vaddr_r6
352 FUNCTION(jump_vaddr_r8):
353 eor r2, r8, r8, lsl #16
356 .size jump_vaddr_r8, .-jump_vaddr_r8
357 FUNCTION(jump_vaddr_r9):
358 eor r2, r9, r9, lsl #16
361 .size jump_vaddr_r9, .-jump_vaddr_r9
362 FUNCTION(jump_vaddr_r10):
363 eor r2, r10, r10, lsl #16
366 .size jump_vaddr_r10, .-jump_vaddr_r10
367 FUNCTION(jump_vaddr_r12):
368 eor r2, r12, r12, lsl #16
371 .size jump_vaddr_r12, .-jump_vaddr_r12
372 FUNCTION(jump_vaddr_r7):
373 eor r2, r7, r7, lsl #16
375 .size jump_vaddr_r7, .-jump_vaddr_r7
376 FUNCTION(jump_vaddr):
377 load_varadr_ext r1, hash_table
379 and r2, r3, r2, lsr #12
386 str r10, [fp, #LO_cycle_count]
388 ldr r10, [fp, #LO_cycle_count]
390 .size jump_vaddr, .-jump_vaddr
394 FUNCTION(verify_code_ds):
395 str r8, [fp, #LO_branch_target] @ preserve HOST_BTREG?
396 FUNCTION(verify_code):
424 ldr r8, [fp, #LO_branch_target]
429 .size verify_code, .-verify_code
430 .size verify_code_ds, .-verify_code_ds
433 FUNCTION(cc_interrupt):
434 ldr r0, [fp, #LO_last_count]
438 str r1, [fp, #LO_pending_exception]
439 and r2, r2, r10, lsr #17
440 add r3, fp, #LO_restore_candidate
441 str r10, [fp, #LO_cycle] /* PCSX cycles */
442 @@ str r10, [fp, #LO_reg_cop0+36] /* Count */
450 ldr r10, [fp, #LO_cycle]
451 ldr r0, [fp, #LO_next_interupt]
452 ldr r1, [fp, #LO_pending_exception]
453 ldr r2, [fp, #LO_stop]
454 str r0, [fp, #LO_last_count]
457 ldmfdne sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
461 ldr r0, [fp, #LO_pcaddr]
465 /* Move 'dirty' blocks to the 'clean' list */
476 .size cc_interrupt, .-cc_interrupt
479 FUNCTION(fp_exception):
482 ldr r1, [fp, #LO_reg_cop0+48] /* Status */
484 str r0, [fp, #LO_reg_cop0+56] /* EPC */
487 str r1, [fp, #LO_reg_cop0+48] /* Status */
488 str r2, [fp, #LO_reg_cop0+52] /* Cause */
492 .size fp_exception, .-fp_exception
494 FUNCTION(fp_exception_ds):
495 mov r2, #0x90000000 /* Set high bit if delay slot */
497 .size fp_exception_ds, .-fp_exception_ds
500 FUNCTION(jump_syscall):
501 ldr r1, [fp, #LO_reg_cop0+48] /* Status */
503 str r0, [fp, #LO_reg_cop0+56] /* EPC */
506 str r1, [fp, #LO_reg_cop0+48] /* Status */
507 str r2, [fp, #LO_reg_cop0+52] /* Cause */
511 .size jump_syscall, .-jump_syscall
514 /* note: psxException might do recursive recompiler call from it's HLE code,
515 * so be ready for this */
516 FUNCTION(jump_to_new_pc):
517 ldr r1, [fp, #LO_next_interupt]
518 ldr r10, [fp, #LO_cycle]
519 ldr r0, [fp, #LO_pcaddr]
521 str r1, [fp, #LO_last_count]
524 .size jump_to_new_pc, .-jump_to_new_pc
527 FUNCTION(new_dyna_leave):
528 ldr r0, [fp, #LO_last_count]
531 str r10, [fp, #LO_cycle]
532 ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
533 .size new_dyna_leave, .-new_dyna_leave
536 FUNCTION(invalidate_addr_r0):
537 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
538 b invalidate_addr_call
539 .size invalidate_addr_r0, .-invalidate_addr_r0
541 FUNCTION(invalidate_addr_r1):
542 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
544 b invalidate_addr_call
545 .size invalidate_addr_r1, .-invalidate_addr_r1
547 FUNCTION(invalidate_addr_r2):
548 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
550 b invalidate_addr_call
551 .size invalidate_addr_r2, .-invalidate_addr_r2
553 FUNCTION(invalidate_addr_r3):
554 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
556 b invalidate_addr_call
557 .size invalidate_addr_r3, .-invalidate_addr_r3
559 FUNCTION(invalidate_addr_r4):
560 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
562 b invalidate_addr_call
563 .size invalidate_addr_r4, .-invalidate_addr_r4
565 FUNCTION(invalidate_addr_r5):
566 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
568 b invalidate_addr_call
569 .size invalidate_addr_r5, .-invalidate_addr_r5
571 FUNCTION(invalidate_addr_r6):
572 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
574 b invalidate_addr_call
575 .size invalidate_addr_r6, .-invalidate_addr_r6
577 FUNCTION(invalidate_addr_r7):
578 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
580 b invalidate_addr_call
581 .size invalidate_addr_r7, .-invalidate_addr_r7
583 FUNCTION(invalidate_addr_r8):
584 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
586 b invalidate_addr_call
587 .size invalidate_addr_r8, .-invalidate_addr_r8
589 FUNCTION(invalidate_addr_r9):
590 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
592 b invalidate_addr_call
593 .size invalidate_addr_r9, .-invalidate_addr_r9
595 FUNCTION(invalidate_addr_r10):
596 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
598 b invalidate_addr_call
599 .size invalidate_addr_r10, .-invalidate_addr_r10
601 FUNCTION(invalidate_addr_r12):
602 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
604 .size invalidate_addr_r12, .-invalidate_addr_r12
606 invalidate_addr_call:
607 ldr r12, [fp, #LO_inv_code_start]
608 ldr lr, [fp, #LO_inv_code_end]
612 ldmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, pc}
613 .size invalidate_addr_call, .-invalidate_addr_call
616 FUNCTION(new_dyna_start):
617 /* ip is stored to conform EABI alignment */
618 stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
619 mov fp, r0 /* dynarec_local */
620 ldr r0, [fp, #LO_pcaddr]
622 ldr r1, [fp, #LO_next_interupt]
623 ldr r10, [fp, #LO_cycle]
624 str r1, [fp, #LO_last_count]
627 .size new_dyna_start, .-new_dyna_start
629 /* --------------------------------------- */
633 .macro pcsx_read_mem readop tab_shift
634 /* r0 = address, r1 = handler_tab, r2 = cycles */
636 lsr r3, #(20+\tab_shift)
637 ldr r12, [fp, #LO_last_count]
638 ldr r1, [r1, r3, lsl #2]
645 \readop r0, [r1, r3, lsl #\tab_shift]
648 str r2, [fp, #LO_cycle]
652 FUNCTION(jump_handler_read8):
653 add r1, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part
654 pcsx_read_mem ldrbcc, 0
656 FUNCTION(jump_handler_read16):
657 add r1, #0x1000/4*4 @ shift to r16 part
658 pcsx_read_mem ldrhcc, 1
660 FUNCTION(jump_handler_read32):
661 pcsx_read_mem ldrcc, 2
664 .macro memhandler_post
665 ldr r0, [fp, #LO_next_interupt]
666 ldr r2, [fp, #LO_cycle] @ memhandlers can modify cc, like dma
667 str r0, [fp, #LO_last_count]
671 .macro pcsx_write_mem wrtop tab_shift
672 /* r0 = address, r1 = data, r2 = cycles, r3 = handler_tab */
674 lsr r12, #(20+\tab_shift)
675 ldr r3, [r3, r12, lsl #2]
676 str r0, [fp, #LO_address] @ some handlers still need it..
678 mov r0, r2 @ cycle return in case of direct store
683 \wrtop r1, [r3, r12, lsl #\tab_shift]
686 ldr r12, [fp, #LO_last_count]
689 str r2, [fp, #LO_cycle]
691 str lr, [fp, #LO_saved_lr]
693 ldr lr, [fp, #LO_saved_lr]
699 FUNCTION(jump_handler_write8):
700 add r3, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part
701 pcsx_write_mem strbcc, 0
703 FUNCTION(jump_handler_write16):
704 add r3, #0x1000/4*4 @ shift to r16 part
705 pcsx_write_mem strhcc, 1
707 FUNCTION(jump_handler_write32):
708 pcsx_write_mem strcc, 2
710 FUNCTION(jump_handler_write_h):
711 /* r0 = address, r1 = data, r2 = cycles, r3 = handler */
712 ldr r12, [fp, #LO_last_count]
713 str r0, [fp, #LO_address] @ some handlers still need it..
716 str r2, [fp, #LO_cycle]
718 str lr, [fp, #LO_saved_lr]
720 ldr lr, [fp, #LO_saved_lr]
725 FUNCTION(jump_handle_swl):
726 /* r0 = address, r1 = data, r2 = cycles */
727 ldr r3, [fp, #LO_mem_wtab]
729 ldr r3, [r3, r12, lsl #2]
750 lsreq r12, r1, #24 @ 0
760 FUNCTION(jump_handle_swr):
761 /* r0 = address, r1 = data, r2 = cycles */
762 ldr r3, [fp, #LO_mem_wtab]
764 ldr r3, [r3, r12, lsl #2]
786 .macro rcntx_read_mode0 num
787 /* r0 = address, r2 = cycles */
788 ldr r3, [fp, #LO_rcnts+6*4+7*4*\num] @ cycleStart
790 sub r0, r0, r3, lsl #16
795 FUNCTION(rcnt0_read_count_m0):
798 FUNCTION(rcnt1_read_count_m0):
801 FUNCTION(rcnt2_read_count_m0):
804 FUNCTION(rcnt0_read_count_m1):
805 /* r0 = address, r2 = cycles */
806 ldr r3, [fp, #LO_rcnts+6*4+7*4*0] @ cycleStart
809 mul r0, r1, r2 @ /= 5
813 FUNCTION(rcnt1_read_count_m1):
814 /* r0 = address, r2 = cycles */
815 ldr r3, [fp, #LO_rcnts+6*4+7*4*1]
818 umull r3, r0, r1, r2 @ ~ /= hsync_cycles, max ~0x1e6cdd
821 FUNCTION(rcnt2_read_count_m1):
822 /* r0 = address, r2 = cycles */
823 ldr r3, [fp, #LO_rcnts+6*4+7*4*2]
824 mov r0, r2, lsl #16-3
825 sub r0, r0, r3, lsl #16-3
829 FUNCTION(call_gteStall):
830 /* r0 = op_cycles, r1 = cycles */
831 ldr r2, [fp, #LO_last_count]
832 str lr, [fp, #LO_saved_lr]
834 str r1, [fp, #LO_cycle]
835 add r1, fp, #LO_psxRegs
837 ldr lr, [fp, #LO_saved_lr]
841 @ vim:filetype=armasm