1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2011 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
26 #include "emu_if.h" //emulator interface
29 //#define assem_debug printf
30 //#define inv_debug printf
31 #define assem_debug(...)
32 #define inv_debug(...)
35 #include "assem_x86.h"
38 #include "assem_x64.h"
41 #include "assem_arm.h"
45 #define MAX_OUTPUT_BLOCK_SIZE 262144
49 signed char regmap_entry[HOST_REGS];
50 signed char regmap[HOST_REGS];
59 u_int loadedconst; // host regs that have constants loaded
60 u_int waswritten; // MIPS regs that were used as store base before
68 struct ll_entry *next;
74 char insn[MAXBLOCK][10];
75 u_char itype[MAXBLOCK];
76 u_char opcode[MAXBLOCK];
77 u_char opcode2[MAXBLOCK];
85 u_char dep1[MAXBLOCK];
86 u_char dep2[MAXBLOCK];
88 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
89 static uint64_t gte_rt[MAXBLOCK];
90 static uint64_t gte_unneeded[MAXBLOCK];
91 static u_int smrv[32]; // speculated MIPS register values
92 static u_int smrv_strong; // mask or regs that are likely to have correct values
93 static u_int smrv_weak; // same, but somewhat less likely
94 static u_int smrv_strong_next; // same, but after current insn executes
95 static u_int smrv_weak_next;
98 char likely[MAXBLOCK];
101 uint64_t unneeded_reg[MAXBLOCK];
102 uint64_t unneeded_reg_upper[MAXBLOCK];
103 uint64_t branch_unneeded_reg[MAXBLOCK];
104 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
105 uint64_t p32[MAXBLOCK];
106 uint64_t pr32[MAXBLOCK];
107 signed char regmap_pre[MAXBLOCK][HOST_REGS];
108 static uint64_t current_constmap[HOST_REGS];
109 static uint64_t constmap[MAXBLOCK][HOST_REGS];
110 static struct regstat regs[MAXBLOCK];
111 static struct regstat branch_regs[MAXBLOCK];
112 signed char minimum_free_regs[MAXBLOCK];
113 u_int needed_reg[MAXBLOCK];
114 uint64_t requires_32bit[MAXBLOCK];
115 u_int wont_dirty[MAXBLOCK];
116 u_int will_dirty[MAXBLOCK];
119 u_int instr_addr[MAXBLOCK];
120 u_int link_addr[MAXBLOCK][3];
122 u_int stubs[MAXBLOCK*3][8];
124 u_int literals[1024][2];
129 struct ll_entry *jump_in[4096];
130 struct ll_entry *jump_out[4096];
131 struct ll_entry *jump_dirty[4096];
132 u_int hash_table[65536][4] __attribute__((aligned(16)));
133 char shadow[1048576] __attribute__((aligned(16)));
139 static const u_int using_tlb=0;
141 int new_dynarec_did_compile;
142 int new_dynarec_hacks;
143 u_int stop_after_jal;
145 static u_int ram_offset;
147 static const u_int ram_offset=0;
149 extern u_char restore_candidate[512];
150 extern int cycle_count;
152 /* registers that may be allocated */
154 #define HIREG 32 // hi
155 #define LOREG 33 // lo
156 #define FSREG 34 // FPU status (FCSR)
157 #define CSREG 35 // Coprocessor status
158 #define CCREG 36 // Cycle count
159 #define INVCP 37 // Pointer to invalid_code
160 #define MMREG 38 // Pointer to memory_map
161 #define ROREG 39 // ram offset (if rdram!=0x80000000)
163 #define FTEMP 40 // FPU temporary register
164 #define PTEMP 41 // Prefetch temporary register
165 #define TLREG 42 // TLB mapping offset
166 #define RHASH 43 // Return address hash
167 #define RHTBL 44 // Return address hash table address
168 #define RTEMP 45 // JR/JALR address register
170 #define AGEN1 46 // Address generation temporary register
171 #define AGEN2 47 // Address generation temporary register
172 #define MGEN1 48 // Maptable address generation temporary register
173 #define MGEN2 49 // Maptable address generation temporary register
174 #define BTREG 50 // Branch target temporary register
176 /* instruction types */
177 #define NOP 0 // No operation
178 #define LOAD 1 // Load
179 #define STORE 2 // Store
180 #define LOADLR 3 // Unaligned load
181 #define STORELR 4 // Unaligned store
182 #define MOV 5 // Move
183 #define ALU 6 // Arithmetic/logic
184 #define MULTDIV 7 // Multiply/divide
185 #define SHIFT 8 // Shift by register
186 #define SHIFTIMM 9// Shift by immediate
187 #define IMM16 10 // 16-bit immediate
188 #define RJUMP 11 // Unconditional jump to register
189 #define UJUMP 12 // Unconditional jump
190 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
191 #define SJUMP 14 // Conditional branch (regimm format)
192 #define COP0 15 // Coprocessor 0
193 #define COP1 16 // Coprocessor 1
194 #define C1LS 17 // Coprocessor 1 load/store
195 #define FJUMP 18 // Conditional branch (floating point)
196 #define FLOAT 19 // Floating point unit
197 #define FCONV 20 // Convert integer to float
198 #define FCOMP 21 // Floating point compare (sets FSREG)
199 #define SYSCALL 22// SYSCALL
200 #define OTHER 23 // Other
201 #define SPAN 24 // Branch/delay slot spans 2 pages
202 #define NI 25 // Not implemented
203 #define HLECALL 26// PCSX fake opcodes for HLE
204 #define COP2 27 // Coprocessor 2 move
205 #define C2LS 28 // Coprocessor 2 load/store
206 #define C2OP 29 // Coprocessor 2 operation
207 #define INTCALL 30// Call interpreter to handle rare corner cases
216 #define LOADBU_STUB 7
217 #define LOADHU_STUB 8
218 #define STOREB_STUB 9
219 #define STOREH_STUB 10
220 #define STOREW_STUB 11
221 #define STORED_STUB 12
222 #define STORELR_STUB 13
223 #define INVCODE_STUB 14
231 int new_recompile_block(int addr);
232 void *get_addr_ht(u_int vaddr);
233 void invalidate_block(u_int block);
234 void invalidate_addr(u_int addr);
235 void remove_hash(int vaddr);
238 void dyna_linker_ds();
240 void verify_code_vm();
241 void verify_code_ds();
244 void fp_exception_ds();
246 void jump_syscall_hle();
250 void new_dyna_leave();
255 void read_nomem_new();
256 void read_nomemb_new();
257 void read_nomemh_new();
258 void read_nomemd_new();
259 void write_nomem_new();
260 void write_nomemb_new();
261 void write_nomemh_new();
262 void write_nomemd_new();
263 void write_rdram_new();
264 void write_rdramb_new();
265 void write_rdramh_new();
266 void write_rdramd_new();
267 extern u_int memory_map[1048576];
269 // Needed by assembler
270 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
271 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
272 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
273 void load_all_regs(signed char i_regmap[]);
274 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
275 void load_regs_entry(int t);
276 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
280 //#define DEBUG_CYCLE_COUNT 1
282 int cycle_multiplier; // 100 for 1.0
284 static int CLOCK_ADJUST(int x)
287 return (x * cycle_multiplier + s * 50) / 100;
290 static void tlb_hacks()
294 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
298 switch (ROM_HEADER->Country_code&0xFF)
310 // Unknown country code
314 u_int rom_addr=(u_int)rom;
316 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
317 // in the lower 4G of memory to use this hack. Copy it if necessary.
318 if((void *)rom>(void *)0xffffffff) {
319 munmap(ROM_COPY, 67108864);
320 if(mmap(ROM_COPY, 12582912,
321 PROT_READ | PROT_WRITE,
322 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
323 -1, 0) <= 0) {printf("mmap() failed\n");}
324 memcpy(ROM_COPY,rom,12582912);
325 rom_addr=(u_int)ROM_COPY;
329 for(n=0x7F000;n<0x80000;n++) {
330 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
337 static u_int get_page(u_int vaddr)
340 u_int page=(vaddr^0x80000000)>>12;
342 u_int page=vaddr&~0xe0000000;
343 if (page < 0x1000000)
344 page &= ~0x0e00000; // RAM mirrors
348 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
350 if(page>2048) page=2048+(page&2047);
355 static u_int get_vpage(u_int vaddr)
357 u_int vpage=(vaddr^0x80000000)>>12;
359 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
361 if(vpage>2048) vpage=2048+(vpage&2047);
365 // no virtual mem in PCSX
366 static u_int get_vpage(u_int vaddr)
368 return get_page(vaddr);
372 // Get address from virtual address
373 // This is called from the recompiled JR/JALR instructions
374 void *get_addr(u_int vaddr)
376 u_int page=get_page(vaddr);
377 u_int vpage=get_vpage(vaddr);
378 struct ll_entry *head;
379 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
382 if(head->vaddr==vaddr&&head->reg32==0) {
383 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
384 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
387 ht_bin[1]=(int)head->addr;
393 head=jump_dirty[vpage];
395 if(head->vaddr==vaddr&&head->reg32==0) {
396 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
397 // Don't restore blocks which are about to expire from the cache
398 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
399 if(verify_dirty(head->addr)) {
400 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
401 invalid_code[vaddr>>12]=0;
402 inv_code_start=inv_code_end=~0;
404 memory_map[vaddr>>12]|=0x40000000;
408 if(tlb_LUT_r[vaddr>>12]) {
409 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
410 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
413 restore_candidate[vpage>>3]|=1<<(vpage&7);
415 else restore_candidate[page>>3]|=1<<(page&7);
416 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
417 if(ht_bin[0]==vaddr) {
418 ht_bin[1]=(int)head->addr; // Replace existing entry
424 ht_bin[1]=(int)head->addr;
432 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
433 int r=new_recompile_block(vaddr);
434 if(r==0) return get_addr(vaddr);
435 // Execute in unmapped page, generate pagefault execption
437 Cause=(vaddr<<31)|0x8;
438 EPC=(vaddr&1)?vaddr-5:vaddr;
440 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
441 EntryHi=BadVAddr&0xFFFFE000;
442 return get_addr_ht(0x80000000);
444 // Look up address in hash table first
445 void *get_addr_ht(u_int vaddr)
447 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
448 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
449 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
450 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
451 return get_addr(vaddr);
454 void *get_addr_32(u_int vaddr,u_int flags)
457 return get_addr(vaddr);
459 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
460 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
461 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
462 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
463 u_int page=get_page(vaddr);
464 u_int vpage=get_vpage(vaddr);
465 struct ll_entry *head;
468 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
469 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
471 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
473 ht_bin[1]=(int)head->addr;
475 }else if(ht_bin[2]==-1) {
476 ht_bin[3]=(int)head->addr;
479 //ht_bin[3]=ht_bin[1];
480 //ht_bin[2]=ht_bin[0];
481 //ht_bin[1]=(int)head->addr;
488 head=jump_dirty[vpage];
490 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
491 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
492 // Don't restore blocks which are about to expire from the cache
493 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
494 if(verify_dirty(head->addr)) {
495 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
496 invalid_code[vaddr>>12]=0;
497 inv_code_start=inv_code_end=~0;
498 memory_map[vaddr>>12]|=0x40000000;
501 if(tlb_LUT_r[vaddr>>12]) {
502 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
503 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
506 restore_candidate[vpage>>3]|=1<<(vpage&7);
508 else restore_candidate[page>>3]|=1<<(page&7);
510 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
512 ht_bin[1]=(int)head->addr;
514 }else if(ht_bin[2]==-1) {
515 ht_bin[3]=(int)head->addr;
518 //ht_bin[3]=ht_bin[1];
519 //ht_bin[2]=ht_bin[0];
520 //ht_bin[1]=(int)head->addr;
528 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
529 int r=new_recompile_block(vaddr);
530 if(r==0) return get_addr(vaddr);
531 // Execute in unmapped page, generate pagefault execption
533 Cause=(vaddr<<31)|0x8;
534 EPC=(vaddr&1)?vaddr-5:vaddr;
536 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
537 EntryHi=BadVAddr&0xFFFFE000;
538 return get_addr_ht(0x80000000);
542 void clear_all_regs(signed char regmap[])
545 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
548 signed char get_reg(signed char regmap[],int r)
551 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr;
555 // Find a register that is available for two consecutive cycles
556 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
559 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
563 int count_free_regs(signed char regmap[])
567 for(hr=0;hr<HOST_REGS;hr++)
569 if(hr!=EXCLUDE_REG) {
570 if(regmap[hr]<0) count++;
576 void dirty_reg(struct regstat *cur,signed char reg)
580 for (hr=0;hr<HOST_REGS;hr++) {
581 if((cur->regmap[hr]&63)==reg) {
587 // If we dirty the lower half of a 64 bit register which is now being
588 // sign-extended, we need to dump the upper half.
589 // Note: Do this only after completion of the instruction, because
590 // some instructions may need to read the full 64-bit value even if
591 // overwriting it (eg SLTI, DSRA32).
592 static void flush_dirty_uppers(struct regstat *cur)
595 for (hr=0;hr<HOST_REGS;hr++) {
596 if((cur->dirty>>hr)&1) {
599 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
604 void set_const(struct regstat *cur,signed char reg,uint64_t value)
608 for (hr=0;hr<HOST_REGS;hr++) {
609 if(cur->regmap[hr]==reg) {
611 current_constmap[hr]=value;
613 else if((cur->regmap[hr]^64)==reg) {
615 current_constmap[hr]=value>>32;
620 void clear_const(struct regstat *cur,signed char reg)
624 for (hr=0;hr<HOST_REGS;hr++) {
625 if((cur->regmap[hr]&63)==reg) {
626 cur->isconst&=~(1<<hr);
631 int is_const(struct regstat *cur,signed char reg)
636 for (hr=0;hr<HOST_REGS;hr++) {
637 if((cur->regmap[hr]&63)==reg) {
638 return (cur->isconst>>hr)&1;
643 uint64_t get_const(struct regstat *cur,signed char reg)
647 for (hr=0;hr<HOST_REGS;hr++) {
648 if(cur->regmap[hr]==reg) {
649 return current_constmap[hr];
652 printf("Unknown constant in r%d\n",reg);
656 // Least soon needed registers
657 // Look at the next ten instructions and see which registers
658 // will be used. Try not to reallocate these.
659 void lsn(u_char hsn[], int i, int *preferred_reg)
669 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
671 // Don't go past an unconditonal jump
678 if(rs1[i+j]) hsn[rs1[i+j]]=j;
679 if(rs2[i+j]) hsn[rs2[i+j]]=j;
680 if(rt1[i+j]) hsn[rt1[i+j]]=j;
681 if(rt2[i+j]) hsn[rt2[i+j]]=j;
682 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
683 // Stores can allocate zero
687 // On some architectures stores need invc_ptr
688 #if defined(HOST_IMM8)
689 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
693 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
701 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
703 // Follow first branch
704 int t=(ba[i+b]-start)>>2;
705 j=7-b;if(t+j>=slen) j=slen-t-1;
708 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
709 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
710 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
711 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
714 // TODO: preferred register based on backward branch
716 // Delay slot should preferably not overwrite branch conditions or cycle count
717 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
718 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
719 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
725 // Coprocessor load/store needs FTEMP, even if not declared
726 if(itype[i]==C1LS||itype[i]==C2LS) {
729 // Load L/R also uses FTEMP as a temporary register
730 if(itype[i]==LOADLR) {
733 // Also SWL/SWR/SDL/SDR
734 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
737 // Don't remove the TLB registers either
738 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
741 // Don't remove the miniht registers
742 if(itype[i]==UJUMP||itype[i]==RJUMP)
749 // We only want to allocate registers if we're going to use them again soon
750 int needed_again(int r, int i)
756 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
758 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
759 return 0; // Don't need any registers if exiting the block
767 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
769 // Don't go past an unconditonal jump
773 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
780 if(rs1[i+j]==r) rn=j;
781 if(rs2[i+j]==r) rn=j;
782 if((unneeded_reg[i+j]>>r)&1) rn=10;
783 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
791 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
793 // Follow first branch
795 int t=(ba[i+b]-start)>>2;
796 j=7-b;if(t+j>=slen) j=slen-t-1;
799 if(!((unneeded_reg[t+j]>>r)&1)) {
800 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
801 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
811 // Try to match register allocations at the end of a loop with those
813 int loop_reg(int i, int r, int hr)
822 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
824 // Don't go past an unconditonal jump
831 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
836 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
837 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
838 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
840 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
842 int t=(ba[i+k]-start)>>2;
843 int reg=get_reg(regs[t].regmap_entry,r);
844 if(reg>=0) return reg;
845 //reg=get_reg(regs[t+1].regmap_entry,r);
846 //if(reg>=0) return reg;
854 // Allocate every register, preserving source/target regs
855 void alloc_all(struct regstat *cur,int i)
859 for(hr=0;hr<HOST_REGS;hr++) {
860 if(hr!=EXCLUDE_REG) {
861 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
862 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
865 cur->dirty&=~(1<<hr);
868 if((cur->regmap[hr]&63)==0)
871 cur->dirty&=~(1<<hr);
878 void div64(int64_t dividend,int64_t divisor)
882 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
883 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
885 void divu64(uint64_t dividend,uint64_t divisor)
889 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
890 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
893 void mult64(uint64_t m1,uint64_t m2)
895 unsigned long long int op1, op2, op3, op4;
896 unsigned long long int result1, result2, result3, result4;
897 unsigned long long int temp1, temp2, temp3, temp4;
913 op1 = op2 & 0xFFFFFFFF;
914 op2 = (op2 >> 32) & 0xFFFFFFFF;
915 op3 = op4 & 0xFFFFFFFF;
916 op4 = (op4 >> 32) & 0xFFFFFFFF;
919 temp2 = (temp1 >> 32) + op1 * op4;
921 temp4 = (temp3 >> 32) + op2 * op4;
923 result1 = temp1 & 0xFFFFFFFF;
924 result2 = temp2 + (temp3 & 0xFFFFFFFF);
925 result3 = (result2 >> 32) + temp4;
926 result4 = (result3 >> 32);
928 lo = result1 | (result2 << 32);
929 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
938 void multu64(uint64_t m1,uint64_t m2)
940 unsigned long long int op1, op2, op3, op4;
941 unsigned long long int result1, result2, result3, result4;
942 unsigned long long int temp1, temp2, temp3, temp4;
944 op1 = m1 & 0xFFFFFFFF;
945 op2 = (m1 >> 32) & 0xFFFFFFFF;
946 op3 = m2 & 0xFFFFFFFF;
947 op4 = (m2 >> 32) & 0xFFFFFFFF;
950 temp2 = (temp1 >> 32) + op1 * op4;
952 temp4 = (temp3 >> 32) + op2 * op4;
954 result1 = temp1 & 0xFFFFFFFF;
955 result2 = temp2 + (temp3 & 0xFFFFFFFF);
956 result3 = (result2 >> 32) + temp4;
957 result4 = (result3 >> 32);
959 lo = result1 | (result2 << 32);
960 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
962 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
963 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
966 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
974 else original=loaded;
977 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
980 original>>=64-(bits^56);
981 original<<=64-(bits^56);
985 else original=loaded;
991 #include "assem_x86.c"
994 #include "assem_x64.c"
997 #include "assem_arm.c"
1000 // Add virtual address mapping to linked list
1001 void ll_add(struct ll_entry **head,int vaddr,void *addr)
1003 struct ll_entry *new_entry;
1004 new_entry=malloc(sizeof(struct ll_entry));
1005 assert(new_entry!=NULL);
1006 new_entry->vaddr=vaddr;
1008 new_entry->addr=addr;
1009 new_entry->next=*head;
1013 // Add virtual address mapping for 32-bit compiled block
1014 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
1016 ll_add(head,vaddr,addr);
1018 (*head)->reg32=reg32;
1022 // Check if an address is already compiled
1023 // but don't return addresses which are about to expire from the cache
1024 void *check_addr(u_int vaddr)
1026 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
1027 if(ht_bin[0]==vaddr) {
1028 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1029 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1031 if(ht_bin[2]==vaddr) {
1032 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1033 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1035 u_int page=get_page(vaddr);
1036 struct ll_entry *head;
1039 if(head->vaddr==vaddr&&head->reg32==0) {
1040 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1041 // Update existing entry with current address
1042 if(ht_bin[0]==vaddr) {
1043 ht_bin[1]=(int)head->addr;
1046 if(ht_bin[2]==vaddr) {
1047 ht_bin[3]=(int)head->addr;
1050 // Insert into hash table with low priority.
1051 // Don't evict existing entries, as they are probably
1052 // addresses that are being accessed frequently.
1054 ht_bin[1]=(int)head->addr;
1056 }else if(ht_bin[2]==-1) {
1057 ht_bin[3]=(int)head->addr;
1068 void remove_hash(int vaddr)
1070 //printf("remove hash: %x\n",vaddr);
1071 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1072 if(ht_bin[2]==vaddr) {
1073 ht_bin[2]=ht_bin[3]=-1;
1075 if(ht_bin[0]==vaddr) {
1076 ht_bin[0]=ht_bin[2];
1077 ht_bin[1]=ht_bin[3];
1078 ht_bin[2]=ht_bin[3]=-1;
1082 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1084 struct ll_entry *next;
1086 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1087 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1089 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1090 remove_hash((*head)->vaddr);
1097 head=&((*head)->next);
1102 // Remove all entries from linked list
1103 void ll_clear(struct ll_entry **head)
1105 struct ll_entry *cur;
1106 struct ll_entry *next;
1117 // Dereference the pointers and remove if it matches
1118 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1121 int ptr=get_pointer(head->addr);
1122 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1123 if(((ptr>>shift)==(addr>>shift)) ||
1124 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1126 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1127 u_int host_addr=(u_int)kill_pointer(head->addr);
1129 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1136 // This is called when we write to a compiled block (see do_invstub)
1137 void invalidate_page(u_int page)
1139 struct ll_entry *head;
1140 struct ll_entry *next;
1144 inv_debug("INVALIDATE: %x\n",head->vaddr);
1145 remove_hash(head->vaddr);
1150 head=jump_out[page];
1153 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1154 u_int host_addr=(u_int)kill_pointer(head->addr);
1156 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1164 static void invalidate_block_range(u_int block, u_int first, u_int last)
1166 u_int page=get_page(block<<12);
1167 //printf("first=%d last=%d\n",first,last);
1168 invalidate_page(page);
1169 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1170 assert(last<page+5);
1171 // Invalidate the adjacent pages if a block crosses a 4K boundary
1173 invalidate_page(first);
1176 for(first=page+1;first<last;first++) {
1177 invalidate_page(first);
1183 // Don't trap writes
1184 invalid_code[block]=1;
1186 // If there is a valid TLB entry for this page, remove write protect
1187 if(tlb_LUT_w[block]) {
1188 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1189 // CHECK: Is this right?
1190 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1191 u_int real_block=tlb_LUT_w[block]>>12;
1192 invalid_code[real_block]=1;
1193 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1195 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1199 memset(mini_ht,-1,sizeof(mini_ht));
1203 void invalidate_block(u_int block)
1205 u_int page=get_page(block<<12);
1206 u_int vpage=get_vpage(block<<12);
1207 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1208 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1211 struct ll_entry *head;
1212 head=jump_dirty[vpage];
1213 //printf("page=%d vpage=%d\n",page,vpage);
1216 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1217 get_bounds((int)head->addr,&start,&end);
1218 //printf("start: %x end: %x\n",start,end);
1219 if(page<2048&&start>=(u_int)rdram&&end<(u_int)rdram+RAM_SIZE) {
1220 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1221 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1222 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1226 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1227 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1228 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1229 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1236 invalidate_block_range(block,first,last);
1239 void invalidate_addr(u_int addr)
1243 // this check is done by the caller
1244 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1245 u_int page=get_vpage(addr);
1246 if(page<2048) { // RAM
1247 struct ll_entry *head;
1248 u_int addr_min=~0, addr_max=0;
1249 u_int mask=RAM_SIZE-1;
1250 u_int addr_main=0x80000000|(addr&mask);
1252 inv_code_start=addr_main&~0xfff;
1253 inv_code_end=addr_main|0xfff;
1256 // must check previous page too because of spans..
1258 inv_code_start-=0x1000;
1260 for(;pg1<=page;pg1++) {
1261 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1263 get_bounds((int)head->addr,&start,&end);
1268 if(start<=addr_main&&addr_main<end) {
1269 if(start<addr_min) addr_min=start;
1270 if(end>addr_max) addr_max=end;
1272 else if(addr_main<start) {
1273 if(start<inv_code_end)
1274 inv_code_end=start-1;
1277 if(end>inv_code_start)
1283 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1284 inv_code_start=inv_code_end=~0;
1285 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1289 inv_code_start=(addr&~mask)|(inv_code_start&mask);
1290 inv_code_end=(addr&~mask)|(inv_code_end&mask);
1291 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
1296 invalidate_block(addr>>12);
1299 // This is called when loading a save state.
1300 // Anything could have changed, so invalidate everything.
1301 void invalidate_all_pages()
1304 for(page=0;page<4096;page++)
1305 invalidate_page(page);
1306 for(page=0;page<1048576;page++)
1307 if(!invalid_code[page]) {
1308 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1309 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1312 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1315 memset(mini_ht,-1,sizeof(mini_ht));
1319 for(page=0;page<0x100000;page++) {
1320 if(tlb_LUT_r[page]) {
1321 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1322 if(!tlb_LUT_w[page]||!invalid_code[page])
1323 memory_map[page]|=0x40000000; // Write protect
1325 else memory_map[page]=-1;
1326 if(page==0x80000) page=0xC0000;
1332 // Add an entry to jump_out after making a link
1333 void add_link(u_int vaddr,void *src)
1335 u_int page=get_page(vaddr);
1336 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1337 int *ptr=(int *)(src+4);
1338 assert((*ptr&0x0fff0000)==0x059f0000);
1339 ll_add(jump_out+page,vaddr,src);
1340 //int ptr=get_pointer(src);
1341 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1344 // If a code block was found to be unmodified (bit was set in
1345 // restore_candidate) and it remains unmodified (bit is clear
1346 // in invalid_code) then move the entries for that 4K page from
1347 // the dirty list to the clean list.
1348 void clean_blocks(u_int page)
1350 struct ll_entry *head;
1351 inv_debug("INV: clean_blocks page=%d\n",page);
1352 head=jump_dirty[page];
1354 if(!invalid_code[head->vaddr>>12]) {
1355 // Don't restore blocks which are about to expire from the cache
1356 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1358 if(verify_dirty((int)head->addr)) {
1359 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1362 get_bounds((int)head->addr,&start,&end);
1363 if(start-(u_int)rdram<RAM_SIZE) {
1364 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1365 inv|=invalid_code[i];
1369 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1370 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1371 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1372 if(addr<start||addr>=end) inv=1;
1375 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1379 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1380 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1383 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1385 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1386 //printf("page=%x, addr=%x\n",page,head->vaddr);
1387 //assert(head->vaddr>>12==(page|0x80000));
1388 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1389 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1391 if(ht_bin[0]==head->vaddr) {
1392 ht_bin[1]=(int)clean_addr; // Replace existing entry
1394 if(ht_bin[2]==head->vaddr) {
1395 ht_bin[3]=(int)clean_addr; // Replace existing entry
1408 void mov_alloc(struct regstat *current,int i)
1410 // Note: Don't need to actually alloc the source registers
1411 if((~current->is32>>rs1[i])&1) {
1412 //alloc_reg64(current,i,rs1[i]);
1413 alloc_reg64(current,i,rt1[i]);
1414 current->is32&=~(1LL<<rt1[i]);
1416 //alloc_reg(current,i,rs1[i]);
1417 alloc_reg(current,i,rt1[i]);
1418 current->is32|=(1LL<<rt1[i]);
1420 clear_const(current,rs1[i]);
1421 clear_const(current,rt1[i]);
1422 dirty_reg(current,rt1[i]);
1425 void shiftimm_alloc(struct regstat *current,int i)
1427 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1430 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1432 alloc_reg(current,i,rt1[i]);
1433 current->is32|=1LL<<rt1[i];
1434 dirty_reg(current,rt1[i]);
1435 if(is_const(current,rs1[i])) {
1436 int v=get_const(current,rs1[i]);
1437 if(opcode2[i]==0x00) set_const(current,rt1[i],v<<imm[i]);
1438 if(opcode2[i]==0x02) set_const(current,rt1[i],(u_int)v>>imm[i]);
1439 if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]);
1441 else clear_const(current,rt1[i]);
1446 clear_const(current,rs1[i]);
1447 clear_const(current,rt1[i]);
1450 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1453 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1454 alloc_reg64(current,i,rt1[i]);
1455 current->is32&=~(1LL<<rt1[i]);
1456 dirty_reg(current,rt1[i]);
1459 if(opcode2[i]==0x3c) // DSLL32
1462 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1463 alloc_reg64(current,i,rt1[i]);
1464 current->is32&=~(1LL<<rt1[i]);
1465 dirty_reg(current,rt1[i]);
1468 if(opcode2[i]==0x3e) // DSRL32
1471 alloc_reg64(current,i,rs1[i]);
1473 alloc_reg64(current,i,rt1[i]);
1474 current->is32&=~(1LL<<rt1[i]);
1476 alloc_reg(current,i,rt1[i]);
1477 current->is32|=1LL<<rt1[i];
1479 dirty_reg(current,rt1[i]);
1482 if(opcode2[i]==0x3f) // DSRA32
1485 alloc_reg64(current,i,rs1[i]);
1486 alloc_reg(current,i,rt1[i]);
1487 current->is32|=1LL<<rt1[i];
1488 dirty_reg(current,rt1[i]);
1493 void shift_alloc(struct regstat *current,int i)
1496 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1498 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1499 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1500 alloc_reg(current,i,rt1[i]);
1501 if(rt1[i]==rs2[i]) {
1502 alloc_reg_temp(current,i,-1);
1503 minimum_free_regs[i]=1;
1505 current->is32|=1LL<<rt1[i];
1506 } else { // DSLLV/DSRLV/DSRAV
1507 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1508 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1509 alloc_reg64(current,i,rt1[i]);
1510 current->is32&=~(1LL<<rt1[i]);
1511 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1513 alloc_reg_temp(current,i,-1);
1514 minimum_free_regs[i]=1;
1517 clear_const(current,rs1[i]);
1518 clear_const(current,rs2[i]);
1519 clear_const(current,rt1[i]);
1520 dirty_reg(current,rt1[i]);
1524 void alu_alloc(struct regstat *current,int i)
1526 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1528 if(rs1[i]&&rs2[i]) {
1529 alloc_reg(current,i,rs1[i]);
1530 alloc_reg(current,i,rs2[i]);
1533 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1534 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1536 alloc_reg(current,i,rt1[i]);
1538 current->is32|=1LL<<rt1[i];
1540 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1542 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1544 alloc_reg64(current,i,rs1[i]);
1545 alloc_reg64(current,i,rs2[i]);
1546 alloc_reg(current,i,rt1[i]);
1548 alloc_reg(current,i,rs1[i]);
1549 alloc_reg(current,i,rs2[i]);
1550 alloc_reg(current,i,rt1[i]);
1553 current->is32|=1LL<<rt1[i];
1555 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1557 if(rs1[i]&&rs2[i]) {
1558 alloc_reg(current,i,rs1[i]);
1559 alloc_reg(current,i,rs2[i]);
1563 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1564 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1566 alloc_reg(current,i,rt1[i]);
1567 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1569 if(!((current->uu>>rt1[i])&1)) {
1570 alloc_reg64(current,i,rt1[i]);
1572 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1573 if(rs1[i]&&rs2[i]) {
1574 alloc_reg64(current,i,rs1[i]);
1575 alloc_reg64(current,i,rs2[i]);
1579 // Is is really worth it to keep 64-bit values in registers?
1581 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1582 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1586 current->is32&=~(1LL<<rt1[i]);
1588 current->is32|=1LL<<rt1[i];
1592 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1594 if(rs1[i]&&rs2[i]) {
1595 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1596 alloc_reg64(current,i,rs1[i]);
1597 alloc_reg64(current,i,rs2[i]);
1598 alloc_reg64(current,i,rt1[i]);
1600 alloc_reg(current,i,rs1[i]);
1601 alloc_reg(current,i,rs2[i]);
1602 alloc_reg(current,i,rt1[i]);
1606 alloc_reg(current,i,rt1[i]);
1607 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1608 // DADD used as move, or zeroing
1609 // If we have a 64-bit source, then make the target 64 bits too
1610 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1611 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1612 alloc_reg64(current,i,rt1[i]);
1613 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1614 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1615 alloc_reg64(current,i,rt1[i]);
1617 if(opcode2[i]>=0x2e&&rs2[i]) {
1618 // DSUB used as negation - 64-bit result
1619 // If we have a 32-bit register, extend it to 64 bits
1620 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1621 alloc_reg64(current,i,rt1[i]);
1625 if(rs1[i]&&rs2[i]) {
1626 current->is32&=~(1LL<<rt1[i]);
1628 current->is32&=~(1LL<<rt1[i]);
1629 if((current->is32>>rs1[i])&1)
1630 current->is32|=1LL<<rt1[i];
1632 current->is32&=~(1LL<<rt1[i]);
1633 if((current->is32>>rs2[i])&1)
1634 current->is32|=1LL<<rt1[i];
1636 current->is32|=1LL<<rt1[i];
1640 clear_const(current,rs1[i]);
1641 clear_const(current,rs2[i]);
1642 clear_const(current,rt1[i]);
1643 dirty_reg(current,rt1[i]);
1646 void imm16_alloc(struct regstat *current,int i)
1648 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1650 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1651 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1652 current->is32&=~(1LL<<rt1[i]);
1653 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1654 // TODO: Could preserve the 32-bit flag if the immediate is zero
1655 alloc_reg64(current,i,rt1[i]);
1656 alloc_reg64(current,i,rs1[i]);
1658 clear_const(current,rs1[i]);
1659 clear_const(current,rt1[i]);
1661 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1662 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1663 current->is32|=1LL<<rt1[i];
1664 clear_const(current,rs1[i]);
1665 clear_const(current,rt1[i]);
1667 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1668 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1669 if(rs1[i]!=rt1[i]) {
1670 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1671 alloc_reg64(current,i,rt1[i]);
1672 current->is32&=~(1LL<<rt1[i]);
1675 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1676 if(is_const(current,rs1[i])) {
1677 int v=get_const(current,rs1[i]);
1678 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1679 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1680 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1682 else clear_const(current,rt1[i]);
1684 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1685 if(is_const(current,rs1[i])) {
1686 int v=get_const(current,rs1[i]);
1687 set_const(current,rt1[i],v+imm[i]);
1689 else clear_const(current,rt1[i]);
1690 current->is32|=1LL<<rt1[i];
1693 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1694 current->is32|=1LL<<rt1[i];
1696 dirty_reg(current,rt1[i]);
1699 void load_alloc(struct regstat *current,int i)
1701 clear_const(current,rt1[i]);
1702 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1703 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1704 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1705 if(rt1[i]&&!((current->u>>rt1[i])&1)) {
1706 alloc_reg(current,i,rt1[i]);
1707 assert(get_reg(current->regmap,rt1[i])>=0);
1708 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1710 current->is32&=~(1LL<<rt1[i]);
1711 alloc_reg64(current,i,rt1[i]);
1713 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1715 current->is32&=~(1LL<<rt1[i]);
1716 alloc_reg64(current,i,rt1[i]);
1717 alloc_all(current,i);
1718 alloc_reg64(current,i,FTEMP);
1719 minimum_free_regs[i]=HOST_REGS;
1721 else current->is32|=1LL<<rt1[i];
1722 dirty_reg(current,rt1[i]);
1723 // If using TLB, need a register for pointer to the mapping table
1724 if(using_tlb) alloc_reg(current,i,TLREG);
1725 // LWL/LWR need a temporary register for the old value
1726 if(opcode[i]==0x22||opcode[i]==0x26)
1728 alloc_reg(current,i,FTEMP);
1729 alloc_reg_temp(current,i,-1);
1730 minimum_free_regs[i]=1;
1735 // Load to r0 or unneeded register (dummy load)
1736 // but we still need a register to calculate the address
1737 if(opcode[i]==0x22||opcode[i]==0x26)
1739 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1741 // If using TLB, need a register for pointer to the mapping table
1742 if(using_tlb) alloc_reg(current,i,TLREG);
1743 alloc_reg_temp(current,i,-1);
1744 minimum_free_regs[i]=1;
1745 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1747 alloc_all(current,i);
1748 alloc_reg64(current,i,FTEMP);
1749 minimum_free_regs[i]=HOST_REGS;
1754 void store_alloc(struct regstat *current,int i)
1756 clear_const(current,rs2[i]);
1757 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1758 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1759 alloc_reg(current,i,rs2[i]);
1760 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1761 alloc_reg64(current,i,rs2[i]);
1762 if(rs2[i]) alloc_reg(current,i,FTEMP);
1764 // If using TLB, need a register for pointer to the mapping table
1765 if(using_tlb) alloc_reg(current,i,TLREG);
1766 #if defined(HOST_IMM8)
1767 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1768 else alloc_reg(current,i,INVCP);
1770 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1771 alloc_reg(current,i,FTEMP);
1773 // We need a temporary register for address generation
1774 alloc_reg_temp(current,i,-1);
1775 minimum_free_regs[i]=1;
1778 void c1ls_alloc(struct regstat *current,int i)
1780 //clear_const(current,rs1[i]); // FIXME
1781 clear_const(current,rt1[i]);
1782 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1783 alloc_reg(current,i,CSREG); // Status
1784 alloc_reg(current,i,FTEMP);
1785 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1786 alloc_reg64(current,i,FTEMP);
1788 // If using TLB, need a register for pointer to the mapping table
1789 if(using_tlb) alloc_reg(current,i,TLREG);
1790 #if defined(HOST_IMM8)
1791 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1792 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1793 alloc_reg(current,i,INVCP);
1795 // We need a temporary register for address generation
1796 alloc_reg_temp(current,i,-1);
1799 void c2ls_alloc(struct regstat *current,int i)
1801 clear_const(current,rt1[i]);
1802 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1803 alloc_reg(current,i,FTEMP);
1804 // If using TLB, need a register for pointer to the mapping table
1805 if(using_tlb) alloc_reg(current,i,TLREG);
1806 #if defined(HOST_IMM8)
1807 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1808 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1809 alloc_reg(current,i,INVCP);
1811 // We need a temporary register for address generation
1812 alloc_reg_temp(current,i,-1);
1813 minimum_free_regs[i]=1;
1816 #ifndef multdiv_alloc
1817 void multdiv_alloc(struct regstat *current,int i)
1824 // case 0x1D: DMULTU
1827 clear_const(current,rs1[i]);
1828 clear_const(current,rs2[i]);
1831 if((opcode2[i]&4)==0) // 32-bit
1833 current->u&=~(1LL<<HIREG);
1834 current->u&=~(1LL<<LOREG);
1835 alloc_reg(current,i,HIREG);
1836 alloc_reg(current,i,LOREG);
1837 alloc_reg(current,i,rs1[i]);
1838 alloc_reg(current,i,rs2[i]);
1839 current->is32|=1LL<<HIREG;
1840 current->is32|=1LL<<LOREG;
1841 dirty_reg(current,HIREG);
1842 dirty_reg(current,LOREG);
1846 current->u&=~(1LL<<HIREG);
1847 current->u&=~(1LL<<LOREG);
1848 current->uu&=~(1LL<<HIREG);
1849 current->uu&=~(1LL<<LOREG);
1850 alloc_reg64(current,i,HIREG);
1851 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1852 alloc_reg64(current,i,rs1[i]);
1853 alloc_reg64(current,i,rs2[i]);
1854 alloc_all(current,i);
1855 current->is32&=~(1LL<<HIREG);
1856 current->is32&=~(1LL<<LOREG);
1857 dirty_reg(current,HIREG);
1858 dirty_reg(current,LOREG);
1859 minimum_free_regs[i]=HOST_REGS;
1864 // Multiply by zero is zero.
1865 // MIPS does not have a divide by zero exception.
1866 // The result is undefined, we return zero.
1867 alloc_reg(current,i,HIREG);
1868 alloc_reg(current,i,LOREG);
1869 current->is32|=1LL<<HIREG;
1870 current->is32|=1LL<<LOREG;
1871 dirty_reg(current,HIREG);
1872 dirty_reg(current,LOREG);
1877 void cop0_alloc(struct regstat *current,int i)
1879 if(opcode2[i]==0) // MFC0
1882 clear_const(current,rt1[i]);
1883 alloc_all(current,i);
1884 alloc_reg(current,i,rt1[i]);
1885 current->is32|=1LL<<rt1[i];
1886 dirty_reg(current,rt1[i]);
1889 else if(opcode2[i]==4) // MTC0
1892 clear_const(current,rs1[i]);
1893 alloc_reg(current,i,rs1[i]);
1894 alloc_all(current,i);
1897 alloc_all(current,i); // FIXME: Keep r0
1899 alloc_reg(current,i,0);
1904 // TLBR/TLBWI/TLBWR/TLBP/ERET
1905 assert(opcode2[i]==0x10);
1906 alloc_all(current,i);
1908 minimum_free_regs[i]=HOST_REGS;
1911 void cop1_alloc(struct regstat *current,int i)
1913 alloc_reg(current,i,CSREG); // Load status
1914 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1917 clear_const(current,rt1[i]);
1919 alloc_reg64(current,i,rt1[i]); // DMFC1
1920 current->is32&=~(1LL<<rt1[i]);
1922 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1923 current->is32|=1LL<<rt1[i];
1925 dirty_reg(current,rt1[i]);
1927 alloc_reg_temp(current,i,-1);
1929 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1932 clear_const(current,rs1[i]);
1934 alloc_reg64(current,i,rs1[i]); // DMTC1
1936 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1937 alloc_reg_temp(current,i,-1);
1941 alloc_reg(current,i,0);
1942 alloc_reg_temp(current,i,-1);
1945 minimum_free_regs[i]=1;
1947 void fconv_alloc(struct regstat *current,int i)
1949 alloc_reg(current,i,CSREG); // Load status
1950 alloc_reg_temp(current,i,-1);
1951 minimum_free_regs[i]=1;
1953 void float_alloc(struct regstat *current,int i)
1955 alloc_reg(current,i,CSREG); // Load status
1956 alloc_reg_temp(current,i,-1);
1957 minimum_free_regs[i]=1;
1959 void c2op_alloc(struct regstat *current,int i)
1961 alloc_reg_temp(current,i,-1);
1963 void fcomp_alloc(struct regstat *current,int i)
1965 alloc_reg(current,i,CSREG); // Load status
1966 alloc_reg(current,i,FSREG); // Load flags
1967 dirty_reg(current,FSREG); // Flag will be modified
1968 alloc_reg_temp(current,i,-1);
1969 minimum_free_regs[i]=1;
1972 void syscall_alloc(struct regstat *current,int i)
1974 alloc_cc(current,i);
1975 dirty_reg(current,CCREG);
1976 alloc_all(current,i);
1977 minimum_free_regs[i]=HOST_REGS;
1981 void delayslot_alloc(struct regstat *current,int i)
1992 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1993 printf("Disabled speculative precompilation\n");
1997 imm16_alloc(current,i);
2001 load_alloc(current,i);
2005 store_alloc(current,i);
2008 alu_alloc(current,i);
2011 shift_alloc(current,i);
2014 multdiv_alloc(current,i);
2017 shiftimm_alloc(current,i);
2020 mov_alloc(current,i);
2023 cop0_alloc(current,i);
2027 cop1_alloc(current,i);
2030 c1ls_alloc(current,i);
2033 c2ls_alloc(current,i);
2036 fconv_alloc(current,i);
2039 float_alloc(current,i);
2042 fcomp_alloc(current,i);
2045 c2op_alloc(current,i);
2050 // Special case where a branch and delay slot span two pages in virtual memory
2051 static void pagespan_alloc(struct regstat *current,int i)
2054 current->wasconst=0;
2056 minimum_free_regs[i]=HOST_REGS;
2057 alloc_all(current,i);
2058 alloc_cc(current,i);
2059 dirty_reg(current,CCREG);
2060 if(opcode[i]==3) // JAL
2062 alloc_reg(current,i,31);
2063 dirty_reg(current,31);
2065 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
2067 alloc_reg(current,i,rs1[i]);
2069 alloc_reg(current,i,rt1[i]);
2070 dirty_reg(current,rt1[i]);
2073 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2075 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2076 if(rs2[i]) alloc_reg(current,i,rs2[i]);
2077 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
2079 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2080 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
2084 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2086 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2087 if(!((current->is32>>rs1[i])&1))
2089 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2093 if(opcode[i]==0x11) // BC1
2095 alloc_reg(current,i,FSREG);
2096 alloc_reg(current,i,CSREG);
2101 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2103 stubs[stubcount][0]=type;
2104 stubs[stubcount][1]=addr;
2105 stubs[stubcount][2]=retaddr;
2106 stubs[stubcount][3]=a;
2107 stubs[stubcount][4]=b;
2108 stubs[stubcount][5]=c;
2109 stubs[stubcount][6]=d;
2110 stubs[stubcount][7]=e;
2114 // Write out a single register
2115 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2118 for(hr=0;hr<HOST_REGS;hr++) {
2119 if(hr!=EXCLUDE_REG) {
2120 if((regmap[hr]&63)==r) {
2123 emit_storereg(r,hr);
2125 if((is32>>regmap[hr])&1) {
2126 emit_sarimm(hr,31,hr);
2127 emit_storereg(r|64,hr);
2131 emit_storereg(r|64,hr);
2141 //if(!tracedebug) return 0;
2144 for(i=0;i<2097152;i++) {
2145 unsigned int temp=sum;
2148 sum^=((u_int *)rdram)[i];
2157 sum^=((u_int *)reg)[i];
2165 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2167 #ifndef DISABLE_COP1
2170 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2180 void memdebug(int i)
2182 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2183 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2186 //if(Count>=-2084597794) {
2187 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2189 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2190 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2191 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2194 printf("TRACE: %x\n",(&i)[-1]);
2198 printf("TRACE: %x \n",(&j)[10]);
2199 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2203 //printf("TRACE: %x\n",(&i)[-1]);
2206 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2208 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2211 void alu_assemble(int i,struct regstat *i_regs)
2213 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2215 signed char s1,s2,t;
2216 t=get_reg(i_regs->regmap,rt1[i]);
2218 s1=get_reg(i_regs->regmap,rs1[i]);
2219 s2=get_reg(i_regs->regmap,rs2[i]);
2220 if(rs1[i]&&rs2[i]) {
2223 if(opcode2[i]&2) emit_sub(s1,s2,t);
2224 else emit_add(s1,s2,t);
2227 if(s1>=0) emit_mov(s1,t);
2228 else emit_loadreg(rs1[i],t);
2232 if(opcode2[i]&2) emit_neg(s2,t);
2233 else emit_mov(s2,t);
2236 emit_loadreg(rs2[i],t);
2237 if(opcode2[i]&2) emit_neg(t,t);
2240 else emit_zeroreg(t);
2244 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2246 signed char s1l,s2l,s1h,s2h,tl,th;
2247 tl=get_reg(i_regs->regmap,rt1[i]);
2248 th=get_reg(i_regs->regmap,rt1[i]|64);
2250 s1l=get_reg(i_regs->regmap,rs1[i]);
2251 s2l=get_reg(i_regs->regmap,rs2[i]);
2252 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2253 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2254 if(rs1[i]&&rs2[i]) {
2257 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2258 else emit_adds(s1l,s2l,tl);
2260 #ifdef INVERTED_CARRY
2261 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2263 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2265 else emit_add(s1h,s2h,th);
2269 if(s1l>=0) emit_mov(s1l,tl);
2270 else emit_loadreg(rs1[i],tl);
2272 if(s1h>=0) emit_mov(s1h,th);
2273 else emit_loadreg(rs1[i]|64,th);
2278 if(opcode2[i]&2) emit_negs(s2l,tl);
2279 else emit_mov(s2l,tl);
2282 emit_loadreg(rs2[i],tl);
2283 if(opcode2[i]&2) emit_negs(tl,tl);
2286 #ifdef INVERTED_CARRY
2287 if(s2h>=0) emit_mov(s2h,th);
2288 else emit_loadreg(rs2[i]|64,th);
2290 emit_adcimm(-1,th); // x86 has inverted carry flag
2295 if(s2h>=0) emit_rscimm(s2h,0,th);
2297 emit_loadreg(rs2[i]|64,th);
2298 emit_rscimm(th,0,th);
2301 if(s2h>=0) emit_mov(s2h,th);
2302 else emit_loadreg(rs2[i]|64,th);
2309 if(th>=0) emit_zeroreg(th);
2314 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2316 signed char s1l,s1h,s2l,s2h,t;
2317 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2319 t=get_reg(i_regs->regmap,rt1[i]);
2322 s1l=get_reg(i_regs->regmap,rs1[i]);
2323 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2324 s2l=get_reg(i_regs->regmap,rs2[i]);
2325 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2326 if(rs2[i]==0) // rx<r0
2329 if(opcode2[i]==0x2a) // SLT
2330 emit_shrimm(s1h,31,t);
2331 else // SLTU (unsigned can not be less than zero)
2334 else if(rs1[i]==0) // r0<rx
2337 if(opcode2[i]==0x2a) // SLT
2338 emit_set_gz64_32(s2h,s2l,t);
2339 else // SLTU (set if not zero)
2340 emit_set_nz64_32(s2h,s2l,t);
2343 assert(s1l>=0);assert(s1h>=0);
2344 assert(s2l>=0);assert(s2h>=0);
2345 if(opcode2[i]==0x2a) // SLT
2346 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2348 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2352 t=get_reg(i_regs->regmap,rt1[i]);
2355 s1l=get_reg(i_regs->regmap,rs1[i]);
2356 s2l=get_reg(i_regs->regmap,rs2[i]);
2357 if(rs2[i]==0) // rx<r0
2360 if(opcode2[i]==0x2a) // SLT
2361 emit_shrimm(s1l,31,t);
2362 else // SLTU (unsigned can not be less than zero)
2365 else if(rs1[i]==0) // r0<rx
2368 if(opcode2[i]==0x2a) // SLT
2369 emit_set_gz32(s2l,t);
2370 else // SLTU (set if not zero)
2371 emit_set_nz32(s2l,t);
2374 assert(s1l>=0);assert(s2l>=0);
2375 if(opcode2[i]==0x2a) // SLT
2376 emit_set_if_less32(s1l,s2l,t);
2378 emit_set_if_carry32(s1l,s2l,t);
2384 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2386 signed char s1l,s1h,s2l,s2h,th,tl;
2387 tl=get_reg(i_regs->regmap,rt1[i]);
2388 th=get_reg(i_regs->regmap,rt1[i]|64);
2389 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2393 s1l=get_reg(i_regs->regmap,rs1[i]);
2394 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2395 s2l=get_reg(i_regs->regmap,rs2[i]);
2396 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2397 if(rs1[i]&&rs2[i]) {
2398 assert(s1l>=0);assert(s1h>=0);
2399 assert(s2l>=0);assert(s2h>=0);
2400 if(opcode2[i]==0x24) { // AND
2401 emit_and(s1l,s2l,tl);
2402 emit_and(s1h,s2h,th);
2404 if(opcode2[i]==0x25) { // OR
2405 emit_or(s1l,s2l,tl);
2406 emit_or(s1h,s2h,th);
2408 if(opcode2[i]==0x26) { // XOR
2409 emit_xor(s1l,s2l,tl);
2410 emit_xor(s1h,s2h,th);
2412 if(opcode2[i]==0x27) { // NOR
2413 emit_or(s1l,s2l,tl);
2414 emit_or(s1h,s2h,th);
2421 if(opcode2[i]==0x24) { // AND
2425 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2427 if(s1l>=0) emit_mov(s1l,tl);
2428 else emit_loadreg(rs1[i],tl);
2429 if(s1h>=0) emit_mov(s1h,th);
2430 else emit_loadreg(rs1[i]|64,th);
2434 if(s2l>=0) emit_mov(s2l,tl);
2435 else emit_loadreg(rs2[i],tl);
2436 if(s2h>=0) emit_mov(s2h,th);
2437 else emit_loadreg(rs2[i]|64,th);
2444 if(opcode2[i]==0x27) { // NOR
2446 if(s1l>=0) emit_not(s1l,tl);
2448 emit_loadreg(rs1[i],tl);
2451 if(s1h>=0) emit_not(s1h,th);
2453 emit_loadreg(rs1[i]|64,th);
2459 if(s2l>=0) emit_not(s2l,tl);
2461 emit_loadreg(rs2[i],tl);
2464 if(s2h>=0) emit_not(s2h,th);
2466 emit_loadreg(rs2[i]|64,th);
2482 s1l=get_reg(i_regs->regmap,rs1[i]);
2483 s2l=get_reg(i_regs->regmap,rs2[i]);
2484 if(rs1[i]&&rs2[i]) {
2487 if(opcode2[i]==0x24) { // AND
2488 emit_and(s1l,s2l,tl);
2490 if(opcode2[i]==0x25) { // OR
2491 emit_or(s1l,s2l,tl);
2493 if(opcode2[i]==0x26) { // XOR
2494 emit_xor(s1l,s2l,tl);
2496 if(opcode2[i]==0x27) { // NOR
2497 emit_or(s1l,s2l,tl);
2503 if(opcode2[i]==0x24) { // AND
2506 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2508 if(s1l>=0) emit_mov(s1l,tl);
2509 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2513 if(s2l>=0) emit_mov(s2l,tl);
2514 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2516 else emit_zeroreg(tl);
2518 if(opcode2[i]==0x27) { // NOR
2520 if(s1l>=0) emit_not(s1l,tl);
2522 emit_loadreg(rs1[i],tl);
2528 if(s2l>=0) emit_not(s2l,tl);
2530 emit_loadreg(rs2[i],tl);
2534 else emit_movimm(-1,tl);
2543 void imm16_assemble(int i,struct regstat *i_regs)
2545 if (opcode[i]==0x0f) { // LUI
2548 t=get_reg(i_regs->regmap,rt1[i]);
2551 if(!((i_regs->isconst>>t)&1))
2552 emit_movimm(imm[i]<<16,t);
2556 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2559 t=get_reg(i_regs->regmap,rt1[i]);
2560 s=get_reg(i_regs->regmap,rs1[i]);
2565 if(!((i_regs->isconst>>t)&1)) {
2567 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2568 emit_addimm(t,imm[i],t);
2570 if(!((i_regs->wasconst>>s)&1))
2571 emit_addimm(s,imm[i],t);
2573 emit_movimm(constmap[i][s]+imm[i],t);
2579 if(!((i_regs->isconst>>t)&1))
2580 emit_movimm(imm[i],t);
2585 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2587 signed char sh,sl,th,tl;
2588 th=get_reg(i_regs->regmap,rt1[i]|64);
2589 tl=get_reg(i_regs->regmap,rt1[i]);
2590 sh=get_reg(i_regs->regmap,rs1[i]|64);
2591 sl=get_reg(i_regs->regmap,rs1[i]);
2597 emit_addimm64_32(sh,sl,imm[i],th,tl);
2600 emit_addimm(sl,imm[i],tl);
2603 emit_movimm(imm[i],tl);
2604 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2609 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2611 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2612 signed char sh,sl,t;
2613 t=get_reg(i_regs->regmap,rt1[i]);
2614 sh=get_reg(i_regs->regmap,rs1[i]|64);
2615 sl=get_reg(i_regs->regmap,rs1[i]);
2619 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2620 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2621 if(opcode[i]==0x0a) { // SLTI
2623 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2624 emit_slti32(t,imm[i],t);
2626 emit_slti32(sl,imm[i],t);
2631 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2632 emit_sltiu32(t,imm[i],t);
2634 emit_sltiu32(sl,imm[i],t);
2639 if(opcode[i]==0x0a) // SLTI
2640 emit_slti64_32(sh,sl,imm[i],t);
2642 emit_sltiu64_32(sh,sl,imm[i],t);
2645 // SLTI(U) with r0 is just stupid,
2646 // nonetheless examples can be found
2647 if(opcode[i]==0x0a) // SLTI
2648 if(0<imm[i]) emit_movimm(1,t);
2649 else emit_zeroreg(t);
2652 if(imm[i]) emit_movimm(1,t);
2653 else emit_zeroreg(t);
2659 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2661 signed char sh,sl,th,tl;
2662 th=get_reg(i_regs->regmap,rt1[i]|64);
2663 tl=get_reg(i_regs->regmap,rt1[i]);
2664 sh=get_reg(i_regs->regmap,rs1[i]|64);
2665 sl=get_reg(i_regs->regmap,rs1[i]);
2666 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2667 if(opcode[i]==0x0c) //ANDI
2671 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2672 emit_andimm(tl,imm[i],tl);
2674 if(!((i_regs->wasconst>>sl)&1))
2675 emit_andimm(sl,imm[i],tl);
2677 emit_movimm(constmap[i][sl]&imm[i],tl);
2682 if(th>=0) emit_zeroreg(th);
2688 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2692 emit_loadreg(rs1[i]|64,th);
2697 if(opcode[i]==0x0d) //ORI
2699 emit_orimm(tl,imm[i],tl);
2701 if(!((i_regs->wasconst>>sl)&1))
2702 emit_orimm(sl,imm[i],tl);
2704 emit_movimm(constmap[i][sl]|imm[i],tl);
2706 if(opcode[i]==0x0e) //XORI
2708 emit_xorimm(tl,imm[i],tl);
2710 if(!((i_regs->wasconst>>sl)&1))
2711 emit_xorimm(sl,imm[i],tl);
2713 emit_movimm(constmap[i][sl]^imm[i],tl);
2717 emit_movimm(imm[i],tl);
2718 if(th>=0) emit_zeroreg(th);
2726 void shiftimm_assemble(int i,struct regstat *i_regs)
2728 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2732 t=get_reg(i_regs->regmap,rt1[i]);
2733 s=get_reg(i_regs->regmap,rs1[i]);
2735 if(t>=0&&!((i_regs->isconst>>t)&1)){
2742 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2744 if(opcode2[i]==0) // SLL
2746 emit_shlimm(s<0?t:s,imm[i],t);
2748 if(opcode2[i]==2) // SRL
2750 emit_shrimm(s<0?t:s,imm[i],t);
2752 if(opcode2[i]==3) // SRA
2754 emit_sarimm(s<0?t:s,imm[i],t);
2758 if(s>=0 && s!=t) emit_mov(s,t);
2762 //emit_storereg(rt1[i],t); //DEBUG
2765 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2768 signed char sh,sl,th,tl;
2769 th=get_reg(i_regs->regmap,rt1[i]|64);
2770 tl=get_reg(i_regs->regmap,rt1[i]);
2771 sh=get_reg(i_regs->regmap,rs1[i]|64);
2772 sl=get_reg(i_regs->regmap,rs1[i]);
2777 if(th>=0) emit_zeroreg(th);
2784 if(opcode2[i]==0x38) // DSLL
2786 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2787 emit_shlimm(sl,imm[i],tl);
2789 if(opcode2[i]==0x3a) // DSRL
2791 emit_shrdimm(sl,sh,imm[i],tl);
2792 if(th>=0) emit_shrimm(sh,imm[i],th);
2794 if(opcode2[i]==0x3b) // DSRA
2796 emit_shrdimm(sl,sh,imm[i],tl);
2797 if(th>=0) emit_sarimm(sh,imm[i],th);
2801 if(sl!=tl) emit_mov(sl,tl);
2802 if(th>=0&&sh!=th) emit_mov(sh,th);
2808 if(opcode2[i]==0x3c) // DSLL32
2811 signed char sl,tl,th;
2812 tl=get_reg(i_regs->regmap,rt1[i]);
2813 th=get_reg(i_regs->regmap,rt1[i]|64);
2814 sl=get_reg(i_regs->regmap,rs1[i]);
2823 emit_shlimm(th,imm[i]&31,th);
2828 if(opcode2[i]==0x3e) // DSRL32
2831 signed char sh,tl,th;
2832 tl=get_reg(i_regs->regmap,rt1[i]);
2833 th=get_reg(i_regs->regmap,rt1[i]|64);
2834 sh=get_reg(i_regs->regmap,rs1[i]|64);
2838 if(th>=0) emit_zeroreg(th);
2841 emit_shrimm(tl,imm[i]&31,tl);
2846 if(opcode2[i]==0x3f) // DSRA32
2850 tl=get_reg(i_regs->regmap,rt1[i]);
2851 sh=get_reg(i_regs->regmap,rs1[i]|64);
2857 emit_sarimm(tl,imm[i]&31,tl);
2864 #ifndef shift_assemble
2865 void shift_assemble(int i,struct regstat *i_regs)
2867 printf("Need shift_assemble for this architecture.\n");
2872 void load_assemble(int i,struct regstat *i_regs)
2874 int s,th,tl,addr,map=-1;
2877 int memtarget=0,c=0;
2878 int fastload_reg_override=0;
2880 th=get_reg(i_regs->regmap,rt1[i]|64);
2881 tl=get_reg(i_regs->regmap,rt1[i]);
2882 s=get_reg(i_regs->regmap,rs1[i]);
2884 for(hr=0;hr<HOST_REGS;hr++) {
2885 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2887 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2889 c=(i_regs->wasconst>>s)&1;
2891 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2892 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2895 //printf("load_assemble: c=%d\n",c);
2896 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2897 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2899 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2901 // could be FIFO, must perform the read
2903 assem_debug("(forced read)\n");
2904 tl=get_reg(i_regs->regmap,-1);
2908 if(offset||s<0||c) addr=tl;
2910 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2912 //printf("load_assemble: c=%d\n",c);
2913 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2914 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2916 if(th>=0) reglist&=~(1<<th);
2920 map=get_reg(i_regs->regmap,ROREG);
2921 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2923 //#define R29_HACK 1
2925 // Strmnnrmn's speed hack
2926 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2929 jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
2932 else if(ram_offset&&memtarget) {
2933 emit_addimm(addr,ram_offset,HOST_TEMPREG);
2934 fastload_reg_override=HOST_TEMPREG;
2938 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2939 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2940 map=get_reg(i_regs->regmap,TLREG);
2943 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2944 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2946 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2947 if (opcode[i]==0x20) { // LB
2950 #ifdef HOST_IMM_ADDR32
2952 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2956 //emit_xorimm(addr,3,tl);
2957 //gen_tlb_addr_r(tl,map);
2958 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2960 #ifdef BIG_ENDIAN_MIPS
2961 if(!c) emit_xorimm(addr,3,tl);
2962 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2966 if(fastload_reg_override) a=fastload_reg_override;
2968 emit_movsbl_indexed_tlb(x,a,map,tl);
2972 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2975 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2977 if (opcode[i]==0x21) { // LH
2980 #ifdef HOST_IMM_ADDR32
2982 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2987 #ifdef BIG_ENDIAN_MIPS
2988 if(!c) emit_xorimm(addr,2,tl);
2989 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2993 if(fastload_reg_override) a=fastload_reg_override;
2995 //emit_movswl_indexed_tlb(x,tl,map,tl);
2998 gen_tlb_addr_r(a,map);
2999 emit_movswl_indexed(x,a,tl);
3001 #if 1 //def RAM_OFFSET
3002 emit_movswl_indexed(x,a,tl);
3004 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
3010 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3013 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3015 if (opcode[i]==0x23) { // LW
3019 if(fastload_reg_override) a=fastload_reg_override;
3020 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3021 #ifdef HOST_IMM_ADDR32
3023 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3026 emit_readword_indexed_tlb(0,a,map,tl);
3029 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3032 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3034 if (opcode[i]==0x24) { // LBU
3037 #ifdef HOST_IMM_ADDR32
3039 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
3043 //emit_xorimm(addr,3,tl);
3044 //gen_tlb_addr_r(tl,map);
3045 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
3047 #ifdef BIG_ENDIAN_MIPS
3048 if(!c) emit_xorimm(addr,3,tl);
3049 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3053 if(fastload_reg_override) a=fastload_reg_override;
3055 emit_movzbl_indexed_tlb(x,a,map,tl);
3059 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3062 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3064 if (opcode[i]==0x25) { // LHU
3067 #ifdef HOST_IMM_ADDR32
3069 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
3074 #ifdef BIG_ENDIAN_MIPS
3075 if(!c) emit_xorimm(addr,2,tl);
3076 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3080 if(fastload_reg_override) a=fastload_reg_override;
3082 //emit_movzwl_indexed_tlb(x,tl,map,tl);
3085 gen_tlb_addr_r(a,map);
3086 emit_movzwl_indexed(x,a,tl);
3088 #if 1 //def RAM_OFFSET
3089 emit_movzwl_indexed(x,a,tl);
3091 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3097 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3100 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3102 if (opcode[i]==0x27) { // LWU
3107 if(fastload_reg_override) a=fastload_reg_override;
3108 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3109 #ifdef HOST_IMM_ADDR32
3111 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3114 emit_readword_indexed_tlb(0,a,map,tl);
3117 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3120 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3124 if (opcode[i]==0x37) { // LD
3128 if(fastload_reg_override) a=fastload_reg_override;
3129 //gen_tlb_addr_r(tl,map);
3130 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3131 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3132 #ifdef HOST_IMM_ADDR32
3134 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3137 emit_readdword_indexed_tlb(0,a,map,th,tl);
3140 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3143 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3146 //emit_storereg(rt1[i],tl); // DEBUG
3147 //if(opcode[i]==0x23)
3148 //if(opcode[i]==0x24)
3149 //if(opcode[i]==0x23||opcode[i]==0x24)
3150 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3154 emit_readword((int)&last_count,ECX);
3156 if(get_reg(i_regs->regmap,CCREG)<0)
3157 emit_loadreg(CCREG,HOST_CCREG);
3158 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3159 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3160 emit_writeword(HOST_CCREG,(int)&Count);
3163 if(get_reg(i_regs->regmap,CCREG)<0)
3164 emit_loadreg(CCREG,0);
3166 emit_mov(HOST_CCREG,0);
3168 emit_addimm(0,2*ccadj[i],0);
3169 emit_writeword(0,(int)&Count);
3171 emit_call((int)memdebug);
3173 restore_regs(0x100f);
3177 #ifndef loadlr_assemble
3178 void loadlr_assemble(int i,struct regstat *i_regs)
3180 printf("Need loadlr_assemble for this architecture.\n");
3185 void store_assemble(int i,struct regstat *i_regs)
3190 int jaddr=0,jaddr2,type;
3191 int memtarget=0,c=0;
3192 int agr=AGEN1+(i&1);
3193 int faststore_reg_override=0;
3195 th=get_reg(i_regs->regmap,rs2[i]|64);
3196 tl=get_reg(i_regs->regmap,rs2[i]);
3197 s=get_reg(i_regs->regmap,rs1[i]);
3198 temp=get_reg(i_regs->regmap,agr);
3199 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3202 c=(i_regs->wasconst>>s)&1;
3204 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3205 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3210 for(hr=0;hr<HOST_REGS;hr++) {
3211 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3213 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3214 if(offset||s<0||c) addr=temp;
3220 // Strmnnrmn's speed hack
3221 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3223 emit_cmpimm(addr,RAM_SIZE);
3224 #ifdef DESTRUCTIVE_SHIFT
3225 if(s==addr) emit_mov(s,temp);
3229 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3233 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3234 // Hint to branch predictor that the branch is unlikely to be taken
3236 emit_jno_unlikely(0);
3242 jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
3245 else if(ram_offset&&memtarget) {
3246 emit_addimm(addr,ram_offset,HOST_TEMPREG);
3247 faststore_reg_override=HOST_TEMPREG;
3251 if (opcode[i]==0x28) x=3; // SB
3252 if (opcode[i]==0x29) x=2; // SH
3253 map=get_reg(i_regs->regmap,TLREG);
3256 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3257 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3260 if (opcode[i]==0x28) { // SB
3263 #ifdef BIG_ENDIAN_MIPS
3264 if(!c) emit_xorimm(addr,3,temp);
3265 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3269 if(faststore_reg_override) a=faststore_reg_override;
3270 //gen_tlb_addr_w(temp,map);
3271 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3272 emit_writebyte_indexed_tlb(tl,x,a,map,a);
3276 if (opcode[i]==0x29) { // SH
3279 #ifdef BIG_ENDIAN_MIPS
3280 if(!c) emit_xorimm(addr,2,temp);
3281 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3285 if(faststore_reg_override) a=faststore_reg_override;
3287 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3290 gen_tlb_addr_w(a,map);
3291 emit_writehword_indexed(tl,x,a);
3293 //emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
3294 emit_writehword_indexed(tl,x,a);
3298 if (opcode[i]==0x2B) { // SW
3301 if(faststore_reg_override) a=faststore_reg_override;
3302 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3303 emit_writeword_indexed_tlb(tl,0,a,map,temp);
3307 if (opcode[i]==0x3F) { // SD
3310 if(faststore_reg_override) a=faststore_reg_override;
3313 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3314 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3315 emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
3318 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3319 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3320 emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
3327 // PCSX store handlers don't check invcode again
3329 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3333 if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3335 #ifdef DESTRUCTIVE_SHIFT
3336 // The x86 shift operation is 'destructive'; it overwrites the
3337 // source register, so we need to make a copy first and use that.
3340 #if defined(HOST_IMM8)
3341 int ir=get_reg(i_regs->regmap,INVCP);
3343 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3345 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3347 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3348 emit_callne(invalidate_addr_reg[addr]);
3352 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3356 u_int addr_val=constmap[i][s]+offset;
3358 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3359 } else if(c&&!memtarget) {
3360 inline_writestub(type,i,addr_val,i_regs->regmap,rs2[i],ccadj[i],reglist);
3362 // basic current block modification detection..
3363 // not looking back as that should be in mips cache already
3364 if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
3365 printf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
3366 assert(i_regs->regmap==regs[i].regmap); // not delay slot
3367 if(i_regs->regmap==regs[i].regmap) {
3368 load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
3369 wb_dirtys(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty);
3370 emit_movimm(start+i*4+4,0);
3371 emit_writeword(0,(int)&pcaddr);
3372 emit_jmp((int)do_interrupt);
3375 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3376 //if(opcode[i]==0x2B || opcode[i]==0x28)
3377 //if(opcode[i]==0x2B || opcode[i]==0x29)
3378 //if(opcode[i]==0x2B)
3379 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3387 emit_readword((int)&last_count,ECX);
3389 if(get_reg(i_regs->regmap,CCREG)<0)
3390 emit_loadreg(CCREG,HOST_CCREG);
3391 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3392 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3393 emit_writeword(HOST_CCREG,(int)&Count);
3396 if(get_reg(i_regs->regmap,CCREG)<0)
3397 emit_loadreg(CCREG,0);
3399 emit_mov(HOST_CCREG,0);
3401 emit_addimm(0,2*ccadj[i],0);
3402 emit_writeword(0,(int)&Count);
3404 emit_call((int)memdebug);
3409 restore_regs(0x100f);
3414 void storelr_assemble(int i,struct regstat *i_regs)
3421 int case1,case2,case3;
3422 int done0,done1,done2;
3423 int memtarget=0,c=0;
3424 int agr=AGEN1+(i&1);
3426 th=get_reg(i_regs->regmap,rs2[i]|64);
3427 tl=get_reg(i_regs->regmap,rs2[i]);
3428 s=get_reg(i_regs->regmap,rs1[i]);
3429 temp=get_reg(i_regs->regmap,agr);
3430 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3433 c=(i_regs->isconst>>s)&1;
3435 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3436 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3440 for(hr=0;hr<HOST_REGS;hr++) {
3441 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3446 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3447 if(!offset&&s!=temp) emit_mov(s,temp);
3453 if(!memtarget||!rs1[i]) {
3459 int map=get_reg(i_regs->regmap,ROREG);
3460 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3461 gen_tlb_addr_w(temp,map);
3463 if((u_int)rdram!=0x80000000)
3464 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3467 int map=get_reg(i_regs->regmap,TLREG);
3470 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3471 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3472 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3473 if(!jaddr&&!memtarget) {
3477 gen_tlb_addr_w(temp,map);
3480 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3481 temp2=get_reg(i_regs->regmap,FTEMP);
3482 if(!rs2[i]) temp2=th=tl;
3485 #ifndef BIG_ENDIAN_MIPS
3486 emit_xorimm(temp,3,temp);
3488 emit_testimm(temp,2);
3491 emit_testimm(temp,1);
3495 if (opcode[i]==0x2A) { // SWL
3496 emit_writeword_indexed(tl,0,temp);
3498 if (opcode[i]==0x2E) { // SWR
3499 emit_writebyte_indexed(tl,3,temp);
3501 if (opcode[i]==0x2C) { // SDL
3502 emit_writeword_indexed(th,0,temp);
3503 if(rs2[i]) emit_mov(tl,temp2);
3505 if (opcode[i]==0x2D) { // SDR
3506 emit_writebyte_indexed(tl,3,temp);
3507 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3512 set_jump_target(case1,(int)out);
3513 if (opcode[i]==0x2A) { // SWL
3514 // Write 3 msb into three least significant bytes
3515 if(rs2[i]) emit_rorimm(tl,8,tl);
3516 emit_writehword_indexed(tl,-1,temp);
3517 if(rs2[i]) emit_rorimm(tl,16,tl);
3518 emit_writebyte_indexed(tl,1,temp);
3519 if(rs2[i]) emit_rorimm(tl,8,tl);
3521 if (opcode[i]==0x2E) { // SWR
3522 // Write two lsb into two most significant bytes
3523 emit_writehword_indexed(tl,1,temp);
3525 if (opcode[i]==0x2C) { // SDL
3526 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3527 // Write 3 msb into three least significant bytes
3528 if(rs2[i]) emit_rorimm(th,8,th);
3529 emit_writehword_indexed(th,-1,temp);
3530 if(rs2[i]) emit_rorimm(th,16,th);
3531 emit_writebyte_indexed(th,1,temp);
3532 if(rs2[i]) emit_rorimm(th,8,th);
3534 if (opcode[i]==0x2D) { // SDR
3535 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3536 // Write two lsb into two most significant bytes
3537 emit_writehword_indexed(tl,1,temp);
3542 set_jump_target(case2,(int)out);
3543 emit_testimm(temp,1);
3546 if (opcode[i]==0x2A) { // SWL
3547 // Write two msb into two least significant bytes
3548 if(rs2[i]) emit_rorimm(tl,16,tl);
3549 emit_writehword_indexed(tl,-2,temp);
3550 if(rs2[i]) emit_rorimm(tl,16,tl);
3552 if (opcode[i]==0x2E) { // SWR
3553 // Write 3 lsb into three most significant bytes
3554 emit_writebyte_indexed(tl,-1,temp);
3555 if(rs2[i]) emit_rorimm(tl,8,tl);
3556 emit_writehword_indexed(tl,0,temp);
3557 if(rs2[i]) emit_rorimm(tl,24,tl);
3559 if (opcode[i]==0x2C) { // SDL
3560 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3561 // Write two msb into two least significant bytes
3562 if(rs2[i]) emit_rorimm(th,16,th);
3563 emit_writehword_indexed(th,-2,temp);
3564 if(rs2[i]) emit_rorimm(th,16,th);
3566 if (opcode[i]==0x2D) { // SDR
3567 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3568 // Write 3 lsb into three most significant bytes
3569 emit_writebyte_indexed(tl,-1,temp);
3570 if(rs2[i]) emit_rorimm(tl,8,tl);
3571 emit_writehword_indexed(tl,0,temp);
3572 if(rs2[i]) emit_rorimm(tl,24,tl);
3577 set_jump_target(case3,(int)out);
3578 if (opcode[i]==0x2A) { // SWL
3579 // Write msb into least significant byte
3580 if(rs2[i]) emit_rorimm(tl,24,tl);
3581 emit_writebyte_indexed(tl,-3,temp);
3582 if(rs2[i]) emit_rorimm(tl,8,tl);
3584 if (opcode[i]==0x2E) { // SWR
3585 // Write entire word
3586 emit_writeword_indexed(tl,-3,temp);
3588 if (opcode[i]==0x2C) { // SDL
3589 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3590 // Write msb into least significant byte
3591 if(rs2[i]) emit_rorimm(th,24,th);
3592 emit_writebyte_indexed(th,-3,temp);
3593 if(rs2[i]) emit_rorimm(th,8,th);
3595 if (opcode[i]==0x2D) { // SDR
3596 if(rs2[i]) emit_mov(th,temp2);
3597 // Write entire word
3598 emit_writeword_indexed(tl,-3,temp);
3600 set_jump_target(done0,(int)out);
3601 set_jump_target(done1,(int)out);
3602 set_jump_target(done2,(int)out);
3603 if (opcode[i]==0x2C) { // SDL
3604 emit_testimm(temp,4);
3607 emit_andimm(temp,~3,temp);
3608 emit_writeword_indexed(temp2,4,temp);
3609 set_jump_target(done0,(int)out);
3611 if (opcode[i]==0x2D) { // SDR
3612 emit_testimm(temp,4);
3615 emit_andimm(temp,~3,temp);
3616 emit_writeword_indexed(temp2,-4,temp);
3617 set_jump_target(done0,(int)out);
3620 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3621 if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3623 int map=get_reg(i_regs->regmap,ROREG);
3624 if(map<0) map=HOST_TEMPREG;
3625 gen_orig_addr_w(temp,map);
3627 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3629 #if defined(HOST_IMM8)
3630 int ir=get_reg(i_regs->regmap,INVCP);
3632 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3634 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3636 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3637 emit_callne(invalidate_addr_reg[temp]);
3641 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3646 //save_regs(0x100f);
3647 emit_readword((int)&last_count,ECX);
3648 if(get_reg(i_regs->regmap,CCREG)<0)
3649 emit_loadreg(CCREG,HOST_CCREG);
3650 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3651 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3652 emit_writeword(HOST_CCREG,(int)&Count);
3653 emit_call((int)memdebug);
3655 //restore_regs(0x100f);
3659 void c1ls_assemble(int i,struct regstat *i_regs)
3661 #ifndef DISABLE_COP1
3667 int jaddr,jaddr2=0,jaddr3,type;
3668 int agr=AGEN1+(i&1);
3670 th=get_reg(i_regs->regmap,FTEMP|64);
3671 tl=get_reg(i_regs->regmap,FTEMP);
3672 s=get_reg(i_regs->regmap,rs1[i]);
3673 temp=get_reg(i_regs->regmap,agr);
3674 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3679 for(hr=0;hr<HOST_REGS;hr++) {
3680 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3682 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3683 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3685 // Loads use a temporary register which we need to save
3688 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3692 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3693 //else c=(i_regs->wasconst>>s)&1;
3694 if(s>=0) c=(i_regs->wasconst>>s)&1;
3695 // Check cop1 unusable
3697 signed char rs=get_reg(i_regs->regmap,CSREG);
3699 emit_testimm(rs,0x20000000);
3702 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3705 if (opcode[i]==0x39) { // SWC1 (get float address)
3706 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],tl);
3708 if (opcode[i]==0x3D) { // SDC1 (get double address)
3709 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],tl);
3711 // Generate address + offset
3714 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3718 map=get_reg(i_regs->regmap,TLREG);
3721 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3722 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3724 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3725 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3728 if (opcode[i]==0x39) { // SWC1 (read float)
3729 emit_readword_indexed(0,tl,tl);
3731 if (opcode[i]==0x3D) { // SDC1 (read double)
3732 emit_readword_indexed(4,tl,th);
3733 emit_readword_indexed(0,tl,tl);
3735 if (opcode[i]==0x31) { // LWC1 (get target address)
3736 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],temp);
3738 if (opcode[i]==0x35) { // LDC1 (get target address)
3739 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],temp);
3746 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3748 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3750 #ifdef DESTRUCTIVE_SHIFT
3751 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3752 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3756 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3757 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3759 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3760 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3763 if (opcode[i]==0x31) { // LWC1
3764 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3765 //gen_tlb_addr_r(ar,map);
3766 //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3767 #ifdef HOST_IMM_ADDR32
3768 if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3771 emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3774 if (opcode[i]==0x35) { // LDC1
3776 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3777 //gen_tlb_addr_r(ar,map);
3778 //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3779 //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3780 #ifdef HOST_IMM_ADDR32
3781 if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3784 emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3787 if (opcode[i]==0x39) { // SWC1
3788 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3789 emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3792 if (opcode[i]==0x3D) { // SDC1
3794 //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3795 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3796 emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3799 if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3800 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3801 #ifndef DESTRUCTIVE_SHIFT
3802 temp=offset||c||s<0?ar:s;
3804 #if defined(HOST_IMM8)
3805 int ir=get_reg(i_regs->regmap,INVCP);
3807 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3809 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3811 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3812 emit_callne(invalidate_addr_reg[temp]);
3816 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3820 if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3821 if (opcode[i]==0x31) { // LWC1 (write float)
3822 emit_writeword_indexed(tl,0,temp);
3824 if (opcode[i]==0x35) { // LDC1 (write double)
3825 emit_writeword_indexed(th,4,temp);
3826 emit_writeword_indexed(tl,0,temp);
3828 //if(opcode[i]==0x39)
3829 /*if(opcode[i]==0x39||opcode[i]==0x31)
3832 emit_readword((int)&last_count,ECX);
3833 if(get_reg(i_regs->regmap,CCREG)<0)
3834 emit_loadreg(CCREG,HOST_CCREG);
3835 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3836 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3837 emit_writeword(HOST_CCREG,(int)&Count);
3838 emit_call((int)memdebug);
3842 cop1_unusable(i, i_regs);
3846 void c2ls_assemble(int i,struct regstat *i_regs)
3851 int memtarget=0,c=0;
3852 int jaddr2=0,jaddr3,type;
3853 int agr=AGEN1+(i&1);
3854 int fastio_reg_override=0;
3856 u_int copr=(source[i]>>16)&0x1f;
3857 s=get_reg(i_regs->regmap,rs1[i]);
3858 tl=get_reg(i_regs->regmap,FTEMP);
3864 for(hr=0;hr<HOST_REGS;hr++) {
3865 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3867 if(i_regs->regmap[HOST_CCREG]==CCREG)
3868 reglist&=~(1<<HOST_CCREG);
3871 if (opcode[i]==0x3a) { // SWC2
3872 ar=get_reg(i_regs->regmap,agr);
3873 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3878 if(s>=0) c=(i_regs->wasconst>>s)&1;
3879 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3880 if (!offset&&!c&&s>=0) ar=s;
3883 if (opcode[i]==0x3a) { // SWC2
3884 cop2_get_dreg(copr,tl,HOST_TEMPREG);
3892 emit_jmp(0); // inline_readstub/inline_writestub?
3896 jaddr2=emit_fastpath_cmp_jump(i,ar,&fastio_reg_override);
3898 else if(ram_offset&&memtarget) {
3899 emit_addimm(ar,ram_offset,HOST_TEMPREG);
3900 fastio_reg_override=HOST_TEMPREG;
3902 if (opcode[i]==0x32) { // LWC2
3903 #ifdef HOST_IMM_ADDR32
3904 if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3908 if(fastio_reg_override) a=fastio_reg_override;
3909 emit_readword_indexed(0,a,tl);
3911 if (opcode[i]==0x3a) { // SWC2
3912 #ifdef DESTRUCTIVE_SHIFT
3913 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3916 if(fastio_reg_override) a=fastio_reg_override;
3917 emit_writeword_indexed(tl,0,a);
3921 add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3922 if(opcode[i]==0x3a) // SWC2
3923 if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3924 #if defined(HOST_IMM8)
3925 int ir=get_reg(i_regs->regmap,INVCP);
3927 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3929 emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3931 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3932 emit_callne(invalidate_addr_reg[ar]);
3936 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3939 if (opcode[i]==0x32) { // LWC2
3940 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3944 #ifndef multdiv_assemble
3945 void multdiv_assemble(int i,struct regstat *i_regs)
3947 printf("Need multdiv_assemble for this architecture.\n");
3952 void mov_assemble(int i,struct regstat *i_regs)
3954 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3955 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3957 signed char sh,sl,th,tl;
3958 th=get_reg(i_regs->regmap,rt1[i]|64);
3959 tl=get_reg(i_regs->regmap,rt1[i]);
3962 sh=get_reg(i_regs->regmap,rs1[i]|64);
3963 sl=get_reg(i_regs->regmap,rs1[i]);
3964 if(sl>=0) emit_mov(sl,tl);
3965 else emit_loadreg(rs1[i],tl);
3967 if(sh>=0) emit_mov(sh,th);
3968 else emit_loadreg(rs1[i]|64,th);
3974 #ifndef fconv_assemble
3975 void fconv_assemble(int i,struct regstat *i_regs)
3977 printf("Need fconv_assemble for this architecture.\n");
3983 void float_assemble(int i,struct regstat *i_regs)
3985 printf("Need float_assemble for this architecture.\n");
3990 void syscall_assemble(int i,struct regstat *i_regs)
3992 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3993 assert(ccreg==HOST_CCREG);
3994 assert(!is_delayslot);
3995 emit_movimm(start+i*4,EAX); // Get PC
3996 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3997 emit_jmp((int)jump_syscall_hle); // XXX
4000 void hlecall_assemble(int i,struct regstat *i_regs)
4002 signed char ccreg=get_reg(i_regs->regmap,CCREG);
4003 assert(ccreg==HOST_CCREG);
4004 assert(!is_delayslot);
4005 emit_movimm(start+i*4+4,0); // Get PC
4006 emit_movimm((int)psxHLEt[source[i]&7],1);
4007 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX
4008 emit_jmp((int)jump_hlecall);
4011 void intcall_assemble(int i,struct regstat *i_regs)
4013 signed char ccreg=get_reg(i_regs->regmap,CCREG);
4014 assert(ccreg==HOST_CCREG);
4015 assert(!is_delayslot);
4016 emit_movimm(start+i*4,0); // Get PC
4017 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
4018 emit_jmp((int)jump_intcall);
4021 void ds_assemble(int i,struct regstat *i_regs)
4023 speculate_register_values(i);
4027 alu_assemble(i,i_regs);break;
4029 imm16_assemble(i,i_regs);break;
4031 shift_assemble(i,i_regs);break;
4033 shiftimm_assemble(i,i_regs);break;
4035 load_assemble(i,i_regs);break;
4037 loadlr_assemble(i,i_regs);break;
4039 store_assemble(i,i_regs);break;
4041 storelr_assemble(i,i_regs);break;
4043 cop0_assemble(i,i_regs);break;
4045 cop1_assemble(i,i_regs);break;
4047 c1ls_assemble(i,i_regs);break;
4049 cop2_assemble(i,i_regs);break;
4051 c2ls_assemble(i,i_regs);break;
4053 c2op_assemble(i,i_regs);break;
4055 fconv_assemble(i,i_regs);break;
4057 float_assemble(i,i_regs);break;
4059 fcomp_assemble(i,i_regs);break;
4061 multdiv_assemble(i,i_regs);break;
4063 mov_assemble(i,i_regs);break;
4073 printf("Jump in the delay slot. This is probably a bug.\n");
4078 // Is the branch target a valid internal jump?
4079 int internal_branch(uint64_t i_is32,int addr)
4081 if(addr&1) return 0; // Indirect (register) jump
4082 if(addr>=start && addr<start+slen*4-4)
4084 int t=(addr-start)>>2;
4085 // Delay slots are not valid branch targets
4086 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4087 // 64 -> 32 bit transition requires a recompile
4088 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
4090 if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
4091 else printf("optimizable: yes\n");
4093 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4095 if(requires_32bit[t]&~i_is32) return 0;
4103 #ifndef wb_invalidate
4104 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
4105 uint64_t u,uint64_t uu)
4108 for(hr=0;hr<HOST_REGS;hr++) {
4109 if(hr!=EXCLUDE_REG) {
4110 if(pre[hr]!=entry[hr]) {
4113 if(get_reg(entry,pre[hr])<0) {
4115 if(!((u>>pre[hr])&1)) {
4116 emit_storereg(pre[hr],hr);
4117 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4118 emit_sarimm(hr,31,hr);
4119 emit_storereg(pre[hr]|64,hr);
4123 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
4124 emit_storereg(pre[hr],hr);
4133 // Move from one register to another (no writeback)
4134 for(hr=0;hr<HOST_REGS;hr++) {
4135 if(hr!=EXCLUDE_REG) {
4136 if(pre[hr]!=entry[hr]) {
4137 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4139 if((nr=get_reg(entry,pre[hr]))>=0) {
4149 // Load the specified registers
4150 // This only loads the registers given as arguments because
4151 // we don't want to load things that will be overwritten
4152 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
4156 for(hr=0;hr<HOST_REGS;hr++) {
4157 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4158 if(entry[hr]!=regmap[hr]) {
4159 if(regmap[hr]==rs1||regmap[hr]==rs2)
4166 emit_loadreg(regmap[hr],hr);
4173 for(hr=0;hr<HOST_REGS;hr++) {
4174 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4175 if(entry[hr]!=regmap[hr]) {
4176 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
4178 assert(regmap[hr]!=64);
4179 if((is32>>(regmap[hr]&63))&1) {
4180 int lr=get_reg(regmap,regmap[hr]-64);
4182 emit_sarimm(lr,31,hr);
4184 emit_loadreg(regmap[hr],hr);
4188 emit_loadreg(regmap[hr],hr);
4196 // Load registers prior to the start of a loop
4197 // so that they are not loaded within the loop
4198 static void loop_preload(signed char pre[],signed char entry[])
4201 for(hr=0;hr<HOST_REGS;hr++) {
4202 if(hr!=EXCLUDE_REG) {
4203 if(pre[hr]!=entry[hr]) {
4205 if(get_reg(pre,entry[hr])<0) {
4206 assem_debug("loop preload:\n");
4207 //printf("loop preload: %d\n",hr);
4211 else if(entry[hr]<TEMPREG)
4213 emit_loadreg(entry[hr],hr);
4215 else if(entry[hr]-64<TEMPREG)
4217 emit_loadreg(entry[hr],hr);
4226 // Generate address for load/store instruction
4227 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4228 void address_generation(int i,struct regstat *i_regs,signed char entry[])
4230 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
4232 int agr=AGEN1+(i&1);
4233 int mgr=MGEN1+(i&1);
4234 if(itype[i]==LOAD) {
4235 ra=get_reg(i_regs->regmap,rt1[i]);
4236 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4239 if(itype[i]==LOADLR) {
4240 ra=get_reg(i_regs->regmap,FTEMP);
4242 if(itype[i]==STORE||itype[i]==STORELR) {
4243 ra=get_reg(i_regs->regmap,agr);
4244 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4246 if(itype[i]==C1LS||itype[i]==C2LS) {
4247 if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4248 ra=get_reg(i_regs->regmap,FTEMP);
4249 else { // SWC1/SDC1/SWC2/SDC2
4250 ra=get_reg(i_regs->regmap,agr);
4251 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4254 int rs=get_reg(i_regs->regmap,rs1[i]);
4255 int rm=get_reg(i_regs->regmap,TLREG);
4258 int c=(i_regs->wasconst>>rs)&1;
4260 // Using r0 as a base address
4262 if(!entry||entry[rm]!=mgr) {
4263 generate_map_const(offset,rm);
4264 } // else did it in the previous cycle
4266 if(!entry||entry[ra]!=agr) {
4267 if (opcode[i]==0x22||opcode[i]==0x26) {
4268 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4269 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4270 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4272 emit_movimm(offset,ra);
4274 } // else did it in the previous cycle
4277 if(!entry||entry[ra]!=rs1[i])
4278 emit_loadreg(rs1[i],ra);
4279 //if(!entry||entry[ra]!=rs1[i])
4280 // printf("poor load scheduling!\n");
4285 if(!entry||entry[rm]!=mgr) {
4286 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
4287 // Stores to memory go thru the mapper to detect self-modifying
4288 // code, loads don't.
4289 if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4290 (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
4291 generate_map_const(constmap[i][rs]+offset,rm);
4293 if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4294 generate_map_const(constmap[i][rs]+offset,rm);
4299 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4300 if(!entry||entry[ra]!=agr) {
4301 if (opcode[i]==0x22||opcode[i]==0x26) {
4302 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4303 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4304 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4306 #ifdef HOST_IMM_ADDR32
4307 if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4308 (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4310 emit_movimm(constmap[i][rs]+offset,ra);
4311 regs[i].loadedconst|=1<<ra;
4313 } // else did it in the previous cycle
4314 } // else load_consts already did it
4316 if(offset&&!c&&rs1[i]) {
4318 emit_addimm(rs,offset,ra);
4320 emit_addimm(ra,offset,ra);
4325 // Preload constants for next instruction
4326 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4328 #if !defined(HOST_IMM_ADDR32) && !defined(DISABLE_TLB)
4330 agr=MGEN1+((i+1)&1);
4331 ra=get_reg(i_regs->regmap,agr);
4333 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4334 int offset=imm[i+1];
4335 int c=(regs[i+1].wasconst>>rs)&1;
4337 if(itype[i+1]==STORE||itype[i+1]==STORELR
4338 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4339 // Stores to memory go thru the mapper to detect self-modifying
4340 // code, loads don't.
4341 if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4342 (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
4343 generate_map_const(constmap[i+1][rs]+offset,ra);
4345 if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4346 generate_map_const(constmap[i+1][rs]+offset,ra);
4349 /*else if(rs1[i]==0) {
4350 generate_map_const(offset,ra);
4355 agr=AGEN1+((i+1)&1);
4356 ra=get_reg(i_regs->regmap,agr);
4358 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4359 int offset=imm[i+1];
4360 int c=(regs[i+1].wasconst>>rs)&1;
4361 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4362 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4363 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4364 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4365 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4367 #ifdef HOST_IMM_ADDR32
4368 if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4369 (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4371 emit_movimm(constmap[i+1][rs]+offset,ra);
4372 regs[i+1].loadedconst|=1<<ra;
4375 else if(rs1[i+1]==0) {
4376 // Using r0 as a base address
4377 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4378 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4379 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4380 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4382 emit_movimm(offset,ra);
4389 int get_final_value(int hr, int i, int *value)
4391 int reg=regs[i].regmap[hr];
4393 if(regs[i+1].regmap[hr]!=reg) break;
4394 if(!((regs[i+1].isconst>>hr)&1)) break;
4399 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4400 *value=constmap[i][hr];
4404 if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4405 // Load in delay slot, out-of-order execution
4406 if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4408 #ifdef HOST_IMM_ADDR32
4409 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4411 // Precompute load address
4412 *value=constmap[i][hr]+imm[i+2];
4416 if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4418 #ifdef HOST_IMM_ADDR32
4419 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4421 // Precompute load address
4422 *value=constmap[i][hr]+imm[i+1];
4423 //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4428 *value=constmap[i][hr];
4429 //printf("c=%x\n",(int)constmap[i][hr]);
4430 if(i==slen-1) return 1;
4432 return !((unneeded_reg[i+1]>>reg)&1);
4434 return !((unneeded_reg_upper[i+1]>>reg)&1);
4438 // Load registers with known constants
4439 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4442 // propagate loaded constant flags
4444 regs[i].loadedconst=0;
4446 for(hr=0;hr<HOST_REGS;hr++) {
4447 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
4448 &®map[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
4450 regs[i].loadedconst|=1<<hr;
4455 for(hr=0;hr<HOST_REGS;hr++) {
4456 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4457 //if(entry[hr]!=regmap[hr]) {
4458 if(!((regs[i].loadedconst>>hr)&1)) {
4459 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4460 int value,similar=0;
4461 if(get_final_value(hr,i,&value)) {
4462 // see if some other register has similar value
4463 for(hr2=0;hr2<HOST_REGS;hr2++) {
4464 if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4465 if(is_similar_value(value,constmap[i][hr2])) {
4473 if(get_final_value(hr2,i,&value2)) // is this needed?
4474 emit_movimm_from(value2,hr2,value,hr);
4476 emit_movimm(value,hr);
4482 emit_movimm(value,hr);
4485 regs[i].loadedconst|=1<<hr;
4491 for(hr=0;hr<HOST_REGS;hr++) {
4492 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4493 //if(entry[hr]!=regmap[hr]) {
4494 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4495 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4496 if((is32>>(regmap[hr]&63))&1) {
4497 int lr=get_reg(regmap,regmap[hr]-64);
4499 emit_sarimm(lr,31,hr);
4504 if(get_final_value(hr,i,&value)) {
4509 emit_movimm(value,hr);
4518 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4522 for(hr=0;hr<HOST_REGS;hr++) {
4523 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4524 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4525 int value=constmap[i][hr];
4530 emit_movimm(value,hr);
4536 for(hr=0;hr<HOST_REGS;hr++) {
4537 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4538 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4539 if((is32>>(regmap[hr]&63))&1) {
4540 int lr=get_reg(regmap,regmap[hr]-64);
4542 emit_sarimm(lr,31,hr);
4546 int value=constmap[i][hr];
4551 emit_movimm(value,hr);
4559 // Write out all dirty registers (except cycle count)
4560 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4563 for(hr=0;hr<HOST_REGS;hr++) {
4564 if(hr!=EXCLUDE_REG) {
4565 if(i_regmap[hr]>0) {
4566 if(i_regmap[hr]!=CCREG) {
4567 if((i_dirty>>hr)&1) {
4568 if(i_regmap[hr]<64) {
4569 emit_storereg(i_regmap[hr],hr);
4571 if( ((i_is32>>i_regmap[hr])&1) ) {
4572 #ifdef DESTRUCTIVE_WRITEBACK
4573 emit_sarimm(hr,31,hr);
4574 emit_storereg(i_regmap[hr]|64,hr);
4576 emit_sarimm(hr,31,HOST_TEMPREG);
4577 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4582 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4583 emit_storereg(i_regmap[hr],hr);
4592 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4593 // This writes the registers not written by store_regs_bt
4594 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4597 int t=(addr-start)>>2;
4598 for(hr=0;hr<HOST_REGS;hr++) {
4599 if(hr!=EXCLUDE_REG) {
4600 if(i_regmap[hr]>0) {
4601 if(i_regmap[hr]!=CCREG) {
4602 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4603 if((i_dirty>>hr)&1) {
4604 if(i_regmap[hr]<64) {
4605 emit_storereg(i_regmap[hr],hr);
4607 if( ((i_is32>>i_regmap[hr])&1) ) {
4608 #ifdef DESTRUCTIVE_WRITEBACK
4609 emit_sarimm(hr,31,hr);
4610 emit_storereg(i_regmap[hr]|64,hr);
4612 emit_sarimm(hr,31,HOST_TEMPREG);
4613 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4618 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4619 emit_storereg(i_regmap[hr],hr);
4630 // Load all registers (except cycle count)
4631 void load_all_regs(signed char i_regmap[])
4634 for(hr=0;hr<HOST_REGS;hr++) {
4635 if(hr!=EXCLUDE_REG) {
4636 if(i_regmap[hr]==0) {
4640 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4642 emit_loadreg(i_regmap[hr],hr);
4648 // Load all current registers also needed by next instruction
4649 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4652 for(hr=0;hr<HOST_REGS;hr++) {
4653 if(hr!=EXCLUDE_REG) {
4654 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4655 if(i_regmap[hr]==0) {
4659 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4661 emit_loadreg(i_regmap[hr],hr);
4668 // Load all regs, storing cycle count if necessary
4669 void load_regs_entry(int t)
4672 if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
4673 else if(ccadj[t]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[t]),HOST_CCREG);
4674 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4675 emit_storereg(CCREG,HOST_CCREG);
4678 for(hr=0;hr<HOST_REGS;hr++) {
4679 if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4680 if(regs[t].regmap_entry[hr]==0) {
4683 else if(regs[t].regmap_entry[hr]!=CCREG)
4685 emit_loadreg(regs[t].regmap_entry[hr],hr);
4690 for(hr=0;hr<HOST_REGS;hr++) {
4691 if(regs[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) {
4692 assert(regs[t].regmap_entry[hr]!=64);
4693 if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4694 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4696 emit_loadreg(regs[t].regmap_entry[hr],hr);
4700 emit_sarimm(lr,31,hr);
4705 emit_loadreg(regs[t].regmap_entry[hr],hr);
4711 // Store dirty registers prior to branch
4712 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4714 if(internal_branch(i_is32,addr))
4716 int t=(addr-start)>>2;
4718 for(hr=0;hr<HOST_REGS;hr++) {
4719 if(hr!=EXCLUDE_REG) {
4720 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4721 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4722 if((i_dirty>>hr)&1) {
4723 if(i_regmap[hr]<64) {
4724 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4725 emit_storereg(i_regmap[hr],hr);
4726 if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4727 #ifdef DESTRUCTIVE_WRITEBACK
4728 emit_sarimm(hr,31,hr);
4729 emit_storereg(i_regmap[hr]|64,hr);
4731 emit_sarimm(hr,31,HOST_TEMPREG);
4732 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4737 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4738 emit_storereg(i_regmap[hr],hr);
4749 // Branch out of this block, write out all dirty regs
4750 wb_dirtys(i_regmap,i_is32,i_dirty);
4754 // Load all needed registers for branch target
4755 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4757 //if(addr>=start && addr<(start+slen*4))
4758 if(internal_branch(i_is32,addr))
4760 int t=(addr-start)>>2;
4762 // Store the cycle count before loading something else
4763 if(i_regmap[HOST_CCREG]!=CCREG) {
4764 assert(i_regmap[HOST_CCREG]==-1);
4766 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4767 emit_storereg(CCREG,HOST_CCREG);
4770 for(hr=0;hr<HOST_REGS;hr++) {
4771 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4772 #ifdef DESTRUCTIVE_WRITEBACK
4773 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4775 if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4777 if(regs[t].regmap_entry[hr]==0) {
4780 else if(regs[t].regmap_entry[hr]!=CCREG)
4782 emit_loadreg(regs[t].regmap_entry[hr],hr);
4788 for(hr=0;hr<HOST_REGS;hr++) {
4789 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) {
4790 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4791 assert(regs[t].regmap_entry[hr]!=64);
4792 if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4793 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4795 emit_loadreg(regs[t].regmap_entry[hr],hr);
4799 emit_sarimm(lr,31,hr);
4804 emit_loadreg(regs[t].regmap_entry[hr],hr);
4807 else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4808 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4810 emit_sarimm(lr,31,hr);
4817 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4819 if(addr>=start && addr<start+slen*4-4)
4821 int t=(addr-start)>>2;
4823 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4824 for(hr=0;hr<HOST_REGS;hr++)
4828 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4830 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4837 if(i_regmap[hr]<TEMPREG)
4839 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4842 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4844 if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4849 else // Same register but is it 32-bit or dirty?
4852 if(!((regs[t].dirty>>hr)&1))
4856 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4858 //printf("%x: dirty no match\n",addr);
4863 if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4865 //printf("%x: is32 no match\n",addr);
4871 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4873 if(requires_32bit[t]&~i_is32) return 0;
4875 // Delay slots are not valid branch targets
4876 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4877 // Delay slots require additional processing, so do not match
4878 if(is_ds[t]) return 0;
4883 for(hr=0;hr<HOST_REGS;hr++)
4889 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4903 // Used when a branch jumps into the delay slot of another branch
4904 void ds_assemble_entry(int i)
4906 int t=(ba[i]-start)>>2;
4907 if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4908 assem_debug("Assemble delay slot at %x\n",ba[i]);
4909 assem_debug("<->\n");
4910 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG)
4911 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4912 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4913 address_generation(t,®s[t],regs[t].regmap_entry);
4914 if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4915 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4920 alu_assemble(t,®s[t]);break;
4922 imm16_assemble(t,®s[t]);break;
4924 shift_assemble(t,®s[t]);break;
4926 shiftimm_assemble(t,®s[t]);break;
4928 load_assemble(t,®s[t]);break;
4930 loadlr_assemble(t,®s[t]);break;
4932 store_assemble(t,®s[t]);break;
4934 storelr_assemble(t,®s[t]);break;
4936 cop0_assemble(t,®s[t]);break;
4938 cop1_assemble(t,®s[t]);break;
4940 c1ls_assemble(t,®s[t]);break;
4942 cop2_assemble(t,®s[t]);break;
4944 c2ls_assemble(t,®s[t]);break;
4946 c2op_assemble(t,®s[t]);break;
4948 fconv_assemble(t,®s[t]);break;
4950 float_assemble(t,®s[t]);break;
4952 fcomp_assemble(t,®s[t]);break;
4954 multdiv_assemble(t,®s[t]);break;
4956 mov_assemble(t,®s[t]);break;
4966 printf("Jump in the delay slot. This is probably a bug.\n");
4968 store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4969 load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4970 if(internal_branch(regs[t].is32,ba[i]+4))
4971 assem_debug("branch: internal\n");
4973 assem_debug("branch: external\n");
4974 assert(internal_branch(regs[t].is32,ba[i]+4));
4975 add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4979 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4988 //if(ba[i]>=start && ba[i]<(start+slen*4))
4989 if(internal_branch(branch_regs[i].is32,ba[i]))
4991 int t=(ba[i]-start)>>2;
4992 if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
5000 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
5002 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
5004 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
5005 emit_andimm(HOST_CCREG,3,HOST_CCREG);
5009 else if(*adj==0||invert) {
5010 emit_addimm_and_set_flags(CLOCK_ADJUST(count+2),HOST_CCREG);
5016 emit_cmpimm(HOST_CCREG,-CLOCK_ADJUST(count+2));
5020 add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
5023 void do_ccstub(int n)
5026 assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
5027 set_jump_target(stubs[n][1],(int)out);
5029 if(stubs[n][6]==NULLDS) {
5030 // Delay slot instruction is nullified ("likely" branch)
5031 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
5033 else if(stubs[n][6]!=TAKEN) {
5034 wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
5037 if(internal_branch(branch_regs[i].is32,ba[i]))
5038 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5042 // Save PC as return address
5043 emit_movimm(stubs[n][5],EAX);
5044 emit_writeword(EAX,(int)&pcaddr);
5048 // Return address depends on which way the branch goes
5049 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
5051 int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5052 int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5053 int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5054 int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5064 if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
5068 #ifdef DESTRUCTIVE_WRITEBACK
5070 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
5071 emit_loadreg(rs1[i],s1l);
5074 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
5075 emit_loadreg(rs2[i],s1l);
5078 if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
5079 emit_loadreg(rs2[i],s2l);
5082 int addr=-1,alt=-1,ntaddr=-1;
5085 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5086 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5087 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5095 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5096 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5097 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5103 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
5107 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5108 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5109 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5115 assert(hr<HOST_REGS);
5117 if((opcode[i]&0x2f)==4) // BEQ
5119 #ifdef HAVE_CMOV_IMM
5121 if(s2l>=0) emit_cmp(s1l,s2l);
5122 else emit_test(s1l,s1l);
5123 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5128 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5130 if(s2h>=0) emit_cmp(s1h,s2h);
5131 else emit_test(s1h,s1h);
5132 emit_cmovne_reg(alt,addr);
5134 if(s2l>=0) emit_cmp(s1l,s2l);
5135 else emit_test(s1l,s1l);
5136 emit_cmovne_reg(alt,addr);
5139 if((opcode[i]&0x2f)==5) // BNE
5141 #ifdef HAVE_CMOV_IMM
5143 if(s2l>=0) emit_cmp(s1l,s2l);
5144 else emit_test(s1l,s1l);
5145 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5150 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5152 if(s2h>=0) emit_cmp(s1h,s2h);
5153 else emit_test(s1h,s1h);
5154 emit_cmovne_reg(alt,addr);
5156 if(s2l>=0) emit_cmp(s1l,s2l);
5157 else emit_test(s1l,s1l);
5158 emit_cmovne_reg(alt,addr);
5161 if((opcode[i]&0x2f)==6) // BLEZ
5163 //emit_movimm(ba[i],alt);
5164 //emit_movimm(start+i*4+8,addr);
5165 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5167 if(s1h>=0) emit_mov(addr,ntaddr);
5168 emit_cmovl_reg(alt,addr);
5171 emit_cmovne_reg(ntaddr,addr);
5172 emit_cmovs_reg(alt,addr);
5175 if((opcode[i]&0x2f)==7) // BGTZ
5177 //emit_movimm(ba[i],addr);
5178 //emit_movimm(start+i*4+8,ntaddr);
5179 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5181 if(s1h>=0) emit_mov(addr,alt);
5182 emit_cmovl_reg(ntaddr,addr);
5185 emit_cmovne_reg(alt,addr);
5186 emit_cmovs_reg(ntaddr,addr);
5189 if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
5191 //emit_movimm(ba[i],alt);
5192 //emit_movimm(start+i*4+8,addr);
5193 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5194 if(s1h>=0) emit_test(s1h,s1h);
5195 else emit_test(s1l,s1l);
5196 emit_cmovs_reg(alt,addr);
5198 if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
5200 //emit_movimm(ba[i],addr);
5201 //emit_movimm(start+i*4+8,alt);
5202 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5203 if(s1h>=0) emit_test(s1h,s1h);
5204 else emit_test(s1l,s1l);
5205 emit_cmovs_reg(alt,addr);
5207 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
5208 if(source[i]&0x10000) // BC1T
5210 //emit_movimm(ba[i],alt);
5211 //emit_movimm(start+i*4+8,addr);
5212 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5213 emit_testimm(s1l,0x800000);
5214 emit_cmovne_reg(alt,addr);
5218 //emit_movimm(ba[i],addr);
5219 //emit_movimm(start+i*4+8,alt);
5220 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5221 emit_testimm(s1l,0x800000);
5222 emit_cmovne_reg(alt,addr);
5225 emit_writeword(addr,(int)&pcaddr);
5230 int r=get_reg(branch_regs[i].regmap,rs1[i]);
5231 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5232 r=get_reg(branch_regs[i].regmap,RTEMP);
5234 emit_writeword(r,(int)&pcaddr);
5236 else {printf("Unknown branch type in do_ccstub\n");exit(1);}
5238 // Update cycle count
5239 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5240 if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
5241 emit_call((int)cc_interrupt);
5242 if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
5243 if(stubs[n][6]==TAKEN) {
5244 if(internal_branch(branch_regs[i].is32,ba[i]))
5245 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5246 else if(itype[i]==RJUMP) {
5247 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5248 emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5250 emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5252 }else if(stubs[n][6]==NOTTAKEN) {
5253 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5254 else load_all_regs(branch_regs[i].regmap);
5255 }else if(stubs[n][6]==NULLDS) {
5256 // Delay slot instruction is nullified ("likely" branch)
5257 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5258 else load_all_regs(regs[i].regmap);
5260 load_all_regs(branch_regs[i].regmap);
5262 emit_jmp(stubs[n][2]); // return address
5264 /* This works but uses a lot of memory...
5265 emit_readword((int)&last_count,ECX);
5266 emit_add(HOST_CCREG,ECX,EAX);
5267 emit_writeword(EAX,(int)&Count);
5268 emit_call((int)gen_interupt);
5269 emit_readword((int)&Count,HOST_CCREG);
5270 emit_readword((int)&next_interupt,EAX);
5271 emit_readword((int)&pending_exception,EBX);
5272 emit_writeword(EAX,(int)&last_count);
5273 emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5275 int jne_instr=(int)out;
5277 if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5278 load_all_regs(branch_regs[i].regmap);
5279 emit_jmp(stubs[n][2]); // return address
5280 set_jump_target(jne_instr,(int)out);
5281 emit_readword((int)&pcaddr,EAX);
5282 // Call get_addr_ht instead of doing the hash table here.
5283 // This code is executed infrequently and takes up a lot of space
5284 // so smaller is better.
5285 emit_storereg(CCREG,HOST_CCREG);
5287 emit_call((int)get_addr_ht);
5288 emit_loadreg(CCREG,HOST_CCREG);
5289 emit_addimm(ESP,4,ESP);
5293 add_to_linker(int addr,int target,int ext)
5295 link_addr[linkcount][0]=addr;
5296 link_addr[linkcount][1]=target;
5297 link_addr[linkcount][2]=ext;
5301 static void ujump_assemble_write_ra(int i)
5304 unsigned int return_address;
5305 rt=get_reg(branch_regs[i].regmap,31);
5306 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5308 return_address=start+i*4+8;
5311 if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
5312 int temp=-1; // note: must be ds-safe
5316 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5317 else emit_movimm(return_address,rt);
5325 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5328 emit_movimm(return_address,rt); // PC into link register
5330 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5336 void ujump_assemble(int i,struct regstat *i_regs)
5338 signed char *i_regmap=i_regs->regmap;
5340 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5341 address_generation(i+1,i_regs,regs[i].regmap_entry);
5343 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5344 if(rt1[i]==31&&temp>=0)
5346 int return_address=start+i*4+8;
5347 if(get_reg(branch_regs[i].regmap,31)>0)
5348 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5351 if(rt1[i]==31&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5352 ujump_assemble_write_ra(i); // writeback ra for DS
5355 ds_assemble(i+1,i_regs);
5356 uint64_t bc_unneeded=branch_regs[i].u;
5357 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5358 bc_unneeded|=1|(1LL<<rt1[i]);
5359 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5360 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5361 bc_unneeded,bc_unneeded_upper);
5362 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5363 if(!ra_done&&rt1[i]==31)
5364 ujump_assemble_write_ra(i);
5366 cc=get_reg(branch_regs[i].regmap,CCREG);
5367 assert(cc==HOST_CCREG);
5368 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5370 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5372 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5373 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5374 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5375 if(internal_branch(branch_regs[i].is32,ba[i]))
5376 assem_debug("branch: internal\n");
5378 assem_debug("branch: external\n");
5379 if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5380 ds_assemble_entry(i);
5383 add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5388 static void rjump_assemble_write_ra(int i)
5390 int rt,return_address;
5391 assert(rt1[i+1]!=rt1[i]);
5392 assert(rt2[i+1]!=rt1[i]);
5393 rt=get_reg(branch_regs[i].regmap,rt1[i]);
5394 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5396 return_address=start+i*4+8;
5400 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5403 emit_movimm(return_address,rt); // PC into link register
5405 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5409 void rjump_assemble(int i,struct regstat *i_regs)
5411 signed char *i_regmap=i_regs->regmap;
5415 rs=get_reg(branch_regs[i].regmap,rs1[i]);
5417 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5418 // Delay slot abuse, make a copy of the branch address register
5419 temp=get_reg(branch_regs[i].regmap,RTEMP);
5421 assert(regs[i].regmap[temp]==RTEMP);
5425 address_generation(i+1,i_regs,regs[i].regmap_entry);
5429 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5430 int return_address=start+i*4+8;
5431 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5437 int rh=get_reg(regs[i].regmap,RHASH);
5438 if(rh>=0) do_preload_rhash(rh);
5441 if(rt1[i]!=0&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5442 rjump_assemble_write_ra(i);
5445 ds_assemble(i+1,i_regs);
5446 uint64_t bc_unneeded=branch_regs[i].u;
5447 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5448 bc_unneeded|=1|(1LL<<rt1[i]);
5449 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5450 bc_unneeded&=~(1LL<<rs1[i]);
5451 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5452 bc_unneeded,bc_unneeded_upper);
5453 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5454 if(!ra_done&&rt1[i]!=0)
5455 rjump_assemble_write_ra(i);
5456 cc=get_reg(branch_regs[i].regmap,CCREG);
5457 assert(cc==HOST_CCREG);
5459 int rh=get_reg(branch_regs[i].regmap,RHASH);
5460 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5462 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5463 do_preload_rhtbl(ht);
5467 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5468 #ifdef DESTRUCTIVE_WRITEBACK
5469 if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5470 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5471 emit_loadreg(rs1[i],rs);
5476 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5480 do_miniht_load(ht,rh);
5483 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5484 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5486 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5487 add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5489 if(itype[i+1]==COP0&&(source[i+1]&0x3f)==0x10)
5490 // special case for RFE
5495 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5498 do_miniht_jump(rs,rh,ht);
5503 //if(rs!=EAX) emit_mov(rs,EAX);
5504 //emit_jmp((int)jump_vaddr_eax);
5505 emit_jmp(jump_vaddr_reg[rs]);
5510 emit_shrimm(rs,16,rs);
5511 emit_xor(temp,rs,rs);
5512 emit_movzwl_reg(rs,rs);
5513 emit_shlimm(rs,4,rs);
5514 emit_cmpmem_indexed((int)hash_table,rs,temp);
5515 emit_jne((int)out+14);
5516 emit_readword_indexed((int)hash_table+4,rs,rs);
5518 emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5519 emit_addimm_no_flags(8,rs);
5520 emit_jeq((int)out-17);
5521 // No hit on hash table, call compiler
5524 #ifdef DEBUG_CYCLE_COUNT
5525 emit_readword((int)&last_count,ECX);
5526 emit_add(HOST_CCREG,ECX,HOST_CCREG);
5527 emit_readword((int)&next_interupt,ECX);
5528 emit_writeword(HOST_CCREG,(int)&Count);
5529 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5530 emit_writeword(ECX,(int)&last_count);
5533 emit_storereg(CCREG,HOST_CCREG);
5534 emit_call((int)get_addr);
5535 emit_loadreg(CCREG,HOST_CCREG);
5536 emit_addimm(ESP,4,ESP);
5538 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5539 if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5543 void cjump_assemble(int i,struct regstat *i_regs)
5545 signed char *i_regmap=i_regs->regmap;
5548 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5549 assem_debug("match=%d\n",match);
5550 int s1h,s1l,s2h,s2l;
5551 int prev_cop1_usable=cop1_usable;
5552 int unconditional=0,nop=0;
5555 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5556 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5557 if(!match) invert=1;
5558 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5559 if(i>(ba[i]-start)>>2) invert=1;
5563 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5564 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5565 s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5566 s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5569 s1l=get_reg(i_regmap,rs1[i]);
5570 s1h=get_reg(i_regmap,rs1[i]|64);
5571 s2l=get_reg(i_regmap,rs2[i]);
5572 s2h=get_reg(i_regmap,rs2[i]|64);
5574 if(rs1[i]==0&&rs2[i]==0)
5576 if(opcode[i]&1) nop=1;
5577 else unconditional=1;
5578 //assert(opcode[i]!=5);
5579 //assert(opcode[i]!=7);
5580 //assert(opcode[i]!=0x15);
5581 //assert(opcode[i]!=0x17);
5587 only32=(regs[i].was32>>rs2[i])&1;
5592 only32=(regs[i].was32>>rs1[i])&1;
5595 only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5599 // Out of order execution (delay slot first)
5601 address_generation(i+1,i_regs,regs[i].regmap_entry);
5602 ds_assemble(i+1,i_regs);
5604 uint64_t bc_unneeded=branch_regs[i].u;
5605 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5606 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5607 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5609 bc_unneeded_upper|=1;
5610 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5611 bc_unneeded,bc_unneeded_upper);
5612 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5613 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5614 cc=get_reg(branch_regs[i].regmap,CCREG);
5615 assert(cc==HOST_CCREG);
5617 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5618 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5619 //assem_debug("cycle count (adj)\n");
5621 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5622 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5623 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5624 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5626 assem_debug("branch: internal\n");
5628 assem_debug("branch: external\n");
5629 if(internal&&is_ds[(ba[i]-start)>>2]) {
5630 ds_assemble_entry(i);
5633 add_to_linker((int)out,ba[i],internal);
5636 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5637 if(((u_int)out)&7) emit_addnop(0);
5642 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5645 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5648 int taken=0,nottaken=0,nottaken1=0;
5649 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5650 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5654 if(opcode[i]==4) // BEQ
5656 if(s2h>=0) emit_cmp(s1h,s2h);
5657 else emit_test(s1h,s1h);
5661 if(opcode[i]==5) // BNE
5663 if(s2h>=0) emit_cmp(s1h,s2h);
5664 else emit_test(s1h,s1h);
5665 if(invert) taken=(int)out;
5666 else add_to_linker((int)out,ba[i],internal);
5669 if(opcode[i]==6) // BLEZ
5672 if(invert) taken=(int)out;
5673 else add_to_linker((int)out,ba[i],internal);
5678 if(opcode[i]==7) // BGTZ
5683 if(invert) taken=(int)out;
5684 else add_to_linker((int)out,ba[i],internal);
5689 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5691 if(opcode[i]==4) // BEQ
5693 if(s2l>=0) emit_cmp(s1l,s2l);
5694 else emit_test(s1l,s1l);
5699 add_to_linker((int)out,ba[i],internal);
5703 if(opcode[i]==5) // BNE
5705 if(s2l>=0) emit_cmp(s1l,s2l);
5706 else emit_test(s1l,s1l);
5711 add_to_linker((int)out,ba[i],internal);
5715 if(opcode[i]==6) // BLEZ
5722 add_to_linker((int)out,ba[i],internal);
5726 if(opcode[i]==7) // BGTZ
5733 add_to_linker((int)out,ba[i],internal);
5738 if(taken) set_jump_target(taken,(int)out);
5739 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5740 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5742 emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5743 add_to_linker((int)out,ba[i],internal);
5746 add_to_linker((int)out,ba[i],internal*2);
5752 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5753 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5754 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5756 assem_debug("branch: internal\n");
5758 assem_debug("branch: external\n");
5759 if(internal&&is_ds[(ba[i]-start)>>2]) {
5760 ds_assemble_entry(i);
5763 add_to_linker((int)out,ba[i],internal);
5767 set_jump_target(nottaken,(int)out);
5770 if(nottaken1) set_jump_target(nottaken1,(int)out);
5772 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
5774 } // (!unconditional)
5778 // In-order execution (branch first)
5779 //if(likely[i]) printf("IOL\n");
5782 int taken=0,nottaken=0,nottaken1=0;
5783 if(!unconditional&&!nop) {
5787 if((opcode[i]&0x2f)==4) // BEQ
5789 if(s2h>=0) emit_cmp(s1h,s2h);
5790 else emit_test(s1h,s1h);
5794 if((opcode[i]&0x2f)==5) // BNE
5796 if(s2h>=0) emit_cmp(s1h,s2h);
5797 else emit_test(s1h,s1h);
5801 if((opcode[i]&0x2f)==6) // BLEZ
5809 if((opcode[i]&0x2f)==7) // BGTZ
5819 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5821 if((opcode[i]&0x2f)==4) // BEQ
5823 if(s2l>=0) emit_cmp(s1l,s2l);
5824 else emit_test(s1l,s1l);
5828 if((opcode[i]&0x2f)==5) // BNE
5830 if(s2l>=0) emit_cmp(s1l,s2l);
5831 else emit_test(s1l,s1l);
5835 if((opcode[i]&0x2f)==6) // BLEZ
5841 if((opcode[i]&0x2f)==7) // BGTZ
5847 } // if(!unconditional)
5849 uint64_t ds_unneeded=branch_regs[i].u;
5850 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5851 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5852 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5853 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5855 ds_unneeded_upper|=1;
5858 if(taken) set_jump_target(taken,(int)out);
5859 assem_debug("1:\n");
5860 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5861 ds_unneeded,ds_unneeded_upper);
5863 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5864 address_generation(i+1,&branch_regs[i],0);
5865 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5866 ds_assemble(i+1,&branch_regs[i]);
5867 cc=get_reg(branch_regs[i].regmap,CCREG);
5869 emit_loadreg(CCREG,cc=HOST_CCREG);
5870 // CHECK: Is the following instruction (fall thru) allocated ok?
5872 assert(cc==HOST_CCREG);
5873 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5874 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5875 assem_debug("cycle count (adj)\n");
5876 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5877 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5879 assem_debug("branch: internal\n");
5881 assem_debug("branch: external\n");
5882 if(internal&&is_ds[(ba[i]-start)>>2]) {
5883 ds_assemble_entry(i);
5886 add_to_linker((int)out,ba[i],internal);
5891 cop1_usable=prev_cop1_usable;
5892 if(!unconditional) {
5893 if(nottaken1) set_jump_target(nottaken1,(int)out);
5894 set_jump_target(nottaken,(int)out);
5895 assem_debug("2:\n");
5897 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5898 ds_unneeded,ds_unneeded_upper);
5899 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5900 address_generation(i+1,&branch_regs[i],0);
5901 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5902 ds_assemble(i+1,&branch_regs[i]);
5904 cc=get_reg(branch_regs[i].regmap,CCREG);
5905 if(cc==-1&&!likely[i]) {
5906 // Cycle count isn't in a register, temporarily load it then write it out
5907 emit_loadreg(CCREG,HOST_CCREG);
5908 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5911 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5912 emit_storereg(CCREG,HOST_CCREG);
5915 cc=get_reg(i_regmap,CCREG);
5916 assert(cc==HOST_CCREG);
5917 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5920 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5926 void sjump_assemble(int i,struct regstat *i_regs)
5928 signed char *i_regmap=i_regs->regmap;
5931 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5932 assem_debug("smatch=%d\n",match);
5934 int prev_cop1_usable=cop1_usable;
5935 int unconditional=0,nevertaken=0;
5938 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5939 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5940 if(!match) invert=1;
5941 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5942 if(i>(ba[i]-start)>>2) invert=1;
5945 //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5946 //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5949 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5950 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5953 s1l=get_reg(i_regmap,rs1[i]);
5954 s1h=get_reg(i_regmap,rs1[i]|64);
5958 if(opcode2[i]&1) unconditional=1;
5960 // These are never taken (r0 is never less than zero)
5961 //assert(opcode2[i]!=0);
5962 //assert(opcode2[i]!=2);
5963 //assert(opcode2[i]!=0x10);
5964 //assert(opcode2[i]!=0x12);
5967 only32=(regs[i].was32>>rs1[i])&1;
5971 // Out of order execution (delay slot first)
5973 address_generation(i+1,i_regs,regs[i].regmap_entry);
5974 ds_assemble(i+1,i_regs);
5976 uint64_t bc_unneeded=branch_regs[i].u;
5977 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5978 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5979 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5981 bc_unneeded_upper|=1;
5982 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5983 bc_unneeded,bc_unneeded_upper);
5984 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5985 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5987 int rt,return_address;
5988 rt=get_reg(branch_regs[i].regmap,31);
5989 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5991 // Save the PC even if the branch is not taken
5992 return_address=start+i*4+8;
5993 emit_movimm(return_address,rt); // PC into link register
5995 if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5999 cc=get_reg(branch_regs[i].regmap,CCREG);
6000 assert(cc==HOST_CCREG);
6002 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6003 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
6004 assem_debug("cycle count (adj)\n");
6006 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
6007 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
6008 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6009 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6011 assem_debug("branch: internal\n");
6013 assem_debug("branch: external\n");
6014 if(internal&&is_ds[(ba[i]-start)>>2]) {
6015 ds_assemble_entry(i);
6018 add_to_linker((int)out,ba[i],internal);
6021 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6022 if(((u_int)out)&7) emit_addnop(0);
6026 else if(nevertaken) {
6027 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6030 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6034 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6035 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6039 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
6046 add_to_linker((int)out,ba[i],internal);
6050 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
6057 add_to_linker((int)out,ba[i],internal);
6065 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
6072 add_to_linker((int)out,ba[i],internal);
6076 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
6083 add_to_linker((int)out,ba[i],internal);
6090 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6091 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
6093 emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6094 add_to_linker((int)out,ba[i],internal);
6097 add_to_linker((int)out,ba[i],internal*2);
6103 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6104 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6105 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6107 assem_debug("branch: internal\n");
6109 assem_debug("branch: external\n");
6110 if(internal&&is_ds[(ba[i]-start)>>2]) {
6111 ds_assemble_entry(i);
6114 add_to_linker((int)out,ba[i],internal);
6118 set_jump_target(nottaken,(int)out);
6122 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
6124 } // (!unconditional)
6128 // In-order execution (branch first)
6132 int rt,return_address;
6133 rt=get_reg(branch_regs[i].regmap,31);
6135 // Save the PC even if the branch is not taken
6136 return_address=start+i*4+8;
6137 emit_movimm(return_address,rt); // PC into link register
6139 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
6143 if(!unconditional) {
6144 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6148 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6154 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6164 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6170 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6177 } // if(!unconditional)
6179 uint64_t ds_unneeded=branch_regs[i].u;
6180 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6181 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6182 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6183 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6185 ds_unneeded_upper|=1;
6188 //assem_debug("1:\n");
6189 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6190 ds_unneeded,ds_unneeded_upper);
6192 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6193 address_generation(i+1,&branch_regs[i],0);
6194 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6195 ds_assemble(i+1,&branch_regs[i]);
6196 cc=get_reg(branch_regs[i].regmap,CCREG);
6198 emit_loadreg(CCREG,cc=HOST_CCREG);
6199 // CHECK: Is the following instruction (fall thru) allocated ok?
6201 assert(cc==HOST_CCREG);
6202 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6203 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6204 assem_debug("cycle count (adj)\n");
6205 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6206 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6208 assem_debug("branch: internal\n");
6210 assem_debug("branch: external\n");
6211 if(internal&&is_ds[(ba[i]-start)>>2]) {
6212 ds_assemble_entry(i);
6215 add_to_linker((int)out,ba[i],internal);
6220 cop1_usable=prev_cop1_usable;
6221 if(!unconditional) {
6222 set_jump_target(nottaken,(int)out);
6223 assem_debug("1:\n");
6225 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6226 ds_unneeded,ds_unneeded_upper);
6227 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6228 address_generation(i+1,&branch_regs[i],0);
6229 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6230 ds_assemble(i+1,&branch_regs[i]);
6232 cc=get_reg(branch_regs[i].regmap,CCREG);
6233 if(cc==-1&&!likely[i]) {
6234 // Cycle count isn't in a register, temporarily load it then write it out
6235 emit_loadreg(CCREG,HOST_CCREG);
6236 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6239 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6240 emit_storereg(CCREG,HOST_CCREG);
6243 cc=get_reg(i_regmap,CCREG);
6244 assert(cc==HOST_CCREG);
6245 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6248 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6254 void fjump_assemble(int i,struct regstat *i_regs)
6256 signed char *i_regmap=i_regs->regmap;
6259 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6260 assem_debug("fmatch=%d\n",match);
6264 int internal=internal_branch(branch_regs[i].is32,ba[i]);
6265 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
6266 if(!match) invert=1;
6267 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6268 if(i>(ba[i]-start)>>2) invert=1;
6272 fs=get_reg(branch_regs[i].regmap,FSREG);
6273 address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6276 fs=get_reg(i_regmap,FSREG);
6279 // Check cop1 unusable
6281 cs=get_reg(i_regmap,CSREG);
6283 emit_testimm(cs,0x20000000);
6286 add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6291 // Out of order execution (delay slot first)
6293 ds_assemble(i+1,i_regs);
6295 uint64_t bc_unneeded=branch_regs[i].u;
6296 uint64_t bc_unneeded_upper=branch_regs[i].uu;
6297 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6298 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6300 bc_unneeded_upper|=1;
6301 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6302 bc_unneeded,bc_unneeded_upper);
6303 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6304 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6305 cc=get_reg(branch_regs[i].regmap,CCREG);
6306 assert(cc==HOST_CCREG);
6307 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6308 assem_debug("cycle count (adj)\n");
6311 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6314 emit_testimm(fs,0x800000);
6315 if(source[i]&0x10000) // BC1T
6321 add_to_linker((int)out,ba[i],internal);
6330 add_to_linker((int)out,ba[i],internal);
6338 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6339 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6340 else if(match) emit_addnop(13);
6342 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6343 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6345 assem_debug("branch: internal\n");
6347 assem_debug("branch: external\n");
6348 if(internal&&is_ds[(ba[i]-start)>>2]) {
6349 ds_assemble_entry(i);
6352 add_to_linker((int)out,ba[i],internal);
6355 set_jump_target(nottaken,(int)out);
6359 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
6361 } // (!unconditional)
6365 // In-order execution (branch first)
6369 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6372 emit_testimm(fs,0x800000);
6373 if(source[i]&0x10000) // BC1T
6384 } // if(!unconditional)
6386 uint64_t ds_unneeded=branch_regs[i].u;
6387 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6388 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6389 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6390 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6392 ds_unneeded_upper|=1;
6394 //assem_debug("1:\n");
6395 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6396 ds_unneeded,ds_unneeded_upper);
6398 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6399 address_generation(i+1,&branch_regs[i],0);
6400 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6401 ds_assemble(i+1,&branch_regs[i]);
6402 cc=get_reg(branch_regs[i].regmap,CCREG);
6404 emit_loadreg(CCREG,cc=HOST_CCREG);
6405 // CHECK: Is the following instruction (fall thru) allocated ok?
6407 assert(cc==HOST_CCREG);
6408 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6409 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6410 assem_debug("cycle count (adj)\n");
6411 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6412 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6414 assem_debug("branch: internal\n");
6416 assem_debug("branch: external\n");
6417 if(internal&&is_ds[(ba[i]-start)>>2]) {
6418 ds_assemble_entry(i);
6421 add_to_linker((int)out,ba[i],internal);
6426 if(1) { // <- FIXME (don't need this)
6427 set_jump_target(nottaken,(int)out);
6428 assem_debug("1:\n");
6430 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6431 ds_unneeded,ds_unneeded_upper);
6432 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6433 address_generation(i+1,&branch_regs[i],0);
6434 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6435 ds_assemble(i+1,&branch_regs[i]);
6437 cc=get_reg(branch_regs[i].regmap,CCREG);
6438 if(cc==-1&&!likely[i]) {
6439 // Cycle count isn't in a register, temporarily load it then write it out
6440 emit_loadreg(CCREG,HOST_CCREG);
6441 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6444 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6445 emit_storereg(CCREG,HOST_CCREG);
6448 cc=get_reg(i_regmap,CCREG);
6449 assert(cc==HOST_CCREG);
6450 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6453 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6459 static void pagespan_assemble(int i,struct regstat *i_regs)
6461 int s1l=get_reg(i_regs->regmap,rs1[i]);
6462 int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6463 int s2l=get_reg(i_regs->regmap,rs2[i]);
6464 int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6465 void *nt_branch=NULL;
6468 int unconditional=0;
6478 if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6482 int addr,alt,ntaddr;
6483 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6487 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6488 (i_regs->regmap[hr]&63)!=rs1[i] &&
6489 (i_regs->regmap[hr]&63)!=rs2[i] )
6498 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6499 (i_regs->regmap[hr]&63)!=rs1[i] &&
6500 (i_regs->regmap[hr]&63)!=rs2[i] )
6506 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6510 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6511 (i_regs->regmap[hr]&63)!=rs1[i] &&
6512 (i_regs->regmap[hr]&63)!=rs2[i] )
6519 assert(hr<HOST_REGS);
6520 if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6521 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6523 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6524 if(opcode[i]==2) // J
6528 if(opcode[i]==3) // JAL
6531 int rt=get_reg(i_regs->regmap,31);
6532 emit_movimm(start+i*4+8,rt);
6535 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6538 if(opcode2[i]==9) // JALR
6540 int rt=get_reg(i_regs->regmap,rt1[i]);
6541 emit_movimm(start+i*4+8,rt);
6544 if((opcode[i]&0x3f)==4) // BEQ
6551 #ifdef HAVE_CMOV_IMM
6553 if(s2l>=0) emit_cmp(s1l,s2l);
6554 else emit_test(s1l,s1l);
6555 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6561 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6563 if(s2h>=0) emit_cmp(s1h,s2h);
6564 else emit_test(s1h,s1h);
6565 emit_cmovne_reg(alt,addr);
6567 if(s2l>=0) emit_cmp(s1l,s2l);
6568 else emit_test(s1l,s1l);
6569 emit_cmovne_reg(alt,addr);
6572 if((opcode[i]&0x3f)==5) // BNE
6574 #ifdef HAVE_CMOV_IMM
6576 if(s2l>=0) emit_cmp(s1l,s2l);
6577 else emit_test(s1l,s1l);
6578 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6584 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6586 if(s2h>=0) emit_cmp(s1h,s2h);
6587 else emit_test(s1h,s1h);
6588 emit_cmovne_reg(alt,addr);
6590 if(s2l>=0) emit_cmp(s1l,s2l);
6591 else emit_test(s1l,s1l);
6592 emit_cmovne_reg(alt,addr);
6595 if((opcode[i]&0x3f)==0x14) // BEQL
6598 if(s2h>=0) emit_cmp(s1h,s2h);
6599 else emit_test(s1h,s1h);
6603 if(s2l>=0) emit_cmp(s1l,s2l);
6604 else emit_test(s1l,s1l);
6605 if(nottaken) set_jump_target(nottaken,(int)out);
6609 if((opcode[i]&0x3f)==0x15) // BNEL
6612 if(s2h>=0) emit_cmp(s1h,s2h);
6613 else emit_test(s1h,s1h);
6617 if(s2l>=0) emit_cmp(s1l,s2l);
6618 else emit_test(s1l,s1l);
6621 if(taken) set_jump_target(taken,(int)out);
6623 if((opcode[i]&0x3f)==6) // BLEZ
6625 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6627 if(s1h>=0) emit_mov(addr,ntaddr);
6628 emit_cmovl_reg(alt,addr);
6631 emit_cmovne_reg(ntaddr,addr);
6632 emit_cmovs_reg(alt,addr);
6635 if((opcode[i]&0x3f)==7) // BGTZ
6637 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6639 if(s1h>=0) emit_mov(addr,alt);
6640 emit_cmovl_reg(ntaddr,addr);
6643 emit_cmovne_reg(alt,addr);
6644 emit_cmovs_reg(ntaddr,addr);
6647 if((opcode[i]&0x3f)==0x16) // BLEZL
6649 assert((opcode[i]&0x3f)!=0x16);
6651 if((opcode[i]&0x3f)==0x17) // BGTZL
6653 assert((opcode[i]&0x3f)!=0x17);
6655 assert(opcode[i]!=1); // BLTZ/BGEZ
6657 //FIXME: Check CSREG
6658 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6659 if((source[i]&0x30000)==0) // BC1F
6661 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6662 emit_testimm(s1l,0x800000);
6663 emit_cmovne_reg(alt,addr);
6665 if((source[i]&0x30000)==0x10000) // BC1T
6667 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6668 emit_testimm(s1l,0x800000);
6669 emit_cmovne_reg(alt,addr);
6671 if((source[i]&0x30000)==0x20000) // BC1FL
6673 emit_testimm(s1l,0x800000);
6677 if((source[i]&0x30000)==0x30000) // BC1TL
6679 emit_testimm(s1l,0x800000);
6685 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6686 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6687 if(likely[i]||unconditional)
6689 emit_movimm(ba[i],HOST_BTREG);
6691 else if(addr!=HOST_BTREG)
6693 emit_mov(addr,HOST_BTREG);
6695 void *branch_addr=out;
6697 int target_addr=start+i*4+5;
6699 void *compiled_target_addr=check_addr(target_addr);
6700 emit_extjump_ds((int)branch_addr,target_addr);
6701 if(compiled_target_addr) {
6702 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6703 add_link(target_addr,stub);
6705 else set_jump_target((int)branch_addr,(int)stub);
6708 set_jump_target((int)nottaken,(int)out);
6709 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6710 void *branch_addr=out;
6712 int target_addr=start+i*4+8;
6714 void *compiled_target_addr=check_addr(target_addr);
6715 emit_extjump_ds((int)branch_addr,target_addr);
6716 if(compiled_target_addr) {
6717 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6718 add_link(target_addr,stub);
6720 else set_jump_target((int)branch_addr,(int)stub);
6724 // Assemble the delay slot for the above
6725 static void pagespan_ds()
6727 assem_debug("initial delay slot:\n");
6728 u_int vaddr=start+1;
6729 u_int page=get_page(vaddr);
6730 u_int vpage=get_vpage(vaddr);
6731 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6733 ll_add(jump_in+page,vaddr,(void *)out);
6734 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6735 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6736 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6737 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6738 emit_writeword(HOST_BTREG,(int)&branch_target);
6739 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6740 address_generation(0,®s[0],regs[0].regmap_entry);
6741 if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6742 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6747 alu_assemble(0,®s[0]);break;
6749 imm16_assemble(0,®s[0]);break;
6751 shift_assemble(0,®s[0]);break;
6753 shiftimm_assemble(0,®s[0]);break;
6755 load_assemble(0,®s[0]);break;
6757 loadlr_assemble(0,®s[0]);break;
6759 store_assemble(0,®s[0]);break;
6761 storelr_assemble(0,®s[0]);break;
6763 cop0_assemble(0,®s[0]);break;
6765 cop1_assemble(0,®s[0]);break;
6767 c1ls_assemble(0,®s[0]);break;
6769 cop2_assemble(0,®s[0]);break;
6771 c2ls_assemble(0,®s[0]);break;
6773 c2op_assemble(0,®s[0]);break;
6775 fconv_assemble(0,®s[0]);break;
6777 float_assemble(0,®s[0]);break;
6779 fcomp_assemble(0,®s[0]);break;
6781 multdiv_assemble(0,®s[0]);break;
6783 mov_assemble(0,®s[0]);break;
6793 printf("Jump in the delay slot. This is probably a bug.\n");
6795 int btaddr=get_reg(regs[0].regmap,BTREG);
6797 btaddr=get_reg(regs[0].regmap,-1);
6798 emit_readword((int)&branch_target,btaddr);
6800 assert(btaddr!=HOST_CCREG);
6801 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6803 emit_movimm(start+4,HOST_TEMPREG);
6804 emit_cmp(btaddr,HOST_TEMPREG);
6806 emit_cmpimm(btaddr,start+4);
6808 int branch=(int)out;
6810 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6811 emit_jmp(jump_vaddr_reg[btaddr]);
6812 set_jump_target(branch,(int)out);
6813 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6814 load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6817 // Basic liveness analysis for MIPS registers
6818 void unneeded_registers(int istart,int iend,int r)
6821 uint64_t u,uu,gte_u,b,bu,gte_bu;
6822 uint64_t temp_u,temp_uu,temp_gte_u=0;
6824 uint64_t gte_u_unknown=0;
6825 if(new_dynarec_hacks&NDHACK_GTE_UNNEEDED)
6829 gte_u=gte_u_unknown;
6831 u=unneeded_reg[iend+1];
6832 uu=unneeded_reg_upper[iend+1];
6834 gte_u=gte_unneeded[iend+1];
6837 for (i=iend;i>=istart;i--)
6839 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6840 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6842 // If subroutine call, flag return address as a possible branch target
6843 if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6845 if(ba[i]<start || ba[i]>=(start+slen*4))
6847 // Branch out of this block, flush all regs
6850 gte_u=gte_u_unknown;
6852 if(itype[i]==UJUMP&&rt1[i]==31)
6854 uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6856 if(itype[i]==RJUMP&&rs1[i]==31)
6858 uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6860 if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
6861 if(itype[i]==UJUMP&&rt1[i]==31)
6863 //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6864 uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6866 if(itype[i]==RJUMP&&rs1[i]==31)
6868 //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6869 uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6872 branch_unneeded_reg[i]=u;
6873 branch_unneeded_reg_upper[i]=uu;
6874 // Merge in delay slot
6875 tdep=(~uu>>rt1[i+1])&1;
6876 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6877 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6878 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6879 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6880 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6883 gte_u&=~gte_rs[i+1];
6884 // If branch is "likely" (and conditional)
6885 // then we skip the delay slot on the fall-thru path
6888 u&=unneeded_reg[i+2];
6889 uu&=unneeded_reg_upper[i+2];
6890 gte_u&=gte_unneeded[i+2];
6896 gte_u=gte_u_unknown;
6902 // Internal branch, flag target
6903 bt[(ba[i]-start)>>2]=1;
6904 if(ba[i]<=start+i*4) {
6906 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6908 // Unconditional branch
6912 // Conditional branch (not taken case)
6913 temp_u=unneeded_reg[i+2];
6914 temp_uu=unneeded_reg_upper[i+2];
6915 temp_gte_u&=gte_unneeded[i+2];
6917 // Merge in delay slot
6918 tdep=(~temp_uu>>rt1[i+1])&1;
6919 temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6920 temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6921 temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6922 temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6923 temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6924 temp_u|=1;temp_uu|=1;
6925 temp_gte_u|=gte_rt[i+1];
6926 temp_gte_u&=~gte_rs[i+1];
6927 // If branch is "likely" (and conditional)
6928 // then we skip the delay slot on the fall-thru path
6931 temp_u&=unneeded_reg[i+2];
6932 temp_uu&=unneeded_reg_upper[i+2];
6933 temp_gte_u&=gte_unneeded[i+2];
6939 temp_gte_u=gte_u_unknown;
6942 tdep=(~temp_uu>>rt1[i])&1;
6943 temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6944 temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6945 temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6946 temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6947 temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6948 temp_u|=1;temp_uu|=1;
6949 temp_gte_u|=gte_rt[i];
6950 temp_gte_u&=~gte_rs[i];
6951 unneeded_reg[i]=temp_u;
6952 unneeded_reg_upper[i]=temp_uu;
6953 gte_unneeded[i]=temp_gte_u;
6954 // Only go three levels deep. This recursion can take an
6955 // excessive amount of time if there are a lot of nested loops.
6957 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6959 unneeded_reg[(ba[i]-start)>>2]=1;
6960 unneeded_reg_upper[(ba[i]-start)>>2]=1;
6961 gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
6964 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6966 // Unconditional branch
6967 u=unneeded_reg[(ba[i]-start)>>2];
6968 uu=unneeded_reg_upper[(ba[i]-start)>>2];
6969 gte_u=gte_unneeded[(ba[i]-start)>>2];
6970 branch_unneeded_reg[i]=u;
6971 branch_unneeded_reg_upper[i]=uu;
6974 //branch_unneeded_reg[i]=u;
6975 //branch_unneeded_reg_upper[i]=uu;
6976 // Merge in delay slot
6977 tdep=(~uu>>rt1[i+1])&1;
6978 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6979 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6980 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6981 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6982 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6985 gte_u&=~gte_rs[i+1];
6987 // Conditional branch
6988 b=unneeded_reg[(ba[i]-start)>>2];
6989 bu=unneeded_reg_upper[(ba[i]-start)>>2];
6990 gte_bu=gte_unneeded[(ba[i]-start)>>2];
6991 branch_unneeded_reg[i]=b;
6992 branch_unneeded_reg_upper[i]=bu;
6995 //branch_unneeded_reg[i]=b;
6996 //branch_unneeded_reg_upper[i]=bu;
6997 // Branch delay slot
6998 tdep=(~uu>>rt1[i+1])&1;
6999 b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
7000 bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
7001 b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
7002 bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
7003 bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
7005 gte_bu|=gte_rt[i+1];
7006 gte_bu&=~gte_rs[i+1];
7007 // If branch is "likely" then we skip the
7008 // delay slot on the fall-thru path
7014 u&=unneeded_reg[i+2];
7015 uu&=unneeded_reg_upper[i+2];
7016 gte_u&=gte_unneeded[i+2];
7028 branch_unneeded_reg[i]&=unneeded_reg[i+2];
7029 branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
7030 //branch_unneeded_reg[i]=1;
7031 //branch_unneeded_reg_upper[i]=1;
7033 branch_unneeded_reg[i]=1;
7034 branch_unneeded_reg_upper[i]=1;
7040 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7042 // SYSCALL instruction (software interrupt)
7046 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7048 // ERET instruction (return from interrupt)
7053 tdep=(~uu>>rt1[i])&1;
7054 // Written registers are unneeded
7060 // Accessed registers are needed
7066 if(gte_rs[i]&&rt1[i]&&(unneeded_reg[i+1]&(1ll<<rt1[i])))
7067 gte_u|=gte_rs[i]>e_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
7068 // Source-target dependencies
7069 uu&=~(tdep<<dep1[i]);
7070 uu&=~(tdep<<dep2[i]);
7071 // R0 is always unneeded
7075 unneeded_reg_upper[i]=uu;
7076 gte_unneeded[i]=gte_u;
7078 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
7081 for(r=1;r<=CCREG;r++) {
7082 if((unneeded_reg[i]>>r)&1) {
7083 if(r==HIREG) printf(" HI");
7084 else if(r==LOREG) printf(" LO");
7085 else printf(" r%d",r);
7089 for(r=1;r<=CCREG;r++) {
7090 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
7091 if(r==HIREG) printf(" HI");
7092 else if(r==LOREG) printf(" LO");
7093 else printf(" r%d",r);
7099 for (i=iend;i>=istart;i--)
7101 unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
7106 // Identify registers which are likely to contain 32-bit values
7107 // This is used to predict whether any branches will jump to a
7108 // location with 64-bit values in registers.
7109 static void provisional_32bit()
7113 uint64_t lastbranch=1;
7118 if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
7119 if(i>1) is32=lastbranch;
7125 if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
7127 if(i>2) is32=lastbranch;
7131 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
7133 if(rs1[i-2]==0||rs2[i-2]==0)
7136 is32|=1LL<<rs1[i-2];
7139 is32|=1LL<<rs2[i-2];
7144 // If something jumps here with 64-bit values
7145 // then promote those registers to 64 bits
7148 uint64_t temp_is32=is32;
7151 if(ba[j]==start+i*4)
7152 //temp_is32&=branch_regs[j].is32;
7157 if(ba[j]==start+i*4)
7168 if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
7169 // Branches don't write registers, consider the delay slot instead.
7180 if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
7181 opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
7190 if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
7191 if(op==0x22) is32|=1LL<<rt; // LWL
7194 if (op==0x08||op==0x09|| // ADDI/ADDIU
7195 op==0x0a||op==0x0b|| // SLTI/SLTIU
7201 if(op==0x18||op==0x19) { // DADDI/DADDIU
7204 // is32|=((is32>>s1)&1LL)<<rt;
7206 if(op==0x0d||op==0x0e) { // ORI/XORI
7207 uint64_t sr=((is32>>s1)&1LL);
7223 if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
7226 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
7229 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
7230 uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
7234 else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
7239 uint64_t sr=((is32>>s1)&1LL);
7244 uint64_t sr=((is32>>s2)&1LL);
7252 else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
7257 uint64_t sr=((is32>>s1)&1LL);
7267 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7268 is32&=~((1LL<<HIREG)|(1LL<<LOREG));
7271 is32|=(1LL<<HIREG)|(1LL<<LOREG);
7276 uint64_t sr=((is32>>s1)&1LL);
7282 if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7283 else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7287 // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7288 if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7291 if(op2==0) is32|=1LL<<rt; // MFC0
7295 if(op2==0) is32|=1LL<<rt; // MFC1
7296 if(op2==1) is32&=~(1LL<<rt); // DMFC1
7297 if(op2==2) is32|=1LL<<rt; // CFC1
7319 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7321 if(rt1[i-1]==31) // JAL/JALR
7323 // Subroutine call will return here, don't alloc any registers
7328 // Internal branch will jump here, match registers to caller
7336 // Identify registers which may be assumed to contain 32-bit values
7337 // and where optimizations will rely on this.
7338 // This is used to determine whether backward branches can safely
7339 // jump to a location with 64-bit values in registers.
7340 static void provisional_r32()
7345 for (i=slen-1;i>=0;i--)
7348 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7350 if(ba[i]<start || ba[i]>=(start+slen*4))
7352 // Branch out of this block, don't need anything
7358 // Need whatever matches the target
7359 // (and doesn't get overwritten by the delay slot instruction)
7361 int t=(ba[i]-start)>>2;
7362 if(ba[i]>start+i*4) {
7364 //if(!(requires_32bit[t]&~regs[i].was32))
7365 // r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7366 if(!(pr32[t]&~regs[i].was32))
7367 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7370 if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7371 r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7374 // Conditional branch may need registers for following instructions
7375 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7378 //r32|=requires_32bit[i+2];
7381 // Mark this address as a branch target since it may be called
7382 // upon return from interrupt
7386 // Merge in delay slot
7388 // These are overwritten unless the branch is "likely"
7389 // and the delay slot is nullified if not taken
7390 r32&=~(1LL<<rt1[i+1]);
7391 r32&=~(1LL<<rt2[i+1]);
7393 // Assume these are needed (delay slot)
7396 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7400 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7402 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7404 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7406 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7408 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7411 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7413 // SYSCALL instruction (software interrupt)
7416 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7418 // ERET instruction (return from interrupt)
7422 r32&=~(1LL<<rt1[i]);
7423 r32&=~(1LL<<rt2[i]);
7426 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7430 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7432 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7434 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7436 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7438 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7440 //requires_32bit[i]=r32;
7443 // Dirty registers which are 32-bit, require 32-bit input
7444 // as they will be written as 32-bit values
7445 for(hr=0;hr<HOST_REGS;hr++)
7447 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
7448 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7449 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7450 pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7451 //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7458 // Write back dirty registers as soon as we will no longer modify them,
7459 // so that we don't end up with lots of writes at the branches.
7460 void clean_registers(int istart,int iend,int wr)
7464 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7465 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7467 will_dirty_i=will_dirty_next=0;
7468 wont_dirty_i=wont_dirty_next=0;
7470 will_dirty_i=will_dirty_next=will_dirty[iend+1];
7471 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7473 for (i=iend;i>=istart;i--)
7475 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7477 if(ba[i]<start || ba[i]>=(start+slen*4))
7479 // Branch out of this block, flush all regs
7480 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7482 // Unconditional branch
7485 // Merge in delay slot (will dirty)
7486 for(r=0;r<HOST_REGS;r++) {
7487 if(r!=EXCLUDE_REG) {
7488 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7489 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7490 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7491 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7492 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7493 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7494 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7495 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7496 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7497 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7498 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7499 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7500 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7501 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7507 // Conditional branch
7509 wont_dirty_i=wont_dirty_next;
7510 // Merge in delay slot (will dirty)
7511 for(r=0;r<HOST_REGS;r++) {
7512 if(r!=EXCLUDE_REG) {
7514 // Might not dirty if likely branch is not taken
7515 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7516 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7517 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7518 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7519 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7520 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7521 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7522 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7523 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7524 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7525 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7526 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7527 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7528 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7533 // Merge in delay slot (wont dirty)
7534 for(r=0;r<HOST_REGS;r++) {
7535 if(r!=EXCLUDE_REG) {
7536 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7537 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7538 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7539 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7540 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7541 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7542 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7543 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7544 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7545 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7549 #ifndef DESTRUCTIVE_WRITEBACK
7550 branch_regs[i].dirty&=wont_dirty_i;
7552 branch_regs[i].dirty|=will_dirty_i;
7558 if(ba[i]<=start+i*4) {
7560 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7562 // Unconditional branch
7565 // Merge in delay slot (will dirty)
7566 for(r=0;r<HOST_REGS;r++) {
7567 if(r!=EXCLUDE_REG) {
7568 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7569 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7570 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7571 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7572 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7573 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7574 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7575 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7576 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7577 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7578 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7579 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7580 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7581 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7585 // Conditional branch (not taken case)
7586 temp_will_dirty=will_dirty_next;
7587 temp_wont_dirty=wont_dirty_next;
7588 // Merge in delay slot (will dirty)
7589 for(r=0;r<HOST_REGS;r++) {
7590 if(r!=EXCLUDE_REG) {
7592 // Will not dirty if likely branch is not taken
7593 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7594 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7595 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7596 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7597 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7598 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7599 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7600 //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7601 //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7602 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7603 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7604 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7605 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7606 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7611 // Merge in delay slot (wont dirty)
7612 for(r=0;r<HOST_REGS;r++) {
7613 if(r!=EXCLUDE_REG) {
7614 if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7615 if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7616 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7617 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7618 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7619 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7620 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7621 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7622 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7623 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7626 // Deal with changed mappings
7628 for(r=0;r<HOST_REGS;r++) {
7629 if(r!=EXCLUDE_REG) {
7630 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7631 temp_will_dirty&=~(1<<r);
7632 temp_wont_dirty&=~(1<<r);
7633 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7634 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7635 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7637 temp_will_dirty|=1<<r;
7638 temp_wont_dirty|=1<<r;
7645 will_dirty[i]=temp_will_dirty;
7646 wont_dirty[i]=temp_wont_dirty;
7647 clean_registers((ba[i]-start)>>2,i-1,0);
7649 // Limit recursion. It can take an excessive amount
7650 // of time if there are a lot of nested loops.
7651 will_dirty[(ba[i]-start)>>2]=0;
7652 wont_dirty[(ba[i]-start)>>2]=-1;
7657 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7659 // Unconditional branch
7662 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7663 for(r=0;r<HOST_REGS;r++) {
7664 if(r!=EXCLUDE_REG) {
7665 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7666 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7667 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7669 if(branch_regs[i].regmap[r]>=0) {
7670 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7671 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7676 // Merge in delay slot
7677 for(r=0;r<HOST_REGS;r++) {
7678 if(r!=EXCLUDE_REG) {
7679 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7680 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7681 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7682 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7683 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7684 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7685 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7686 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7687 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7688 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7689 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7690 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7691 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7692 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7696 // Conditional branch
7697 will_dirty_i=will_dirty_next;
7698 wont_dirty_i=wont_dirty_next;
7699 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7700 for(r=0;r<HOST_REGS;r++) {
7701 if(r!=EXCLUDE_REG) {
7702 signed char target_reg=branch_regs[i].regmap[r];
7703 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7704 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7705 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7707 else if(target_reg>=0) {
7708 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7709 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7711 // Treat delay slot as part of branch too
7712 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7713 will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7714 wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7718 will_dirty[i+1]&=~(1<<r);
7723 // Merge in delay slot
7724 for(r=0;r<HOST_REGS;r++) {
7725 if(r!=EXCLUDE_REG) {
7727 // Might not dirty if likely branch is not taken
7728 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7729 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7730 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7731 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7732 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7733 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7734 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7735 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7736 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7737 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7738 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7739 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7740 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7741 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7746 // Merge in delay slot (won't dirty)
7747 for(r=0;r<HOST_REGS;r++) {
7748 if(r!=EXCLUDE_REG) {
7749 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7750 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7751 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7752 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7753 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7754 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7755 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7756 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7757 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7758 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7762 #ifndef DESTRUCTIVE_WRITEBACK
7763 branch_regs[i].dirty&=wont_dirty_i;
7765 branch_regs[i].dirty|=will_dirty_i;
7770 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7772 // SYSCALL instruction (software interrupt)
7776 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7778 // ERET instruction (return from interrupt)
7782 will_dirty_next=will_dirty_i;
7783 wont_dirty_next=wont_dirty_i;
7784 for(r=0;r<HOST_REGS;r++) {
7785 if(r!=EXCLUDE_REG) {
7786 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7787 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7788 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7789 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7790 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7791 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7792 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7793 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7795 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7797 // Don't store a register immediately after writing it,
7798 // may prevent dual-issue.
7799 if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7800 if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7806 will_dirty[i]=will_dirty_i;
7807 wont_dirty[i]=wont_dirty_i;
7808 // Mark registers that won't be dirtied as not dirty
7810 /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7811 for(r=0;r<HOST_REGS;r++) {
7812 if((will_dirty_i>>r)&1) {
7818 //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7819 regs[i].dirty|=will_dirty_i;
7820 #ifndef DESTRUCTIVE_WRITEBACK
7821 regs[i].dirty&=wont_dirty_i;
7822 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7824 if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7825 for(r=0;r<HOST_REGS;r++) {
7826 if(r!=EXCLUDE_REG) {
7827 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7828 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7829 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7837 for(r=0;r<HOST_REGS;r++) {
7838 if(r!=EXCLUDE_REG) {
7839 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7840 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7841 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7849 // Deal with changed mappings
7850 temp_will_dirty=will_dirty_i;
7851 temp_wont_dirty=wont_dirty_i;
7852 for(r=0;r<HOST_REGS;r++) {
7853 if(r!=EXCLUDE_REG) {
7855 if(regs[i].regmap[r]==regmap_pre[i][r]) {
7857 #ifndef DESTRUCTIVE_WRITEBACK
7858 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7860 regs[i].wasdirty|=will_dirty_i&(1<<r);
7863 else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7864 // Register moved to a different register
7865 will_dirty_i&=~(1<<r);
7866 wont_dirty_i&=~(1<<r);
7867 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7868 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7870 #ifndef DESTRUCTIVE_WRITEBACK
7871 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7873 regs[i].wasdirty|=will_dirty_i&(1<<r);
7877 will_dirty_i&=~(1<<r);
7878 wont_dirty_i&=~(1<<r);
7879 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7880 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7881 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7884 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7894 void disassemble_inst(int i)
7896 if (bt[i]) printf("*"); else printf(" ");
7899 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7901 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7903 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7905 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7907 if (opcode[i]==0x9&&rt1[i]!=31)
7908 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7910 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7913 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7915 if(opcode[i]==0xf) //LUI
7916 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7918 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7922 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7926 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7930 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7933 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7936 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7939 if((opcode2[i]&0x1d)==0x10)
7940 printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7941 else if((opcode2[i]&0x1d)==0x11)
7942 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7944 printf (" %x: %s\n",start+i*4,insn[i]);
7948 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7949 else if(opcode2[i]==4)
7950 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7951 else printf (" %x: %s\n",start+i*4,insn[i]);
7955 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7956 else if(opcode2[i]>3)
7957 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7958 else printf (" %x: %s\n",start+i*4,insn[i]);
7962 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7963 else if(opcode2[i]>3)
7964 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7965 else printf (" %x: %s\n",start+i*4,insn[i]);
7968 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7971 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7974 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7977 //printf (" %s %8x\n",insn[i],source[i]);
7978 printf (" %x: %s\n",start+i*4,insn[i]);
7982 static void disassemble_inst(int i) {}
7985 // clear the state completely, instead of just marking
7986 // things invalid like invalidate_all_pages() does
7987 void new_dynarec_clear_full()
7990 out=(u_char *)BASE_ADDR;
7991 memset(invalid_code,1,sizeof(invalid_code));
7992 memset(hash_table,0xff,sizeof(hash_table));
7993 memset(mini_ht,-1,sizeof(mini_ht));
7994 memset(restore_candidate,0,sizeof(restore_candidate));
7995 memset(shadow,0,sizeof(shadow));
7997 expirep=16384; // Expiry pointer, +2 blocks
7998 pending_exception=0;
8001 inv_code_start=inv_code_end=~0;
8005 for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
8007 for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
8008 memory_map[n]=((u_int)rdram-0x80000000)>>2;
8009 for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
8012 for(n=0;n<4096;n++) ll_clear(jump_in+n);
8013 for(n=0;n<4096;n++) ll_clear(jump_out+n);
8014 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
8017 void new_dynarec_init()
8019 printf("Init new dynarec\n");
8020 out=(u_char *)BASE_ADDR;
8022 if (mmap (out, 1<<TARGET_SIZE_2,
8023 PROT_READ | PROT_WRITE | PROT_EXEC,
8024 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
8025 -1, 0) <= 0) {printf("mmap() failed\n");}
8027 // not all systems allow execute in data segment by default
8028 if (mprotect(out, 1<<TARGET_SIZE_2, PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
8029 printf("mprotect() failed\n");
8032 rdword=&readmem_dword;
8033 fake_pc.f.r.rs=&readmem_dword;
8034 fake_pc.f.r.rt=&readmem_dword;
8035 fake_pc.f.r.rd=&readmem_dword;
8038 cycle_multiplier=200;
8039 new_dynarec_clear_full();
8041 // Copy this into local area so we don't have to put it in every literal pool
8042 invc_ptr=invalid_code;
8045 for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
8046 writemem[n] = write_nomem_new;
8047 writememb[n] = write_nomemb_new;
8048 writememh[n] = write_nomemh_new;
8050 writememd[n] = write_nomemd_new;
8052 readmem[n] = read_nomem_new;
8053 readmemb[n] = read_nomemb_new;
8054 readmemh[n] = read_nomemh_new;
8056 readmemd[n] = read_nomemd_new;
8059 for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
8060 writemem[n] = write_rdram_new;
8061 writememb[n] = write_rdramb_new;
8062 writememh[n] = write_rdramh_new;
8064 writememd[n] = write_rdramd_new;
8067 for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
8068 writemem[n] = write_nomem_new;
8069 writememb[n] = write_nomemb_new;
8070 writememh[n] = write_nomemh_new;
8072 writememd[n] = write_nomemd_new;
8074 readmem[n] = read_nomem_new;
8075 readmemb[n] = read_nomemb_new;
8076 readmemh[n] = read_nomemh_new;
8078 readmemd[n] = read_nomemd_new;
8085 ram_offset=(u_int)rdram-0x80000000;
8088 printf("warning: RAM is not directly mapped, performance will suffer\n");
8091 void new_dynarec_cleanup()
8095 if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
8097 for(n=0;n<4096;n++) ll_clear(jump_in+n);
8098 for(n=0;n<4096;n++) ll_clear(jump_out+n);
8099 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
8101 if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
8105 int new_recompile_block(int addr)
8108 if(addr==0x800cd050) {
8110 for(block=0x80000;block<0x80800;block++) invalidate_block(block);
8112 for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
8115 //if(Count==365117028) tracedebug=1;
8116 assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8117 //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8118 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
8120 //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
8121 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
8122 /*if(Count>=312978186) {
8126 start = (u_int)addr&~3;
8127 //assert(((u_int)addr&1)==0);
8128 new_dynarec_did_compile=1;
8130 if (Config.HLE && start == 0x80001000) // hlecall
8132 // XXX: is this enough? Maybe check hleSoftCall?
8133 u_int beginning=(u_int)out;
8134 u_int page=get_page(start);
8135 invalid_code[start>>12]=0;
8136 emit_movimm(start,0);
8137 emit_writeword(0,(int)&pcaddr);
8138 emit_jmp((int)new_dyna_leave);
8141 __clear_cache((void *)beginning,out);
8143 ll_add(jump_in+page,start,(void *)beginning);
8146 else if ((u_int)addr < 0x00200000 ||
8147 (0xa0000000 <= addr && addr < 0xa0200000)) {
8148 // used for BIOS calls mostly?
8149 source = (u_int *)((u_int)rdram+(start&0x1fffff));
8150 pagelimit = (addr&0xa0000000)|0x00200000;
8152 else if (!Config.HLE && (
8153 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
8154 (0xbfc00000 <= addr && addr < 0xbfc80000))) {
8156 source = (u_int *)((u_int)psxR+(start&0x7ffff));
8157 pagelimit = (addr&0xfff00000)|0x80000;
8162 if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
8163 source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
8164 pagelimit = 0xa4001000;
8168 if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
8169 source = (u_int *)((u_int)rdram+start-0x80000000);
8170 pagelimit = 0x80000000+RAM_SIZE;
8173 else if ((signed int)addr >= (signed int)0xC0000000) {
8174 //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
8175 //if(tlb_LUT_r[start>>12])
8176 //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
8177 if((signed int)memory_map[start>>12]>=0) {
8178 source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
8179 pagelimit=(start+4096)&0xFFFFF000;
8180 int map=memory_map[start>>12];
8183 //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
8184 if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
8186 assem_debug("pagelimit=%x\n",pagelimit);
8187 assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
8190 assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
8191 //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
8192 return -1; // Caller will invoke exception handler
8194 //printf("source= %x\n",(int)source);
8198 printf("Compile at bogus memory address: %x \n", (int)addr);
8202 /* Pass 1: disassemble */
8203 /* Pass 2: register dependencies, branch targets */
8204 /* Pass 3: register allocation */
8205 /* Pass 4: branch dependencies */
8206 /* Pass 5: pre-alloc */
8207 /* Pass 6: optimize clean/dirty state */
8208 /* Pass 7: flag 32-bit registers */
8209 /* Pass 8: assembly */
8210 /* Pass 9: linker */
8211 /* Pass 10: garbage collection / free memory */
8215 unsigned int type,op,op2;
8217 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
8219 /* Pass 1 disassembly */
8221 for(i=0;!done;i++) {
8222 bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
8223 minimum_free_regs[i]=0;
8224 opcode[i]=op=source[i]>>26;
8227 case 0x00: strcpy(insn[i],"special"); type=NI;
8231 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
8232 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
8233 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
8234 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
8235 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
8236 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
8237 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
8238 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
8239 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
8240 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
8241 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
8242 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
8243 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
8244 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
8245 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
8246 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
8247 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
8248 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
8249 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
8250 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
8251 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
8252 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
8253 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
8254 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
8255 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
8256 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
8257 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
8258 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
8259 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
8260 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
8261 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
8262 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
8263 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
8264 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
8265 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
8267 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
8268 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
8269 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
8270 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
8271 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
8272 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
8273 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
8274 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
8275 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
8276 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
8277 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
8278 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
8279 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
8280 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
8281 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
8282 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
8283 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
8287 case 0x01: strcpy(insn[i],"regimm"); type=NI;
8288 op2=(source[i]>>16)&0x1f;
8291 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
8292 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
8293 case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
8294 case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
8295 case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
8296 case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
8297 case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
8298 case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
8299 case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
8300 case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
8301 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
8302 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
8303 case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
8304 case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
8307 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
8308 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
8309 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
8310 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
8311 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
8312 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
8313 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
8314 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
8315 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8316 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8317 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8318 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8319 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8320 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8321 case 0x10: strcpy(insn[i],"cop0"); type=NI;
8322 op2=(source[i]>>21)&0x1f;
8325 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8326 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8327 case 0x10: strcpy(insn[i],"tlb"); type=NI;
8328 switch(source[i]&0x3f)
8330 case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8331 case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8332 case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8333 case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
8335 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8337 case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
8342 case 0x11: strcpy(insn[i],"cop1"); type=NI;
8343 op2=(source[i]>>21)&0x1f;
8346 case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8347 case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8348 case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8349 case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8350 case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8351 case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8352 case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8353 switch((source[i]>>16)&0x3)
8355 case 0x00: strcpy(insn[i],"BC1F"); break;
8356 case 0x01: strcpy(insn[i],"BC1T"); break;
8357 case 0x02: strcpy(insn[i],"BC1FL"); break;
8358 case 0x03: strcpy(insn[i],"BC1TL"); break;
8361 case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8362 switch(source[i]&0x3f)
8364 case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8365 case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8366 case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8367 case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8368 case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8369 case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8370 case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8371 case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8372 case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8373 case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8374 case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8375 case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8376 case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8377 case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8378 case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8379 case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8380 case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8381 case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8382 case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8383 case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8384 case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8385 case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8386 case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8387 case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8388 case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8389 case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8390 case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8391 case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8392 case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8393 case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8394 case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8395 case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8396 case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8397 case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8398 case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8401 case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8402 switch(source[i]&0x3f)
8404 case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8405 case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8406 case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8407 case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8408 case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8409 case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8410 case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8411 case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8412 case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8413 case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8414 case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8415 case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8416 case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8417 case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8418 case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8419 case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8420 case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8421 case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8422 case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8423 case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8424 case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8425 case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8426 case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8427 case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8428 case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8429 case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8430 case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8431 case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8432 case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8433 case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8434 case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8435 case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8436 case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8437 case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8438 case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8441 case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8442 switch(source[i]&0x3f)
8444 case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8445 case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8448 case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8449 switch(source[i]&0x3f)
8451 case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8452 case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8458 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8459 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8460 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8461 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8462 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8463 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8464 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8465 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8467 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8468 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8469 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8470 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8471 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8472 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8473 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8475 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8477 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8478 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8479 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8480 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8482 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8483 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8485 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8486 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8487 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8488 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8490 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8491 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8492 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8494 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8495 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8497 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8498 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8499 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8502 case 0x12: strcpy(insn[i],"COP2"); type=NI;
8503 op2=(source[i]>>21)&0x1f;
8505 if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
8506 if (gte_handlers[source[i]&0x3f]!=NULL) {
8507 if (gte_regnames[source[i]&0x3f]!=NULL)
8508 strcpy(insn[i],gte_regnames[source[i]&0x3f]);
8510 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8516 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8517 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8518 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8519 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8522 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8523 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8524 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8526 default: strcpy(insn[i],"???"); type=NI;
8527 printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
8532 /* Get registers/immediates */
8538 gte_rs[i]=gte_rt[i]=0;
8541 rs1[i]=(source[i]>>21)&0x1f;
8543 rt1[i]=(source[i]>>16)&0x1f;
8545 imm[i]=(short)source[i];
8549 rs1[i]=(source[i]>>21)&0x1f;
8550 rs2[i]=(source[i]>>16)&0x1f;
8553 imm[i]=(short)source[i];
8554 if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8557 // LWL/LWR only load part of the register,
8558 // therefore the target register must be treated as a source too
8559 rs1[i]=(source[i]>>21)&0x1f;
8560 rs2[i]=(source[i]>>16)&0x1f;
8561 rt1[i]=(source[i]>>16)&0x1f;
8563 imm[i]=(short)source[i];
8564 if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8565 if(op==0x26) dep1[i]=rt1[i]; // LWR
8568 if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8569 else rs1[i]=(source[i]>>21)&0x1f;
8571 rt1[i]=(source[i]>>16)&0x1f;
8573 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8574 imm[i]=(unsigned short)source[i];
8576 imm[i]=(short)source[i];
8578 if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8579 if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8580 if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8587 // The JAL instruction writes to r31.
8594 rs1[i]=(source[i]>>21)&0x1f;
8598 // The JALR instruction writes to rd.
8600 rt1[i]=(source[i]>>11)&0x1f;
8605 rs1[i]=(source[i]>>21)&0x1f;
8606 rs2[i]=(source[i]>>16)&0x1f;
8609 if(op&2) { // BGTZ/BLEZ
8617 rs1[i]=(source[i]>>21)&0x1f;
8622 if(op2&0x10) { // BxxAL
8624 // NOTE: If the branch is not taken, r31 is still overwritten
8626 likely[i]=(op2&2)>>1;
8633 likely[i]=((source[i])>>17)&1;
8636 rs1[i]=(source[i]>>21)&0x1f; // source
8637 rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8638 rt1[i]=(source[i]>>11)&0x1f; // destination
8640 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8641 us1[i]=rs1[i];us2[i]=rs2[i];
8643 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8644 dep1[i]=rs1[i];dep2[i]=rs2[i];
8646 else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8647 dep1[i]=rs1[i];dep2[i]=rs2[i];
8651 rs1[i]=(source[i]>>21)&0x1f; // source
8652 rs2[i]=(source[i]>>16)&0x1f; // divisor
8655 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8656 us1[i]=rs1[i];us2[i]=rs2[i];
8664 if(op2==0x10) rs1[i]=HIREG; // MFHI
8665 if(op2==0x11) rt1[i]=HIREG; // MTHI
8666 if(op2==0x12) rs1[i]=LOREG; // MFLO
8667 if(op2==0x13) rt1[i]=LOREG; // MTLO
8668 if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8669 if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8673 rs1[i]=(source[i]>>16)&0x1f; // target of shift
8674 rs2[i]=(source[i]>>21)&0x1f; // shift amount
8675 rt1[i]=(source[i]>>11)&0x1f; // destination
8677 // DSLLV/DSRLV/DSRAV are 64-bit
8678 if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8681 rs1[i]=(source[i]>>16)&0x1f;
8683 rt1[i]=(source[i]>>11)&0x1f;
8685 imm[i]=(source[i]>>6)&0x1f;
8686 // DSxx32 instructions
8687 if(op2>=0x3c) imm[i]|=0x20;
8688 // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8689 if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8696 if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8697 if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8698 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8699 if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8706 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8707 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8708 if(op2==5) us1[i]=rs1[i]; // DMTC1
8716 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC2/CFC2
8717 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC2/CTC2
8719 int gr=(source[i]>>11)&0x1F;
8722 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
8723 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
8724 case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
8725 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
8729 rs1[i]=(source[i]>>21)&0x1F;
8733 imm[i]=(short)source[i];
8736 rs1[i]=(source[i]>>21)&0x1F;
8740 imm[i]=(short)source[i];
8741 if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
8742 else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
8749 gte_rs[i]=gte_reg_reads[source[i]&0x3f];
8750 gte_rt[i]=gte_reg_writes[source[i]&0x3f];
8751 gte_rt[i]|=1ll<<63; // every op changes flags
8752 if((source[i]&0x3f)==GTE_MVMVA) {
8753 int v = (source[i] >> 15) & 3;
8754 gte_rs[i]&=~0xe3fll;
8755 if(v==3) gte_rs[i]|=0xe00ll;
8756 else gte_rs[i]|=3ll<<(v*2);
8786 /* Calculate branch target addresses */
8788 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8789 else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8790 ba[i]=start+i*4+8; // Ignore never taken branch
8791 else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8792 ba[i]=start+i*4+8; // Ignore never taken branch
8793 else if(type==CJUMP||type==SJUMP||type==FJUMP)
8794 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8797 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
8799 // branch in delay slot?
8800 if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8801 // don't handle first branch and call interpreter if it's hit
8802 printf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
8805 // basic load delay detection
8806 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
8807 int t=(ba[i-1]-start)/4;
8808 if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
8809 // jump target wants DS result - potential load delay effect
8810 printf("load delay @%08x (%08x)\n", addr + i*4, addr);
8812 bt[t+1]=1; // expected return from interpreter
8814 else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
8815 !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
8816 // v0 overwrite like this is a sign of trouble, bail out
8817 printf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
8823 rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
8827 i--; // don't compile the DS
8831 /* Is this the end of the block? */
8832 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8833 if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8837 if(stop_after_jal) done=1;
8839 if((source[i+1]&0xfc00003f)==0x0d) done=1;
8841 // Don't recompile stuff that's already compiled
8842 if(check_addr(start+i*4+4)) done=1;
8843 // Don't get too close to the limit
8844 if(i>MAXBLOCK/2) done=1;
8846 if(itype[i]==SYSCALL&&stop_after_jal) done=1;
8847 if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8849 // Does the block continue due to a branch?
8852 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
8853 if(ba[j]==start+i*4+4) done=j=0;
8854 if(ba[j]==start+i*4+8) done=j=0;
8857 //assert(i<MAXBLOCK-1);
8858 if(start+i*4==pagelimit-4) done=1;
8859 assert(start+i*4<pagelimit);
8860 if (i==MAXBLOCK-1) done=1;
8861 // Stop if we're compiling junk
8862 if(itype[i]==NI&&opcode[i]==0x11) {
8863 done=stop_after_jal=1;
8864 printf("Disabled speculative precompilation\n");
8868 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8869 if(start+i*4==pagelimit) {
8875 /* Pass 2 - Register dependencies and branch targets */
8877 unneeded_registers(0,slen-1,0);
8879 /* Pass 3 - Register allocation */
8881 struct regstat current; // Current register allocations/status
8884 current.u=unneeded_reg[0];
8885 current.uu=unneeded_reg_upper[0];
8886 clear_all_regs(current.regmap);
8887 alloc_reg(¤t,0,CCREG);
8888 dirty_reg(¤t,CCREG);
8891 current.waswritten=0;
8897 provisional_32bit();
8900 // First instruction is delay slot
8905 unneeded_reg_upper[0]=1;
8906 current.regmap[HOST_BTREG]=BTREG;
8914 for(hr=0;hr<HOST_REGS;hr++)
8916 // Is this really necessary?
8917 if(current.regmap[hr]==0) current.regmap[hr]=-1;
8920 current.waswritten=0;
8924 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8926 if(rs1[i-2]==0||rs2[i-2]==0)
8929 current.is32|=1LL<<rs1[i-2];
8930 int hr=get_reg(current.regmap,rs1[i-2]|64);
8931 if(hr>=0) current.regmap[hr]=-1;
8934 current.is32|=1LL<<rs2[i-2];
8935 int hr=get_reg(current.regmap,rs2[i-2]|64);
8936 if(hr>=0) current.regmap[hr]=-1;
8942 // If something jumps here with 64-bit values
8943 // then promote those registers to 64 bits
8946 uint64_t temp_is32=current.is32;
8949 if(ba[j]==start+i*4)
8950 temp_is32&=branch_regs[j].is32;
8954 if(ba[j]==start+i*4)
8958 if(temp_is32!=current.is32) {
8959 //printf("dumping 32-bit regs (%x)\n",start+i*4);
8960 #ifndef DESTRUCTIVE_WRITEBACK
8963 for(hr=0;hr<HOST_REGS;hr++)
8965 int r=current.regmap[hr];
8968 if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8970 //printf("restore %d\n",r);
8974 current.is32=temp_is32;
8981 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8982 regs[i].wasconst=current.isconst;
8983 regs[i].was32=current.is32;
8984 regs[i].wasdirty=current.dirty;
8985 regs[i].loadedconst=0;
8986 #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
8987 // To change a dirty register from 32 to 64 bits, we must write
8988 // it out during the previous cycle (for branches, 2 cycles)
8989 if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8991 uint64_t temp_is32=current.is32;
8994 if(ba[j]==start+i*4+4)
8995 temp_is32&=branch_regs[j].is32;
8999 if(ba[j]==start+i*4+4)
9003 if(temp_is32!=current.is32) {
9004 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
9005 for(hr=0;hr<HOST_REGS;hr++)
9007 int r=current.regmap[hr];
9010 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
9011 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
9013 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
9015 //printf("dump %d/r%d\n",hr,r);
9016 current.regmap[hr]=-1;
9017 if(get_reg(current.regmap,r|64)>=0)
9018 current.regmap[get_reg(current.regmap,r|64)]=-1;
9026 else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
9028 uint64_t temp_is32=current.is32;
9031 if(ba[j]==start+i*4+8)
9032 temp_is32&=branch_regs[j].is32;
9036 if(ba[j]==start+i*4+8)
9040 if(temp_is32!=current.is32) {
9041 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
9042 for(hr=0;hr<HOST_REGS;hr++)
9044 int r=current.regmap[hr];
9047 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
9048 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
9050 //printf("dump %d/r%d\n",hr,r);
9051 current.regmap[hr]=-1;
9052 if(get_reg(current.regmap,r|64)>=0)
9053 current.regmap[get_reg(current.regmap,r|64)]=-1;
9061 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9063 current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9064 current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9065 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9074 current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
9075 current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9076 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9077 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
9078 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9081 } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
9085 ds=0; // Skip delay slot, already allocated as part of branch
9086 // ...but we need to alloc it in case something jumps here
9088 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
9089 current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
9091 current.u=branch_unneeded_reg[i-1];
9092 current.uu=branch_unneeded_reg_upper[i-1];
9094 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
9095 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9096 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9099 struct regstat temp;
9100 memcpy(&temp,¤t,sizeof(current));
9101 temp.wasdirty=temp.dirty;
9102 temp.was32=temp.is32;
9103 // TODO: Take into account unconditional branches, as below
9104 delayslot_alloc(&temp,i);
9105 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
9106 regs[i].wasdirty=temp.wasdirty;
9107 regs[i].was32=temp.was32;
9108 regs[i].dirty=temp.dirty;
9109 regs[i].is32=temp.is32;
9113 // Create entry (branch target) regmap
9114 for(hr=0;hr<HOST_REGS;hr++)
9116 int r=temp.regmap[hr];
9118 if(r!=regmap_pre[i][hr]) {
9119 regs[i].regmap_entry[hr]=-1;
9124 if((current.u>>r)&1) {
9125 regs[i].regmap_entry[hr]=-1;
9126 regs[i].regmap[hr]=-1;
9127 //Don't clear regs in the delay slot as the branch might need them
9128 //current.regmap[hr]=-1;
9130 regs[i].regmap_entry[hr]=r;
9133 if((current.uu>>(r&63))&1) {
9134 regs[i].regmap_entry[hr]=-1;
9135 regs[i].regmap[hr]=-1;
9136 //Don't clear regs in the delay slot as the branch might need them
9137 //current.regmap[hr]=-1;
9139 regs[i].regmap_entry[hr]=r;
9143 // First instruction expects CCREG to be allocated
9144 if(i==0&&hr==HOST_CCREG)
9145 regs[i].regmap_entry[hr]=CCREG;
9147 regs[i].regmap_entry[hr]=-1;
9151 else { // Not delay slot
9154 //current.isconst=0; // DEBUG
9155 //current.wasconst=0; // DEBUG
9156 //regs[i].wasconst=0; // DEBUG
9157 clear_const(¤t,rt1[i]);
9158 alloc_cc(¤t,i);
9159 dirty_reg(¤t,CCREG);
9161 alloc_reg(¤t,i,31);
9162 dirty_reg(¤t,31);
9163 //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
9164 //assert(rt1[i+1]!=rt1[i]);
9166 alloc_reg(¤t,i,PTEMP);
9168 //current.is32|=1LL<<rt1[i];
9171 delayslot_alloc(¤t,i+1);
9172 //current.isconst=0; // DEBUG
9174 //printf("i=%d, isconst=%x\n",i,current.isconst);
9177 //current.isconst=0;
9178 //current.wasconst=0;
9179 //regs[i].wasconst=0;
9180 clear_const(¤t,rs1[i]);
9181 clear_const(¤t,rt1[i]);
9182 alloc_cc(¤t,i);
9183 dirty_reg(¤t,CCREG);
9184 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
9185 alloc_reg(¤t,i,rs1[i]);
9187 alloc_reg(¤t,i,rt1[i]);
9188 dirty_reg(¤t,rt1[i]);
9189 assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
9190 assert(rt1[i+1]!=rt1[i]);
9192 alloc_reg(¤t,i,PTEMP);
9196 if(rs1[i]==31) { // JALR
9197 alloc_reg(¤t,i,RHASH);
9198 #ifndef HOST_IMM_ADDR32
9199 alloc_reg(¤t,i,RHTBL);
9203 delayslot_alloc(¤t,i+1);
9205 // The delay slot overwrites our source register,
9206 // allocate a temporary register to hold the old value.
9210 delayslot_alloc(¤t,i+1);
9212 alloc_reg(¤t,i,RTEMP);
9214 //current.isconst=0; // DEBUG
9219 //current.isconst=0;
9220 //current.wasconst=0;
9221 //regs[i].wasconst=0;
9222 clear_const(¤t,rs1[i]);
9223 clear_const(¤t,rs2[i]);
9224 if((opcode[i]&0x3E)==4) // BEQ/BNE
9226 alloc_cc(¤t,i);
9227 dirty_reg(¤t,CCREG);
9228 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9229 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
9230 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9232 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9233 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
9235 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
9236 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
9237 // The delay slot overwrites one of our conditions.
9238 // Allocate the branch condition registers instead.
9242 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9243 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
9244 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9246 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9247 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
9253 delayslot_alloc(¤t,i+1);
9257 if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
9259 alloc_cc(¤t,i);
9260 dirty_reg(¤t,CCREG);
9261 alloc_reg(¤t,i,rs1[i]);
9262 if(!(current.is32>>rs1[i]&1))
9264 alloc_reg64(¤t,i,rs1[i]);
9266 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
9267 // The delay slot overwrites one of our conditions.
9268 // Allocate the branch condition registers instead.
9272 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9273 if(!((current.is32>>rs1[i])&1))
9275 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9281 delayslot_alloc(¤t,i+1);
9285 // Don't alloc the delay slot yet because we might not execute it
9286 if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
9291 alloc_cc(¤t,i);
9292 dirty_reg(¤t,CCREG);
9293 alloc_reg(¤t,i,rs1[i]);
9294 alloc_reg(¤t,i,rs2[i]);
9295 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9297 alloc_reg64(¤t,i,rs1[i]);
9298 alloc_reg64(¤t,i,rs2[i]);
9302 if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
9307 alloc_cc(¤t,i);
9308 dirty_reg(¤t,CCREG);
9309 alloc_reg(¤t,i,rs1[i]);
9310 if(!(current.is32>>rs1[i]&1))
9312 alloc_reg64(¤t,i,rs1[i]);
9316 //current.isconst=0;
9319 //current.isconst=0;
9320 //current.wasconst=0;
9321 //regs[i].wasconst=0;
9322 clear_const(¤t,rs1[i]);
9323 clear_const(¤t,rt1[i]);
9324 //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
9325 if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
9327 alloc_cc(¤t,i);
9328 dirty_reg(¤t,CCREG);
9329 alloc_reg(¤t,i,rs1[i]);
9330 if(!(current.is32>>rs1[i]&1))
9332 alloc_reg64(¤t,i,rs1[i]);
9334 if (rt1[i]==31) { // BLTZAL/BGEZAL
9335 alloc_reg(¤t,i,31);
9336 dirty_reg(¤t,31);
9337 //#ifdef REG_PREFETCH
9338 //alloc_reg(¤t,i,PTEMP);
9340 //current.is32|=1LL<<rt1[i];
9342 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
9343 ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
9344 // Allocate the branch condition registers instead.
9348 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9349 if(!((current.is32>>rs1[i])&1))
9351 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9357 delayslot_alloc(¤t,i+1);
9361 // Don't alloc the delay slot yet because we might not execute it
9362 if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
9367 alloc_cc(¤t,i);
9368 dirty_reg(¤t,CCREG);
9369 alloc_reg(¤t,i,rs1[i]);
9370 if(!(current.is32>>rs1[i]&1))
9372 alloc_reg64(¤t,i,rs1[i]);
9376 //current.isconst=0;
9382 if(likely[i]==0) // BC1F/BC1T
9384 // TODO: Theoretically we can run out of registers here on x86.
9385 // The delay slot can allocate up to six, and we need to check
9386 // CSREG before executing the delay slot. Possibly we can drop
9387 // the cycle count and then reload it after checking that the
9388 // FPU is in a usable state, or don't do out-of-order execution.
9389 alloc_cc(¤t,i);
9390 dirty_reg(¤t,CCREG);
9391 alloc_reg(¤t,i,FSREG);
9392 alloc_reg(¤t,i,CSREG);
9393 if(itype[i+1]==FCOMP) {
9394 // The delay slot overwrites the branch condition.
9395 // Allocate the branch condition registers instead.
9396 alloc_cc(¤t,i);
9397 dirty_reg(¤t,CCREG);
9398 alloc_reg(¤t,i,CSREG);
9399 alloc_reg(¤t,i,FSREG);
9403 delayslot_alloc(¤t,i+1);
9404 alloc_reg(¤t,i+1,CSREG);
9408 // Don't alloc the delay slot yet because we might not execute it
9409 if(likely[i]) // BC1FL/BC1TL
9411 alloc_cc(¤t,i);
9412 dirty_reg(¤t,CCREG);
9413 alloc_reg(¤t,i,CSREG);
9414 alloc_reg(¤t,i,FSREG);
9420 imm16_alloc(¤t,i);
9424 load_alloc(¤t,i);
9428 store_alloc(¤t,i);
9431 alu_alloc(¤t,i);
9434 shift_alloc(¤t,i);
9437 multdiv_alloc(¤t,i);
9440 shiftimm_alloc(¤t,i);
9443 mov_alloc(¤t,i);
9446 cop0_alloc(¤t,i);
9450 cop1_alloc(¤t,i);
9453 c1ls_alloc(¤t,i);
9456 c2ls_alloc(¤t,i);
9459 c2op_alloc(¤t,i);
9462 fconv_alloc(¤t,i);
9465 float_alloc(¤t,i);
9468 fcomp_alloc(¤t,i);
9473 syscall_alloc(¤t,i);
9476 pagespan_alloc(¤t,i);
9480 // Drop the upper half of registers that have become 32-bit
9481 current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9482 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9483 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9484 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9487 current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9488 current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9489 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9490 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9494 // Create entry (branch target) regmap
9495 for(hr=0;hr<HOST_REGS;hr++)
9498 r=current.regmap[hr];
9500 if(r!=regmap_pre[i][hr]) {
9501 // TODO: delay slot (?)
9502 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9503 if(or<0||(r&63)>=TEMPREG){
9504 regs[i].regmap_entry[hr]=-1;
9508 // Just move it to a different register
9509 regs[i].regmap_entry[hr]=r;
9510 // If it was dirty before, it's still dirty
9511 if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r&63);
9518 regs[i].regmap_entry[hr]=0;
9522 if((current.u>>r)&1) {
9523 regs[i].regmap_entry[hr]=-1;
9524 //regs[i].regmap[hr]=-1;
9525 current.regmap[hr]=-1;
9527 regs[i].regmap_entry[hr]=r;
9530 if((current.uu>>(r&63))&1) {
9531 regs[i].regmap_entry[hr]=-1;
9532 //regs[i].regmap[hr]=-1;
9533 current.regmap[hr]=-1;
9535 regs[i].regmap_entry[hr]=r;
9539 // Branches expect CCREG to be allocated at the target
9540 if(regmap_pre[i][hr]==CCREG)
9541 regs[i].regmap_entry[hr]=CCREG;
9543 regs[i].regmap_entry[hr]=-1;
9546 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9549 if(i>0&&(itype[i-1]==STORE||itype[i-1]==STORELR||(itype[i-1]==C2LS&&opcode[i-1]==0x3a))&&(u_int)imm[i-1]<0x800)
9550 current.waswritten|=1<<rs1[i-1];
9551 current.waswritten&=~(1<<rt1[i]);
9552 current.waswritten&=~(1<<rt2[i]);
9553 if((itype[i]==STORE||itype[i]==STORELR||(itype[i]==C2LS&&opcode[i]==0x3a))&&(u_int)imm[i]>=0x800)
9554 current.waswritten&=~(1<<rs1[i]);
9556 /* Branch post-alloc */
9559 current.was32=current.is32;
9560 current.wasdirty=current.dirty;
9561 switch(itype[i-1]) {
9563 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9564 branch_regs[i-1].isconst=0;
9565 branch_regs[i-1].wasconst=0;
9566 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9567 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9568 alloc_cc(&branch_regs[i-1],i-1);
9569 dirty_reg(&branch_regs[i-1],CCREG);
9570 if(rt1[i-1]==31) { // JAL
9571 alloc_reg(&branch_regs[i-1],i-1,31);
9572 dirty_reg(&branch_regs[i-1],31);
9573 branch_regs[i-1].is32|=1LL<<31;
9575 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9576 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9579 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9580 branch_regs[i-1].isconst=0;
9581 branch_regs[i-1].wasconst=0;
9582 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9583 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9584 alloc_cc(&branch_regs[i-1],i-1);
9585 dirty_reg(&branch_regs[i-1],CCREG);
9586 alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9587 if(rt1[i-1]!=0) { // JALR
9588 alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9589 dirty_reg(&branch_regs[i-1],rt1[i-1]);
9590 branch_regs[i-1].is32|=1LL<<rt1[i-1];
9593 if(rs1[i-1]==31) { // JALR
9594 alloc_reg(&branch_regs[i-1],i-1,RHASH);
9595 #ifndef HOST_IMM_ADDR32
9596 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9600 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9601 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9604 if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9606 alloc_cc(¤t,i-1);
9607 dirty_reg(¤t,CCREG);
9608 if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9609 (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9610 // The delay slot overwrote one of our conditions
9611 // Delay slot goes after the test (in order)
9612 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9613 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9614 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9617 delayslot_alloc(¤t,i);
9622 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9623 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9624 // Alloc the branch condition registers
9625 if(rs1[i-1]) alloc_reg(¤t,i-1,rs1[i-1]);
9626 if(rs2[i-1]) alloc_reg(¤t,i-1,rs2[i-1]);
9627 if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9629 if(rs1[i-1]) alloc_reg64(¤t,i-1,rs1[i-1]);
9630 if(rs2[i-1]) alloc_reg64(¤t,i-1,rs2[i-1]);
9633 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9634 branch_regs[i-1].isconst=0;
9635 branch_regs[i-1].wasconst=0;
9636 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9637 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9640 if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9642 alloc_cc(¤t,i-1);
9643 dirty_reg(¤t,CCREG);
9644 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9645 // The delay slot overwrote the branch condition
9646 // Delay slot goes after the test (in order)
9647 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9648 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9649 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9652 delayslot_alloc(¤t,i);
9657 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9658 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9659 // Alloc the branch condition register
9660 alloc_reg(¤t,i-1,rs1[i-1]);
9661 if(!(current.is32>>rs1[i-1]&1))
9663 alloc_reg64(¤t,i-1,rs1[i-1]);
9666 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9667 branch_regs[i-1].isconst=0;
9668 branch_regs[i-1].wasconst=0;
9669 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9670 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9673 // Alloc the delay slot in case the branch is taken
9674 if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9676 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9677 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9678 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9679 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9680 alloc_cc(&branch_regs[i-1],i);
9681 dirty_reg(&branch_regs[i-1],CCREG);
9682 delayslot_alloc(&branch_regs[i-1],i);
9683 branch_regs[i-1].isconst=0;
9684 alloc_reg(¤t,i,CCREG); // Not taken path
9685 dirty_reg(¤t,CCREG);
9686 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9689 if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9691 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9692 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9693 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9694 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9695 alloc_cc(&branch_regs[i-1],i);
9696 dirty_reg(&branch_regs[i-1],CCREG);
9697 delayslot_alloc(&branch_regs[i-1],i);
9698 branch_regs[i-1].isconst=0;
9699 alloc_reg(¤t,i,CCREG); // Not taken path
9700 dirty_reg(¤t,CCREG);
9701 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9705 //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9706 if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9708 alloc_cc(¤t,i-1);
9709 dirty_reg(¤t,CCREG);
9710 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9711 // The delay slot overwrote the branch condition
9712 // Delay slot goes after the test (in order)
9713 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9714 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9715 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9718 delayslot_alloc(¤t,i);
9723 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9724 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9725 // Alloc the branch condition register
9726 alloc_reg(¤t,i-1,rs1[i-1]);
9727 if(!(current.is32>>rs1[i-1]&1))
9729 alloc_reg64(¤t,i-1,rs1[i-1]);
9732 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9733 branch_regs[i-1].isconst=0;
9734 branch_regs[i-1].wasconst=0;
9735 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9736 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9739 // Alloc the delay slot in case the branch is taken
9740 if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9742 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9743 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9744 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9745 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9746 alloc_cc(&branch_regs[i-1],i);
9747 dirty_reg(&branch_regs[i-1],CCREG);
9748 delayslot_alloc(&branch_regs[i-1],i);
9749 branch_regs[i-1].isconst=0;
9750 alloc_reg(¤t,i,CCREG); // Not taken path
9751 dirty_reg(¤t,CCREG);
9752 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9754 // FIXME: BLTZAL/BGEZAL
9755 if(opcode2[i-1]&0x10) { // BxxZAL
9756 alloc_reg(&branch_regs[i-1],i-1,31);
9757 dirty_reg(&branch_regs[i-1],31);
9758 branch_regs[i-1].is32|=1LL<<31;
9762 if(likely[i-1]==0) // BC1F/BC1T
9764 alloc_cc(¤t,i-1);
9765 dirty_reg(¤t,CCREG);
9766 if(itype[i]==FCOMP) {
9767 // The delay slot overwrote the branch condition
9768 // Delay slot goes after the test (in order)
9769 delayslot_alloc(¤t,i);
9774 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9775 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9776 // Alloc the branch condition register
9777 alloc_reg(¤t,i-1,FSREG);
9779 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9780 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9784 // Alloc the delay slot in case the branch is taken
9785 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9786 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9787 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9788 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9789 alloc_cc(&branch_regs[i-1],i);
9790 dirty_reg(&branch_regs[i-1],CCREG);
9791 delayslot_alloc(&branch_regs[i-1],i);
9792 branch_regs[i-1].isconst=0;
9793 alloc_reg(¤t,i,CCREG); // Not taken path
9794 dirty_reg(¤t,CCREG);
9795 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9800 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9802 if(rt1[i-1]==31) // JAL/JALR
9804 // Subroutine call will return here, don't alloc any registers
9807 clear_all_regs(current.regmap);
9808 alloc_reg(¤t,i,CCREG);
9809 dirty_reg(¤t,CCREG);
9813 // Internal branch will jump here, match registers to caller
9814 current.is32=0x3FFFFFFFFLL;
9816 clear_all_regs(current.regmap);
9817 alloc_reg(¤t,i,CCREG);
9818 dirty_reg(¤t,CCREG);
9821 if(ba[j]==start+i*4+4) {
9822 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9823 current.is32=branch_regs[j].is32;
9824 current.dirty=branch_regs[j].dirty;
9829 if(ba[j]==start+i*4+4) {
9830 for(hr=0;hr<HOST_REGS;hr++) {
9831 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9832 current.regmap[hr]=-1;
9834 current.is32&=branch_regs[j].is32;
9835 current.dirty&=branch_regs[j].dirty;
9844 // Count cycles in between branches
9846 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9850 #if defined(PCSX) && !defined(DRC_DBG)
9851 else if(itype[i]==C2OP&>e_cycletab[source[i]&0x3f]>2)
9853 // GTE runs in parallel until accessed, divide by 2 for a rough guess
9854 cc+=gte_cycletab[source[i]&0x3f]/2;
9856 else if(/*itype[i]==LOAD||*/itype[i]==STORE||itype[i]==C1LS) // load causes weird timing issues
9858 cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
9860 else if(itype[i]==C2LS)
9870 flush_dirty_uppers(¤t);
9872 regs[i].is32=current.is32;
9873 regs[i].dirty=current.dirty;
9874 regs[i].isconst=current.isconst;
9875 memcpy(constmap[i],current_constmap,sizeof(current_constmap));
9877 for(hr=0;hr<HOST_REGS;hr++) {
9878 if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) {
9879 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9880 regs[i].wasconst&=~(1<<hr);
9884 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9885 regs[i].waswritten=current.waswritten;
9888 /* Pass 4 - Cull unused host registers */
9892 for (i=slen-1;i>=0;i--)
9895 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9897 if(ba[i]<start || ba[i]>=(start+slen*4))
9899 // Branch out of this block, don't need anything
9905 // Need whatever matches the target
9907 int t=(ba[i]-start)>>2;
9908 for(hr=0;hr<HOST_REGS;hr++)
9910 if(regs[i].regmap_entry[hr]>=0) {
9911 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9915 // Conditional branch may need registers for following instructions
9916 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9919 nr|=needed_reg[i+2];
9920 for(hr=0;hr<HOST_REGS;hr++)
9922 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9923 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9927 // Don't need stuff which is overwritten
9928 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9929 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9930 // Merge in delay slot
9931 for(hr=0;hr<HOST_REGS;hr++)
9934 // These are overwritten unless the branch is "likely"
9935 // and the delay slot is nullified if not taken
9936 if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9937 if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9939 if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9940 if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9941 if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9942 if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9943 if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9944 if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9945 if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9946 if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9947 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9948 if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9949 if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9951 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9952 if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9953 if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9955 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
9956 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9957 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9961 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
9963 // SYSCALL instruction (software interrupt)
9966 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9968 // ERET instruction (return from interrupt)
9974 for(hr=0;hr<HOST_REGS;hr++) {
9975 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9976 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9977 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9978 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9982 for(hr=0;hr<HOST_REGS;hr++)
9984 // Overwritten registers are not needed
9985 if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9986 if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9987 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9988 // Source registers are needed
9989 if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9990 if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9991 if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9992 if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9993 if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9994 if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9995 if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9996 if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9997 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9998 if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9999 if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10001 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
10002 if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
10003 if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10005 if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
10006 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
10007 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
10009 // Don't store a register immediately after writing it,
10010 // may prevent dual-issue.
10011 // But do so if this is a branch target, otherwise we
10012 // might have to load the register before the branch.
10013 if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
10014 if((regmap_pre[i][hr]>0&®map_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
10015 (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
10016 if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
10017 if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
10019 if((regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
10020 (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
10021 if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10022 if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10026 // Cycle count is needed at branches. Assume it is needed at the target too.
10027 if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
10028 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
10029 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
10034 // Deallocate unneeded registers
10035 for(hr=0;hr<HOST_REGS;hr++)
10037 if(!((nr>>hr)&1)) {
10038 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
10039 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
10040 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10041 (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
10043 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10046 regs[i].regmap[hr]=-1;
10047 regs[i].isconst&=~(1<<hr);
10049 regmap_pre[i+2][hr]=-1;
10050 regs[i+2].wasconst&=~(1<<hr);
10055 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10057 int d1=0,d2=0,map=0,temp=0;
10058 if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
10064 if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
10065 itype[i+1]==STORE || itype[i+1]==STORELR ||
10066 itype[i+1]==C1LS || itype[i+1]==C2LS)
10069 if(itype[i+1]==STORE || itype[i+1]==STORELR ||
10070 (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
10073 if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
10074 itype[i+1]==C1LS || itype[i+1]==C2LS)
10076 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
10077 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10078 (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
10079 (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
10080 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
10081 regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
10082 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
10083 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
10084 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
10085 regs[i].regmap[hr]!=map )
10087 regs[i].regmap[hr]=-1;
10088 regs[i].isconst&=~(1<<hr);
10089 if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
10090 (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
10091 (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
10092 (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
10093 (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
10094 branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
10095 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
10096 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
10097 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
10098 branch_regs[i].regmap[hr]!=map)
10100 branch_regs[i].regmap[hr]=-1;
10101 branch_regs[i].regmap_entry[hr]=-1;
10102 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10104 if(!likely[i]&&i<slen-2) {
10105 regmap_pre[i+2][hr]=-1;
10106 regs[i+2].wasconst&=~(1<<hr);
10117 int d1=0,d2=0,map=-1,temp=-1;
10118 if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
10124 if(itype[i]==LOAD || itype[i]==LOADLR ||
10125 itype[i]==STORE || itype[i]==STORELR ||
10126 itype[i]==C1LS || itype[i]==C2LS)
10128 } else if(itype[i]==STORE || itype[i]==STORELR ||
10129 (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
10132 if(itype[i]==LOADLR || itype[i]==STORELR ||
10133 itype[i]==C1LS || itype[i]==C2LS)
10135 if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10136 (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
10137 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
10138 regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
10139 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
10140 (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
10142 if(i<slen-1&&!is_ds[i]) {
10143 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
10144 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
10145 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
10147 printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
10148 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
10150 regmap_pre[i+1][hr]=-1;
10151 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
10152 regs[i+1].wasconst&=~(1<<hr);
10154 regs[i].regmap[hr]=-1;
10155 regs[i].isconst&=~(1<<hr);
10163 /* Pass 5 - Pre-allocate registers */
10165 // If a register is allocated during a loop, try to allocate it for the
10166 // entire loop, if possible. This avoids loading/storing registers
10167 // inside of the loop.
10169 signed char f_regmap[HOST_REGS];
10170 clear_all_regs(f_regmap);
10171 for(i=0;i<slen-1;i++)
10173 if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10175 if(ba[i]>=start && ba[i]<(start+i*4))
10176 if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
10177 ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
10178 ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
10179 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
10180 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
10181 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
10183 int t=(ba[i]-start)>>2;
10184 if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
10185 if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
10186 for(hr=0;hr<HOST_REGS;hr++)
10188 if(regs[i].regmap[hr]>64) {
10189 if(!((regs[i].dirty>>hr)&1))
10190 f_regmap[hr]=regs[i].regmap[hr];
10191 else f_regmap[hr]=-1;
10193 else if(regs[i].regmap[hr]>=0) {
10194 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10195 // dealloc old register
10197 for(n=0;n<HOST_REGS;n++)
10199 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10201 // and alloc new one
10202 f_regmap[hr]=regs[i].regmap[hr];
10205 if(branch_regs[i].regmap[hr]>64) {
10206 if(!((branch_regs[i].dirty>>hr)&1))
10207 f_regmap[hr]=branch_regs[i].regmap[hr];
10208 else f_regmap[hr]=-1;
10210 else if(branch_regs[i].regmap[hr]>=0) {
10211 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
10212 // dealloc old register
10214 for(n=0;n<HOST_REGS;n++)
10216 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
10218 // and alloc new one
10219 f_regmap[hr]=branch_regs[i].regmap[hr];
10223 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
10224 f_regmap[hr]=branch_regs[i].regmap[hr];
10226 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
10227 f_regmap[hr]=branch_regs[i].regmap[hr];
10229 // Avoid dirty->clean transition
10230 #ifdef DESTRUCTIVE_WRITEBACK
10231 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
10233 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
10234 // case above, however it's always a good idea. We can't hoist the
10235 // load if the register was already allocated, so there's no point
10236 // wasting time analyzing most of these cases. It only "succeeds"
10237 // when the mapping was different and the load can be replaced with
10238 // a mov, which is of negligible benefit. So such cases are
10240 if(f_regmap[hr]>0) {
10241 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
10242 int r=f_regmap[hr];
10245 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10246 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
10247 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
10249 // NB This can exclude the case where the upper-half
10250 // register is lower numbered than the lower-half
10251 // register. Not sure if it's worth fixing...
10252 if(get_reg(regs[j].regmap,r&63)<0) break;
10253 if(get_reg(regs[j].regmap_entry,r&63)<0) break;
10254 if(regs[j].is32&(1LL<<(r&63))) break;
10256 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
10257 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10259 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
10260 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
10262 if(get_reg(regs[i].regmap,r&63)<0) break;
10263 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
10266 while(k>1&®s[k-1].regmap[hr]==-1) {
10267 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10268 //printf("no free regs for store %x\n",start+(k-1)*4);
10271 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
10272 //printf("no-match due to different register\n");
10275 if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
10276 //printf("no-match due to branch\n");
10279 // call/ret fast path assumes no registers allocated
10280 if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
10284 // NB This can exclude the case where the upper-half
10285 // register is lower numbered than the lower-half
10286 // register. Not sure if it's worth fixing...
10287 if(get_reg(regs[k-1].regmap,r&63)<0) break;
10288 if(regs[k-1].is32&(1LL<<(r&63))) break;
10293 if((regs[k].is32&(1LL<<f_regmap[hr]))!=
10294 (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
10295 //printf("bad match after branch\n");
10299 if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) {
10300 //printf("Extend r%d, %x ->\n",hr,start+k*4);
10302 regs[k].regmap_entry[hr]=f_regmap[hr];
10303 regs[k].regmap[hr]=f_regmap[hr];
10304 regmap_pre[k+1][hr]=f_regmap[hr];
10305 regs[k].wasdirty&=~(1<<hr);
10306 regs[k].dirty&=~(1<<hr);
10307 regs[k].wasdirty|=(1<<hr)®s[k-1].dirty;
10308 regs[k].dirty|=(1<<hr)®s[k].wasdirty;
10309 regs[k].wasconst&=~(1<<hr);
10310 regs[k].isconst&=~(1<<hr);
10315 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
10318 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
10319 if(regs[i-1].regmap[hr]==f_regmap[hr]&®map_pre[i][hr]==f_regmap[hr]) {
10320 //printf("OK fill %x (r%d)\n",start+i*4,hr);
10321 regs[i].regmap_entry[hr]=f_regmap[hr];
10322 regs[i].regmap[hr]=f_regmap[hr];
10323 regs[i].wasdirty&=~(1<<hr);
10324 regs[i].dirty&=~(1<<hr);
10325 regs[i].wasdirty|=(1<<hr)®s[i-1].dirty;
10326 regs[i].dirty|=(1<<hr)®s[i-1].dirty;
10327 regs[i].wasconst&=~(1<<hr);
10328 regs[i].isconst&=~(1<<hr);
10329 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
10330 branch_regs[i].wasdirty&=~(1<<hr);
10331 branch_regs[i].wasdirty|=(1<<hr)®s[i].dirty;
10332 branch_regs[i].regmap[hr]=f_regmap[hr];
10333 branch_regs[i].dirty&=~(1<<hr);
10334 branch_regs[i].dirty|=(1<<hr)®s[i].dirty;
10335 branch_regs[i].wasconst&=~(1<<hr);
10336 branch_regs[i].isconst&=~(1<<hr);
10337 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
10338 regmap_pre[i+2][hr]=f_regmap[hr];
10339 regs[i+2].wasdirty&=~(1<<hr);
10340 regs[i+2].wasdirty|=(1<<hr)®s[i].dirty;
10341 assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
10342 (regs[i+2].was32&(1LL<<f_regmap[hr])));
10347 // Alloc register clean at beginning of loop,
10348 // but may dirty it in pass 6
10349 regs[k].regmap_entry[hr]=f_regmap[hr];
10350 regs[k].regmap[hr]=f_regmap[hr];
10351 regs[k].dirty&=~(1<<hr);
10352 regs[k].wasconst&=~(1<<hr);
10353 regs[k].isconst&=~(1<<hr);
10354 if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
10355 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
10356 branch_regs[k].regmap[hr]=f_regmap[hr];
10357 branch_regs[k].dirty&=~(1<<hr);
10358 branch_regs[k].wasconst&=~(1<<hr);
10359 branch_regs[k].isconst&=~(1<<hr);
10360 if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
10361 regmap_pre[k+2][hr]=f_regmap[hr];
10362 regs[k+2].wasdirty&=~(1<<hr);
10363 assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
10364 (regs[k+2].was32&(1LL<<f_regmap[hr])));
10369 regmap_pre[k+1][hr]=f_regmap[hr];
10370 regs[k+1].wasdirty&=~(1<<hr);
10373 if(regs[j].regmap[hr]==f_regmap[hr])
10374 regs[j].regmap_entry[hr]=f_regmap[hr];
10378 if(regs[j].regmap[hr]>=0)
10380 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
10381 //printf("no-match due to different register\n");
10384 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
10385 //printf("32/64 mismatch %x %d\n",start+j*4,hr);
10388 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10390 // Stop on unconditional branch
10393 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
10396 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
10399 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
10402 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
10403 //printf("no-match due to different register (branch)\n");
10407 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10408 //printf("No free regs for store %x\n",start+j*4);
10411 if(f_regmap[hr]>=64) {
10412 if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10417 if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10428 // Non branch or undetermined branch target
10429 for(hr=0;hr<HOST_REGS;hr++)
10431 if(hr!=EXCLUDE_REG) {
10432 if(regs[i].regmap[hr]>64) {
10433 if(!((regs[i].dirty>>hr)&1))
10434 f_regmap[hr]=regs[i].regmap[hr];
10436 else if(regs[i].regmap[hr]>=0) {
10437 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10438 // dealloc old register
10440 for(n=0;n<HOST_REGS;n++)
10442 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10444 // and alloc new one
10445 f_regmap[hr]=regs[i].regmap[hr];
10450 // Try to restore cycle count at branch targets
10452 for(j=i;j<slen-1;j++) {
10453 if(regs[j].regmap[HOST_CCREG]!=-1) break;
10454 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10455 //printf("no free regs for store %x\n",start+j*4);
10459 if(regs[j].regmap[HOST_CCREG]==CCREG) {
10461 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10463 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10464 regs[k].regmap[HOST_CCREG]=CCREG;
10465 regmap_pre[k+1][HOST_CCREG]=CCREG;
10466 regs[k+1].wasdirty|=1<<HOST_CCREG;
10467 regs[k].dirty|=1<<HOST_CCREG;
10468 regs[k].wasconst&=~(1<<HOST_CCREG);
10469 regs[k].isconst&=~(1<<HOST_CCREG);
10472 regs[j].regmap_entry[HOST_CCREG]=CCREG;
10474 // Work backwards from the branch target
10475 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10477 //printf("Extend backwards\n");
10480 while(regs[k-1].regmap[HOST_CCREG]==-1) {
10481 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10482 //printf("no free regs for store %x\n",start+(k-1)*4);
10487 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10488 //printf("Extend CC, %x ->\n",start+k*4);
10490 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10491 regs[k].regmap[HOST_CCREG]=CCREG;
10492 regmap_pre[k+1][HOST_CCREG]=CCREG;
10493 regs[k+1].wasdirty|=1<<HOST_CCREG;
10494 regs[k].dirty|=1<<HOST_CCREG;
10495 regs[k].wasconst&=~(1<<HOST_CCREG);
10496 regs[k].isconst&=~(1<<HOST_CCREG);
10501 //printf("Fail Extend CC, %x ->\n",start+k*4);
10505 if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10506 itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10507 itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
10508 itype[i]!=FCONV&&itype[i]!=FCOMP)
10510 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10515 // Cache memory offset or tlb map pointer if a register is available
10516 #ifndef HOST_IMM_ADDR32
10521 int earliest_available[HOST_REGS];
10522 int loop_start[HOST_REGS];
10523 int score[HOST_REGS];
10524 int end[HOST_REGS];
10525 int reg=using_tlb?MMREG:ROREG;
10528 for(hr=0;hr<HOST_REGS;hr++) {
10529 score[hr]=0;earliest_available[hr]=0;
10530 loop_start[hr]=MAXBLOCK;
10532 for(i=0;i<slen-1;i++)
10534 // Can't do anything if no registers are available
10535 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) {
10536 for(hr=0;hr<HOST_REGS;hr++) {
10537 score[hr]=0;earliest_available[hr]=i+1;
10538 loop_start[hr]=MAXBLOCK;
10541 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10543 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) {
10544 for(hr=0;hr<HOST_REGS;hr++) {
10545 score[hr]=0;earliest_available[hr]=i+1;
10546 loop_start[hr]=MAXBLOCK;
10550 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) {
10551 for(hr=0;hr<HOST_REGS;hr++) {
10552 score[hr]=0;earliest_available[hr]=i+1;
10553 loop_start[hr]=MAXBLOCK;
10558 // Mark unavailable registers
10559 for(hr=0;hr<HOST_REGS;hr++) {
10560 if(regs[i].regmap[hr]>=0) {
10561 score[hr]=0;earliest_available[hr]=i+1;
10562 loop_start[hr]=MAXBLOCK;
10564 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10565 if(branch_regs[i].regmap[hr]>=0) {
10566 score[hr]=0;earliest_available[hr]=i+2;
10567 loop_start[hr]=MAXBLOCK;
10571 // No register allocations after unconditional jumps
10572 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10574 for(hr=0;hr<HOST_REGS;hr++) {
10575 score[hr]=0;earliest_available[hr]=i+2;
10576 loop_start[hr]=MAXBLOCK;
10578 i++; // Skip delay slot too
10579 //printf("skip delay slot: %x\n",start+i*4);
10583 if(itype[i]==LOAD||itype[i]==LOADLR||
10584 itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
10585 for(hr=0;hr<HOST_REGS;hr++) {
10586 if(hr!=EXCLUDE_REG) {
10588 for(j=i;j<slen-1;j++) {
10589 if(regs[j].regmap[hr]>=0) break;
10590 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10591 if(branch_regs[j].regmap[hr]>=0) break;
10593 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break;
10595 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break;
10598 else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break;
10599 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10600 int t=(ba[j]-start)>>2;
10601 if(t<j&&t>=earliest_available[hr]) {
10602 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated
10603 // Score a point for hoisting loop invariant
10604 if(t<loop_start[hr]) loop_start[hr]=t;
10605 //printf("set loop_start: i=%x j=%x (%x)\n",start+i*4,start+j*4,start+t*4);
10611 if(regs[t].regmap[hr]==reg) {
10612 // Score a point if the branch target matches this register
10617 if(itype[j+1]==LOAD||itype[j+1]==LOADLR||
10618 itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) {
10623 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10625 // Stop on unconditional branch
10629 if(itype[j]==LOAD||itype[j]==LOADLR||
10630 itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) {
10637 // Find highest score and allocate that register
10639 for(hr=0;hr<HOST_REGS;hr++) {
10640 if(hr!=EXCLUDE_REG) {
10641 if(score[hr]>score[maxscore]) {
10643 //printf("highest score: %d %d (%x->%x)\n",score[hr],hr,start+i*4,start+end[hr]*4);
10647 if(score[maxscore]>1)
10649 if(i<loop_start[maxscore]) loop_start[maxscore]=i;
10650 for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) {
10651 //if(regs[j].regmap[maxscore]>=0) {printf("oops: %x %x was %d=%d\n",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);}
10652 assert(regs[j].regmap[maxscore]<0);
10653 if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg;
10654 regs[j].regmap[maxscore]=reg;
10655 regs[j].dirty&=~(1<<maxscore);
10656 regs[j].wasconst&=~(1<<maxscore);
10657 regs[j].isconst&=~(1<<maxscore);
10658 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10659 branch_regs[j].regmap[maxscore]=reg;
10660 branch_regs[j].wasdirty&=~(1<<maxscore);
10661 branch_regs[j].dirty&=~(1<<maxscore);
10662 branch_regs[j].wasconst&=~(1<<maxscore);
10663 branch_regs[j].isconst&=~(1<<maxscore);
10664 if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) {
10665 regmap_pre[j+2][maxscore]=reg;
10666 regs[j+2].wasdirty&=~(1<<maxscore);
10668 // loop optimization (loop_preload)
10669 int t=(ba[j]-start)>>2;
10670 if(t==loop_start[maxscore]) {
10671 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated
10672 regs[t].regmap_entry[maxscore]=reg;
10677 if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) {
10678 regmap_pre[j+1][maxscore]=reg;
10679 regs[j+1].wasdirty&=~(1<<maxscore);
10684 if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot
10685 for(hr=0;hr<HOST_REGS;hr++) {
10686 score[hr]=0;earliest_available[hr]=i+i;
10687 loop_start[hr]=MAXBLOCK;
10695 // This allocates registers (if possible) one instruction prior
10696 // to use, which can avoid a load-use penalty on certain CPUs.
10697 for(i=0;i<slen-1;i++)
10699 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10703 if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10704 ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
10707 if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10709 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10711 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10712 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10713 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10714 regs[i].isconst&=~(1<<hr);
10715 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10716 constmap[i][hr]=constmap[i+1][hr];
10717 regs[i+1].wasdirty&=~(1<<hr);
10718 regs[i].dirty&=~(1<<hr);
10723 if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10725 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10727 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10728 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10729 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10730 regs[i].isconst&=~(1<<hr);
10731 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10732 constmap[i][hr]=constmap[i+1][hr];
10733 regs[i+1].wasdirty&=~(1<<hr);
10734 regs[i].dirty&=~(1<<hr);
10738 // Preload target address for load instruction (non-constant)
10739 if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10740 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10742 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10744 regs[i].regmap[hr]=rs1[i+1];
10745 regmap_pre[i+1][hr]=rs1[i+1];
10746 regs[i+1].regmap_entry[hr]=rs1[i+1];
10747 regs[i].isconst&=~(1<<hr);
10748 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10749 constmap[i][hr]=constmap[i+1][hr];
10750 regs[i+1].wasdirty&=~(1<<hr);
10751 regs[i].dirty&=~(1<<hr);
10755 // Load source into target register
10756 if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10757 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10759 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10761 regs[i].regmap[hr]=rs1[i+1];
10762 regmap_pre[i+1][hr]=rs1[i+1];
10763 regs[i+1].regmap_entry[hr]=rs1[i+1];
10764 regs[i].isconst&=~(1<<hr);
10765 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10766 constmap[i][hr]=constmap[i+1][hr];
10767 regs[i+1].wasdirty&=~(1<<hr);
10768 regs[i].dirty&=~(1<<hr);
10772 // Preload map address
10773 #ifndef HOST_IMM_ADDR32
10774 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
10775 hr=get_reg(regs[i+1].regmap,TLREG);
10777 int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10778 if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10780 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10782 regs[i].regmap[hr]=MGEN1+((i+1)&1);
10783 regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10784 regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10785 regs[i].isconst&=~(1<<hr);
10786 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10787 constmap[i][hr]=constmap[i+1][hr];
10788 regs[i+1].wasdirty&=~(1<<hr);
10789 regs[i].dirty&=~(1<<hr);
10791 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10793 // move it to another register
10794 regs[i+1].regmap[hr]=-1;
10795 regmap_pre[i+2][hr]=-1;
10796 regs[i+1].regmap[nr]=TLREG;
10797 regmap_pre[i+2][nr]=TLREG;
10798 regs[i].regmap[nr]=MGEN1+((i+1)&1);
10799 regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10800 regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10801 regs[i].isconst&=~(1<<nr);
10802 regs[i+1].isconst&=~(1<<nr);
10803 regs[i].dirty&=~(1<<nr);
10804 regs[i+1].wasdirty&=~(1<<nr);
10805 regs[i+1].dirty&=~(1<<nr);
10806 regs[i+2].wasdirty&=~(1<<nr);
10812 // Address for store instruction (non-constant)
10813 if(itype[i+1]==STORE||itype[i+1]==STORELR
10814 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10815 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10816 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10817 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10818 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10820 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10822 regs[i].regmap[hr]=rs1[i+1];
10823 regmap_pre[i+1][hr]=rs1[i+1];
10824 regs[i+1].regmap_entry[hr]=rs1[i+1];
10825 regs[i].isconst&=~(1<<hr);
10826 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10827 constmap[i][hr]=constmap[i+1][hr];
10828 regs[i+1].wasdirty&=~(1<<hr);
10829 regs[i].dirty&=~(1<<hr);
10833 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10834 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10836 hr=get_reg(regs[i+1].regmap,FTEMP);
10838 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10840 regs[i].regmap[hr]=rs1[i+1];
10841 regmap_pre[i+1][hr]=rs1[i+1];
10842 regs[i+1].regmap_entry[hr]=rs1[i+1];
10843 regs[i].isconst&=~(1<<hr);
10844 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10845 constmap[i][hr]=constmap[i+1][hr];
10846 regs[i+1].wasdirty&=~(1<<hr);
10847 regs[i].dirty&=~(1<<hr);
10849 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10851 // move it to another register
10852 regs[i+1].regmap[hr]=-1;
10853 regmap_pre[i+2][hr]=-1;
10854 regs[i+1].regmap[nr]=FTEMP;
10855 regmap_pre[i+2][nr]=FTEMP;
10856 regs[i].regmap[nr]=rs1[i+1];
10857 regmap_pre[i+1][nr]=rs1[i+1];
10858 regs[i+1].regmap_entry[nr]=rs1[i+1];
10859 regs[i].isconst&=~(1<<nr);
10860 regs[i+1].isconst&=~(1<<nr);
10861 regs[i].dirty&=~(1<<nr);
10862 regs[i+1].wasdirty&=~(1<<nr);
10863 regs[i+1].dirty&=~(1<<nr);
10864 regs[i+2].wasdirty&=~(1<<nr);
10868 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10869 if(itype[i+1]==LOAD)
10870 hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10871 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10872 hr=get_reg(regs[i+1].regmap,FTEMP);
10873 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10874 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10875 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10877 if(hr>=0&®s[i].regmap[hr]<0) {
10878 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10879 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10880 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10881 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10882 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10883 regs[i].isconst&=~(1<<hr);
10884 regs[i+1].wasdirty&=~(1<<hr);
10885 regs[i].dirty&=~(1<<hr);
10894 /* Pass 6 - Optimize clean/dirty state */
10895 clean_registers(0,slen-1,1);
10897 /* Pass 7 - Identify 32-bit registers */
10903 for (i=slen-1;i>=0;i--)
10906 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10908 if(ba[i]<start || ba[i]>=(start+slen*4))
10910 // Branch out of this block, don't need anything
10916 // Need whatever matches the target
10917 // (and doesn't get overwritten by the delay slot instruction)
10919 int t=(ba[i]-start)>>2;
10920 if(ba[i]>start+i*4) {
10922 if(!(requires_32bit[t]&~regs[i].was32))
10923 r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10926 //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10927 // r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10928 if(!(pr32[t]&~regs[i].was32))
10929 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10932 // Conditional branch may need registers for following instructions
10933 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10936 r32|=requires_32bit[i+2];
10937 r32&=regs[i].was32;
10938 // Mark this address as a branch target since it may be called
10939 // upon return from interrupt
10943 // Merge in delay slot
10945 // These are overwritten unless the branch is "likely"
10946 // and the delay slot is nullified if not taken
10947 r32&=~(1LL<<rt1[i+1]);
10948 r32&=~(1LL<<rt2[i+1]);
10950 // Assume these are needed (delay slot)
10953 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10957 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10959 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10961 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10963 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10965 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10968 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
10970 // SYSCALL instruction (software interrupt)
10973 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10975 // ERET instruction (return from interrupt)
10979 r32&=~(1LL<<rt1[i]);
10980 r32&=~(1LL<<rt2[i]);
10983 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10987 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10989 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10991 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10993 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10995 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10997 requires_32bit[i]=r32;
10999 // Dirty registers which are 32-bit, require 32-bit input
11000 // as they will be written as 32-bit values
11001 for(hr=0;hr<HOST_REGS;hr++)
11003 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
11004 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
11005 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
11006 requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
11010 //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
11013 for (i=slen-1;i>=0;i--)
11015 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
11017 // Conditional branch
11018 if((source[i]>>16)!=0x1000&&i<slen-2) {
11019 // Mark this address as a branch target since it may be called
11020 // upon return from interrupt
11027 if(itype[slen-1]==SPAN) {
11028 bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
11032 /* Debug/disassembly */
11033 for(i=0;i<slen;i++)
11037 for(r=1;r<=CCREG;r++) {
11038 if((unneeded_reg[i]>>r)&1) {
11039 if(r==HIREG) printf(" HI");
11040 else if(r==LOREG) printf(" LO");
11041 else printf(" r%d",r);
11046 for(r=1;r<=CCREG;r++) {
11047 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
11048 if(r==HIREG) printf(" HI");
11049 else if(r==LOREG) printf(" LO");
11050 else printf(" r%d",r);
11054 for(r=0;r<=CCREG;r++) {
11055 //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11056 if((regs[i].was32>>r)&1) {
11057 if(r==CCREG) printf(" CC");
11058 else if(r==HIREG) printf(" HI");
11059 else if(r==LOREG) printf(" LO");
11060 else printf(" r%d",r);
11065 #if defined(__i386__) || defined(__x86_64__)
11066 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
11069 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
11072 if(needed_reg[i]&1) printf("eax ");
11073 if((needed_reg[i]>>1)&1) printf("ecx ");
11074 if((needed_reg[i]>>2)&1) printf("edx ");
11075 if((needed_reg[i]>>3)&1) printf("ebx ");
11076 if((needed_reg[i]>>5)&1) printf("ebp ");
11077 if((needed_reg[i]>>6)&1) printf("esi ");
11078 if((needed_reg[i]>>7)&1) printf("edi ");
11080 for(r=0;r<=CCREG;r++) {
11081 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11082 if((requires_32bit[i]>>r)&1) {
11083 if(r==CCREG) printf(" CC");
11084 else if(r==HIREG) printf(" HI");
11085 else if(r==LOREG) printf(" LO");
11086 else printf(" r%d",r);
11091 for(r=0;r<=CCREG;r++) {
11092 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11093 if((pr32[i]>>r)&1) {
11094 if(r==CCREG) printf(" CC");
11095 else if(r==HIREG) printf(" HI");
11096 else if(r==LOREG) printf(" LO");
11097 else printf(" r%d",r);
11100 if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
11102 #if defined(__i386__) || defined(__x86_64__)
11103 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
11105 if(regs[i].wasdirty&1) printf("eax ");
11106 if((regs[i].wasdirty>>1)&1) printf("ecx ");
11107 if((regs[i].wasdirty>>2)&1) printf("edx ");
11108 if((regs[i].wasdirty>>3)&1) printf("ebx ");
11109 if((regs[i].wasdirty>>5)&1) printf("ebp ");
11110 if((regs[i].wasdirty>>6)&1) printf("esi ");
11111 if((regs[i].wasdirty>>7)&1) printf("edi ");
11114 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
11116 if(regs[i].wasdirty&1) printf("r0 ");
11117 if((regs[i].wasdirty>>1)&1) printf("r1 ");
11118 if((regs[i].wasdirty>>2)&1) printf("r2 ");
11119 if((regs[i].wasdirty>>3)&1) printf("r3 ");
11120 if((regs[i].wasdirty>>4)&1) printf("r4 ");
11121 if((regs[i].wasdirty>>5)&1) printf("r5 ");
11122 if((regs[i].wasdirty>>6)&1) printf("r6 ");
11123 if((regs[i].wasdirty>>7)&1) printf("r7 ");
11124 if((regs[i].wasdirty>>8)&1) printf("r8 ");
11125 if((regs[i].wasdirty>>9)&1) printf("r9 ");
11126 if((regs[i].wasdirty>>10)&1) printf("r10 ");
11127 if((regs[i].wasdirty>>12)&1) printf("r12 ");
11130 disassemble_inst(i);
11131 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
11132 #if defined(__i386__) || defined(__x86_64__)
11133 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
11134 if(regs[i].dirty&1) printf("eax ");
11135 if((regs[i].dirty>>1)&1) printf("ecx ");
11136 if((regs[i].dirty>>2)&1) printf("edx ");
11137 if((regs[i].dirty>>3)&1) printf("ebx ");
11138 if((regs[i].dirty>>5)&1) printf("ebp ");
11139 if((regs[i].dirty>>6)&1) printf("esi ");
11140 if((regs[i].dirty>>7)&1) printf("edi ");
11143 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
11144 if(regs[i].dirty&1) printf("r0 ");
11145 if((regs[i].dirty>>1)&1) printf("r1 ");
11146 if((regs[i].dirty>>2)&1) printf("r2 ");
11147 if((regs[i].dirty>>3)&1) printf("r3 ");
11148 if((regs[i].dirty>>4)&1) printf("r4 ");
11149 if((regs[i].dirty>>5)&1) printf("r5 ");
11150 if((regs[i].dirty>>6)&1) printf("r6 ");
11151 if((regs[i].dirty>>7)&1) printf("r7 ");
11152 if((regs[i].dirty>>8)&1) printf("r8 ");
11153 if((regs[i].dirty>>9)&1) printf("r9 ");
11154 if((regs[i].dirty>>10)&1) printf("r10 ");
11155 if((regs[i].dirty>>12)&1) printf("r12 ");
11158 if(regs[i].isconst) {
11159 printf("constants: ");
11160 #if defined(__i386__) || defined(__x86_64__)
11161 if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
11162 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
11163 if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
11164 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
11165 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
11166 if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
11167 if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
11170 if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
11171 if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
11172 if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
11173 if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
11174 if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
11175 if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
11176 if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
11177 if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
11178 if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
11179 if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
11180 if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
11181 if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
11187 for(r=0;r<=CCREG;r++) {
11188 if((regs[i].is32>>r)&1) {
11189 if(r==CCREG) printf(" CC");
11190 else if(r==HIREG) printf(" HI");
11191 else if(r==LOREG) printf(" LO");
11192 else printf(" r%d",r);
11198 for(r=0;r<=CCREG;r++) {
11199 if((p32[i]>>r)&1) {
11200 if(r==CCREG) printf(" CC");
11201 else if(r==HIREG) printf(" HI");
11202 else if(r==LOREG) printf(" LO");
11203 else printf(" r%d",r);
11206 if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
11207 else printf("\n");*/
11208 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
11209 #if defined(__i386__) || defined(__x86_64__)
11210 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
11211 if(branch_regs[i].dirty&1) printf("eax ");
11212 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
11213 if((branch_regs[i].dirty>>2)&1) printf("edx ");
11214 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
11215 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
11216 if((branch_regs[i].dirty>>6)&1) printf("esi ");
11217 if((branch_regs[i].dirty>>7)&1) printf("edi ");
11220 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
11221 if(branch_regs[i].dirty&1) printf("r0 ");
11222 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
11223 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
11224 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
11225 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
11226 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
11227 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
11228 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
11229 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
11230 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
11231 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
11232 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
11236 for(r=0;r<=CCREG;r++) {
11237 if((branch_regs[i].is32>>r)&1) {
11238 if(r==CCREG) printf(" CC");
11239 else if(r==HIREG) printf(" HI");
11240 else if(r==LOREG) printf(" LO");
11241 else printf(" r%d",r);
11250 /* Pass 8 - Assembly */
11251 linkcount=0;stubcount=0;
11252 ds=0;is_delayslot=0;
11254 uint64_t is32_pre=0;
11256 u_int beginning=(u_int)out;
11257 if((u_int)addr&1) {
11261 u_int instr_addr0_override=0;
11264 if (start == 0x80030000) {
11265 // nasty hack for fastbios thing
11266 // override block entry to this code
11267 instr_addr0_override=(u_int)out;
11268 emit_movimm(start,0);
11269 // abuse io address var as a flag that we
11270 // have already returned here once
11271 emit_readword((int)&address,1);
11272 emit_writeword(0,(int)&pcaddr);
11273 emit_writeword(0,(int)&address);
11275 emit_jne((int)new_dyna_leave);
11278 for(i=0;i<slen;i++)
11280 //if(ds) printf("ds: ");
11281 disassemble_inst(i);
11283 ds=0; // Skip delay slot
11284 if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
11287 speculate_register_values(i);
11288 #ifndef DESTRUCTIVE_WRITEBACK
11289 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11291 wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
11292 unneeded_reg[i],unneeded_reg_upper[i]);
11293 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
11294 unneeded_reg[i],unneeded_reg_upper[i]);
11296 if((itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)&&!likely[i]) {
11297 is32_pre=branch_regs[i].is32;
11298 dirty_pre=branch_regs[i].dirty;
11300 is32_pre=regs[i].is32;
11301 dirty_pre=regs[i].dirty;
11305 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11307 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
11308 unneeded_reg[i],unneeded_reg_upper[i]);
11309 loop_preload(regmap_pre[i],regs[i].regmap_entry);
11311 // branch target entry point
11312 instr_addr[i]=(u_int)out;
11313 assem_debug("<->\n");
11315 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG)
11316 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
11317 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
11318 address_generation(i,®s[i],regs[i].regmap_entry);
11319 load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
11320 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
11322 // Load the delay slot registers if necessary
11323 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
11324 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11325 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
11326 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11327 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
11328 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11332 // Preload registers for following instruction
11333 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
11334 if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
11335 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11336 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
11337 if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
11338 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11340 // TODO: if(is_ooo(i)) address_generation(i+1);
11341 if(itype[i]==CJUMP||itype[i]==FJUMP)
11342 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
11343 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
11344 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11345 if(bt[i]) cop1_usable=0;
11349 alu_assemble(i,®s[i]);break;
11351 imm16_assemble(i,®s[i]);break;
11353 shift_assemble(i,®s[i]);break;
11355 shiftimm_assemble(i,®s[i]);break;
11357 load_assemble(i,®s[i]);break;
11359 loadlr_assemble(i,®s[i]);break;
11361 store_assemble(i,®s[i]);break;
11363 storelr_assemble(i,®s[i]);break;
11365 cop0_assemble(i,®s[i]);break;
11367 cop1_assemble(i,®s[i]);break;
11369 c1ls_assemble(i,®s[i]);break;
11371 cop2_assemble(i,®s[i]);break;
11373 c2ls_assemble(i,®s[i]);break;
11375 c2op_assemble(i,®s[i]);break;
11377 fconv_assemble(i,®s[i]);break;
11379 float_assemble(i,®s[i]);break;
11381 fcomp_assemble(i,®s[i]);break;
11383 multdiv_assemble(i,®s[i]);break;
11385 mov_assemble(i,®s[i]);break;
11387 syscall_assemble(i,®s[i]);break;
11389 hlecall_assemble(i,®s[i]);break;
11391 intcall_assemble(i,®s[i]);break;
11393 ujump_assemble(i,®s[i]);ds=1;break;
11395 rjump_assemble(i,®s[i]);ds=1;break;
11397 cjump_assemble(i,®s[i]);ds=1;break;
11399 sjump_assemble(i,®s[i]);ds=1;break;
11401 fjump_assemble(i,®s[i]);ds=1;break;
11403 pagespan_assemble(i,®s[i]);break;
11405 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
11406 literal_pool(1024);
11408 literal_pool_jumpover(256);
11411 //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
11412 // If the block did not end with an unconditional branch,
11413 // add a jump to the next instruction.
11415 if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
11416 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11418 if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
11419 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11420 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11421 emit_loadreg(CCREG,HOST_CCREG);
11422 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
11424 else if(!likely[i-2])
11426 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
11427 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
11431 store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
11432 assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
11434 add_to_linker((int)out,start+i*4,0);
11441 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11442 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11443 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11444 emit_loadreg(CCREG,HOST_CCREG);
11445 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
11446 add_to_linker((int)out,start+i*4,0);
11450 // TODO: delay slot stubs?
11452 for(i=0;i<stubcount;i++)
11454 switch(stubs[i][0])
11462 do_readstub(i);break;
11467 do_writestub(i);break;
11469 do_ccstub(i);break;
11471 do_invstub(i);break;
11473 do_cop1stub(i);break;
11475 do_unalignedwritestub(i);break;
11479 if (instr_addr0_override)
11480 instr_addr[0] = instr_addr0_override;
11482 /* Pass 9 - Linker */
11483 for(i=0;i<linkcount;i++)
11485 assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
11487 if(!link_addr[i][2])
11490 void *addr=check_addr(link_addr[i][1]);
11491 emit_extjump(link_addr[i][0],link_addr[i][1]);
11493 set_jump_target(link_addr[i][0],(int)addr);
11494 add_link(link_addr[i][1],stub);
11496 else set_jump_target(link_addr[i][0],(int)stub);
11501 int target=(link_addr[i][1]-start)>>2;
11502 assert(target>=0&&target<slen);
11503 assert(instr_addr[target]);
11504 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11505 //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
11507 set_jump_target(link_addr[i][0],instr_addr[target]);
11511 // External Branch Targets (jump_in)
11512 if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
11513 for(i=0;i<slen;i++)
11517 if(instr_addr[i]) // TODO - delay slots (=null)
11519 u_int vaddr=start+i*4;
11520 u_int page=get_page(vaddr);
11521 u_int vpage=get_vpage(vaddr);
11523 //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
11525 if(!requires_32bit[i])
11530 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11531 assem_debug("jump_in: %x\n",start+i*4);
11532 ll_add(jump_dirty+vpage,vaddr,(void *)out);
11533 int entry_point=do_dirty_stub(i);
11534 ll_add(jump_in+page,vaddr,(void *)entry_point);
11535 // If there was an existing entry in the hash table,
11536 // replace it with the new address.
11537 // Don't add new entries. We'll insert the
11538 // ones that actually get used in check_addr().
11539 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
11540 if(ht_bin[0]==vaddr) {
11541 ht_bin[1]=entry_point;
11543 if(ht_bin[2]==vaddr) {
11544 ht_bin[3]=entry_point;
11549 u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
11550 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11551 assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
11552 //int entry_point=(int)out;
11553 ////assem_debug("entry_point: %x\n",entry_point);
11554 //load_regs_entry(i);
11555 //if(entry_point==(int)out)
11556 // entry_point=instr_addr[i];
11558 // emit_jmp(instr_addr[i]);
11559 //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11560 ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
11561 int entry_point=do_dirty_stub(i);
11562 ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11567 // Write out the literal pool if necessary
11569 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11571 if(((u_int)out)&7) emit_addnop(13);
11573 assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
11574 //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
11575 memcpy(copy,source,slen*4);
11579 __clear_cache((void *)beginning,out);
11582 // If we're within 256K of the end of the buffer,
11583 // start over from the beginning. (Is 256K enough?)
11584 if((u_int)out>(u_int)BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
11586 // Trap writes to any of the pages we compiled
11587 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
11589 #ifndef DISABLE_TLB
11590 memory_map[i]|=0x40000000;
11591 if((signed int)start>=(signed int)0xC0000000) {
11593 j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
11595 memory_map[j]|=0x40000000;
11596 //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
11600 inv_code_start=inv_code_end=~0;
11602 // for PCSX we need to mark all mirrors too
11603 if(get_page(start)<(RAM_SIZE>>12))
11604 for(i=start>>12;i<=(start+slen*4)>>12;i++)
11605 invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
11606 invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
11607 invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
11610 /* Pass 10 - Free memory by expiring oldest blocks */
11612 int end=((((int)out-(int)BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
11613 while(expirep!=end)
11615 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
11616 int base=(int)BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
11617 inv_debug("EXP: Phase %d\n",expirep);
11618 switch((expirep>>11)&3)
11621 // Clear jump_in and jump_dirty
11622 ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11623 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11624 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11625 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11629 ll_kill_pointers(jump_out[expirep&2047],base,shift);
11630 ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11633 // Clear hash table
11634 for(i=0;i<32;i++) {
11635 int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11636 if((ht_bin[3]>>shift)==(base>>shift) ||
11637 ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11638 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11639 ht_bin[2]=ht_bin[3]=-1;
11641 if((ht_bin[1]>>shift)==(base>>shift) ||
11642 ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11643 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11644 ht_bin[0]=ht_bin[2];
11645 ht_bin[1]=ht_bin[3];
11646 ht_bin[2]=ht_bin[3]=-1;
11653 if((expirep&2047)==0)
11656 ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11657 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11660 expirep=(expirep+1)&65535;
11665 // vim:shiftwidth=2:expandtab