2 * (C) GraÅžvydas "notaz" Ignotas, 2010-2011
4 * This work is licensed under the terms of GNU GPL version 2 or later.
5 * See the COPYING file in the top-level directory.
13 #include "../psxmem_map.h"
18 #error the dynarec is incompatible with Thumb functions,
19 #error please add -marm to compile flags
22 //#define memprintf printf
23 #define memprintf(...)
25 static uintptr_t *mem_readtab;
26 static uintptr_t *mem_writetab;
27 static uintptr_t mem_iortab[(1+2+4) * 0x1000 / 4];
28 static uintptr_t mem_iowtab[(1+2+4) * 0x1000 / 4];
29 static uintptr_t mem_ffrtab[(1+2+4) * 0x1000 / 4];
30 static uintptr_t mem_ffwtab[(1+2+4) * 0x1000 / 4];
31 //static uintptr_t mem_unmrtab[(1+2+4) * 0x1000 / 4];
32 static uintptr_t mem_unmwtab[(1+2+4) * 0x1000 / 4];
36 // When this is called in a loop, and 'h' is a function pointer, clang will crash.
37 __attribute__ ((noinline))
39 void map_item(uintptr_t *out, const void *h, uintptr_t flag)
41 uintptr_t hv = (uintptr_t)h;
43 SysPrintf("FATAL: %p has LSB set\n", h);
46 *out = (hv >> 1) | (flag << (sizeof(hv) * 8 - 1));
49 // size must be power of 2, at least 4k
50 #define map_l1_mem(tab, i, addr, size, base) \
51 map_item(&tab[((u32)(addr) >> 12) + i], \
52 (u8 *)(base) - (u32)((addr) + ((i << 12) & ~(size - 1))), 0)
54 #define IOMEM32(a) (((a) & 0xfff) / 4)
55 #define IOMEM16(a) (0x1000/4 + (((a) & 0xfff) / 2))
56 #define IOMEM8(a) (0x1000/4 + 0x1000/2 + ((a) & 0xfff))
58 u32 zero_mem[0x1000/4];
59 static u32 ffff_mem[0x1000/4];
61 static u32 read_mem_dummy(u32 addr)
63 // use 'addr' and not 'address', yes the api is weird...
64 memprintf("unmapped r %08x @%08x %u\n", addr, psxRegs.pc, psxRegs.cycle);
68 static void write_mem_dummy(u32 data)
70 if (!(psxRegs.CP0.n.SR & (1 << 16)))
71 memprintf("unmapped w %08x, %08x @%08x %u\n",
72 address, data, psxRegs.pc, psxRegs.cycle);
76 static u32 io_read_sio16()
78 return sioRead8() | (sioRead8() << 8);
81 static u32 io_read_sio32()
83 return sioRead8() | (sioRead8() << 8) | (sioRead8() << 16) | (sioRead8() << 24);
86 static void io_write_sio16(u32 value)
88 sioWrite8((unsigned char)value);
89 sioWrite8((unsigned char)(value>>8));
92 static void io_write_sio32(u32 value)
94 sioWrite8((unsigned char)value);
95 sioWrite8((unsigned char)(value >> 8));
96 sioWrite8((unsigned char)(value >> 16));
97 sioWrite8((unsigned char)(value >> 24));
100 #if !defined(DRC_DBG) && defined(__arm__)
102 static void map_rcnt_rcount0(u32 mode)
104 if (mode & 0x001) { // sync mode
105 map_item(&mem_iortab[IOMEM32(0x1100)], psxRcntRcount0, 1);
106 map_item(&mem_iortab[IOMEM16(0x1100)], psxRcntRcount0, 1);
108 else if (mode & 0x100) { // pixel clock
109 map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m1, 1);
110 map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m1, 1);
113 map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m0, 1);
114 map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m0, 1);
118 static void map_rcnt_rcount1(u32 mode)
120 if (mode & 0x001) { // sync mode
121 map_item(&mem_iortab[IOMEM32(0x1110)], psxRcntRcount1, 1);
122 map_item(&mem_iortab[IOMEM16(0x1110)], psxRcntRcount1, 1);
124 else if (mode & 0x100) { // hcnt
125 map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m1, 1);
126 map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m1, 1);
129 map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m0, 1);
130 map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m0, 1);
134 static void map_rcnt_rcount2(u32 mode)
136 if ((mode & 7) == 1 || (mode & 7) == 7) { // sync mode
137 map_item(&mem_iortab[IOMEM32(0x1120)], &psxH[0x1000], 0);
138 map_item(&mem_iortab[IOMEM16(0x1120)], &psxH[0x1000], 0);
140 else if (mode & 0x200) { // clk/8
141 map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m1, 1);
142 map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m1, 1);
145 map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m0, 1);
146 map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m0, 1);
151 #define map_rcnt_rcount0(mode)
152 #define map_rcnt_rcount1(mode)
153 #define map_rcnt_rcount2(mode)
156 #define make_rcnt_funcs(i) \
157 static u32 io_rcnt_read_mode##i() { return psxRcntRmode(i); } \
158 static u32 io_rcnt_read_target##i() { return psxRcntRtarget(i); } \
159 static void io_rcnt_write_count##i(u32 val) { psxRcntWcount(i, val & 0xffff); } \
160 static void io_rcnt_write_mode##i(u32 val) { psxRcntWmode(i, val); map_rcnt_rcount##i(val); } \
161 static void io_rcnt_write_target##i(u32 val) { psxRcntWtarget(i, val & 0xffff); }
167 #define make_dma_func(n) \
168 static void io_write_chcr##n(u32 value) \
170 HW_DMA##n##_CHCR = value; \
171 if (value & 0x01000000 && HW_DMA_PCR & (8 << (n * 4))) { \
172 psxDma##n(HW_DMA##n##_MADR, HW_DMA##n##_BCR, value); \
183 static u32 io_spu_read8_even(u32 addr)
185 return SPU_readRegister(addr, psxRegs.cycle) & 0xff;
188 static u32 io_spu_read8_odd(u32 addr)
190 return SPU_readRegister(addr, psxRegs.cycle) >> 8;
193 static u32 io_spu_read16(u32 addr)
195 return SPU_readRegister(addr, psxRegs.cycle);
198 static u32 io_spu_read32(u32 addr)
201 ret = SPU_readRegister(addr, psxRegs.cycle);
202 ret |= SPU_readRegister(addr + 2, psxRegs.cycle) << 16;
206 static void io_spu_write16(u32 value)
209 SPU_writeRegister(address, value, psxRegs.cycle);
212 static void io_spu_write32(u32 value)
214 SPUwriteRegister wfunc = SPU_writeRegister;
217 wfunc(a, value & 0xffff, psxRegs.cycle);
218 wfunc(a + 2, value >> 16, psxRegs.cycle);
221 void new_dyna_pcsx_mem_isolate(int enable)
225 // note: apparently 0xa0000000 uncached access still works,
226 // at least read does for sure, so assume write does too
227 memprintf("mem isolate %d\n", enable);
229 for (i = 0; i < (0x800000 >> 12); i++) {
230 map_item(&mem_writetab[0x80000|i], mem_unmwtab, 1);
231 map_item(&mem_writetab[0x00000|i], mem_unmwtab, 1);
232 //map_item(&mem_writetab[0xa0000|i], mem_unmwtab, 1);
236 for (i = 0; i < (0x800000 >> 12); i++) {
237 map_l1_mem(mem_writetab, i, 0x80000000, 0x200000, psxM);
238 map_l1_mem(mem_writetab, i, 0x00000000, 0x200000, psxM);
239 map_l1_mem(mem_writetab, i, 0xa0000000, 0x200000, psxM);
244 static u32 read_biu(u32 addr)
246 if (addr != 0xfffe0130)
247 return read_mem_dummy(addr);
249 memprintf("read_biu %08x @%08x %u\n",
250 psxRegs.biuReg, psxRegs.pc, psxRegs.cycle);
251 return psxRegs.biuReg;
254 static void write_biu(u32 value)
256 if (address != 0xfffe0130) {
257 write_mem_dummy(value);
261 memprintf("write_biu %08x @%08x %u\n", value, psxRegs.pc, psxRegs.cycle);
262 psxRegs.biuReg = value;
265 void new_dyna_pcsx_mem_load_state(void)
267 map_rcnt_rcount0(rcnts[0].mode);
268 map_rcnt_rcount1(rcnts[1].mode);
269 map_rcnt_rcount2(rcnts[2].mode);
272 int pcsxmem_is_handler_dynamic(unsigned int addr)
274 if ((addr & 0xfffff000) != 0x1f801000)
278 return addr == 0x1100 || addr == 0x1110 || addr == 0x1120;
281 void new_dyna_pcsx_mem_init(void)
285 memset(ffff_mem, 0xff, sizeof(ffff_mem));
287 // have to map these further to keep tcache close to .text
288 mem_readtab = psxMap(0x08000000, 0x200000 * sizeof(mem_readtab[0]), 0, MAP_TAG_LUTS);
289 if (mem_readtab == NULL) {
290 SysPrintf("failed to map mem tables\n");
293 mem_writetab = mem_readtab + 0x100000;
299 // 0: direct mem variable
302 // default/unmapped memhandlers
303 for (i = 0; i < 0x100000; i++) {
304 //map_item(&mem_readtab[i], mem_unmrtab, 1);
305 map_l1_mem(mem_readtab, i, 0, 0x1000, ffff_mem);
306 map_item(&mem_writetab[i], mem_unmwtab, 1);
309 // RAM and it's mirrors
310 for (i = 0; i < (0x800000 >> 12); i++) {
311 map_l1_mem(mem_readtab, i, 0x80000000, 0x200000, psxM);
312 map_l1_mem(mem_readtab, i, 0x00000000, 0x200000, psxM);
313 map_l1_mem(mem_readtab, i, 0xa0000000, 0x200000, psxM);
315 new_dyna_pcsx_mem_isolate(0);
317 // BIOS and it's mirrors
318 for (i = 0; i < (0x80000 >> 12); i++) {
319 map_l1_mem(mem_readtab, i, 0x1fc00000, 0x80000, psxR);
320 map_l1_mem(mem_readtab, i, 0xbfc00000, 0x80000, psxR);
324 map_l1_mem(mem_readtab, 0, 0x1f800000, 0x1000, psxH);
325 map_l1_mem(mem_readtab, 0, 0x9f800000, 0x1000, psxH);
326 map_l1_mem(mem_writetab, 0, 0x1f800000, 0x1000, psxH);
327 map_l1_mem(mem_writetab, 0, 0x9f800000, 0x1000, psxH);
330 map_item(&mem_readtab[0x1f801000u >> 12], mem_iortab, 1);
331 map_item(&mem_readtab[0x9f801000u >> 12], mem_iortab, 1);
332 map_item(&mem_readtab[0xbf801000u >> 12], mem_iortab, 1);
333 map_item(&mem_writetab[0x1f801000u >> 12], mem_iowtab, 1);
334 map_item(&mem_writetab[0x9f801000u >> 12], mem_iowtab, 1);
335 map_item(&mem_writetab[0xbf801000u >> 12], mem_iowtab, 1);
339 for (i = 0; i < (1+2+4) * 0x1000 / 4; i++)
340 map_item(&mem_unmwtab[i], write_mem_dummy, 1);
343 for (i = 0; i < 0x1000/4; i++) {
344 map_item(&mem_iortab[i], &psxH[0x1000], 0);
345 map_item(&mem_iowtab[i], &psxH[0x1000], 0);
347 for (; i < 0x1000/4 + 0x1000/2; i++) {
348 map_item(&mem_iortab[i], &psxH[0x1000], 0);
349 map_item(&mem_iowtab[i], &psxH[0x1000], 0);
351 for (; i < 0x1000/4 + 0x1000/2 + 0x1000; i++) {
352 map_item(&mem_iortab[i], &psxH[0x1000], 0);
353 map_item(&mem_iowtab[i], &psxH[0x1000], 0);
356 map_item(&mem_iortab[IOMEM32(0x1040)], io_read_sio32, 1);
357 map_item(&mem_iortab[IOMEM32(0x1100)], psxRcntRcount0, 1);
358 map_item(&mem_iortab[IOMEM32(0x1104)], io_rcnt_read_mode0, 1);
359 map_item(&mem_iortab[IOMEM32(0x1108)], io_rcnt_read_target0, 1);
360 map_item(&mem_iortab[IOMEM32(0x1110)], psxRcntRcount1, 1);
361 map_item(&mem_iortab[IOMEM32(0x1114)], io_rcnt_read_mode1, 1);
362 map_item(&mem_iortab[IOMEM32(0x1118)], io_rcnt_read_target1, 1);
363 map_item(&mem_iortab[IOMEM32(0x1120)], psxRcntRcount2, 1);
364 map_item(&mem_iortab[IOMEM32(0x1124)], io_rcnt_read_mode2, 1);
365 map_item(&mem_iortab[IOMEM32(0x1128)], io_rcnt_read_target2, 1);
366 // map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
367 map_item(&mem_iortab[IOMEM32(0x1814)], psxHwReadGpuSR, 1);
368 map_item(&mem_iortab[IOMEM32(0x1820)], mdecRead0, 1);
369 map_item(&mem_iortab[IOMEM32(0x1824)], mdecRead1, 1);
371 map_item(&mem_iortab[IOMEM16(0x1040)], io_read_sio16, 1);
372 map_item(&mem_iortab[IOMEM16(0x1044)], sioReadStat16, 1);
373 map_item(&mem_iortab[IOMEM16(0x1048)], sioReadMode16, 1);
374 map_item(&mem_iortab[IOMEM16(0x104a)], sioReadCtrl16, 1);
375 map_item(&mem_iortab[IOMEM16(0x104e)], sioReadBaud16, 1);
376 map_item(&mem_iortab[IOMEM16(0x1100)], psxRcntRcount0, 1);
377 map_item(&mem_iortab[IOMEM16(0x1104)], io_rcnt_read_mode0, 1);
378 map_item(&mem_iortab[IOMEM16(0x1108)], io_rcnt_read_target0, 1);
379 map_item(&mem_iortab[IOMEM16(0x1110)], psxRcntRcount1, 1);
380 map_item(&mem_iortab[IOMEM16(0x1114)], io_rcnt_read_mode1, 1);
381 map_item(&mem_iortab[IOMEM16(0x1118)], io_rcnt_read_target1, 1);
382 map_item(&mem_iortab[IOMEM16(0x1120)], psxRcntRcount2, 1);
383 map_item(&mem_iortab[IOMEM16(0x1124)], io_rcnt_read_mode2, 1);
384 map_item(&mem_iortab[IOMEM16(0x1128)], io_rcnt_read_target2, 1);
386 map_item(&mem_iortab[IOMEM8(0x1040)], sioRead8, 1);
387 map_item(&mem_iortab[IOMEM8(0x1800)], cdrRead0, 1);
388 map_item(&mem_iortab[IOMEM8(0x1801)], cdrRead1, 1);
389 map_item(&mem_iortab[IOMEM8(0x1802)], cdrRead2, 1);
390 map_item(&mem_iortab[IOMEM8(0x1803)], cdrRead3, 1);
392 for (i = 0x1c00; i < 0x2000; i += 2) {
393 map_item(&mem_iortab[IOMEM8(i)], io_spu_read8_even, 1);
394 map_item(&mem_iortab[IOMEM8(i+1)], io_spu_read8_odd, 1);
395 map_item(&mem_iortab[IOMEM16(i)], io_spu_read16, 1);
396 map_item(&mem_iortab[IOMEM32(i)], io_spu_read32, 1);
400 map_item(&mem_iowtab[IOMEM32(0x1040)], io_write_sio32, 1);
401 map_item(&mem_iowtab[IOMEM32(0x1070)], psxHwWriteIstat, 1);
402 map_item(&mem_iowtab[IOMEM32(0x1074)], psxHwWriteImask, 1);
403 map_item(&mem_iowtab[IOMEM32(0x1088)], io_write_chcr0, 1);
404 map_item(&mem_iowtab[IOMEM32(0x1098)], io_write_chcr1, 1);
405 map_item(&mem_iowtab[IOMEM32(0x10a8)], io_write_chcr2, 1);
406 map_item(&mem_iowtab[IOMEM32(0x10b8)], io_write_chcr3, 1);
407 map_item(&mem_iowtab[IOMEM32(0x10c8)], io_write_chcr4, 1);
408 map_item(&mem_iowtab[IOMEM32(0x10e8)], io_write_chcr6, 1);
409 map_item(&mem_iowtab[IOMEM32(0x10f4)], psxHwWriteDmaIcr32, 1);
410 map_item(&mem_iowtab[IOMEM32(0x1100)], io_rcnt_write_count0, 1);
411 map_item(&mem_iowtab[IOMEM32(0x1104)], io_rcnt_write_mode0, 1);
412 map_item(&mem_iowtab[IOMEM32(0x1108)], io_rcnt_write_target0, 1);
413 map_item(&mem_iowtab[IOMEM32(0x1110)], io_rcnt_write_count1, 1);
414 map_item(&mem_iowtab[IOMEM32(0x1114)], io_rcnt_write_mode1, 1);
415 map_item(&mem_iowtab[IOMEM32(0x1118)], io_rcnt_write_target1, 1);
416 map_item(&mem_iowtab[IOMEM32(0x1120)], io_rcnt_write_count2, 1);
417 map_item(&mem_iowtab[IOMEM32(0x1124)], io_rcnt_write_mode2, 1);
418 map_item(&mem_iowtab[IOMEM32(0x1128)], io_rcnt_write_target2, 1);
419 // map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
420 map_item(&mem_iowtab[IOMEM32(0x1814)], psxHwWriteGpuSR, 1);
421 map_item(&mem_iowtab[IOMEM32(0x1820)], mdecWrite0, 1);
422 map_item(&mem_iowtab[IOMEM32(0x1824)], mdecWrite1, 1);
424 map_item(&mem_iowtab[IOMEM16(0x1040)], io_write_sio16, 1);
425 map_item(&mem_iowtab[IOMEM16(0x1044)], sioWriteStat16, 1);
426 map_item(&mem_iowtab[IOMEM16(0x1048)], sioWriteMode16, 1);
427 map_item(&mem_iowtab[IOMEM16(0x104a)], sioWriteCtrl16, 1);
428 map_item(&mem_iowtab[IOMEM16(0x104e)], sioWriteBaud16, 1);
429 map_item(&mem_iowtab[IOMEM16(0x1070)], psxHwWriteIstat, 1);
430 map_item(&mem_iowtab[IOMEM16(0x1074)], psxHwWriteImask, 1);
431 map_item(&mem_iowtab[IOMEM16(0x1100)], io_rcnt_write_count0, 1);
432 map_item(&mem_iowtab[IOMEM16(0x1104)], io_rcnt_write_mode0, 1);
433 map_item(&mem_iowtab[IOMEM16(0x1108)], io_rcnt_write_target0, 1);
434 map_item(&mem_iowtab[IOMEM16(0x1110)], io_rcnt_write_count1, 1);
435 map_item(&mem_iowtab[IOMEM16(0x1114)], io_rcnt_write_mode1, 1);
436 map_item(&mem_iowtab[IOMEM16(0x1118)], io_rcnt_write_target1, 1);
437 map_item(&mem_iowtab[IOMEM16(0x1120)], io_rcnt_write_count2, 1);
438 map_item(&mem_iowtab[IOMEM16(0x1124)], io_rcnt_write_mode2, 1);
439 map_item(&mem_iowtab[IOMEM16(0x1128)], io_rcnt_write_target2, 1);
441 map_item(&mem_iowtab[IOMEM8(0x1040)], sioWrite8, 1);
442 map_item(&mem_iowtab[IOMEM8(0x1800)], cdrWrite0, 1);
443 map_item(&mem_iowtab[IOMEM8(0x1801)], cdrWrite1, 1);
444 map_item(&mem_iowtab[IOMEM8(0x1802)], cdrWrite2, 1);
445 map_item(&mem_iowtab[IOMEM8(0x1803)], cdrWrite3, 1);
447 for (i = 0x1c00; i < 0x2000; i += 2) {
448 map_item(&mem_iowtab[IOMEM16(i)], io_spu_write16, 1);
449 map_item(&mem_iowtab[IOMEM32(i)], io_spu_write32, 1);
453 map_item(&mem_readtab[0xfffe0130u >> 12], mem_ffrtab, 1);
454 map_item(&mem_writetab[0xfffe0130u >> 12], mem_ffwtab, 1);
455 for (i = 0; i < 0x1000/4 + 0x1000/2 + 0x1000; i++) {
456 map_item(&mem_ffrtab[i], read_biu, 1);
457 map_item(&mem_ffwtab[i], write_biu, 1);
460 mem_rtab = mem_readtab;
461 mem_wtab = mem_writetab;
463 new_dyna_pcsx_mem_load_state();
466 void new_dyna_pcsx_mem_reset(void)
468 // plugins might change so update the pointers
469 map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
470 map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
471 if (Config.hacks.gpu_busy_hack)
472 map_item(&mem_iortab[IOMEM32(0x1814)], psxHwReadGpuSRbusyHack, 1);
474 map_item(&mem_iortab[IOMEM32(0x1814)], psxHwReadGpuSR, 1);
477 void new_dyna_pcsx_mem_shutdown(void)
479 psxUnmap(mem_readtab, 0x200000 * sizeof(mem_readtab[0]), MAP_TAG_LUTS);
480 mem_writetab = mem_readtab = NULL;