1 /***************************************************************************
2 * Copyright (C) 2010 by Blade_Arma *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
18 ***************************************************************************/
21 * Internal PSX counters.
24 #include "psxcounters.h"
27 /******************************************************************************/
32 u32 rate, irq, counterState, irqState;
33 u32 cycle, cycleStart;
38 Rc0Gate = 0x0001, // 0 not implemented
39 Rc1Gate = 0x0001, // 0 not implemented
40 Rc2Disable = 0x0001, // 0 partially implemented
41 RcUnknown1 = 0x0002, // 1 ?
42 RcUnknown2 = 0x0004, // 2 ?
43 RcCountToTarget = 0x0008, // 3
44 RcIrqOnTarget = 0x0010, // 4
45 RcIrqOnOverflow = 0x0020, // 5
46 RcIrqRegenerate = 0x0040, // 6
47 RcUnknown7 = 0x0080, // 7 ?
48 Rc0PixelClock = 0x0100, // 8 fake implementation
49 Rc1HSyncClock = 0x0100, // 8
50 Rc2Unknown8 = 0x0100, // 8 ?
51 Rc0Unknown9 = 0x0200, // 9 ?
52 Rc1Unknown9 = 0x0200, // 9 ?
53 Rc2OneEighthClock = 0x0200, // 9
54 RcUnknown10 = 0x0400, // 10 ?
55 RcCountEqTarget = 0x0800, // 11
56 RcOverflow = 0x1000, // 12
57 RcUnknown13 = 0x2000, // 13 ? (always zero)
58 RcUnknown14 = 0x4000, // 14 ? (always zero)
59 RcUnknown15 = 0x8000, // 15 ? (always zero)
62 #define CounterQuantity ( 4 )
63 //static const u32 CounterQuantity = 4;
65 static const u32 CountToOverflow = 0;
66 static const u32 CountToTarget = 1;
68 static const u32 FrameRate[] = { 60, 50 };
69 static const u32 VBlankStart[] = { 240, 256 };
70 static const u32 HSyncTotal[] = { 263, 313 };
71 static const u32 SpuUpdInterval[] = { 23, 22 };
73 static const s32 VerboseLevel = 0;
75 /******************************************************************************/
77 static Rcnt rcnts[ CounterQuantity ];
79 static u32 hSyncCount = 0;
80 static u32 spuSyncCount = 0;
81 static u32 hsync_steps = 0;
82 static u32 gpu_wants_hcnt = 0;
84 u32 psxNextCounter = 0, psxNextsCounter = 0;
86 /******************************************************************************/
89 void setIrq( u32 irq )
91 psxHu32ref(0x1070) |= SWAPu32(irq);
95 void verboseLog( s32 level, const char *str, ... )
97 if( level <= VerboseLevel )
103 vsprintf( buf, str, va );
111 /******************************************************************************/
114 void _psxRcntWcount( u32 index, u32 value )
118 verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value );
122 rcnts[index].cycleStart = psxRegs.cycle;
123 rcnts[index].cycleStart -= value * rcnts[index].rate;
126 if( value < rcnts[index].target )
128 rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
129 rcnts[index].counterState = CountToTarget;
133 rcnts[index].cycle = 0xffff * rcnts[index].rate;
134 rcnts[index].counterState = CountToOverflow;
139 u32 _psxRcntRcount( u32 index )
143 count = psxRegs.cycle;
144 count -= rcnts[index].cycleStart;
145 if (rcnts[index].rate > 1)
146 count /= rcnts[index].rate;
150 verboseLog( 1, "[RCNT %i] rcount > 0xffff: %x\n", index, count );
157 /******************************************************************************/
165 psxNextsCounter = psxRegs.cycle;
166 psxNextCounter = 0x7fffffff;
168 for( i = 0; i < CounterQuantity; ++i )
170 countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart);
172 if( countToUpdate < 0 )
178 if( countToUpdate < (s32)psxNextCounter )
180 psxNextCounter = countToUpdate;
185 /******************************************************************************/
188 void psxRcntReset( u32 index )
192 if( rcnts[index].counterState == CountToTarget )
194 if( rcnts[index].mode & RcCountToTarget )
196 count = psxRegs.cycle;
197 count -= rcnts[index].cycleStart;
198 if (rcnts[index].rate > 1)
199 count /= rcnts[index].rate;
200 count -= rcnts[index].target;
204 count = _psxRcntRcount( index );
207 _psxRcntWcount( index, count );
209 if( rcnts[index].mode & RcIrqOnTarget )
211 if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
213 verboseLog( 3, "[RCNT %i] irq: %x\n", index, count );
214 setIrq( rcnts[index].irq );
215 rcnts[index].irqState = 1;
219 rcnts[index].mode |= RcCountEqTarget;
221 else if( rcnts[index].counterState == CountToOverflow )
223 count = psxRegs.cycle;
224 count -= rcnts[index].cycleStart;
225 if (rcnts[index].rate > 1)
226 count /= rcnts[index].rate;
229 _psxRcntWcount( index, count );
231 if( rcnts[index].mode & RcIrqOnOverflow )
233 if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
235 verboseLog( 3, "[RCNT %i] irq: %x\n", index, count );
236 setIrq( rcnts[index].irq );
237 rcnts[index].irqState = 1;
241 rcnts[index].mode |= RcOverflow;
244 rcnts[index].mode |= RcUnknown10;
253 cycle = psxRegs.cycle;
256 if( cycle - rcnts[0].cycleStart >= rcnts[0].cycle )
262 if( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
268 if( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
274 if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
276 u32 leftover_cycles = cycle - rcnts[3].cycleStart - rcnts[3].cycle;
277 u32 next_vsync, next_lace;
279 spuSyncCount += hsync_steps;
280 hSyncCount += hsync_steps;
283 if( spuSyncCount >= SpuUpdInterval[Config.PsxType] )
289 SPU_async( SpuUpdInterval[Config.PsxType] * rcnts[3].target );
294 if( hSyncCount == VBlankStart[Config.PsxType] )
296 GPU_vBlank( 1, &hSyncCount, &gpu_wants_hcnt );
298 // For the best times. :D
302 // Update lace. (with InuYasha fix)
303 if( hSyncCount >= (Config.VSyncWA ? HSyncTotal[Config.PsxType] / BIAS : HSyncTotal[Config.PsxType]) )
307 GPU_vBlank( 0, &hSyncCount, &gpu_wants_hcnt );
314 // Schedule next call, in hsyncs
315 hsync_steps = SpuUpdInterval[Config.PsxType] - spuSyncCount;
316 next_vsync = VBlankStart[Config.PsxType] - hSyncCount; // ok to overflow
317 next_lace = HSyncTotal[Config.PsxType] - hSyncCount;
318 if( next_vsync && next_vsync < hsync_steps )
319 hsync_steps = next_vsync;
320 if( next_lace && next_lace < hsync_steps )
321 hsync_steps = next_lace;
325 rcnts[3].cycleStart = cycle - leftover_cycles;
326 rcnts[3].cycle = hsync_steps * rcnts[3].target;
335 /******************************************************************************/
337 void psxRcntWcount( u32 index, u32 value )
339 verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );
343 _psxRcntWcount( index, value );
347 void psxRcntWmode( u32 index, u32 value )
349 verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );
353 rcnts[index].mode = value;
354 rcnts[index].irqState = 0;
359 if( value & Rc0PixelClock )
361 rcnts[index].rate = 5;
365 rcnts[index].rate = 1;
369 if( value & Rc1HSyncClock )
371 rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
375 rcnts[index].rate = 1;
379 if( value & Rc2OneEighthClock )
381 rcnts[index].rate = 8;
385 rcnts[index].rate = 1;
388 // TODO: wcount must work.
389 if( value & Rc2Disable )
391 rcnts[index].rate = 0xffffffff;
396 _psxRcntWcount( index, 0 );
400 void psxRcntWtarget( u32 index, u32 value )
402 verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );
406 rcnts[index].target = value;
408 _psxRcntWcount( index, _psxRcntRcount( index ) );
412 /******************************************************************************/
414 u32 psxRcntRcount( u32 index )
420 count = _psxRcntRcount( index );
422 // Parasite Eve 2 fix.
427 if( rcnts[index].counterState == CountToTarget )
434 verboseLog( 2, "[RCNT %i] rcount: %x\n", index, count );
439 u32 psxRcntRmode( u32 index )
445 mode = rcnts[index].mode;
446 rcnts[index].mode &= 0xe7ff;
448 verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode );
453 u32 psxRcntRtarget( u32 index )
455 verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target );
457 return rcnts[index].target;
460 /******************************************************************************/
480 rcnts[3].mode = RcCountToTarget;
481 rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
483 for( i = 0; i < CounterQuantity; ++i )
485 _psxRcntWcount( i, 0 );
495 /******************************************************************************/
497 s32 psxRcntFreeze( gzFile f, s32 Mode )
499 gzfreeze( &rcnts, sizeof(rcnts) );
500 gzfreeze( &hSyncCount, sizeof(hSyncCount) );
501 gzfreeze( &spuSyncCount, sizeof(spuSyncCount) );
502 gzfreeze( &psxNextCounter, sizeof(psxNextCounter) );
503 gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) );
506 hsync_steps = (psxRegs.cycle - rcnts[3].cycleStart) / rcnts[3].target;
511 /******************************************************************************/