1 /***************************************************************************
2 * Copyright (C) 2010 by Blade_Arma *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
18 ***************************************************************************/
21 * Internal PSX counters.
24 #include "psxcounters.h"
25 #include "psxevents.h"
30 /******************************************************************************/
34 RcSyncModeEnable = 0x0001, // 0
35 Rc01BlankPause = 0 << 1, // 1,2
36 Rc01UnblankReset = 1 << 1, // 1,2
37 Rc01UnblankReset2 = 2 << 1, // 1,2
38 Rc2Stop = 0 << 1, // 1,2
39 Rc2Stop2 = 3 << 1, // 1,2
40 RcCountToTarget = 0x0008, // 3
41 RcIrqOnTarget = 0x0010, // 4
42 RcIrqOnOverflow = 0x0020, // 5
43 RcIrqRegenerate = 0x0040, // 6
44 RcUnknown7 = 0x0080, // 7 ?
45 Rc0PixelClock = 0x0100, // 8 fake implementation
46 Rc1HSyncClock = 0x0100, // 8
47 Rc2Unknown8 = 0x0100, // 8 ?
48 Rc0Unknown9 = 0x0200, // 9 ?
49 Rc1Unknown9 = 0x0200, // 9 ?
50 Rc2OneEighthClock = 0x0200, // 9
51 RcUnknown10 = 0x0400, // 10 ?
52 RcCountEqTarget = 0x0800, // 11
53 RcOverflow = 0x1000, // 12
54 RcUnknown13 = 0x2000, // 13 ? (always zero)
55 RcUnknown14 = 0x4000, // 14 ? (always zero)
56 RcUnknown15 = 0x8000, // 15 ? (always zero)
59 #define CounterQuantity ( 4 )
60 //static const u32 CounterQuantity = 4;
62 static const u32 CountToOverflow = 0;
63 static const u32 CountToTarget = 1;
65 static const u32 HSyncTotal[] = { 263, 314 };
66 #define VBlankStart 240 // todo: depend on the actual GPU setting
68 #define VERBOSE_LEVEL 0
70 /******************************************************************************/
72 Rcnt rcnts[ CounterQuantity ];
75 u32 frame_counter = 0;
76 static u32 hsync_steps = 0;
78 u32 psxNextCounter = 0, psxNextsCounter = 0;
80 /******************************************************************************/
86 return PSXCLK / 50 / HSyncTotal[1];
88 return PSXCLK / 60 / HSyncTotal[0];
92 void setIrq( u32 irq )
94 psxHu32ref(0x1070) |= SWAPu32(irq);
98 void verboseLog( u32 level, const char *str, ... )
100 #if VERBOSE_LEVEL > 0
101 if( level <= VERBOSE_LEVEL )
107 vsprintf( buf, str, va );
116 /******************************************************************************/
119 void _psxRcntWcount( u32 index, u32 value )
123 verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value );
127 rcnts[index].cycleStart = psxRegs.cycle;
128 rcnts[index].cycleStart -= value * rcnts[index].rate;
131 if( value < rcnts[index].target )
133 rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
134 rcnts[index].counterState = CountToTarget;
138 rcnts[index].cycle = 0x10000 * rcnts[index].rate;
139 rcnts[index].counterState = CountToOverflow;
144 u32 _psxRcntRcount( u32 index )
148 count = psxRegs.cycle;
149 count -= rcnts[index].cycleStart;
150 if (rcnts[index].rate > 1)
151 count /= rcnts[index].rate;
153 if( count > 0x10000 )
155 verboseLog( 1, "[RCNT %i] rcount > 0x10000: %x\n", index, count );
163 void _psxRcntWmode( u32 index, u32 value )
165 rcnts[index].mode = value;
170 if( value & Rc0PixelClock )
172 rcnts[index].rate = 5;
176 rcnts[index].rate = 1;
180 if( value & Rc1HSyncClock )
182 rcnts[index].rate = lineCycles();
186 rcnts[index].rate = 1;
190 if( value & Rc2OneEighthClock )
192 rcnts[index].rate = 8;
196 rcnts[index].rate = 1;
199 // TODO: wcount must work.
200 if( (value & 7) == (RcSyncModeEnable | Rc2Stop) ||
201 (value & 7) == (RcSyncModeEnable | Rc2Stop2) )
203 rcnts[index].rate = 0xffffffff;
209 /******************************************************************************/
217 psxNextsCounter = psxRegs.cycle;
218 psxNextCounter = 0x7fffffff;
220 for( i = 0; i < CounterQuantity; ++i )
222 countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart);
224 if( countToUpdate < 0 )
230 if( countToUpdate < (s32)psxNextCounter )
232 psxNextCounter = countToUpdate;
236 set_event(PSXINT_RCNT, psxNextCounter);
239 /******************************************************************************/
242 void psxRcntReset( u32 index )
246 rcnts[index].mode |= RcUnknown10;
248 if( rcnts[index].counterState == CountToTarget )
250 rcycles = psxRegs.cycle - rcnts[index].cycleStart;
251 if( rcnts[index].mode & RcCountToTarget )
253 rcycles -= rcnts[index].target * rcnts[index].rate;
254 rcnts[index].cycleStart = psxRegs.cycle - rcycles;
258 rcnts[index].cycle = 0x10000 * rcnts[index].rate;
259 rcnts[index].counterState = CountToOverflow;
262 if( rcnts[index].mode & RcIrqOnTarget )
264 if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
266 verboseLog( 3, "[RCNT %i] irq\n", index );
267 setIrq( rcnts[index].irq );
268 rcnts[index].irqState = 1;
272 rcnts[index].mode |= RcCountEqTarget;
274 if( rcycles < 0x10000 * rcnts[index].rate )
278 if( rcnts[index].counterState == CountToOverflow )
280 rcycles = psxRegs.cycle - rcnts[index].cycleStart;
281 rcycles -= 0x10000 * rcnts[index].rate;
283 rcnts[index].cycleStart = psxRegs.cycle - rcycles;
285 if( rcycles < rcnts[index].target * rcnts[index].rate )
287 rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
288 rcnts[index].counterState = CountToTarget;
291 if( rcnts[index].mode & RcIrqOnOverflow )
293 if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
295 verboseLog( 3, "[RCNT %i] irq\n", index );
296 setIrq( rcnts[index].irq );
297 rcnts[index].irqState = 1;
301 rcnts[index].mode |= RcOverflow;
305 static void scheduleRcntBase(void)
307 // Schedule next call, in hsyncs
308 if (hSyncCount < VBlankStart)
309 hsync_steps = VBlankStart - hSyncCount;
311 hsync_steps = HSyncTotal[Config.PsxType] - hSyncCount;
313 if (hSyncCount + hsync_steps == HSyncTotal[Config.PsxType])
315 rcnts[3].cycle = Config.PsxType ? PSXCLK / 50 : PSXCLK / 60;
319 // clk / 50 / 314 ~= 2157.25
320 // clk / 60 / 263 ~= 2146.31
321 u32 mult = Config.PsxType ? 8836089 : 8791293;
322 rcnts[3].cycle = hsync_steps * mult >> 12;
328 u32 cycle, cycles_passed;
330 cycle = psxRegs.cycle;
333 cycles_passed = cycle - rcnts[0].cycleStart;
334 while( cycles_passed >= rcnts[0].cycle )
336 if (((rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset) ||
337 (rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset2))
338 && cycles_passed > lineCycles())
340 u32 q = cycles_passed / (lineCycles() + 1u);
341 rcnts[0].cycleStart += q * lineCycles();
347 cycles_passed = cycle - rcnts[0].cycleStart;
351 while( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
357 while( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
363 if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
365 hSyncCount += hsync_steps;
368 if( hSyncCount == VBlankStart )
370 HW_GPU_STATUS &= SWAP32(~PSXGPU_LCF);
379 SPU_async( cycle, 1 );
384 if( hSyncCount >= HSyncTotal[Config.PsxType] )
386 u32 status, field = 0;
387 rcnts[3].cycleStart += Config.PsxType ? PSXCLK / 50 : PSXCLK / 60;
392 status = SWAP32(HW_GPU_STATUS) | PSXGPU_FIELD;
393 if ((status & PSXGPU_ILACE_BITS) == PSXGPU_ILACE_BITS) {
394 field = frame_counter & 1;
395 status |= field << 31;
396 status ^= field << 13;
398 HW_GPU_STATUS = SWAP32(status);
399 GPU_vBlank(0, field);
400 if ((s32)(psxRegs.gpuIdleAfter - psxRegs.cycle) < 0)
401 psxRegs.gpuIdleAfter = psxRegs.cycle - 1; // prevent overflow
403 if ((rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset) ||
404 (rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset2))
406 rcnts[0].cycleStart = rcnts[3].cycleStart;
409 if ((rcnts[1].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset) ||
410 (rcnts[1].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset2))
412 rcnts[1].cycleStart = rcnts[3].cycleStart;
414 else if (rcnts[1].mode & Rc1HSyncClock)
416 // adjust to remove the rounding error
417 _psxRcntWcount(1, (psxRegs.cycle - rcnts[1].cycleStart) / rcnts[1].rate);
431 /******************************************************************************/
433 void psxRcntWcount( u32 index, u32 value )
435 verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );
437 _psxRcntWcount( index, value );
441 void psxRcntWmode( u32 index, u32 value )
443 verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );
445 _psxRcntWmode( index, value );
446 _psxRcntWcount( index, 0 );
448 rcnts[index].irqState = 0;
452 void psxRcntWtarget( u32 index, u32 value )
454 verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );
456 rcnts[index].target = value;
458 _psxRcntWcount( index, _psxRcntRcount( index ) );
462 /******************************************************************************/
469 if ((rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset) ||
470 (rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset2))
472 count = psxRegs.cycle - rcnts[index].cycleStart;
473 //count = ((16u * count) % (16u * PSXCLK / 60 / 263)) / 16u;
474 count = count % lineCycles();
475 rcnts[index].cycleStart = psxRegs.cycle - count;
478 count = _psxRcntRcount( index );
480 verboseLog( 2, "[RCNT 0] rcount: %04x m: %04x\n", count, rcnts[index].mode);
490 count = _psxRcntRcount( index );
492 verboseLog( 2, "[RCNT 1] rcount: %04x m: %04x\n", count, rcnts[index].mode);
502 count = _psxRcntRcount( index );
504 verboseLog( 2, "[RCNT 2] rcount: %04x m: %04x\n", count, rcnts[index].mode);
509 u32 psxRcntRmode( u32 index )
513 mode = rcnts[index].mode;
514 rcnts[index].mode &= 0xe7ff;
516 verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode );
521 u32 psxRcntRtarget( u32 index )
523 verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target );
525 return rcnts[index].target;
528 /******************************************************************************/
549 for( i = 0; i < CounterQuantity; ++i )
551 _psxRcntWcount( i, 0 );
561 /******************************************************************************/
563 s32 psxRcntFreeze( void *f, s32 Mode )
565 u32 spuSyncCount = 0;
569 gzfreeze( &rcnts, sizeof(Rcnt) * CounterQuantity );
570 gzfreeze( &hSyncCount, sizeof(hSyncCount) );
571 gzfreeze( &spuSyncCount, sizeof(spuSyncCount) );
572 gzfreeze( &psxNextCounter, sizeof(psxNextCounter) );
573 gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) );
578 for( i = 0; i < CounterQuantity - 1; ++i )
580 _psxRcntWmode( i, rcnts[i].mode );
581 count = (psxRegs.cycle - rcnts[i].cycleStart) / rcnts[i].rate;
583 _psxRcntWcount( i, count & 0xffff );
592 /******************************************************************************/
593 // vim:ts=4:shiftwidth=4:expandtab