1 /***************************************************************************
2 * Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
18 ***************************************************************************/
21 * Functions for PSX hardware control.
30 //#define PSXHW_LOG printf
36 memset(psxH, 0, 0x10000);
38 mdecInit(); // initialize mdec decoder
41 HW_GPU_STATUS = SWAP32(0x14802000);
44 void psxHwWriteIstat(u32 value)
46 u32 stat = psxHu16(0x1070) & value;
47 psxHu16ref(0x1070) = SWAPu16(stat);
49 psxRegs.CP0.n.Cause &= ~0x400;
50 if (stat & psxHu16(0x1074))
51 psxRegs.CP0.n.Cause |= 0x400;
54 void psxHwWriteImask(u32 value)
56 u32 stat = psxHu16(0x1070);
57 psxHu16ref(0x1074) = SWAPu16(value);
59 //if ((psxRegs.CP0.n.SR & 0x401) == 0x401)
60 // log_unhandled("irq on unmask @%08x\n", psxRegs.pc);
61 new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
63 psxRegs.CP0.n.Cause &= ~0x400;
65 psxRegs.CP0.n.Cause |= 0x400;
68 void psxHwWriteDmaIcr32(u32 value)
70 u32 tmp = value & 0x00ff803f;
71 tmp |= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000;
72 if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000)
73 || tmp & HW_DMA_ICR_BUS_ERROR) {
74 if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT))
75 psxHu32ref(0x1070) |= SWAP32(8);
76 tmp |= HW_DMA_ICR_IRQ_SENT;
78 HW_DMA_ICR = SWAPu32(tmp);
81 u8 psxHwRead8(u32 add) {
84 switch (add & 0x1fffffff) {
85 case 0x1f801040: hard = sioRead8(); break;
86 case 0x1f801800: hard = cdrRead0(); break;
87 case 0x1f801801: hard = cdrRead1(); break;
88 case 0x1f801802: hard = cdrRead2(); break;
89 case 0x1f801803: hard = cdrRead3(); break;
91 case 0x1f801041: case 0x1f801042: case 0x1f801043:
92 case 0x1f801044: case 0x1f801045:
93 case 0x1f801046: case 0x1f801047:
94 case 0x1f801048: case 0x1f801049:
95 case 0x1f80104a: case 0x1f80104b:
96 case 0x1f80104c: case 0x1f80104d:
97 case 0x1f80104e: case 0x1f80104f:
98 case 0x1f801050: case 0x1f801051:
99 case 0x1f801054: case 0x1f801055:
100 case 0x1f801058: case 0x1f801059:
101 case 0x1f80105a: case 0x1f80105b:
102 case 0x1f80105c: case 0x1f80105d:
103 case 0x1f801100: case 0x1f801101:
104 case 0x1f801104: case 0x1f801105:
105 case 0x1f801108: case 0x1f801109:
106 case 0x1f801110: case 0x1f801111:
107 case 0x1f801114: case 0x1f801115:
108 case 0x1f801118: case 0x1f801119:
109 case 0x1f801120: case 0x1f801121:
110 case 0x1f801124: case 0x1f801125:
111 case 0x1f801128: case 0x1f801129:
112 case 0x1f801810: case 0x1f801811:
113 case 0x1f801812: case 0x1f801813:
114 case 0x1f801814: case 0x1f801815:
115 case 0x1f801816: case 0x1f801817:
116 case 0x1f801820: case 0x1f801821:
117 case 0x1f801822: case 0x1f801823:
118 case 0x1f801824: case 0x1f801825:
119 case 0x1f801826: case 0x1f801827:
120 log_unhandled("unhandled r8 %08x @%08x\n", add, psxRegs.pc);
123 if (0x1f801c00 <= add && add < 0x1f802000)
124 log_unhandled("spu r8 %02x @%08x\n", add, psxRegs.pc);
127 PSXHW_LOG("*Unkwnown 8bit read at address %x\n", add);
133 PSXHW_LOG("*Known 8bit read at address %x value %x\n", add, hard);
138 u16 psxHwRead16(u32 add) {
141 switch (add & 0x1fffffff) {
143 case 0x1f801070: PSXHW_LOG("IREG 16bit read %x\n", psxHu16(0x1070));
144 return psxHu16(0x1070);
145 case 0x1f801074: PSXHW_LOG("IMASK 16bit read %x\n", psxHu16(0x1074));
146 return psxHu16(0x1074);
150 hard|= sioRead8() << 8;
151 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
154 hard = sioReadStat16();
155 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
158 hard = sioReadMode16();
159 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
162 hard = sioReadCtrl16();
163 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
166 hard = sioReadBaud16();
167 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
170 /* Fixes Armored Core misdetecting the Link cable being detected.
171 * We want to turn that thing off and force it to do local multiplayer instead.
172 * Thanks Sony for the fix, they fixed it in their PS Classic fork.
178 hard = psxRcntRcount0();
180 PSXHW_LOG("T0 count read16: %x\n", hard);
184 hard = psxRcntRmode(0);
186 PSXHW_LOG("T0 mode read16: %x\n", hard);
190 hard = psxRcntRtarget(0);
192 PSXHW_LOG("T0 target read16: %x\n", hard);
196 hard = psxRcntRcount1();
198 PSXHW_LOG("T1 count read16: %x\n", hard);
202 hard = psxRcntRmode(1);
204 PSXHW_LOG("T1 mode read16: %x\n", hard);
208 hard = psxRcntRtarget(1);
210 PSXHW_LOG("T1 target read16: %x\n", hard);
214 hard = psxRcntRcount2();
216 PSXHW_LOG("T2 count read16: %x\n", hard);
220 hard = psxRcntRmode(2);
222 PSXHW_LOG("T2 mode read16: %x\n", hard);
226 hard = psxRcntRtarget(2);
228 PSXHW_LOG("T2 target read16: %x\n", hard);
232 //case 0x1f802030: hard = //int_2000????
233 //case 0x1f802040: hard =//dip switches...??
252 log_unhandled("unhandled r16 %08x @%08x\n", add, psxRegs.pc);
255 if (0x1f801c00 <= add && add < 0x1f802000)
256 return SPU_readRegister(add, psxRegs.cycle);
259 PSXHW_LOG("*Unkwnown 16bit read at address %x\n", add);
265 PSXHW_LOG("*Known 16bit read at address %x value %x\n", add, hard);
270 u32 psxHwRead32(u32 add) {
273 switch (add & 0x1fffffff) {
276 hard |= sioRead8() << 8;
277 hard |= sioRead8() << 16;
278 hard |= sioRead8() << 24;
279 PAD_LOG("sio read32 ;ret = %x\n", hard);
282 hard = sioReadStat16();
283 PAD_LOG("sio read32 %x; ret = %x\n", add&0xf, hard);
287 PSXHW_LOG("RAM size read %x\n", psxHu32(0x1060));
288 return psxHu32(0x1060);
289 case 0x1f801070: PSXHW_LOG("IREG 32bit read %x\n", psxHu32(0x1070));
290 return psxHu32(0x1070);
291 case 0x1f801074: PSXHW_LOG("IMASK 32bit read %x\n", psxHu32(0x1074));
292 return psxHu32(0x1074);
296 hard = GPU_readData();
298 PSXHW_LOG("GPU DATA 32bit read %x\n", hard);
303 hard = SWAP32(HW_GPU_STATUS);
304 if (hSyncCount < 240 && (hard & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS)
305 hard |= PSXGPU_LCF & (psxRegs.cycle << 20);
307 PSXHW_LOG("GPU STATUS 32bit read %x\n", hard);
311 case 0x1f801820: hard = mdecRead0(); break;
312 case 0x1f801824: hard = mdecRead1(); break;
316 PSXHW_LOG("DMA2 MADR 32bit read %x\n", psxHu32(0x10a0));
317 return SWAPu32(HW_DMA2_MADR);
319 PSXHW_LOG("DMA2 BCR 32bit read %x\n", psxHu32(0x10a4));
320 return SWAPu32(HW_DMA2_BCR);
322 PSXHW_LOG("DMA2 CHCR 32bit read %x\n", psxHu32(0x10a8));
323 return SWAPu32(HW_DMA2_CHCR);
328 PSXHW_LOG("DMA3 MADR 32bit read %x\n", psxHu32(0x10b0));
329 return SWAPu32(HW_DMA3_MADR);
331 PSXHW_LOG("DMA3 BCR 32bit read %x\n", psxHu32(0x10b4));
332 return SWAPu32(HW_DMA3_BCR);
334 PSXHW_LOG("DMA3 CHCR 32bit read %x\n", psxHu32(0x10b8));
335 return SWAPu32(HW_DMA3_CHCR);
340 PSXHW_LOG("DMA PCR 32bit read %x\n", psxHu32(0x10f0));
341 return SWAPu32(HW_DMA_PCR); // dma rest channel
343 PSXHW_LOG("DMA ICR 32bit read %x\n", psxHu32(0x10f4));
344 return SWAPu32(HW_DMA_ICR); // interrupt enabler?*/
347 // time for rootcounters :)
349 hard = psxRcntRcount0();
351 PSXHW_LOG("T0 count read32: %x\n", hard);
355 hard = psxRcntRmode(0);
357 PSXHW_LOG("T0 mode read32: %x\n", hard);
361 hard = psxRcntRtarget(0);
363 PSXHW_LOG("T0 target read32: %x\n", hard);
367 hard = psxRcntRcount1();
369 PSXHW_LOG("T1 count read32: %x\n", hard);
373 hard = psxRcntRmode(1);
375 PSXHW_LOG("T1 mode read32: %x\n", hard);
379 hard = psxRcntRtarget(1);
381 PSXHW_LOG("T1 target read32: %x\n", hard);
385 hard = psxRcntRcount2();
387 PSXHW_LOG("T2 count read32: %x\n", hard);
391 hard = psxRcntRmode(2);
393 PSXHW_LOG("T2 mode read32: %x\n", hard);
397 hard = psxRcntRtarget(2);
399 PSXHW_LOG("T2 target read32: %x\n", hard);
410 log_unhandled("unhandled r32 %08x @%08x\n", add, psxRegs.pc);
413 if (0x1f801c00 <= add && add < 0x1f802000) {
414 hard = SPU_readRegister(add, psxRegs.cycle);
415 hard |= SPU_readRegister(add + 2, psxRegs.cycle) << 16;
420 PSXHW_LOG("*Unkwnown 32bit read at address %x\n", add);
425 PSXHW_LOG("*Known 32bit read at address %x\n", add);
430 void psxHwWrite8(u32 add, u8 value) {
431 switch (add & 0x1fffffff) {
432 case 0x1f801040: sioWrite8(value); break;
\r
433 case 0x1f801800: cdrWrite0(value); break;
434 case 0x1f801801: cdrWrite1(value); break;
435 case 0x1f801802: cdrWrite2(value); break;
436 case 0x1f801803: cdrWrite3(value); break;
438 case 0x1f801041: case 0x1f801042: case 0x1f801043:
439 case 0x1f801044: case 0x1f801045:
440 case 0x1f801046: case 0x1f801047:
441 case 0x1f801048: case 0x1f801049:
442 case 0x1f80104a: case 0x1f80104b:
443 case 0x1f80104c: case 0x1f80104d:
444 case 0x1f80104e: case 0x1f80104f:
445 case 0x1f801050: case 0x1f801051:
446 case 0x1f801054: case 0x1f801055:
447 case 0x1f801058: case 0x1f801059:
448 case 0x1f80105a: case 0x1f80105b:
449 case 0x1f80105c: case 0x1f80105d:
450 case 0x1f801100: case 0x1f801101:
451 case 0x1f801104: case 0x1f801105:
452 case 0x1f801108: case 0x1f801109:
453 case 0x1f801110: case 0x1f801111:
454 case 0x1f801114: case 0x1f801115:
455 case 0x1f801118: case 0x1f801119:
456 case 0x1f801120: case 0x1f801121:
457 case 0x1f801124: case 0x1f801125:
458 case 0x1f801128: case 0x1f801129:
459 case 0x1f801810: case 0x1f801811:
460 case 0x1f801812: case 0x1f801813:
461 case 0x1f801814: case 0x1f801815:
462 case 0x1f801816: case 0x1f801817:
463 case 0x1f801820: case 0x1f801821:
464 case 0x1f801822: case 0x1f801823:
465 case 0x1f801824: case 0x1f801825:
466 case 0x1f801826: case 0x1f801827:
467 log_unhandled("unhandled w8 %08x @%08x\n", add, psxRegs.pc);
470 if (0x1f801c00 <= add && add < 0x1f802000) {
471 log_unhandled("spu w8 %02x @%08x\n", value, psxRegs.pc);
473 SPU_writeRegister(add, value, psxRegs.cycle);
479 PSXHW_LOG("*Unknown 8bit write at address %x value %x\n", add, value);
485 PSXHW_LOG("*Known 8bit write at address %x value %x\n", add, value);
489 void psxHwWrite16(u32 add, u16 value) {
490 switch (add & 0x1fffffff) {
492 sioWrite8((unsigned char)value);
493 sioWrite8((unsigned char)(value>>8));
494 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
497 sioWriteStat16(value);
498 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
501 sioWriteMode16(value);
502 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
504 case 0x1f80104a: // control register
505 sioWriteCtrl16(value);
506 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
508 case 0x1f80104e: // baudrate register
509 sioWriteBaud16(value);
510 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
514 PSXHW_LOG("IREG 16bit write %x\n", value);
516 psxHwWriteIstat(value);
521 PSXHW_LOG("IMASK 16bit write %x\n", value);
523 psxHwWriteImask(value);
528 PSXHW_LOG("COUNTER 0 COUNT 16bit write %x\n", value);
530 psxRcntWcount(0, value); return;
533 PSXHW_LOG("COUNTER 0 MODE 16bit write %x\n", value);
535 psxRcntWmode(0, value); return;
538 PSXHW_LOG("COUNTER 0 TARGET 16bit write %x\n", value);
540 psxRcntWtarget(0, value); return;
544 PSXHW_LOG("COUNTER 1 COUNT 16bit write %x\n", value);
546 psxRcntWcount(1, value); return;
549 PSXHW_LOG("COUNTER 1 MODE 16bit write %x\n", value);
551 psxRcntWmode(1, value); return;
554 PSXHW_LOG("COUNTER 1 TARGET 16bit write %x\n", value);
556 psxRcntWtarget(1, value); return;
560 PSXHW_LOG("COUNTER 2 COUNT 16bit write %x\n", value);
562 psxRcntWcount(2, value); return;
565 PSXHW_LOG("COUNTER 2 MODE 16bit write %x\n", value);
567 psxRcntWmode(2, value); return;
570 PSXHW_LOG("COUNTER 2 TARGET 16bit write %x\n", value);
572 psxRcntWtarget(2, value); return;
592 log_unhandled("unhandled w16 %08x @%08x\n", add, psxRegs.pc);
595 if (0x1f801c00 <= add && add < 0x1f802000) {
596 SPU_writeRegister(add, value, psxRegs.cycle);
600 psxHu16ref(add) = SWAPu16(value);
602 PSXHW_LOG("*Unknown 16bit write at address %x value %x\n", add, value);
606 psxHu16ref(add) = SWAPu16(value);
608 PSXHW_LOG("*Known 16bit write at address %x value %x\n", add, value);
612 #define DmaExec(n) { \
613 if (value & SWAPu32(HW_DMA##n##_CHCR) & 0x01000000) \
614 log_unhandled("dma" #n " %08x -> %08x\n", HW_DMA##n##_CHCR, value); \
615 HW_DMA##n##_CHCR = SWAPu32(value); \
617 if (SWAPu32(HW_DMA##n##_CHCR) & 0x01000000 && SWAPu32(HW_DMA_PCR) & (8 << (n * 4))) { \
618 psxDma##n(SWAPu32(HW_DMA##n##_MADR), SWAPu32(HW_DMA##n##_BCR), SWAPu32(HW_DMA##n##_CHCR)); \
622 void psxHwWrite32(u32 add, u32 value) {
623 switch (add & 0x1fffffff) {
625 sioWrite8((unsigned char)value);
626 sioWrite8((unsigned char)((value&0xff) >> 8));
627 sioWrite8((unsigned char)((value&0xff) >> 16));
628 sioWrite8((unsigned char)((value&0xff) >> 24));
629 PAD_LOG("sio write32 %x\n", value);
633 PSXHW_LOG("RAM size write %x\n", value);
634 psxHu32ref(add) = SWAPu32(value);
640 PSXHW_LOG("IREG 32bit write %x\n", value);
642 psxHwWriteIstat(value);
646 PSXHW_LOG("IMASK 32bit write %x\n", value);
648 psxHwWriteImask(value);
653 PSXHW_LOG("DMA0 MADR 32bit write %x\n", value);
654 HW_DMA0_MADR = SWAPu32(value); return; // DMA0 madr
656 PSXHW_LOG("DMA0 BCR 32bit write %x\n", value);
657 HW_DMA0_BCR = SWAPu32(value); return; // DMA0 bcr
661 PSXHW_LOG("DMA0 CHCR 32bit write %x\n", value);
663 DmaExec(0); // DMA0 chcr (MDEC in DMA)
668 PSXHW_LOG("DMA1 MADR 32bit write %x\n", value);
669 HW_DMA1_MADR = SWAPu32(value); return; // DMA1 madr
671 PSXHW_LOG("DMA1 BCR 32bit write %x\n", value);
672 HW_DMA1_BCR = SWAPu32(value); return; // DMA1 bcr
676 PSXHW_LOG("DMA1 CHCR 32bit write %x\n", value);
678 DmaExec(1); // DMA1 chcr (MDEC out DMA)
683 PSXHW_LOG("DMA2 MADR 32bit write %x\n", value);
684 HW_DMA2_MADR = SWAPu32(value); return; // DMA2 madr
686 PSXHW_LOG("DMA2 BCR 32bit write %x\n", value);
687 HW_DMA2_BCR = SWAPu32(value); return; // DMA2 bcr
691 PSXHW_LOG("DMA2 CHCR 32bit write %x\n", value);
693 DmaExec(2); // DMA2 chcr (GPU DMA)
698 PSXHW_LOG("DMA3 MADR 32bit write %x\n", value);
699 HW_DMA3_MADR = SWAPu32(value); return; // DMA3 madr
701 PSXHW_LOG("DMA3 BCR 32bit write %x\n", value);
702 HW_DMA3_BCR = SWAPu32(value); return; // DMA3 bcr
706 PSXHW_LOG("DMA3 CHCR 32bit write %x\n", value);
708 DmaExec(3); // DMA3 chcr (CDROM DMA)
714 PSXHW_LOG("DMA4 MADR 32bit write %x\n", value);
715 HW_DMA4_MADR = SWAPu32(value); return; // DMA4 madr
717 PSXHW_LOG("DMA4 BCR 32bit write %x\n", value);
718 HW_DMA4_BCR = SWAPu32(value); return; // DMA4 bcr
722 PSXHW_LOG("DMA4 CHCR 32bit write %x\n", value);
724 DmaExec(4); // DMA4 chcr (SPU DMA)
728 case 0x1f8010d0: break; //DMA5write_madr();
729 case 0x1f8010d4: break; //DMA5write_bcr();
730 case 0x1f8010d8: break; //DMA5write_chcr(); // Not needed
735 PSXHW_LOG("DMA6 MADR 32bit write %x\n", value);
736 HW_DMA6_MADR = SWAPu32(value); return; // DMA6 bcr
738 PSXHW_LOG("DMA6 BCR 32bit write %x\n", value);
739 HW_DMA6_BCR = SWAPu32(value); return; // DMA6 bcr
743 PSXHW_LOG("DMA6 CHCR 32bit write %x\n", value);
745 DmaExec(6); // DMA6 chcr (OT clear)
750 PSXHW_LOG("DMA PCR 32bit write %x\n", value);
751 HW_DMA_PCR = SWAPu32(value);
757 PSXHW_LOG("DMA ICR 32bit write %x\n", value);
759 psxHwWriteDmaIcr32(value);
764 PSXHW_LOG("GPU DATA 32bit write %x\n", value);
766 GPU_writeData(value); return;
769 PSXHW_LOG("GPU STATUS 32bit write %x\n", value);
771 GPU_writeStatus(value);
776 mdecWrite0(value); break;
778 mdecWrite1(value); break;
782 PSXHW_LOG("COUNTER 0 COUNT 32bit write %x\n", value);
784 psxRcntWcount(0, value & 0xffff); return;
787 PSXHW_LOG("COUNTER 0 MODE 32bit write %x\n", value);
789 psxRcntWmode(0, value); return;
792 PSXHW_LOG("COUNTER 0 TARGET 32bit write %x\n", value);
794 psxRcntWtarget(0, value & 0xffff); return; // HW_DMA_ICR&= SWAP32((~value)&0xff000000);
798 PSXHW_LOG("COUNTER 1 COUNT 32bit write %x\n", value);
800 psxRcntWcount(1, value & 0xffff); return;
803 PSXHW_LOG("COUNTER 1 MODE 32bit write %x\n", value);
805 psxRcntWmode(1, value); return;
808 PSXHW_LOG("COUNTER 1 TARGET 32bit write %x\n", value);
810 psxRcntWtarget(1, value & 0xffff); return;
814 PSXHW_LOG("COUNTER 2 COUNT 32bit write %x\n", value);
816 psxRcntWcount(2, value & 0xffff); return;
819 PSXHW_LOG("COUNTER 2 MODE 32bit write %x\n", value);
821 psxRcntWmode(2, value); return;
824 PSXHW_LOG("COUNTER 2 TARGET 32bit write %x\n", value);
826 psxRcntWtarget(2, value & 0xffff); return;
836 log_unhandled("unhandled w32 %08x @%08x\n", add, psxRegs.pc);
839 // Dukes of Hazard 2 - car engine noise
840 if (0x1f801c00 <= add && add < 0x1f802000) {
841 SPU_writeRegister(add, value&0xffff, psxRegs.cycle);
842 SPU_writeRegister(add + 2, value>>16, psxRegs.cycle);
846 psxHu32ref(add) = SWAPu32(value);
848 PSXHW_LOG("*Unknown 32bit write at address %x value %x\n", add, value);
852 psxHu32ref(add) = SWAPu32(value);
854 PSXHW_LOG("*Known 32bit write at address %x value %x\n", add, value);
858 int psxHwFreeze(void *f, int Mode) {