1 /***************************************************************************
2 * Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
18 ***************************************************************************/
21 * Functions for PSX hardware control.
25 #include "psxevents.h"
31 //#define PSXHW_LOG printf
36 static u32 (*psxHwReadGpuSRptr)(void) = psxHwReadGpuSR;
39 memset(psxH, 0, 0x10000);
41 mdecInit(); // initialize mdec decoder
44 HW_GPU_STATUS = SWAP32(0x10802000);
45 psxHwReadGpuSRptr = Config.hacks.gpu_busy_hack
46 ? psxHwReadGpuSRbusyHack : psxHwReadGpuSR;
49 void psxHwWriteIstat(u32 value)
51 u32 stat = psxHu16(0x1070) & value;
52 psxHu16ref(0x1070) = SWAPu16(stat);
54 psxRegs.CP0.n.Cause &= ~0x400;
55 if (stat & psxHu16(0x1074))
56 psxRegs.CP0.n.Cause |= 0x400;
59 void psxHwWriteImask(u32 value)
61 u32 stat = psxHu16(0x1070);
62 psxHu16ref(0x1074) = SWAPu16(value);
64 //if ((psxRegs.CP0.n.SR & 0x401) == 0x401)
65 // log_unhandled("irq on unmask @%08x\n", psxRegs.pc);
66 set_event(PSXINT_NEWDRC_CHECK, 1);
68 psxRegs.CP0.n.Cause &= ~0x400;
70 psxRegs.CP0.n.Cause |= 0x400;
73 void psxHwWriteDmaIcr32(u32 value)
75 u32 tmp = value & 0x00ff803f;
76 tmp |= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000;
77 if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000)
78 || tmp & HW_DMA_ICR_BUS_ERROR) {
79 if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT))
80 psxHu32ref(0x1070) |= SWAP32(8);
81 tmp |= HW_DMA_ICR_IRQ_SENT;
83 HW_DMA_ICR = SWAPu32(tmp);
86 void psxHwWriteGpuSR(u32 value)
88 GPU_writeStatus(value);
92 u32 psxHwReadGpuSR(void)
94 u32 v, c = psxRegs.cycle;
96 // meh2, syncing for img bit, might want to avoid it..
98 v = SWAP32(HW_GPU_STATUS);
99 v |= ((s32)(psxRegs.gpuIdleAfter - c) >> 31) & PSXGPU_nBUSY;
101 // XXX: because of large timeslices can't use hSyncCount, using rough
102 // approximization instead. Perhaps better use hcounter code here or something.
103 if (hSyncCount < 240 && (v & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS)
104 v |= PSXGPU_LCF & (c << 20);
108 // a hack due to poor timing of gpu idle bit
109 // to get rid of this, GPU draw times, DMAs, cpu timing has to fall within
110 // certain timing window or else games like "ToHeart" softlock
111 u32 psxHwReadGpuSRbusyHack(void)
113 u32 v = psxHwReadGpuSR();
120 u8 psxHwRead8(u32 add) {
123 switch (add & 0x1fffffff) {
124 case 0x1f801040: hard = sioRead8(); break;
125 case 0x1f801800: hard = cdrRead0(); break;
126 case 0x1f801801: hard = cdrRead1(); break;
127 case 0x1f801802: hard = cdrRead2(); break;
128 case 0x1f801803: hard = cdrRead3(); break;
130 case 0x1f801041: case 0x1f801042: case 0x1f801043:
131 case 0x1f801044: case 0x1f801045:
132 case 0x1f801046: case 0x1f801047:
133 case 0x1f801048: case 0x1f801049:
134 case 0x1f80104a: case 0x1f80104b:
135 case 0x1f80104c: case 0x1f80104d:
136 case 0x1f80104e: case 0x1f80104f:
137 case 0x1f801050: case 0x1f801051:
138 case 0x1f801054: case 0x1f801055:
139 case 0x1f801058: case 0x1f801059:
140 case 0x1f80105a: case 0x1f80105b:
141 case 0x1f80105c: case 0x1f80105d:
142 case 0x1f801100: case 0x1f801101:
143 case 0x1f801104: case 0x1f801105:
144 case 0x1f801108: case 0x1f801109:
145 case 0x1f801110: case 0x1f801111:
146 case 0x1f801114: case 0x1f801115:
147 case 0x1f801118: case 0x1f801119:
148 case 0x1f801120: case 0x1f801121:
149 case 0x1f801124: case 0x1f801125:
150 case 0x1f801128: case 0x1f801129:
151 case 0x1f801810: case 0x1f801811:
152 case 0x1f801812: case 0x1f801813:
153 case 0x1f801814: case 0x1f801815:
154 case 0x1f801816: case 0x1f801817:
155 case 0x1f801820: case 0x1f801821:
156 case 0x1f801822: case 0x1f801823:
157 case 0x1f801824: case 0x1f801825:
158 case 0x1f801826: case 0x1f801827:
159 log_unhandled("unhandled r8 %08x @%08x\n", add, psxRegs.pc);
162 if (0x1f801c00 <= add && add < 0x1f802000) {
163 u16 val = SPU_readRegister(add & ~1, psxRegs.cycle);
164 hard = (add & 1) ? val >> 8 : val;
169 PSXHW_LOG("*Unkwnown 8bit read at address %x\n", add);
175 PSXHW_LOG("*Known 8bit read at address %x value %x\n", add, hard);
180 u16 psxHwRead16(u32 add) {
183 switch (add & 0x1fffffff) {
185 case 0x1f801070: PSXHW_LOG("IREG 16bit read %x\n", psxHu16(0x1070));
186 return psxHu16(0x1070);
187 case 0x1f801074: PSXHW_LOG("IMASK 16bit read %x\n", psxHu16(0x1074));
188 return psxHu16(0x1074);
192 hard|= sioRead8() << 8;
193 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
196 hard = sioReadStat16();
197 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
200 hard = sioReadMode16();
201 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
204 hard = sioReadCtrl16();
205 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
208 hard = sioReadBaud16();
209 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
212 /* Fixes Armored Core misdetecting the Link cable being detected.
213 * We want to turn that thing off and force it to do local multiplayer instead.
214 * Thanks Sony for the fix, they fixed it in their PS Classic fork.
220 hard = psxRcntRcount0();
222 PSXHW_LOG("T0 count read16: %x\n", hard);
226 hard = psxRcntRmode(0);
228 PSXHW_LOG("T0 mode read16: %x\n", hard);
232 hard = psxRcntRtarget(0);
234 PSXHW_LOG("T0 target read16: %x\n", hard);
238 hard = psxRcntRcount1();
240 PSXHW_LOG("T1 count read16: %x\n", hard);
244 hard = psxRcntRmode(1);
246 PSXHW_LOG("T1 mode read16: %x\n", hard);
250 hard = psxRcntRtarget(1);
252 PSXHW_LOG("T1 target read16: %x\n", hard);
256 hard = psxRcntRcount2();
258 PSXHW_LOG("T2 count read16: %x\n", hard);
262 hard = psxRcntRmode(2);
264 PSXHW_LOG("T2 mode read16: %x\n", hard);
268 hard = psxRcntRtarget(2);
270 PSXHW_LOG("T2 target read16: %x\n", hard);
274 //case 0x1f802030: hard = //int_2000????
275 //case 0x1f802040: hard =//dip switches...??
294 log_unhandled("unhandled r16 %08x @%08x\n", add, psxRegs.pc);
297 if (0x1f801c00 <= add && add < 0x1f802000)
298 return SPU_readRegister(add, psxRegs.cycle);
301 PSXHW_LOG("*Unkwnown 16bit read at address %x\n", add);
307 PSXHW_LOG("*Known 16bit read at address %x value %x\n", add, hard);
312 u32 psxHwRead32(u32 add) {
315 switch (add & 0x1fffffff) {
318 hard |= sioRead8() << 8;
319 hard |= sioRead8() << 16;
320 hard |= sioRead8() << 24;
321 PAD_LOG("sio read32 ;ret = %x\n", hard);
324 hard = sioReadStat16();
325 PAD_LOG("sio read32 %x; ret = %x\n", add&0xf, hard);
329 PSXHW_LOG("RAM size read %x\n", psxHu32(0x1060));
330 return psxHu32(0x1060);
331 case 0x1f801070: PSXHW_LOG("IREG 32bit read %x\n", psxHu32(0x1070));
332 return psxHu32(0x1070);
333 case 0x1f801074: PSXHW_LOG("IMASK 32bit read %x\n", psxHu32(0x1074));
334 return psxHu32(0x1074);
338 hard = GPU_readData();
340 PSXHW_LOG("GPU DATA 32bit read %x\n", hard);
344 hard = psxHwReadGpuSRptr();
346 PSXHW_LOG("GPU STATUS 32bit read %x\n", hard);
350 case 0x1f801820: hard = mdecRead0(); break;
351 case 0x1f801824: hard = mdecRead1(); break;
355 PSXHW_LOG("DMA2 MADR 32bit read %x\n", psxHu32(0x10a0));
356 return SWAPu32(HW_DMA2_MADR);
358 PSXHW_LOG("DMA2 BCR 32bit read %x\n", psxHu32(0x10a4));
359 return SWAPu32(HW_DMA2_BCR);
361 PSXHW_LOG("DMA2 CHCR 32bit read %x\n", psxHu32(0x10a8));
362 return SWAPu32(HW_DMA2_CHCR);
367 PSXHW_LOG("DMA3 MADR 32bit read %x\n", psxHu32(0x10b0));
368 return SWAPu32(HW_DMA3_MADR);
370 PSXHW_LOG("DMA3 BCR 32bit read %x\n", psxHu32(0x10b4));
371 return SWAPu32(HW_DMA3_BCR);
373 PSXHW_LOG("DMA3 CHCR 32bit read %x\n", psxHu32(0x10b8));
374 return SWAPu32(HW_DMA3_CHCR);
379 PSXHW_LOG("DMA PCR 32bit read %x\n", psxHu32(0x10f0));
380 return SWAPu32(HW_DMA_PCR); // dma rest channel
382 PSXHW_LOG("DMA ICR 32bit read %x\n", psxHu32(0x10f4));
383 return SWAPu32(HW_DMA_ICR); // interrupt enabler?*/
386 // time for rootcounters :)
388 hard = psxRcntRcount0();
390 PSXHW_LOG("T0 count read32: %x\n", hard);
394 hard = psxRcntRmode(0);
396 PSXHW_LOG("T0 mode read32: %x\n", hard);
400 hard = psxRcntRtarget(0);
402 PSXHW_LOG("T0 target read32: %x\n", hard);
406 hard = psxRcntRcount1();
408 PSXHW_LOG("T1 count read32: %x\n", hard);
412 hard = psxRcntRmode(1);
414 PSXHW_LOG("T1 mode read32: %x\n", hard);
418 hard = psxRcntRtarget(1);
420 PSXHW_LOG("T1 target read32: %x\n", hard);
424 hard = psxRcntRcount2();
426 PSXHW_LOG("T2 count read32: %x\n", hard);
430 hard = psxRcntRmode(2);
432 PSXHW_LOG("T2 mode read32: %x\n", hard);
436 hard = psxRcntRtarget(2);
438 PSXHW_LOG("T2 target read32: %x\n", hard);
449 log_unhandled("unhandled r32 %08x @%08x\n", add, psxRegs.pc);
452 if (0x1f801c00 <= add && add < 0x1f802000) {
453 hard = SPU_readRegister(add, psxRegs.cycle);
454 hard |= SPU_readRegister(add + 2, psxRegs.cycle) << 16;
459 PSXHW_LOG("*Unkwnown 32bit read at address %x\n", add);
464 PSXHW_LOG("*Known 32bit read at address %x\n", add);
469 void psxHwWrite8(u32 add, u8 value) {
470 switch (add & 0x1fffffff) {
471 case 0x1f801040: sioWrite8(value); break;
\r
472 case 0x1f801800: cdrWrite0(value); break;
473 case 0x1f801801: cdrWrite1(value); break;
474 case 0x1f801802: cdrWrite2(value); break;
475 case 0x1f801803: cdrWrite3(value); break;
477 case 0x1f801041: case 0x1f801042: case 0x1f801043:
478 case 0x1f801044: case 0x1f801045:
479 case 0x1f801046: case 0x1f801047:
480 case 0x1f801048: case 0x1f801049:
481 case 0x1f80104a: case 0x1f80104b:
482 case 0x1f80104c: case 0x1f80104d:
483 case 0x1f80104e: case 0x1f80104f:
484 case 0x1f801050: case 0x1f801051:
485 case 0x1f801054: case 0x1f801055:
486 case 0x1f801058: case 0x1f801059:
487 case 0x1f80105a: case 0x1f80105b:
488 case 0x1f80105c: case 0x1f80105d:
489 case 0x1f801100: case 0x1f801101:
490 case 0x1f801104: case 0x1f801105:
491 case 0x1f801108: case 0x1f801109:
492 case 0x1f801110: case 0x1f801111:
493 case 0x1f801114: case 0x1f801115:
494 case 0x1f801118: case 0x1f801119:
495 case 0x1f801120: case 0x1f801121:
496 case 0x1f801124: case 0x1f801125:
497 case 0x1f801128: case 0x1f801129:
498 case 0x1f801810: case 0x1f801811:
499 case 0x1f801812: case 0x1f801813:
500 case 0x1f801814: case 0x1f801815:
501 case 0x1f801816: case 0x1f801817:
502 case 0x1f801820: case 0x1f801821:
503 case 0x1f801822: case 0x1f801823:
504 case 0x1f801824: case 0x1f801825:
505 case 0x1f801826: case 0x1f801827:
506 log_unhandled("unhandled w8 %08x @%08x\n", add, psxRegs.pc);
509 if (0x1f801c00 <= add && add < 0x1f802000) {
510 log_unhandled("spu w8 %02x @%08x\n", value, psxRegs.pc);
512 SPU_writeRegister(add, value, psxRegs.cycle);
518 PSXHW_LOG("*Unknown 8bit write at address %x value %x\n", add, value);
524 PSXHW_LOG("*Known 8bit write at address %x value %x\n", add, value);
528 void psxHwWrite16(u32 add, u16 value) {
529 switch (add & 0x1fffffff) {
531 sioWrite8((unsigned char)value);
532 sioWrite8((unsigned char)(value>>8));
533 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
536 sioWriteStat16(value);
537 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
540 sioWriteMode16(value);
541 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
543 case 0x1f80104a: // control register
544 sioWriteCtrl16(value);
545 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
547 case 0x1f80104e: // baudrate register
548 sioWriteBaud16(value);
549 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
553 PSXHW_LOG("IREG 16bit write %x\n", value);
555 psxHwWriteIstat(value);
560 PSXHW_LOG("IMASK 16bit write %x\n", value);
562 psxHwWriteImask(value);
567 PSXHW_LOG("COUNTER 0 COUNT 16bit write %x\n", value);
569 psxRcntWcount(0, value); return;
572 PSXHW_LOG("COUNTER 0 MODE 16bit write %x\n", value);
574 psxRcntWmode(0, value); return;
577 PSXHW_LOG("COUNTER 0 TARGET 16bit write %x\n", value);
579 psxRcntWtarget(0, value); return;
583 PSXHW_LOG("COUNTER 1 COUNT 16bit write %x\n", value);
585 psxRcntWcount(1, value); return;
588 PSXHW_LOG("COUNTER 1 MODE 16bit write %x\n", value);
590 psxRcntWmode(1, value); return;
593 PSXHW_LOG("COUNTER 1 TARGET 16bit write %x\n", value);
595 psxRcntWtarget(1, value); return;
599 PSXHW_LOG("COUNTER 2 COUNT 16bit write %x\n", value);
601 psxRcntWcount(2, value); return;
604 PSXHW_LOG("COUNTER 2 MODE 16bit write %x\n", value);
606 psxRcntWmode(2, value); return;
609 PSXHW_LOG("COUNTER 2 TARGET 16bit write %x\n", value);
611 psxRcntWtarget(2, value); return;
631 log_unhandled("unhandled w16 %08x @%08x\n", add, psxRegs.pc);
634 if (0x1f801c00 <= add && add < 0x1f802000) {
635 SPU_writeRegister(add, value, psxRegs.cycle);
639 psxHu16ref(add) = SWAPu16(value);
641 PSXHW_LOG("*Unknown 16bit write at address %x value %x\n", add, value);
645 psxHu16ref(add) = SWAPu16(value);
647 PSXHW_LOG("*Known 16bit write at address %x value %x\n", add, value);
651 #define DmaExec(n) { \
652 if (value & SWAPu32(HW_DMA##n##_CHCR) & 0x01000000) \
653 log_unhandled("dma" #n " %08x -> %08x\n", HW_DMA##n##_CHCR, value); \
654 HW_DMA##n##_CHCR = SWAPu32(value); \
656 if (SWAPu32(HW_DMA##n##_CHCR) & 0x01000000 && SWAPu32(HW_DMA_PCR) & (8 << (n * 4))) { \
657 psxDma##n(SWAPu32(HW_DMA##n##_MADR), SWAPu32(HW_DMA##n##_BCR), SWAPu32(HW_DMA##n##_CHCR)); \
661 void psxHwWrite32(u32 add, u32 value) {
662 switch (add & 0x1fffffff) {
664 sioWrite8((unsigned char)value);
665 sioWrite8((unsigned char)((value&0xff) >> 8));
666 sioWrite8((unsigned char)((value&0xff) >> 16));
667 sioWrite8((unsigned char)((value&0xff) >> 24));
668 PAD_LOG("sio write32 %x\n", value);
672 PSXHW_LOG("RAM size write %x\n", value);
673 psxHu32ref(add) = SWAPu32(value);
679 PSXHW_LOG("IREG 32bit write %x\n", value);
681 psxHwWriteIstat(value);
685 PSXHW_LOG("IMASK 32bit write %x\n", value);
687 psxHwWriteImask(value);
692 PSXHW_LOG("DMA0 MADR 32bit write %x\n", value);
693 HW_DMA0_MADR = SWAPu32(value); return; // DMA0 madr
695 PSXHW_LOG("DMA0 BCR 32bit write %x\n", value);
696 HW_DMA0_BCR = SWAPu32(value); return; // DMA0 bcr
700 PSXHW_LOG("DMA0 CHCR 32bit write %x\n", value);
702 DmaExec(0); // DMA0 chcr (MDEC in DMA)
707 PSXHW_LOG("DMA1 MADR 32bit write %x\n", value);
708 HW_DMA1_MADR = SWAPu32(value); return; // DMA1 madr
710 PSXHW_LOG("DMA1 BCR 32bit write %x\n", value);
711 HW_DMA1_BCR = SWAPu32(value); return; // DMA1 bcr
715 PSXHW_LOG("DMA1 CHCR 32bit write %x\n", value);
717 DmaExec(1); // DMA1 chcr (MDEC out DMA)
722 PSXHW_LOG("DMA2 MADR 32bit write %x\n", value);
723 HW_DMA2_MADR = SWAPu32(value); return; // DMA2 madr
725 PSXHW_LOG("DMA2 BCR 32bit write %x\n", value);
726 HW_DMA2_BCR = SWAPu32(value); return; // DMA2 bcr
730 PSXHW_LOG("DMA2 CHCR 32bit write %x\n", value);
732 DmaExec(2); // DMA2 chcr (GPU DMA)
737 PSXHW_LOG("DMA3 MADR 32bit write %x\n", value);
738 HW_DMA3_MADR = SWAPu32(value); return; // DMA3 madr
740 PSXHW_LOG("DMA3 BCR 32bit write %x\n", value);
741 HW_DMA3_BCR = SWAPu32(value); return; // DMA3 bcr
745 PSXHW_LOG("DMA3 CHCR 32bit write %x\n", value);
747 DmaExec(3); // DMA3 chcr (CDROM DMA)
753 PSXHW_LOG("DMA4 MADR 32bit write %x\n", value);
754 HW_DMA4_MADR = SWAPu32(value); return; // DMA4 madr
756 PSXHW_LOG("DMA4 BCR 32bit write %x\n", value);
757 HW_DMA4_BCR = SWAPu32(value); return; // DMA4 bcr
761 PSXHW_LOG("DMA4 CHCR 32bit write %x\n", value);
763 DmaExec(4); // DMA4 chcr (SPU DMA)
767 case 0x1f8010d0: break; //DMA5write_madr();
768 case 0x1f8010d4: break; //DMA5write_bcr();
769 case 0x1f8010d8: break; //DMA5write_chcr(); // Not needed
774 PSXHW_LOG("DMA6 MADR 32bit write %x\n", value);
775 HW_DMA6_MADR = SWAPu32(value); return; // DMA6 bcr
777 PSXHW_LOG("DMA6 BCR 32bit write %x\n", value);
778 HW_DMA6_BCR = SWAPu32(value); return; // DMA6 bcr
782 PSXHW_LOG("DMA6 CHCR 32bit write %x\n", value);
784 DmaExec(6); // DMA6 chcr (OT clear)
789 PSXHW_LOG("DMA PCR 32bit write %x\n", value);
790 HW_DMA_PCR = SWAPu32(value);
796 PSXHW_LOG("DMA ICR 32bit write %x\n", value);
798 psxHwWriteDmaIcr32(value);
803 PSXHW_LOG("GPU DATA 32bit write %x\n", value);
805 GPU_writeData(value); return;
808 PSXHW_LOG("GPU STATUS 32bit write %x\n", value);
810 psxHwWriteGpuSR(value);
814 mdecWrite0(value); break;
816 mdecWrite1(value); break;
820 PSXHW_LOG("COUNTER 0 COUNT 32bit write %x\n", value);
822 psxRcntWcount(0, value & 0xffff); return;
825 PSXHW_LOG("COUNTER 0 MODE 32bit write %x\n", value);
827 psxRcntWmode(0, value); return;
830 PSXHW_LOG("COUNTER 0 TARGET 32bit write %x\n", value);
832 psxRcntWtarget(0, value & 0xffff); return; // HW_DMA_ICR&= SWAP32((~value)&0xff000000);
836 PSXHW_LOG("COUNTER 1 COUNT 32bit write %x\n", value);
838 psxRcntWcount(1, value & 0xffff); return;
841 PSXHW_LOG("COUNTER 1 MODE 32bit write %x\n", value);
843 psxRcntWmode(1, value); return;
846 PSXHW_LOG("COUNTER 1 TARGET 32bit write %x\n", value);
848 psxRcntWtarget(1, value & 0xffff); return;
852 PSXHW_LOG("COUNTER 2 COUNT 32bit write %x\n", value);
854 psxRcntWcount(2, value & 0xffff); return;
857 PSXHW_LOG("COUNTER 2 MODE 32bit write %x\n", value);
859 psxRcntWmode(2, value); return;
862 PSXHW_LOG("COUNTER 2 TARGET 32bit write %x\n", value);
864 psxRcntWtarget(2, value & 0xffff); return;
874 log_unhandled("unhandled w32 %08x @%08x\n", add, psxRegs.pc);
877 // Dukes of Hazard 2 - car engine noise
878 if (0x1f801c00 <= add && add < 0x1f802000) {
879 SPU_writeRegister(add, value&0xffff, psxRegs.cycle);
880 SPU_writeRegister(add + 2, value>>16, psxRegs.cycle);
884 psxHu32ref(add) = SWAPu32(value);
886 PSXHW_LOG("*Unknown 32bit write at address %x value %x\n", add, value);
890 psxHu32ref(add) = SWAPu32(value);
892 PSXHW_LOG("*Known 32bit write at address %x value %x\n", add, value);
896 int psxHwFreeze(void *f, int Mode) {