1 /***************************************************************************
2 * Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
18 ***************************************************************************/
21 * Functions for PSX hardware control.
30 //#define PSXHW_LOG printf
35 static u32 (*psxHwReadGpuSRptr)(void) = psxHwReadGpuSR;
38 memset(psxH, 0, 0x10000);
40 mdecInit(); // initialize mdec decoder
43 HW_GPU_STATUS = SWAP32(0x14802000);
44 psxHwReadGpuSRptr = Config.hacks.gpu_busy_hack
45 ? psxHwReadGpuSRbusyHack : psxHwReadGpuSR;
48 void psxHwWriteIstat(u32 value)
50 u32 stat = psxHu16(0x1070) & value;
51 psxHu16ref(0x1070) = SWAPu16(stat);
53 psxRegs.CP0.n.Cause &= ~0x400;
54 if (stat & psxHu16(0x1074))
55 psxRegs.CP0.n.Cause |= 0x400;
58 void psxHwWriteImask(u32 value)
60 u32 stat = psxHu16(0x1070);
61 psxHu16ref(0x1074) = SWAPu16(value);
63 //if ((psxRegs.CP0.n.SR & 0x401) == 0x401)
64 // log_unhandled("irq on unmask @%08x\n", psxRegs.pc);
65 new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
67 psxRegs.CP0.n.Cause &= ~0x400;
69 psxRegs.CP0.n.Cause |= 0x400;
72 void psxHwWriteDmaIcr32(u32 value)
74 u32 tmp = value & 0x00ff803f;
75 tmp |= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000;
76 if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000)
77 || tmp & HW_DMA_ICR_BUS_ERROR) {
78 if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT))
79 psxHu32ref(0x1070) |= SWAP32(8);
80 tmp |= HW_DMA_ICR_IRQ_SENT;
82 HW_DMA_ICR = SWAPu32(tmp);
85 void psxHwWriteGpuSR(u32 value)
87 GPU_writeStatus(value);
91 u32 psxHwReadGpuSR(void)
95 // meh2, syncing for img bit, might want to avoid it..
99 // XXX: because of large timeslices can't use hSyncCount, using rough
100 // approximization instead. Perhaps better use hcounter code here or something.
101 if (hSyncCount < 240 && (HW_GPU_STATUS & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS)
102 v |= PSXGPU_LCF & (psxRegs.cycle << 20);
106 // a hack due to poor timing of gpu idle bit
107 // to get rid of this, GPU draw times, DMAs, cpu timing has to fall within
108 // certain timing window or else games like "ToHeart" softlock
109 u32 psxHwReadGpuSRbusyHack(void)
111 u32 v = psxHwReadGpuSR();
118 u8 psxHwRead8(u32 add) {
121 switch (add & 0x1fffffff) {
122 case 0x1f801040: hard = sioRead8(); break;
123 case 0x1f801800: hard = cdrRead0(); break;
124 case 0x1f801801: hard = cdrRead1(); break;
125 case 0x1f801802: hard = cdrRead2(); break;
126 case 0x1f801803: hard = cdrRead3(); break;
128 case 0x1f801041: case 0x1f801042: case 0x1f801043:
129 case 0x1f801044: case 0x1f801045:
130 case 0x1f801046: case 0x1f801047:
131 case 0x1f801048: case 0x1f801049:
132 case 0x1f80104a: case 0x1f80104b:
133 case 0x1f80104c: case 0x1f80104d:
134 case 0x1f80104e: case 0x1f80104f:
135 case 0x1f801050: case 0x1f801051:
136 case 0x1f801054: case 0x1f801055:
137 case 0x1f801058: case 0x1f801059:
138 case 0x1f80105a: case 0x1f80105b:
139 case 0x1f80105c: case 0x1f80105d:
140 case 0x1f801100: case 0x1f801101:
141 case 0x1f801104: case 0x1f801105:
142 case 0x1f801108: case 0x1f801109:
143 case 0x1f801110: case 0x1f801111:
144 case 0x1f801114: case 0x1f801115:
145 case 0x1f801118: case 0x1f801119:
146 case 0x1f801120: case 0x1f801121:
147 case 0x1f801124: case 0x1f801125:
148 case 0x1f801128: case 0x1f801129:
149 case 0x1f801810: case 0x1f801811:
150 case 0x1f801812: case 0x1f801813:
151 case 0x1f801814: case 0x1f801815:
152 case 0x1f801816: case 0x1f801817:
153 case 0x1f801820: case 0x1f801821:
154 case 0x1f801822: case 0x1f801823:
155 case 0x1f801824: case 0x1f801825:
156 case 0x1f801826: case 0x1f801827:
157 log_unhandled("unhandled r8 %08x @%08x\n", add, psxRegs.pc);
160 if (0x1f801c00 <= add && add < 0x1f802000) {
161 u16 val = SPU_readRegister(add & ~1, psxRegs.cycle);
162 hard = (add & 1) ? val >> 8 : val;
167 PSXHW_LOG("*Unkwnown 8bit read at address %x\n", add);
173 PSXHW_LOG("*Known 8bit read at address %x value %x\n", add, hard);
178 u16 psxHwRead16(u32 add) {
181 switch (add & 0x1fffffff) {
183 case 0x1f801070: PSXHW_LOG("IREG 16bit read %x\n", psxHu16(0x1070));
184 return psxHu16(0x1070);
185 case 0x1f801074: PSXHW_LOG("IMASK 16bit read %x\n", psxHu16(0x1074));
186 return psxHu16(0x1074);
190 hard|= sioRead8() << 8;
191 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
194 hard = sioReadStat16();
195 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
198 hard = sioReadMode16();
199 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
202 hard = sioReadCtrl16();
203 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
206 hard = sioReadBaud16();
207 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
210 /* Fixes Armored Core misdetecting the Link cable being detected.
211 * We want to turn that thing off and force it to do local multiplayer instead.
212 * Thanks Sony for the fix, they fixed it in their PS Classic fork.
218 hard = psxRcntRcount0();
220 PSXHW_LOG("T0 count read16: %x\n", hard);
224 hard = psxRcntRmode(0);
226 PSXHW_LOG("T0 mode read16: %x\n", hard);
230 hard = psxRcntRtarget(0);
232 PSXHW_LOG("T0 target read16: %x\n", hard);
236 hard = psxRcntRcount1();
238 PSXHW_LOG("T1 count read16: %x\n", hard);
242 hard = psxRcntRmode(1);
244 PSXHW_LOG("T1 mode read16: %x\n", hard);
248 hard = psxRcntRtarget(1);
250 PSXHW_LOG("T1 target read16: %x\n", hard);
254 hard = psxRcntRcount2();
256 PSXHW_LOG("T2 count read16: %x\n", hard);
260 hard = psxRcntRmode(2);
262 PSXHW_LOG("T2 mode read16: %x\n", hard);
266 hard = psxRcntRtarget(2);
268 PSXHW_LOG("T2 target read16: %x\n", hard);
272 //case 0x1f802030: hard = //int_2000????
273 //case 0x1f802040: hard =//dip switches...??
292 log_unhandled("unhandled r16 %08x @%08x\n", add, psxRegs.pc);
295 if (0x1f801c00 <= add && add < 0x1f802000)
296 return SPU_readRegister(add, psxRegs.cycle);
299 PSXHW_LOG("*Unkwnown 16bit read at address %x\n", add);
305 PSXHW_LOG("*Known 16bit read at address %x value %x\n", add, hard);
310 u32 psxHwRead32(u32 add) {
313 switch (add & 0x1fffffff) {
316 hard |= sioRead8() << 8;
317 hard |= sioRead8() << 16;
318 hard |= sioRead8() << 24;
319 PAD_LOG("sio read32 ;ret = %x\n", hard);
322 hard = sioReadStat16();
323 PAD_LOG("sio read32 %x; ret = %x\n", add&0xf, hard);
327 PSXHW_LOG("RAM size read %x\n", psxHu32(0x1060));
328 return psxHu32(0x1060);
329 case 0x1f801070: PSXHW_LOG("IREG 32bit read %x\n", psxHu32(0x1070));
330 return psxHu32(0x1070);
331 case 0x1f801074: PSXHW_LOG("IMASK 32bit read %x\n", psxHu32(0x1074));
332 return psxHu32(0x1074);
336 hard = GPU_readData();
338 PSXHW_LOG("GPU DATA 32bit read %x\n", hard);
342 hard = psxHwReadGpuSRptr();
344 PSXHW_LOG("GPU STATUS 32bit read %x\n", hard);
348 case 0x1f801820: hard = mdecRead0(); break;
349 case 0x1f801824: hard = mdecRead1(); break;
353 PSXHW_LOG("DMA2 MADR 32bit read %x\n", psxHu32(0x10a0));
354 return SWAPu32(HW_DMA2_MADR);
356 PSXHW_LOG("DMA2 BCR 32bit read %x\n", psxHu32(0x10a4));
357 return SWAPu32(HW_DMA2_BCR);
359 PSXHW_LOG("DMA2 CHCR 32bit read %x\n", psxHu32(0x10a8));
360 return SWAPu32(HW_DMA2_CHCR);
365 PSXHW_LOG("DMA3 MADR 32bit read %x\n", psxHu32(0x10b0));
366 return SWAPu32(HW_DMA3_MADR);
368 PSXHW_LOG("DMA3 BCR 32bit read %x\n", psxHu32(0x10b4));
369 return SWAPu32(HW_DMA3_BCR);
371 PSXHW_LOG("DMA3 CHCR 32bit read %x\n", psxHu32(0x10b8));
372 return SWAPu32(HW_DMA3_CHCR);
377 PSXHW_LOG("DMA PCR 32bit read %x\n", psxHu32(0x10f0));
378 return SWAPu32(HW_DMA_PCR); // dma rest channel
380 PSXHW_LOG("DMA ICR 32bit read %x\n", psxHu32(0x10f4));
381 return SWAPu32(HW_DMA_ICR); // interrupt enabler?*/
384 // time for rootcounters :)
386 hard = psxRcntRcount0();
388 PSXHW_LOG("T0 count read32: %x\n", hard);
392 hard = psxRcntRmode(0);
394 PSXHW_LOG("T0 mode read32: %x\n", hard);
398 hard = psxRcntRtarget(0);
400 PSXHW_LOG("T0 target read32: %x\n", hard);
404 hard = psxRcntRcount1();
406 PSXHW_LOG("T1 count read32: %x\n", hard);
410 hard = psxRcntRmode(1);
412 PSXHW_LOG("T1 mode read32: %x\n", hard);
416 hard = psxRcntRtarget(1);
418 PSXHW_LOG("T1 target read32: %x\n", hard);
422 hard = psxRcntRcount2();
424 PSXHW_LOG("T2 count read32: %x\n", hard);
428 hard = psxRcntRmode(2);
430 PSXHW_LOG("T2 mode read32: %x\n", hard);
434 hard = psxRcntRtarget(2);
436 PSXHW_LOG("T2 target read32: %x\n", hard);
447 log_unhandled("unhandled r32 %08x @%08x\n", add, psxRegs.pc);
450 if (0x1f801c00 <= add && add < 0x1f802000) {
451 hard = SPU_readRegister(add, psxRegs.cycle);
452 hard |= SPU_readRegister(add + 2, psxRegs.cycle) << 16;
457 PSXHW_LOG("*Unkwnown 32bit read at address %x\n", add);
462 PSXHW_LOG("*Known 32bit read at address %x\n", add);
467 void psxHwWrite8(u32 add, u8 value) {
468 switch (add & 0x1fffffff) {
469 case 0x1f801040: sioWrite8(value); break;
\r
470 case 0x1f801800: cdrWrite0(value); break;
471 case 0x1f801801: cdrWrite1(value); break;
472 case 0x1f801802: cdrWrite2(value); break;
473 case 0x1f801803: cdrWrite3(value); break;
475 case 0x1f801041: case 0x1f801042: case 0x1f801043:
476 case 0x1f801044: case 0x1f801045:
477 case 0x1f801046: case 0x1f801047:
478 case 0x1f801048: case 0x1f801049:
479 case 0x1f80104a: case 0x1f80104b:
480 case 0x1f80104c: case 0x1f80104d:
481 case 0x1f80104e: case 0x1f80104f:
482 case 0x1f801050: case 0x1f801051:
483 case 0x1f801054: case 0x1f801055:
484 case 0x1f801058: case 0x1f801059:
485 case 0x1f80105a: case 0x1f80105b:
486 case 0x1f80105c: case 0x1f80105d:
487 case 0x1f801100: case 0x1f801101:
488 case 0x1f801104: case 0x1f801105:
489 case 0x1f801108: case 0x1f801109:
490 case 0x1f801110: case 0x1f801111:
491 case 0x1f801114: case 0x1f801115:
492 case 0x1f801118: case 0x1f801119:
493 case 0x1f801120: case 0x1f801121:
494 case 0x1f801124: case 0x1f801125:
495 case 0x1f801128: case 0x1f801129:
496 case 0x1f801810: case 0x1f801811:
497 case 0x1f801812: case 0x1f801813:
498 case 0x1f801814: case 0x1f801815:
499 case 0x1f801816: case 0x1f801817:
500 case 0x1f801820: case 0x1f801821:
501 case 0x1f801822: case 0x1f801823:
502 case 0x1f801824: case 0x1f801825:
503 case 0x1f801826: case 0x1f801827:
504 log_unhandled("unhandled w8 %08x @%08x\n", add, psxRegs.pc);
507 if (0x1f801c00 <= add && add < 0x1f802000) {
508 log_unhandled("spu w8 %02x @%08x\n", value, psxRegs.pc);
510 SPU_writeRegister(add, value, psxRegs.cycle);
516 PSXHW_LOG("*Unknown 8bit write at address %x value %x\n", add, value);
522 PSXHW_LOG("*Known 8bit write at address %x value %x\n", add, value);
526 void psxHwWrite16(u32 add, u16 value) {
527 switch (add & 0x1fffffff) {
529 sioWrite8((unsigned char)value);
530 sioWrite8((unsigned char)(value>>8));
531 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
534 sioWriteStat16(value);
535 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
538 sioWriteMode16(value);
539 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
541 case 0x1f80104a: // control register
542 sioWriteCtrl16(value);
543 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
545 case 0x1f80104e: // baudrate register
546 sioWriteBaud16(value);
547 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
551 PSXHW_LOG("IREG 16bit write %x\n", value);
553 psxHwWriteIstat(value);
558 PSXHW_LOG("IMASK 16bit write %x\n", value);
560 psxHwWriteImask(value);
565 PSXHW_LOG("COUNTER 0 COUNT 16bit write %x\n", value);
567 psxRcntWcount(0, value); return;
570 PSXHW_LOG("COUNTER 0 MODE 16bit write %x\n", value);
572 psxRcntWmode(0, value); return;
575 PSXHW_LOG("COUNTER 0 TARGET 16bit write %x\n", value);
577 psxRcntWtarget(0, value); return;
581 PSXHW_LOG("COUNTER 1 COUNT 16bit write %x\n", value);
583 psxRcntWcount(1, value); return;
586 PSXHW_LOG("COUNTER 1 MODE 16bit write %x\n", value);
588 psxRcntWmode(1, value); return;
591 PSXHW_LOG("COUNTER 1 TARGET 16bit write %x\n", value);
593 psxRcntWtarget(1, value); return;
597 PSXHW_LOG("COUNTER 2 COUNT 16bit write %x\n", value);
599 psxRcntWcount(2, value); return;
602 PSXHW_LOG("COUNTER 2 MODE 16bit write %x\n", value);
604 psxRcntWmode(2, value); return;
607 PSXHW_LOG("COUNTER 2 TARGET 16bit write %x\n", value);
609 psxRcntWtarget(2, value); return;
629 log_unhandled("unhandled w16 %08x @%08x\n", add, psxRegs.pc);
632 if (0x1f801c00 <= add && add < 0x1f802000) {
633 SPU_writeRegister(add, value, psxRegs.cycle);
637 psxHu16ref(add) = SWAPu16(value);
639 PSXHW_LOG("*Unknown 16bit write at address %x value %x\n", add, value);
643 psxHu16ref(add) = SWAPu16(value);
645 PSXHW_LOG("*Known 16bit write at address %x value %x\n", add, value);
649 #define DmaExec(n) { \
650 if (value & SWAPu32(HW_DMA##n##_CHCR) & 0x01000000) \
651 log_unhandled("dma" #n " %08x -> %08x\n", HW_DMA##n##_CHCR, value); \
652 HW_DMA##n##_CHCR = SWAPu32(value); \
654 if (SWAPu32(HW_DMA##n##_CHCR) & 0x01000000 && SWAPu32(HW_DMA_PCR) & (8 << (n * 4))) { \
655 psxDma##n(SWAPu32(HW_DMA##n##_MADR), SWAPu32(HW_DMA##n##_BCR), SWAPu32(HW_DMA##n##_CHCR)); \
659 void psxHwWrite32(u32 add, u32 value) {
660 switch (add & 0x1fffffff) {
662 sioWrite8((unsigned char)value);
663 sioWrite8((unsigned char)((value&0xff) >> 8));
664 sioWrite8((unsigned char)((value&0xff) >> 16));
665 sioWrite8((unsigned char)((value&0xff) >> 24));
666 PAD_LOG("sio write32 %x\n", value);
670 PSXHW_LOG("RAM size write %x\n", value);
671 psxHu32ref(add) = SWAPu32(value);
677 PSXHW_LOG("IREG 32bit write %x\n", value);
679 psxHwWriteIstat(value);
683 PSXHW_LOG("IMASK 32bit write %x\n", value);
685 psxHwWriteImask(value);
690 PSXHW_LOG("DMA0 MADR 32bit write %x\n", value);
691 HW_DMA0_MADR = SWAPu32(value); return; // DMA0 madr
693 PSXHW_LOG("DMA0 BCR 32bit write %x\n", value);
694 HW_DMA0_BCR = SWAPu32(value); return; // DMA0 bcr
698 PSXHW_LOG("DMA0 CHCR 32bit write %x\n", value);
700 DmaExec(0); // DMA0 chcr (MDEC in DMA)
705 PSXHW_LOG("DMA1 MADR 32bit write %x\n", value);
706 HW_DMA1_MADR = SWAPu32(value); return; // DMA1 madr
708 PSXHW_LOG("DMA1 BCR 32bit write %x\n", value);
709 HW_DMA1_BCR = SWAPu32(value); return; // DMA1 bcr
713 PSXHW_LOG("DMA1 CHCR 32bit write %x\n", value);
715 DmaExec(1); // DMA1 chcr (MDEC out DMA)
720 PSXHW_LOG("DMA2 MADR 32bit write %x\n", value);
721 HW_DMA2_MADR = SWAPu32(value); return; // DMA2 madr
723 PSXHW_LOG("DMA2 BCR 32bit write %x\n", value);
724 HW_DMA2_BCR = SWAPu32(value); return; // DMA2 bcr
728 PSXHW_LOG("DMA2 CHCR 32bit write %x\n", value);
730 DmaExec(2); // DMA2 chcr (GPU DMA)
735 PSXHW_LOG("DMA3 MADR 32bit write %x\n", value);
736 HW_DMA3_MADR = SWAPu32(value); return; // DMA3 madr
738 PSXHW_LOG("DMA3 BCR 32bit write %x\n", value);
739 HW_DMA3_BCR = SWAPu32(value); return; // DMA3 bcr
743 PSXHW_LOG("DMA3 CHCR 32bit write %x\n", value);
745 DmaExec(3); // DMA3 chcr (CDROM DMA)
751 PSXHW_LOG("DMA4 MADR 32bit write %x\n", value);
752 HW_DMA4_MADR = SWAPu32(value); return; // DMA4 madr
754 PSXHW_LOG("DMA4 BCR 32bit write %x\n", value);
755 HW_DMA4_BCR = SWAPu32(value); return; // DMA4 bcr
759 PSXHW_LOG("DMA4 CHCR 32bit write %x\n", value);
761 DmaExec(4); // DMA4 chcr (SPU DMA)
765 case 0x1f8010d0: break; //DMA5write_madr();
766 case 0x1f8010d4: break; //DMA5write_bcr();
767 case 0x1f8010d8: break; //DMA5write_chcr(); // Not needed
772 PSXHW_LOG("DMA6 MADR 32bit write %x\n", value);
773 HW_DMA6_MADR = SWAPu32(value); return; // DMA6 bcr
775 PSXHW_LOG("DMA6 BCR 32bit write %x\n", value);
776 HW_DMA6_BCR = SWAPu32(value); return; // DMA6 bcr
780 PSXHW_LOG("DMA6 CHCR 32bit write %x\n", value);
782 DmaExec(6); // DMA6 chcr (OT clear)
787 PSXHW_LOG("DMA PCR 32bit write %x\n", value);
788 HW_DMA_PCR = SWAPu32(value);
794 PSXHW_LOG("DMA ICR 32bit write %x\n", value);
796 psxHwWriteDmaIcr32(value);
801 PSXHW_LOG("GPU DATA 32bit write %x\n", value);
803 GPU_writeData(value); return;
806 PSXHW_LOG("GPU STATUS 32bit write %x\n", value);
808 psxHwWriteGpuSR(value);
812 mdecWrite0(value); break;
814 mdecWrite1(value); break;
818 PSXHW_LOG("COUNTER 0 COUNT 32bit write %x\n", value);
820 psxRcntWcount(0, value & 0xffff); return;
823 PSXHW_LOG("COUNTER 0 MODE 32bit write %x\n", value);
825 psxRcntWmode(0, value); return;
828 PSXHW_LOG("COUNTER 0 TARGET 32bit write %x\n", value);
830 psxRcntWtarget(0, value & 0xffff); return; // HW_DMA_ICR&= SWAP32((~value)&0xff000000);
834 PSXHW_LOG("COUNTER 1 COUNT 32bit write %x\n", value);
836 psxRcntWcount(1, value & 0xffff); return;
839 PSXHW_LOG("COUNTER 1 MODE 32bit write %x\n", value);
841 psxRcntWmode(1, value); return;
844 PSXHW_LOG("COUNTER 1 TARGET 32bit write %x\n", value);
846 psxRcntWtarget(1, value & 0xffff); return;
850 PSXHW_LOG("COUNTER 2 COUNT 32bit write %x\n", value);
852 psxRcntWcount(2, value & 0xffff); return;
855 PSXHW_LOG("COUNTER 2 MODE 32bit write %x\n", value);
857 psxRcntWmode(2, value); return;
860 PSXHW_LOG("COUNTER 2 TARGET 32bit write %x\n", value);
862 psxRcntWtarget(2, value & 0xffff); return;
872 log_unhandled("unhandled w32 %08x @%08x\n", add, psxRegs.pc);
875 // Dukes of Hazard 2 - car engine noise
876 if (0x1f801c00 <= add && add < 0x1f802000) {
877 SPU_writeRegister(add, value&0xffff, psxRegs.cycle);
878 SPU_writeRegister(add + 2, value>>16, psxRegs.cycle);
882 psxHu32ref(add) = SWAPu32(value);
884 PSXHW_LOG("*Unknown 32bit write at address %x value %x\n", add, value);
888 psxHu32ref(add) = SWAPu32(value);
890 PSXHW_LOG("*Known 32bit write at address %x value %x\n", add, value);
894 int psxHwFreeze(void *f, int Mode) {