1 /***************************************************************************
2 * Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
18 ***************************************************************************/
21 * R3000A CPU functions.
28 #include "psxinterpreter.h"
30 R3000Acpu *psxCpu = NULL;
36 SysPrintf(_("Running PCSX Version %s (%s).\n"), PCSX_VERSION, __DATE__);
39 if (Config.Cpu == CPU_INTERPRETER) {
41 } else psxCpu = &psxRec;
43 Config.Cpu = CPU_INTERPRETER;
49 if (psxMemInit() == -1) return -1;
51 return psxCpu->Init();
57 memset(&psxRegs, 0, sizeof(psxRegs));
59 psxRegs.pc = 0xbfc00000; // Start in bootstrap
61 psxRegs.CP0.r[12] = 0x10900000; // COP0 enabled | BEV = 1 | TS = 1
62 psxRegs.CP0.r[15] = 0x00000002; // PRevID = Revision ID, same as R3000A
73 EMU_LOG("*BIOS END*\n");
86 void psxException(u32 code, u32 bd) {
87 psxRegs.code = PSXMu32(psxRegs.pc);
89 if (!Config.HLE && ((((psxRegs.code) >> 24) & 0xfe) == 0x4a)) {
90 // "hokuto no ken" / "Crash Bandicot 2" ...
91 // BIOS does not allow to return to GTE instructions
92 // (just skips it, supposedly because it's scheduled already)
93 // so we execute it here
94 psxCP2[psxRegs.code & 0x3f](&psxRegs.CP2);
98 psxRegs.CP0.n.Cause = (psxRegs.CP0.n.Cause & 0x300) | code;
103 PSXCPU_LOG("bd set!!!\n");
105 psxRegs.CP0.n.Cause |= 0x80000000;
106 psxRegs.CP0.n.EPC = (psxRegs.pc - 4);
108 psxRegs.CP0.n.EPC = (psxRegs.pc);
110 if (psxRegs.CP0.n.Status & 0x400000)
111 psxRegs.pc = 0xbfc00180;
113 psxRegs.pc = 0x80000080;
116 psxRegs.CP0.n.Status = (psxRegs.CP0.n.Status &~0x3f) |
117 ((psxRegs.CP0.n.Status & 0xf) << 2);
119 if (Config.HLE) psxBiosException();
122 void psxBranchTest() {
123 if ((psxRegs.cycle - psxNextsCounter) >= psxNextCounter)
126 if (psxRegs.interrupt) {
127 if ((psxRegs.interrupt & (1 << PSXINT_SIO))) { // sio
128 if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SIO].sCycle) >= psxRegs.intCycle[PSXINT_SIO].cycle) {
129 psxRegs.interrupt &= ~(1 << PSXINT_SIO);
133 if (psxRegs.interrupt & (1 << PSXINT_CDR)) { // cdr
134 if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDR].sCycle) >= psxRegs.intCycle[PSXINT_CDR].cycle) {
135 psxRegs.interrupt &= ~(1 << PSXINT_CDR);
139 if (psxRegs.interrupt & (1 << PSXINT_CDREAD)) { // cdr read
140 if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDREAD].sCycle) >= psxRegs.intCycle[PSXINT_CDREAD].cycle) {
141 psxRegs.interrupt &= ~(1 << PSXINT_CDREAD);
142 cdrPlayReadInterrupt();
145 if (psxRegs.interrupt & (1 << PSXINT_GPUDMA)) { // gpu dma
146 if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_GPUDMA].sCycle) >= psxRegs.intCycle[PSXINT_GPUDMA].cycle) {
147 psxRegs.interrupt &= ~(1 << PSXINT_GPUDMA);
151 if (psxRegs.interrupt & (1 << PSXINT_MDECOUTDMA)) { // mdec out dma
152 if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_MDECOUTDMA].sCycle) >= psxRegs.intCycle[PSXINT_MDECOUTDMA].cycle) {
153 psxRegs.interrupt &= ~(1 << PSXINT_MDECOUTDMA);
157 if (psxRegs.interrupt & (1 << PSXINT_SPUDMA)) { // spu dma
158 if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SPUDMA].sCycle) >= psxRegs.intCycle[PSXINT_SPUDMA].cycle) {
159 psxRegs.interrupt &= ~(1 << PSXINT_SPUDMA);
163 if (psxRegs.interrupt & (1 << PSXINT_MDECINDMA)) { // mdec in
164 if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_MDECINDMA].sCycle) >= psxRegs.intCycle[PSXINT_MDECINDMA].cycle) {
165 psxRegs.interrupt &= ~(1 << PSXINT_MDECINDMA);
169 if (psxRegs.interrupt & (1 << PSXINT_GPUOTCDMA)) { // gpu otc
170 if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_GPUOTCDMA].sCycle) >= psxRegs.intCycle[PSXINT_GPUOTCDMA].cycle) {
171 psxRegs.interrupt &= ~(1 << PSXINT_GPUOTCDMA);
175 if (psxRegs.interrupt & (1 << PSXINT_CDRDMA)) { // cdrom
176 if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDRDMA].sCycle) >= psxRegs.intCycle[PSXINT_CDRDMA].cycle) {
177 psxRegs.interrupt &= ~(1 << PSXINT_CDRDMA);
181 if (psxRegs.interrupt & (1 << PSXINT_CDRLID)) { // cdr lid states
182 if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDRLID].sCycle) >= psxRegs.intCycle[PSXINT_CDRLID].cycle) {
183 psxRegs.interrupt &= ~(1 << PSXINT_CDRLID);
184 cdrLidSeekInterrupt();
187 if (psxRegs.interrupt & (1 << PSXINT_SPU_UPDATE)) { // scheduled spu update
188 if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SPU_UPDATE].sCycle) >= psxRegs.intCycle[PSXINT_SPU_UPDATE].cycle) {
189 psxRegs.interrupt &= ~(1 << PSXINT_SPU_UPDATE);
195 if (psxHu32(0x1070) & psxHu32(0x1074)) {
196 if ((psxRegs.CP0.n.Status & 0x401) == 0x401) {
198 PSXCPU_LOG("Interrupt: %x %x\n", psxHu32(0x1070), psxHu32(0x1074));
200 // SysPrintf("Interrupt (%x): %x %x\n", psxRegs.cycle, psxHu32(0x1070), psxHu32(0x1074));
201 psxException(0x400, 0);
207 if (!Config.HLE && Config.PsxOut) {
208 u32 call = psxRegs.GPR.n.t1 & 0xff;
209 switch (psxRegs.pc & 0x1fffff) {
212 if (call != 0x28 && call != 0xe) {
213 PSXBIOS_LOG("Bios call a0: %s (%x) %x,%x,%x,%x\n", biosA0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3); }
220 if (call != 0x17 && call != 0xb) {
221 PSXBIOS_LOG("Bios call b0: %s (%x) %x,%x,%x,%x\n", biosB0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3); }
228 PSXBIOS_LOG("Bios call c0: %s (%x) %x,%x,%x,%x\n", biosC0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3);
237 void psxExecuteBios() {
238 while (psxRegs.pc != 0x80030000)
239 psxCpu->ExecuteBlock();