1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * linkage_arm.s for PCSX *
3 * Copyright (C) 2009-2011 Ari64 *
4 * Copyright (C) 2010-2013 GraÅžvydas "notaz" Ignotas *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
20 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include "arm_features.h"
23 #include "new_dynarec_config.h"
24 #include "linkage_offsets.h"
28 #define dynarec_local ESYM(dynarec_local)
29 #define ndrc_add_jump_out ESYM(ndrc_add_jump_out)
30 #define ndrc_try_restore_block ESYM(ndrc_try_restore_block)
31 #define ndrc_get_addr_ht ESYM(ndrc_get_addr_ht)
32 #define ndrc_get_addr_ht_param ESYM(ndrc_get_addr_ht_param)
33 #define ndrc_write_invalidate_one ESYM(ndrc_write_invalidate_one)
34 #define gen_interupt ESYM(gen_interupt)
35 #define gteCheckStallRaw ESYM(gteCheckStallRaw)
36 #define psxException ESYM(psxException)
42 .type dynarec_local, %object
43 .size dynarec_local, LO_dynarec_local_size
45 .space LO_dynarec_local_size
47 #define DRC_VAR_(name, vname, size_) \
48 vname = dynarec_local + LO_##name; \
50 .type vname, %object; \
53 #define DRC_VAR(name, size_) \
54 DRC_VAR_(name, ESYM(name), size_)
56 DRC_VAR(next_interupt, 4)
57 DRC_VAR(cycle_count, 4)
58 DRC_VAR(last_count, 4)
59 DRC_VAR(pending_exception, 4)
61 DRC_VAR(branch_target, 4)
64 DRC_VAR(psxRegs, LO_psxRegs_end - LO_psxRegs)
70 DRC_VAR(reg_cop0, 128)
71 DRC_VAR(reg_cop2d, 128)
72 DRC_VAR(reg_cop2c, 128)
76 @DRC_VAR(interrupt, 4)
77 @DRC_VAR(intCycle, 256)
80 DRC_VAR(inv_code_start, 4)
81 DRC_VAR(inv_code_end, 4)
85 DRC_VAR(zeromem_ptr, 4)
87 DRC_VAR(scratch_buf_ptr, 4)
88 DRC_VAR(ram_offset, 4)
103 .macro load_varadr reg var
104 #if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN)
105 movw \reg, #:lower16:(\var-(1678f+8))
106 movt \reg, #:upper16:(\var-(1678f+8))
109 #elif defined(HAVE_ARMV7) && !defined(__PIC__)
110 movw \reg, #:lower16:\var
111 movt \reg, #:upper16:\var
117 .macro load_varadr_ext reg var
118 #if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN)
119 movw \reg, #:lower16:(ptr_\var-(1678f+8))
120 movt \reg, #:upper16:(ptr_\var-(1678f+8))
124 load_varadr \reg \var
128 .macro mov_16 reg imm
132 mov \reg, #(\imm & 0x00ff)
133 orr \reg, #(\imm & 0xff00)
137 .macro mov_24 reg imm
139 movw \reg, #(\imm & 0xffff)
140 movt \reg, #(\imm >> 16)
142 mov \reg, #(\imm & 0x0000ff)
143 orr \reg, #(\imm & 0x00ff00)
144 orr \reg, #(\imm & 0xff0000)
148 FUNCTION(dyna_linker):
149 /* r0 = virtual target address */
150 /* r1 = pointer to an instruction to patch */
151 #ifndef NO_WRITE_EXEC
157 /* must not compile - that might expire the caller block */
159 bl ndrc_get_addr_ht_param
163 add r6, r5, r6, asr #6 /* old target */
165 moveq pc, r0 /* Stale i-cache */
171 and r1, r7, #0xff000000
174 add r1, r1, r2, lsr #8
180 /* XXX: should be able to do better than this... */
184 .size dyna_linker, .-dyna_linker
187 FUNCTION(jump_vaddr_r1):
190 .size jump_vaddr_r1, .-jump_vaddr_r1
191 FUNCTION(jump_vaddr_r2):
194 .size jump_vaddr_r2, .-jump_vaddr_r2
195 FUNCTION(jump_vaddr_r3):
198 .size jump_vaddr_r3, .-jump_vaddr_r3
199 FUNCTION(jump_vaddr_r4):
202 .size jump_vaddr_r4, .-jump_vaddr_r4
203 FUNCTION(jump_vaddr_r5):
206 .size jump_vaddr_r5, .-jump_vaddr_r5
207 FUNCTION(jump_vaddr_r6):
210 .size jump_vaddr_r6, .-jump_vaddr_r6
211 FUNCTION(jump_vaddr_r8):
214 .size jump_vaddr_r8, .-jump_vaddr_r8
215 FUNCTION(jump_vaddr_r9):
218 .size jump_vaddr_r9, .-jump_vaddr_r9
219 FUNCTION(jump_vaddr_r10):
222 .size jump_vaddr_r10, .-jump_vaddr_r10
223 FUNCTION(jump_vaddr_r12):
226 .size jump_vaddr_r12, .-jump_vaddr_r12
227 FUNCTION(jump_vaddr_r7):
229 .size jump_vaddr_r7, .-jump_vaddr_r7
230 FUNCTION(jump_vaddr_r0):
233 .size jump_vaddr_r0, .-jump_vaddr_r0
236 FUNCTION(cc_interrupt):
237 ldr r0, [fp, #LO_last_count]
240 str r1, [fp, #LO_pending_exception]
241 str r10, [fp, #LO_cycle] /* PCSX cycles */
242 @@ str r10, [fp, #LO_reg_cop0+36] /* Count - not on PSX */
247 ldr r10, [fp, #LO_cycle]
248 ldr r0, [fp, #LO_next_interupt]
249 ldr r1, [fp, #LO_pending_exception]
250 ldr r2, [fp, #LO_stop]
251 str r0, [fp, #LO_last_count]
254 ldmfdne sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
257 ldr r0, [fp, #LO_pcaddr]
260 .size cc_interrupt, .-cc_interrupt
263 FUNCTION(fp_exception):
266 ldr r1, [fp, #LO_reg_cop0+48] /* Status */
268 str r0, [fp, #LO_reg_cop0+56] /* EPC */
271 str r1, [fp, #LO_reg_cop0+48] /* Status */
272 str r2, [fp, #LO_reg_cop0+52] /* Cause */
276 .size fp_exception, .-fp_exception
278 FUNCTION(fp_exception_ds):
279 mov r2, #0x90000000 /* Set high bit if delay slot */
281 .size fp_exception_ds, .-fp_exception_ds
284 FUNCTION(jump_break_ds):
288 FUNCTION(jump_break):
292 FUNCTION(jump_syscall_ds):
296 FUNCTION(jump_syscall):
301 ldr r3, [fp, #LO_last_count]
302 str r2, [fp, #LO_pcaddr]
304 str r10, [fp, #LO_cycle] /* PCSX cycles */
307 /* note: psxException might do recursive recompiler call from it's HLE code,
308 * so be ready for this */
309 FUNCTION(jump_to_new_pc):
310 ldr r1, [fp, #LO_next_interupt]
311 ldr r10, [fp, #LO_cycle]
312 ldr r0, [fp, #LO_pcaddr]
314 str r1, [fp, #LO_last_count]
317 .size jump_to_new_pc, .-jump_to_new_pc
320 FUNCTION(new_dyna_leave):
321 ldr r0, [fp, #LO_last_count]
324 str r10, [fp, #LO_cycle]
325 ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
326 .size new_dyna_leave, .-new_dyna_leave
329 FUNCTION(invalidate_addr_r0):
330 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
331 b invalidate_addr_call
332 .size invalidate_addr_r0, .-invalidate_addr_r0
334 FUNCTION(invalidate_addr_r1):
335 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
337 b invalidate_addr_call
338 .size invalidate_addr_r1, .-invalidate_addr_r1
340 FUNCTION(invalidate_addr_r2):
341 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
343 b invalidate_addr_call
344 .size invalidate_addr_r2, .-invalidate_addr_r2
346 FUNCTION(invalidate_addr_r3):
347 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
349 b invalidate_addr_call
350 .size invalidate_addr_r3, .-invalidate_addr_r3
352 FUNCTION(invalidate_addr_r4):
353 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
355 b invalidate_addr_call
356 .size invalidate_addr_r4, .-invalidate_addr_r4
358 FUNCTION(invalidate_addr_r5):
359 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
361 b invalidate_addr_call
362 .size invalidate_addr_r5, .-invalidate_addr_r5
364 FUNCTION(invalidate_addr_r6):
365 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
367 b invalidate_addr_call
368 .size invalidate_addr_r6, .-invalidate_addr_r6
370 FUNCTION(invalidate_addr_r7):
371 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
373 b invalidate_addr_call
374 .size invalidate_addr_r7, .-invalidate_addr_r7
376 FUNCTION(invalidate_addr_r8):
377 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
379 b invalidate_addr_call
380 .size invalidate_addr_r8, .-invalidate_addr_r8
382 FUNCTION(invalidate_addr_r9):
383 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
385 b invalidate_addr_call
386 .size invalidate_addr_r9, .-invalidate_addr_r9
388 FUNCTION(invalidate_addr_r10):
389 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
391 b invalidate_addr_call
392 .size invalidate_addr_r10, .-invalidate_addr_r10
394 FUNCTION(invalidate_addr_r12):
395 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
397 .size invalidate_addr_r12, .-invalidate_addr_r12
399 invalidate_addr_call:
400 ldr r12, [fp, #LO_inv_code_start]
401 ldr lr, [fp, #LO_inv_code_end]
404 blcc ndrc_write_invalidate_one
405 ldmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, pc}
406 .size invalidate_addr_call, .-invalidate_addr_call
409 FUNCTION(new_dyna_start):
410 /* ip is stored to conform EABI alignment */
411 stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
412 mov fp, r0 /* dynarec_local */
413 ldr r0, [fp, #LO_pcaddr]
415 ldr r1, [fp, #LO_next_interupt]
416 ldr r10, [fp, #LO_cycle]
417 str r1, [fp, #LO_last_count]
420 .size new_dyna_start, .-new_dyna_start
422 /* --------------------------------------- */
426 .macro pcsx_read_mem readop tab_shift
427 /* r0 = address, r1 = handler_tab, r2 = cycles */
429 lsr r3, #(20+\tab_shift)
430 ldr r12, [fp, #LO_last_count]
431 ldr r1, [r1, r3, lsl #2]
438 \readop r0, [r1, r3, lsl #\tab_shift]
441 str r2, [fp, #LO_cycle]
445 FUNCTION(jump_handler_read8):
446 add r1, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part
447 pcsx_read_mem ldrbcc, 0
449 FUNCTION(jump_handler_read16):
450 add r1, #0x1000/4*4 @ shift to r16 part
451 pcsx_read_mem ldrhcc, 1
453 FUNCTION(jump_handler_read32):
454 pcsx_read_mem ldrcc, 2
457 .macro memhandler_post
458 ldr r0, [fp, #LO_next_interupt]
459 ldr r2, [fp, #LO_cycle] @ memhandlers can modify cc, like dma
460 str r0, [fp, #LO_last_count]
464 .macro pcsx_write_mem wrtop tab_shift
465 /* r0 = address, r1 = data, r2 = cycles, r3 = handler_tab */
467 lsr r12, #(20+\tab_shift)
468 ldr r3, [r3, r12, lsl #2]
469 str r0, [fp, #LO_address] @ some handlers still need it..
471 mov r0, r2 @ cycle return in case of direct store
476 \wrtop r1, [r3, r12, lsl #\tab_shift]
479 ldr r12, [fp, #LO_last_count]
482 str r2, [fp, #LO_cycle]
484 str lr, [fp, #LO_saved_lr]
486 ldr lr, [fp, #LO_saved_lr]
492 FUNCTION(jump_handler_write8):
493 add r3, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part
494 pcsx_write_mem strbcc, 0
496 FUNCTION(jump_handler_write16):
497 add r3, #0x1000/4*4 @ shift to r16 part
498 pcsx_write_mem strhcc, 1
500 FUNCTION(jump_handler_write32):
501 pcsx_write_mem strcc, 2
503 FUNCTION(jump_handler_write_h):
504 /* r0 = address, r1 = data, r2 = cycles, r3 = handler */
505 ldr r12, [fp, #LO_last_count]
506 str r0, [fp, #LO_address] @ some handlers still need it..
509 str r2, [fp, #LO_cycle]
511 str lr, [fp, #LO_saved_lr]
513 ldr lr, [fp, #LO_saved_lr]
518 FUNCTION(jump_handle_swl):
519 /* r0 = address, r1 = data, r2 = cycles */
520 ldr r3, [fp, #LO_mem_wtab]
522 ldr r3, [r3, r12, lsl #2]
543 lsreq r12, r1, #24 @ 0
553 FUNCTION(jump_handle_swr):
554 /* r0 = address, r1 = data, r2 = cycles */
555 ldr r3, [fp, #LO_mem_wtab]
557 ldr r3, [r3, r12, lsl #2]
579 .macro rcntx_read_mode0 num
580 /* r0 = address, r2 = cycles */
581 ldr r3, [fp, #LO_rcnts+6*4+7*4*\num] @ cycleStart
583 sub r0, r0, r3, lsl #16
588 FUNCTION(rcnt0_read_count_m0):
591 FUNCTION(rcnt1_read_count_m0):
594 FUNCTION(rcnt2_read_count_m0):
597 FUNCTION(rcnt0_read_count_m1):
598 /* r0 = address, r2 = cycles */
599 ldr r3, [fp, #LO_rcnts+6*4+7*4*0] @ cycleStart
602 mul r0, r1, r2 @ /= 5
606 FUNCTION(rcnt1_read_count_m1):
607 /* r0 = address, r2 = cycles */
608 ldr r3, [fp, #LO_rcnts+6*4+7*4*1]
611 umull r3, r0, r1, r2 @ ~ /= hsync_cycles, max ~0x1e6cdd
614 FUNCTION(rcnt2_read_count_m1):
615 /* r0 = address, r2 = cycles */
616 ldr r3, [fp, #LO_rcnts+6*4+7*4*2]
617 mov r0, r2, lsl #16-3
618 sub r0, r0, r3, lsl #16-3
622 FUNCTION(call_gteStall):
623 /* r0 = op_cycles, r1 = cycles */
624 ldr r2, [fp, #LO_last_count]
625 str lr, [fp, #LO_saved_lr]
627 str r1, [fp, #LO_cycle]
628 add r1, fp, #LO_psxRegs
630 ldr lr, [fp, #LO_saved_lr]
640 orr r1, r1, r1, lsl #8
642 orr r1, r1, r1, lsl #16 @ searched char in every byte
643 ldrb r0, [r0, #12] @ last byte
651 orr r3, r3, #0xff000000 @ EXCLUDE_REG
652 uadd8 r0, r12, r1 @ add and set GE bits when not 0 (match)
654 sel r0, r12, r1 @ 0 if no match, else ff in some byte
660 clz r0, r0 @ 0, 8, 16, 24 or 32
663 sub r0, r12, r0, lsr #3 @ 3, 2, 1, 0 or -1
664 sub r2, r12, r2, lsr #3
665 sub r3, r12, r3, lsr #3
672 #endif /* HAVE_ARMV6 */
674 @ vim:filetype=armasm